JP2007074552A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of achieving power consumption reduction while taking environments into account without expanding circuit scale by constructing a means, for supplying a high-speed clock to a system LSI 13, from a little circuits and circuit elements. <P>SOLUTION: An oscillation circuit comprises first and second connecting terminals 9 and 10 to which a resonance circuit 14 or an LSI tester is connected externally; a connecting terminal 11 connected to the system LSI 13; a first serial connection circuit of a first transfer circuit 4 and a first inverter 2 connected between the first and second connecting terminals 9 and 10; a negative feedback resistor 3 connected in parallel to the first serial connecting circuit; a second serial connecting circuit of a second transfer circuit 6 and a second inverter 5 connected between an output terminal of the first inverter 2 and the connecting terminal 11; and a third serial connecting circuit of a third transfer circuit 8 and a third inverter 7 connected between the first connecting terminal 9 and the connecting terminal 11. The first to third transfer circuits 2, 5, 7 are comprised of parallel circuits of complementary MOS transistors wherein complementary TE signal are supplied to gates, and the polarity of complementary TE signals to be supplied to the first and second transfer circuits 2 and 5 and the polarity of a complementary TE signal to be supplied to the third transfer circuit 7 become inverse to each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an oscillation circuit, and more particularly to a system LSI that is mounted on a semiconductor integrated circuit and is driven by a high-speed operation clock obtained from the LSI tester when an LSI tester is selectively connected to an external connection terminal. The present invention relates to an oscillation circuit capable of performing a high-speed operation test of an LSI.

  2. Description of the Related Art In recent years, system LSIs composed of semiconductor integrated circuits have been required to perform high-speed operation tests of system LSIs using LSI testers as their operation clock speeds up. An operation clock used for such a high-speed operation test of the system LSI is formed by an oscillation circuit mounted inside the system LSI, and the oscillation circuit has an external circuit connection terminal and is negative with the inverter circuit. When using an oscillation circuit, when an external circuit connection terminal is connected to a resonance circuit including a crystal resonator, the oscillation circuit generates a clock with an oscillation frequency that depends on the resonance frequency of the resonance circuit. This clock is supplied to the system LSI.

  Such an oscillation circuit has a frequency range in which a clock can be generated in a stable state from several MHz to several tens of MHz, and further generates a high-speed clock having a frequency of several hundreds of MHz in a stable state. In order to achieve this, a phase synchronization circuit (PLL) is built in the system LSI, a clock having a frequency of several MHz to several tens of MHz formed by this oscillation circuit is input to the phase synchronization circuit, and an integer of the input frequency is input to the phase synchronization circuit. This is realized by forming a high-speed clock having a double frequency.

  Further, when an LSI tester is externally connected to the external circuit connection terminal of the oscillation circuit, a high-speed clock of several hundreds of megahertz output from the LSI tester can be directly input into the system LSI due to the retention performance of the LSI tester. Therefore, it is possible to perform a high-speed operation test of the system LSI using such a high-speed clock. In this case, even if an attempt is made to input a high-speed clock of several hundred MHz output from the LSI tester to the system LSI, the oscillation circuit mounted on the system LSI has low adaptability to the high-speed clock output from the LSI tester. The LSI cannot be driven with a high-speed clock, and a stable high-speed clock of several hundred MHz cannot be supplied to the system LSI.

  For this reason, in this type of oscillation circuit, it is considered to separately provide a driving means that can supply a stable high-speed clock of several hundreds of MHz to the system LSI. There is an oscillation circuit disclosed in Japanese Patent No. 85535.

  Here, FIG. 5 is an oscillation circuit disclosed in the above-mentioned Japanese Patent Laid-Open No. 6-85535, and is a circuit diagram showing a configuration of a main part thereof.

  As shown in FIG. 5, the oscillation circuit includes external circuit connection terminals 50 and 51, an output terminal 52, a first inverter 53, a negative feedback resistor 54, a second inverter 55, a test enable terminal 56, The third inverter 57, the NAND circuit 58, the NOR circuit 59, the PMOS transistor 60, and the NMOS transistor 61 are included. The third inverter 57, the NAND circuit 58, the NOR circuit 59, the PMOS transistor 60, and the NMOS transistor are included. A circuit portion including the transistor 61 constitutes a tristate (three state) buffer circuit 62. In addition, a resonance circuit 66 or an LSI tester (not shown in FIG. 5) including a crystal resonator 63 and two shunt capacitors 64 and 65 is selectively connected to the external circuit connection terminals 50 and 51.

  The operation of this oscillation circuit is as follows.

  During normal operation of the oscillation circuit, the resonance circuit 66 is externally connected to the external circuit connection terminals 50 and 51, and a low level (L) enable (EN) signal is input to the test enable terminal 56. At this time, the tristate buffer circuit 62 is brought into an operation stop state by the supply of the low level enable signal, and the circuit portion including the first inverter 53, the negative feedback resistor 54, and the resonance circuit 66 is in resonance with the resonance circuit 66. The oscillation circuit generates a clock having a frequency corresponding to the frequency, and the clock generated from the oscillation circuit is supplied into the system LSI in a state where the polarity is inverted through the second inverter 55.

On the other hand, in a high-speed operation test of the oscillation circuit, an LSI tester is externally connected to the external circuit connection terminals 50 and 51, and a high level (H) enable (EN) signal is input to the test enable terminal 56. At this time, the LSI tester generates a high-speed clock having a frequency of several hundreds of MHz, and the tri-state buffer circuit 62 is activated by the supply of a high-level enable signal. Therefore, the high-speed clock output from the LSI tester is Some are supplied to the system LSI through the first inverter 53 and the second inverter 55, and some are supplied to the system LSI by driving the operating tristate buffer circuit 62. Since driving by the circuit 62 is dominant, a high-speed clock is supplied into the system LSI at a relatively high level, and a high-speed operation test of the system LSI can be performed.
JP-A-6-85535

  The oscillation circuit disclosed in Japanese Patent Application Laid-Open No. 6-85535 is provided with a high-speed clock driving capability enhancement means including a tri-state buffer circuit 62, so that a high-level high-speed clock is supplied into the system LSI. Although the operation test can be performed effectively, it comprises a tri-state buffer circuit 62, in particular, a third inverter 57, a NAND circuit 58, a NOR circuit 59, a PMOS transistor 60, and an NMOS transistor 61 as high-speed clock drive capability enhancing means. Since the tri-state buffer circuit 62 is provided, a plurality of circuits and circuit elements necessary for configuring the tri-state buffer circuit 62 are required, and not only the circuit scale of the oscillation circuit increases, The power consumption of the oscillation circuit will also increase.

  In addition, the oscillation circuit disclosed in Japanese Patent Laid-Open No. 6-85535 is used as a path for supplying a high-speed clock output from the LSI tester into the system LSI during a high-speed operation test of the system LSI to which the LSI tester is externally connected. A path to be supplied into the system LSI through the first inverter 53 and the second inverter 55 and a path to be supplied into the system LSI by driving the operating tristate buffer circuit 62 are formed in parallel. When the clock is transmitted, the circuit configuration in each path is different, so the phase of the high-speed clock may differ when the high-speed clock that passes through these paths is supplied into the system LSI. At that time, a stable high-speed clock cannot be supplied into the system LSI. Time, are those which do not always be a high-speed operation test by the LSI tester.

  The present invention has been made in view of such a technical background, and an object of the present invention is to configure a high-speed clock driving capability enhancing means for supplying a high-speed clock in a system LSI with a small number of circuits and circuit elements, and to reduce the circuit scale. An object of the present invention is to provide an oscillation circuit that can achieve power consumption in consideration of the environment without being increased.

  To achieve the above object, an oscillation circuit according to the present invention is connected to a system LSI and first and second external circuit connection terminals to which a resonance circuit or LSI tester including a crystal resonator is selectively connected. A first series connection circuit of an internal connection terminal, a first transmission circuit and a first inverter connected between the first and second external circuit connection terminals, and a negative feedback resistor connected in parallel to the first series connection circuit A second transmission circuit connected between the output terminal of the first inverter and the internal connection terminal, a second series connection circuit of the second inverter, and a second connection circuit connected between the first external circuit connection terminal and the internal connection terminal. 3 transmission circuit and a third series connection circuit of a third inverter, and the first to third transmission circuits are supplied with a controllable complementary test enable signal at the gate. The polarity of the complementary test enable signal supplied to the first and second transmission circuits is opposite to the polarity of the complementary test enable signal supplied to the third transmission circuit. The first means is provided.

  In order to achieve the above object, an oscillation circuit according to the present invention is connected to a system LSI and first and second external circuit connection terminals to which a resonance circuit or an LSI tester that selectively includes a crystal resonator is externally connected. A first serial connection circuit of a first transmission circuit and a first inverter connected between the internal connection terminal, the first and second external connection circuit connection terminals, and the first serial connection circuit connected in parallel A negative feedback resistor; a second series connection circuit of a second transmission circuit and a second inverter connected between the output terminal of the first inverter circuit and the internal connection terminal; and an output terminal of the first inverter and the internal connection terminal. And a third series connection circuit of a third transmission circuit and a third inverter connected to each other, wherein the first to third transmission circuits each have a complementary test rice that can be controlled by a gate. And the polarity of the complementary test enable signal supplied to the first transmission circuit and the polarity of the complementary test enable signal supplied to the third transmission circuit. Comprises second means having opposite polarities.

  As described above, according to the oscillation circuit of the present invention, the high-speed clock driving capability enhancing means for supplying the high-speed clock into the system LSI is used, and the high-speed clock driving capability enhancing means is used as a circuit such as a logic circuit. And the number of circuit elements such as transistors constituting the circuit are small, so the high-speed clock supplied from the LSI tester can be used in the system LSI in a stable state at a high level during the high-speed operation test using the LSI tester. The high-speed operation test can be performed at all times, and the circuit scale of the oscillation circuit is not increased, the environment is considered, and the power consumption of the oscillation circuit can be reduced. is there.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 and FIG. 2 relate to the first embodiment of the oscillation circuit according to the present invention, and are circuit diagrams showing the configuration of the main part thereof. FIG. 1 shows that a resonance circuit is externally connected between external circuit connection terminals. FIG. 2 shows a state when the LSI tester is externally connected between the external circuit connection terminals.

  1 and 2, the oscillation circuit 1 includes a first inverter 2, a negative feedback resistor 3, a first transmission circuit 4, a second inverter 5, a second transmission circuit 6, a third inverter 7, A third transmission circuit 8, a first external circuit connection terminal 9, a second external circuit connection terminal 10, an output terminal 11, and a complementary test enable signal generation circuit 12 are formed. It is integrated with the system LSI 13 to be connected. As a circuit externally connected to the oscillation circuit 1, the resonance circuit 14 is selectively externally connected to the first and second external circuit connection terminals 9 and 10 (FIG. 1), and the LSI tester 15 is connected to the first and second external circuits. 2 Externally connected to the external circuit connection terminals 9 and 10 selectively.

  In this case, the first transmission circuit 4 includes a PMOS transistor 4 (1) and an NMOS transistor 4 (2) connected in parallel, and the second transmission circuit 6 includes a PMOS transistor 6 (1) and an NMOS transistor connected in parallel. 6 (2), and the third transmission circuit 8 includes a PMOS transistor 8 (1) and a MOS transistor 8 (2) connected in parallel. The complementary test enable signal generation circuit 12 includes a test enable signal input terminal 12 (1), a fourth inverter 12 (2), an in-phase test enable signal output terminal 12 (3), and an inverted test enable signal output terminal 12 ( 4). The resonance circuit 14 includes a crystal resonator 14 (1), a first shunt capacitor 14 (2), and a second shunt capacitor 14 (3).

  The first inverter 2 and the first transmission circuit 4 are connected in series to form a first series connection circuit, and the negative feedback resistor 3 is connected in parallel to the first series connection circuit. One end (input end) is connected to the first external circuit connection terminal 9, and the other end (output end) of the first series connection circuit is connected to the second external circuit connection terminal 10. The second inverter 5 and the second transmission circuit 6 are connected in series to form a second series connection circuit, and one end (input end) of the second series connection circuit is connected to the second external circuit connection terminal 10 in the second series connection. The other end (output end) of the circuit is connected to the output terminal 11. The third inverter 7 and the third transmission circuit 8 are connected in series to form a third series connection circuit, and one end (input end) of the third series connection circuit is connected to the first external circuit connection terminal 9 in the third series connection. The other end (output end) of the circuit is connected to the output terminal 11. In the complementary test enable signal generation circuit 12, the test enable signal input terminal 12 (1) is directly connected to the in-phase test enable signal output terminal 12 (3) and through the fourth inverter 12 (2). Inverted test enable signal output terminal 12 (4) is connected.

  Further, although not shown in FIGS. 1 and 2, the gates of the PMOS transistors 4 (1) and 6 (1) and the NMOS transistor 8 (2) are connected to the test enable signal input terminal 12 (1). The gates of the NMOS transistors 4 (2), 6 (2) and the PMOS transistor 8 (1) are connected to the inverted test enable signal output terminal 12 (4). The resonance circuit 14 has one end of the crystal resonator 14 (1) connected to the first external circuit connection terminal 9 and grounded through the first shunt capacitor 14 (2). Are connected to the second external circuit connection terminal 10 and grounded through the second shunt capacitor 14 (3).

  The oscillation circuit according to the first embodiment having the above configuration operates as follows.

  During normal operation of this oscillation circuit, as shown in FIG. 1, a resonance circuit 14 is connected between the first external circuit connection terminal 9 and the second external circuit connection terminal 10, and the complementary test enable signal generation circuit 12 A high level (H) test enable (TE) signal is supplied to the test enable signal input terminal 12 (1). During this normal operation, the high level test enable signal output from the in-phase test enable signal output terminal 12 (3) is supplied to the PMOS transistors 4 (1) and 6 (1) of the first and second transmission circuits 4 and 6, respectively. ) And the NMOS transistor 8 (2) of the third transmission circuit 8, and the low level (L) inverted test enable (TEN) signal output from the inverted test enable signal output terminal 12 (4) is supplied. The NMOS transistors 4 (2), 6 (2) of the first and second transmission circuits 4 and 6 and the PMOS transistor 8 (1) of the third transmission circuit 8 are supplied to the first and second transmission circuits 4 and 6, respectively. 6 are turned on, and the third transmission circuit 8 is turned off.

  In the first series connection circuit composed of the first transmission circuit 4 and the first inverter 2 in the on state, the negative feedback resistor 3 and the resonance circuit 14 are connected to the feedback path. It oscillates at a frequency that depends on and generates a normal-speed clock. The normal speed clock is input to the second inverter 5 through the second transmission circuit 6 in the ON state, and the clock inverted and output from the second inverter 5 is supplied to the system LSI 13 through the output terminal 11. At this time, even if the normal speed clock generated in the first series connection circuit composed of the first transmission circuit 4 and the first inverter 2 is supplied to the third series connection circuit composed of the third transmission circuit 8 and the third inverter 7. At this time, the third transmission circuit 8 is in the OFF state, so that the normal speed clock is not supplied from the third series connection circuit to the system LSI 13 through the output terminal 11, thereby stabilizing the system LSI 13. In this state, a normal speed clock can be supplied.

  Further, at the time of a high-speed operation test by the LSI tester 15 of this oscillation circuit, as shown in FIG. 2, the LSI tester 15 is connected between the first external circuit connection terminal 9 and the second external circuit connection terminal 10 so that the complementary test is performed. A low level (L) test enable (TEN) signal is supplied to the test enable signal input terminal 12 (1) of the enable signal generation circuit 12. In this high-speed operation test, the low-level test enable signal output from the common-mode test enable signal output terminal 12 (3) is supplied to the PMOS transistors 4 (1) and 6 (1) of the first and second transmission circuits 4 and 6, respectively. 1) and a high level (H) inverted test enable (TEN) signal supplied to the NMOS transistor 8 (2) of the third transmission circuit 8 and output from the inverted test enable signal output terminal 12 (4), respectively. Are supplied to the NMOS transistors 4 (2), 6 (2) of the first and second transmission circuits 4, 6 and the PMOS transistor 8 (1) of the third transmission circuit 8, respectively, thereby providing the first and second transmission circuits. 4 and 6 are turned off, and the third transmission circuit 8 is turned on. It made.

  The LSI tester 15 externally connected between the first external circuit connection terminal 9 and the second external circuit connection terminal 10 during the high-speed operation test generates a high-speed clock and passes through the first and second external circuit connection terminals 9 and 10. A high-speed clock is supplied to the oscillation circuit 1. At this time, since the third transmission circuit 8 is in an ON state, the third series connection circuit including the third transmission circuit 8 and the third inverter 7 is changed from the first external circuit connection terminal 9 to the third series connection circuit. The supplied high-speed clock is inverted by the third inverter 7 and then supplied to the system LSI 13 through the output terminal 11. On the other hand, in the first series connection circuit including the first transmission circuit 4 and the first inverter 2, the first transmission circuit 4 is in the OFF state, and the second transmission circuit 6 and the second inverter 5 are the second. Since the second transmission circuit 6 is also in the OFF state in the series connection circuit, even if the high-speed clock is supplied to the first series connection circuit and the second series connection circuit, the first transmission circuit 4 and the second transmission circuit 6, the high-speed clock is not supplied from the second series connection circuit to the system LSI 13 through the output terminal 11, so that a high-level high-speed clock can be supplied to the system LSI 13 in a stable state. .

  Next, FIG. 3 and FIG. 4 relate to the second embodiment of the oscillation circuit according to the present invention, and are circuit diagrams showing the configuration of the main part thereof. FIG. FIG. 4 shows a state when the LSI tester is externally connected between the external circuit connection terminals.

  The oscillation circuit 1 according to the second embodiment shown in FIGS. 3 and 4 (hereinafter referred to as the former circuit) and the oscillation circuit 1 according to the first embodiment shown in FIGS. Hereinafter, this is referred to as the latter circuit) in that the third transmission circuit 8 and the third series connection circuit composed of the third inverter 7 are connected at different points. A third series connection circuit composed of three transmission circuits 8 and a third inverter 7 is a first series connection circuit composed of the first transmission circuit 4 and the first inverter 2, and a second series composed of the second transmission circuit 6 and the second inverter 5. It is formed so as to bridge the connection circuit, that is, the third series connection circuit is connected in parallel to the series connection circuit of the first series connection circuit and the second series connection circuit. On the other hand, the former circuit is formed such that the third series connection circuit bridges only the second series connection circuit, that is, the third series connection circuit is connected in parallel to the second series connection circuit. However, there is no difference between the former circuit and the latter circuit in other configurations.

  For this reason, the components shown in FIGS. 3 and 4 are given the same reference numerals to the same components shown in FIGS. 1 and 2, and the configuration of the oscillation circuit 1 according to the second embodiment is described. Will not be described any further.

  The operation of the oscillation circuit 1 (the former circuit) according to the second embodiment having the above configuration is basically the same as the operation of the oscillation circuit 1 (the latter circuit) according to the first embodiment already described. The former circuit and the latter circuit have slightly different circuit configurations, and there are some differences in the operation. Therefore, even if the description is duplicated here, the operation of the former circuit will be described in detail. To do.

  During normal operation of this oscillation circuit, as shown in FIG. 3, a resonance circuit 14 is connected between the first external circuit connection terminal 9 and the second external circuit connection terminal 10, and the complementary test enable signal generation circuit 12 A high level (H) test enable (TE) signal is supplied to the test enable signal input terminal 12 (1). During this normal operation, the high level test enable signal output from the common-mode test enable signal output terminal 12 (3) is supplied to the PMOS transistors 4 (1), 6 of the first and second transmission circuits 4, 6. (1) and the low level (L) inverted test enable (TEN) supplied to the NMOS transistor 8 (2) of the third transmission circuit 8 and output from the inverted test enable signal output terminal 12 (4), respectively. Signals are supplied to the NMOS transistors 4 (2), 6 (2) of the first and second transmission circuits 4, 6 and the PMOS transistor 8 (1) of the third transmission circuit 8, respectively, whereby the first and second transmissions are transmitted. Circuits 4 and 6 are turned on and third transmission circuit 8 is turned off To become.

  In the first series connection circuit composed of the first transmission circuit 4 and the first inverter 2 in the on state, the negative feedback resistor 3 and the resonance circuit 14 are connected to the feedback path. It oscillates at a frequency that depends on and generates a normal-speed clock. The normal speed clock is input to the second inverter 5 through the second transmission circuit 6 in the ON state, and the clock inverted and output from the second inverter 5 is supplied to the system LSI 13 through the output terminal 11. At this time, even if the normal speed clock generated in the first series connection circuit composed of the first transmission circuit 4 and the first inverter 2 is supplied to the third series connection circuit composed of the third transmission circuit 8 and the third inverter 7. At this time, the third transmission circuit 8 is in the OFF state, so that the normal speed clock is not supplied from the third series connection circuit to the system LSI 13 through the output terminal 11, thereby stabilizing the system LSI 13. In this state, a normal speed clock can be supplied.

  In the high-speed operation test of the oscillation circuit by the LSI tester 15, as shown in FIG. 4, the LSI tester 15 is connected between the first external circuit connection terminal 9 and the second external circuit connection terminal 10, so that the complementary test is performed. A low level (L) test enable (TEN) signal is supplied to the test enable signal input terminal 12 (1) of the enable signal generation circuit 12. In this high-speed operation test, the low-level test enable signal output from the common-mode test enable signal output terminal 12 (3) is supplied to the PMOS transistors 4 (1) and 6 (1) of the first and second transmission circuits 4 and 6, respectively. 1) and a high level (H) inverted test enable (TEN) signal supplied to the NMOS transistor 8 (2) of the third transmission circuit 8 and output from the inverted test enable signal output terminal 12 (4), respectively. Are supplied to the NMOS transistors 4 (2), 6 (2) of the first and second transmission circuits 4, 6 and the PMOS transistor 8 (1) of the third transmission circuit 8, respectively, thereby providing the first and second transmission circuits. 4 and 6 are turned off, and the third transmission circuit 8 is turned on. It made.

  The LSI tester 15 externally connected between the first external circuit connection terminal 9 and the second external circuit connection terminal 10 during the high-speed operation test generates a high-speed clock and passes through the first and second external circuit connection terminals 9 and 10. A high-speed clock is supplied to the oscillation circuit 1. At this time, since the third transmission circuit 8 is in the ON state, the third series connection circuit including the third transmission circuit 8 and the third inverter 7 is connected to the third series connection circuit through the second external circuit connection terminal 10. The supplied high-speed clock is inverted by the third inverter 7 and then supplied to the system LSI 13 through the output terminal 11. On the other hand, in the first series connection circuit including the first transmission circuit 4 and the first inverter 2, the first transmission circuit 4 is in the OFF state, and the second transmission circuit 6 and the second inverter 5 are the second. Since the second transmission circuit 6 is also in the OFF state in the series connection circuit, even if the high-speed clock is supplied to the first series connection circuit and the second series connection circuit, the first transmission circuit 4 and the second transmission circuit 6, the high-speed clock is not supplied from the second series connection circuit to the system LSI 13 through the output terminal 11, so that a high-level high-speed clock can be supplied to the system LSI 13 in a stable state. .

FIG. 2 is a circuit diagram showing a main configuration of the oscillation circuit according to the first embodiment of the present invention, and shows a state when a resonance circuit is externally connected between external circuit connection terminals. FIG. 2 is a circuit diagram showing a main configuration of the oscillation circuit according to the first embodiment of the present invention, and shows a state when external connection is made between LSI circuit testers between external circuit connection terminals. FIG. 7 is a circuit diagram showing a main configuration of an oscillation circuit according to a second embodiment of the present invention, and shows a state when a resonance circuit is externally connected between external circuit connection terminals. FIG. 7 is a circuit diagram showing a main configuration of an oscillation circuit according to a second embodiment of the present invention, and shows a state when an LSI tester is externally connected between external circuit connection terminals. FIG. 2 is a circuit diagram showing a main part configuration of a known oscillation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Oscillation circuit 2 1st inverter 3 Negative feedback resistance 4 1st transmission circuit 4 (1), 6 (1), 8 (1) PMOS transistor 4 (2), 6 (2), 8 (2) NMOS transistor 5 1st 2 inverter 6 second transmission circuit 7 third inverter 8 third transmission circuit 9 first external circuit connection terminal 10 second external circuit connection terminal 11 output terminal 12 complementary test enable signal generation circuit 12 (1) test enable signal input Terminal 12 (2) Fourth inverter 12 (3) In-phase test enable signal output terminal 12 (4) Grounded through the inverted test enable signal output terminal, and the other end of the crystal unit 14 (1) is the second external circuit. Connected to the connection terminal 10 and the second shunt capacitor 14 (3)
13 System LSI
14 Resonant circuit 14 (1) Crystal resonator 14 (2) First shunt capacitor 14 (3) Second shunt capacitor 15 LSI tester

Claims (4)

First and second external circuit connection terminals to which a resonance circuit or LSI tester including a crystal resonator is selectively connected externally, an internal connection terminal connected to a system LSI, and the first and second external circuit connection terminals A first series connection circuit of a first transmission circuit and a first inverter connected in between; a negative feedback resistor connected in parallel to the first series connection circuit; an output terminal of the first inverter and the internal connection terminal A second serial connection circuit of a second transmission circuit and a second inverter connected between each other, and a third transmission circuit and a third inverter connected between the first external circuit connection terminal and the internal connection terminal. The first to third transmission circuits each include a PMOS transistor to which a controllable complementary test enable signal is supplied to a gate. The polarity of the complementary test enable signal supplied to the first and second transmission circuits and the polarity of the complementary test enable signal supplied to the third transmission circuit are opposite to each other. An oscillation circuit characterized by being. The oscillation circuit according to claim 1, wherein the oscillation circuit is mounted on a semiconductor integrated circuit. First and second external circuit connection terminals to which a resonant circuit or LSI tester including a crystal resonator is selectively connected externally, an internal connection terminal connected to a system LSI, and the first and second external connection circuits A first series connection circuit of a first transmission circuit and a first inverter connected between the terminals, a negative feedback resistor connected in parallel to the first series connection circuit, an output terminal of the first inverter, and the internal connection A second transmission circuit connected between terminals and a second series connection circuit of the second inverter; a third transmission circuit connected between the output terminal of the first inverter and the internal connection terminal; and a third inverter. A third serial connection circuit, and the first to third transmission circuits each include a PMOS transistor to which a controllable complementary test enable signal is supplied to a gate. The polarity of the complementary test enable signal supplied to the first and second transmission circuits is opposite to the polarity of the complementary test enable signal supplied to the third transmission circuit. An oscillation circuit characterized by being. The oscillation circuit according to claim 3, wherein the oscillation circuit is mounted on a semiconductor integrated circuit.

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