JP2007074160A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To expand an operation environmental range of a synchronous type circuit which latches input/output data of a logic circuit in synchronism with a clock. <P>SOLUTION: A semiconductor device is provided with a variable delay circuit 10 which delays output data of the logic circuit 5 between the logic circuit 5 and an output latch circuit 2 and equipped with a control circuit 6 which controls a delay quantity of the variable delay circuit 109 based upon an observed operation environment. As the operation environment, temperature, delay of a circuit element accompanying process variation and a source voltage, etc. are observed. Instead of the variable delay circuit 10, a variable delay circuit may be provided which delays a clock CK of the latch circuit 2. One operation range is permitted for each of a plurality delay quantities that the variable delay circuit 10 employs, and the semiconductor device operates over all the operation ranges and then has the wide operation range. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a latch circuit that latches input / output data of a logic circuit in synchronization with a clock, and more particularly to a semiconductor device in which a timing margin of the latch circuit is ensured over a wide range of operating environments.

  In a semiconductor device that performs a logical operation, a synchronous circuit that latches input data and output data of a logic circuit by a latch circuit in synchronization with a clock is widely used.

  Conventionally, the timing adjustment of such a synchronous circuit is performed by analyzing the hold margin and the setup margin of the latch circuit using a static timing analysis (STA) tool, and ensuring that these margins are secured. This is done by inserting a buffer circuit to adjust the data delay time of each circuit. Hereinafter, timing adjustment of a semiconductor circuit using a static timing analysis tool will be described.

  FIG. 7 is a circuit diagram of a conventional logic circuit and its peripheral circuits, showing a circuit including the logic circuit and a latch circuit for latching input / output data thereof. Referring to FIG. 7, input data Din input to input terminal D of latch circuit 1 is latched by latch circuit 1 in synchronization with clock CK 1 and output from output terminal Q of latch circuit 1. The output data of the latch circuit 1 is input to the logic circuit 5, and the logical operation result is output from the logic circuit 5. The output data of the logic circuit 5 is applied to the input terminal D of the latch circuit 2 through the delay circuit 3. The data D2 applied to the input terminal D of the latch circuit 2 is latched by the latch circuit 2 in synchronization with the clock CK2, and is output as a logical operation result from the output terminal Q of the latch circuit 2.

  A conventional semiconductor device having such a logic circuit tentatively lays out circuit elements, performs timing analysis on the tentatively laid out circuit using a static tamming analysis tool, and corrects until all timings are satisfied. It is designed by that.

  FIG. 8 is a timing chart of a conventional logic circuit, showing the timing at which the latch circuit 2 latches the output data of the logic circuit 5. In FIG. 8, D2 represents data applied to the input terminal D of the latch circuit 2.

  Referring to FIG. 8, data D1 (input data Din) latched in latch circuit 1 at rising time t0 of clock CK1 is between latch circuit 1, logic circuit 5, delay circuit 3, and latch circuit 1 and latch circuit 2. After the delay time td due to the wiring of elapses, the calculation result reaches the input terminal D of the latch circuit 2 as data D2. This delay time td differs depending on factors that affect the operation speed of these circuits 1, 2, 3, and 5 and the contents of the logic operation of the logic circuit 5. This is because the operation speed of the circuit directly affects the delay time of the circuit, and the difference in logic operation changes the paths P1 to P4 of data propagating in the logic circuit 5.

  The static timing analysis tool calculates the delay time td of the data D2 under the Best condition that is the operating environment in which the operation speed of the circuit is the highest and the worst condition in which the operation speed is the lowest, and the rising time t1 of the clock CK2 (Latch timing). Then, it is analyzed whether or not the data D2 satisfies the latch timing condition, that is, the setup time ts and the hold time th.

  In this timing analysis, under the Best condition, the shortest path P1 of the logic circuit that minimizes the delay time td is selected. At this time, a hold error is a problem. On the other hand, in the worst condition, the longest path P4 of the logic circuit having the maximum delay time td is selected. At this time, a setup error is a problem.

When a hold error occurs, a delay element is added to the delay circuit 3 that delays the output data of the logic circuit 5 with reference to FIG. On the other hand, when a setup error occurs, the delay element of the delay circuit 3 is reduced to shorten the delay time, or a delay element is added to the clock delay circuit 4-2 that delays the clock CK2, and the clock CK1 and the clock CK2 Eliminate the problem by increasing the time interval. By repeating such timing analysis and correction, the delay times of the delay circuit 3 and the clock delay circuit 4-2 are determined so as to satisfy the timing condition. (See, for example, Patent Document 1 for data delaying; see, for example, Patent Document 2 for delaying a clock.)
The operation range of the semiconductor device designed in this way will be described.

  FIG. 9 is an explanatory diagram of the operation range of the conventional logic circuit, and shows the range of the operation environment in which the setup margin and the hold margin of the latch circuit 2 are secured and the output data of the logic circuit is correctly latched in the latch circuit 2. Yes. The vertical axis represents operating conditions that affect the operating environment, that is, the operating speed of the latch circuits 1 and 2 and the logic circuit 5 of the semiconductor device, such as temperature, power supply voltage, and manufacturing process of the semiconductor device. In the present specification, the condition for increasing the operation speed (downward in the figure) is represented as the Best direction, and the condition for increasing the operation speed (upper in the figure) is represented as the Worst direction.

  9 represent the rise and fall times of the data D2min (shortest path data) that has passed through the shortest path P1 of the logic circuit 5. Straight lines C and D represent the rise and fall times of the data D2max (longest path data) via the longest path P1 of the logic circuit 5. These rising and falling times move in a direction in which the delay increases as the operating environment changes from the Best direction to the Worst direction, as shown by the straight lines A to D. Note that the shortest path data D2min and the longest path data D2max differ in the number of series connection of circuit elements involved in the delay, so that the delay change caused by the operating environment is generally different and has different slopes as shown in FIG.

In the conventional semiconductor device described above, the longest path data D2max satisfies the setup time ts when the operating environment is in the Best direction from Condition 1 as indicated by the straight line C in FIG. On the other hand, as indicated by the straight line B, the shortest path data D2min satisfies the hold time th when the operating environment is in the worst direction from condition 2. Therefore, this semiconductor device operates correctly without causing a setup error and a hold error between condition 1 and condition 2.
JP 2003-162556 A JP 2004-185466 A

  A conventional semiconductor device designed using the above-described static timing analysis tool is corrected at the design stage, and cannot be applied to a semiconductor device already manufactured and corrected. For example, when the manufacturing process conditions, the use environment temperature, or the power supply voltage is out of the design standard, it cannot be corrected so as to operate normally even under these conditions. For this reason, it has been necessary to design the manufacturing process conditions, operating environment temperature, and power supply voltage in advance with a sufficient design margin, and there is a problem that the operation guarantee range for these conditions is narrowed.

  Further, in the conventional semiconductor device, when designing using the static timing analysis tool, when the correction under the worst condition does not satisfy the timing under the best condition, or conversely, the correction under the best condition causes the timing under the worst condition to be corrected. There are many cases where it is not satisfied, and there is a problem that the convergence of the static timing analysis is slow or may not converge.

  The present invention provides a semiconductor device capable of correcting the timing in accordance with the operating environment when the semiconductor device is manufactured or designed using a static timing analysis tool. An object of the present invention is to provide a semiconductor device in which static timing analysis at the time of design converges quickly.

  In order to solve the above problems, a semiconductor device according to a first configuration of the present invention relates to a semiconductor device including a logic circuit that inputs output data of a first latch circuit and outputs an operation result to a second latch circuit. A variable delay circuit that delays the output data of the circuit and outputs the delayed output data to the second latch circuit, and the output data of the logic circuit is correctly latched under the operating environment indicated by the input observation data of the operating environment And a control circuit for controlling the delay time of the variable delay circuit.

  In the first configuration, the delay time of the output data of the logic circuit is adjusted by controlling the delay time of the variable delay circuit by the control circuit. Therefore, the timing adjustment can be performed by changing the delay time of the output data of the logic circuit after manufacturing the process step of the semiconductor device, for example, after the end of the wafer step.

  As described above, the timing adjustment can be performed by changing the delay time of the output data of the logic circuit after the manufacture, so that the operation speed of the circuit element due to the process condition change, the operating environment temperature, the power supply voltage, etc. Even if there are fluctuations in the circuit operating speed based on factors found after manufacturing, such as fluctuations in the operating environment, it is easy to change this to meet the timing conditions. For this reason, the margin of the design standard in the design stage of the semiconductor device can be reduced.

  In addition, since a variable delay circuit is used for timing adjustment, static timing analysis can be performed independently for each different delay time, and the operation range for all delay times can be set as the operation range of the semiconductor device. . Therefore, the operation range is greatly expanded as compared with the conventional semiconductor device in which the delay time is fixed to one. In addition, since the operating range for the delay time of one path can be set narrower than the operating range of the semiconductor device, the convergence of the static timing analysis is improved. It is possible to avoid a situation where the hold time is incompatible.

  The control circuit receives the observation data of the operating environment that affects the operation speed of the circuit inside the semiconductor device, and the control device correctly latches the output data of the logic circuit under the operating environment displayed by this observation data. The delay time of the variable delay circuit is controlled. For this control, for example, each delay time that can be taken by the variable delay circuit and an operating environment range in which the output data of the logic circuit is correctly latched under each delay time are set in advance, and the operation indicated by the observation data This can be realized by comparing the environment and the range of the set operating environment and controlling the variable delay circuit so as to take a delay time in which the output data of the logic circuit is correctly latched.

  This variable delay circuit may be any circuit as long as the control circuit can control the delay time. For example, the variable delay circuit may be composed of a plurality of different delay circuits, and one of the delay circuits may be selected using a selector.

  As described above, the control device controls the delay time of the variable delay circuit based on the observation data of the operating environment. In other words, when the operating environment deviates from the allowable operating range with a certain delay time, another delay time including the operating environment after the departure in the operating range is selected, and this other delay time is taken. Control the variable delay circuit. Therefore, even if the operating range allowed for one delay time is narrow, the operating range of the semiconductor device of the first configuration is very wide.

  The observation data input to the control circuit described above is an observation of the operating environment that affects the operating speed of the circuit inside the semiconductor device, particularly the operating environment that affects the operating speed of the logic circuit or the first or second latch circuit. It is data. Such operating environments include the chip temperature of the semiconductor device, the package temperature and the ambient temperature, and the temperature of the connection point between the lead of the semiconductor device and the circuit board. Further, the power supply voltage supplied to the semiconductor device or the power supply voltage actually applied to the logic circuit 5 can be included. Furthermore, the process conditions for manufacturing the circuit of the semiconductor device can be one of operating environments in which the delay of the circuit element is varied.

  Of these, the temperature is converted into an electric signal by a thermometer or a temperature measuring circuit, and this electric signal is input to the control circuit as observation data. A thermometer or a temperature measurement circuit can be provided in the chip. The process condition is observed by monitoring a monitor circuit (for example, a circuit for observing the oscillation frequency of the ring oscillator) that measures the gate delay incorporated in the semiconductor device, and the observation data (for example, a voltage corresponding to the oscillation frequency). ) Is input to the control circuit.

  The variable delay circuit described above can be inserted at an arbitrary position between the first latch circuit and the second latch circuit. However, since the logic circuit may be related to a signal transmitted from another latch circuit, the timing of the other latch circuit may have to be changed if it is inserted before the output of the logic circuit. Further, depending on the path in the logic circuit, another timing error may occur due to a change in the delay time. In these cases, further analysis and correction are required. For this reason, the variable delay circuit is preferably inserted after the output of the logic circuit.

  In the second configuration of the present invention, a variable delay circuit for delaying the clock of the second latch circuit is provided.

  In the second configuration, the setup error and the hold error are corrected by delaying the second clock that determines the latch time of the second latch circuit instead of delaying the output data of the logic circuit. The operation of the second configuration is substantially the same except that the timing adjustment is performed by delaying the latch time of the second latch circuit instead of delaying the output data in the first configuration and adjusting the timing. .

  In the present configuration, in particular, when a plurality of second latch circuits driven by one second clock are provided corresponding to each of the plurality of logic circuits, one variable delay circuit that delays the second clock. There is an advantage that it is sufficient to provide. In the first configuration, a variable delay circuit must be provided for each logic circuit.

  Further, a variable logic circuit that delays output data of the logic circuit and a variable delay circuit that delays the clock of the second latch circuit may be provided. In this configuration, timing adjustment is performed using two of the output data of the logic circuit and the clock of the second latch circuit as variables, so that a wider operating range can be secured.

  According to the present invention, since timing adjustment is possible after manufacturing a semiconductor device, a semiconductor device that operates in a wide operating environment and that converges quickly in a design using a static timing analysis tool is provided. can do.

  FIG. 1 is a circuit diagram of a first embodiment of the present invention, showing a logic circuit and its peripheral circuits. Referring to FIG. 1, a first embodiment of the present invention relates to a semiconductor device that adjusts a delay of output data of a logic circuit 5 using a variable delay circuit 10.

  In the first embodiment, two latch circuits 1 and 2 composed of D flip-flops that constitute a latch circuit 1 that latches input data of the logic circuit 5 and a latch circuit 2 that latches output data of the logic circuit 5. Is provided.

  The latch circuit 1 latches the input data Din applied to the input terminal D in synchronization with the rising edge of the clock CK1, and outputs the latched data from the output terminal Q to the logic circuit 5. The logic circuit 5 is composed of a multi-stage logic circuit, and outputs the result of the logic operation to the variable delay circuit 10 as output data. The variable delay circuit 10 includes a plurality of delay circuits 3-1 and 3-2 and a selector 8 that selects one of the outputs and outputs the selected output to the latch circuit 2. The latch circuit 2 latches the output of the selector 8 (that is, the output data of the logic circuit 5 delayed by one of the delay circuits 3-1 and 3-2) in synchronization with the rising edge of the clock CK2. The data D2 latched by the latch circuit 2 is output from the output terminal D of the latch circuit 2 as output data Dout.

  The clocks CK1 and CK2 of the latch circuits 1 and 2 are supplied from the common clock CK via the clock delay circuit 4-1 and the clock delay circuit 4-2, respectively. The clock delay circuits 4-1 and 4-2 are provided for timing adjustment of the clock CK1 and the clock CK2.

  The control circuit 6 determines the delay time that the variable delay circuit 10 can take (that is, the delay time of the variable delay circuit 10 when the selector 8 selects the delay circuit 3-1 or the delay circuit 3-2) and the delay time. The range of operating environments allowed when the variable delay circuit 10 is set (that is, the range of operating environments that are correctly latched) is stored in a table in advance.

  Then, the table is searched using the operating environment indicated by the input observation data Dob, and the delay time of the variable delay circuit that is correctly latched under this operating environment is extracted.

  Next, the extracted delay time is compared with the current delay time of the variable delay circuit 8, and when one of the extracted delay times is equal to the currently selected delay time, the selection of the selector 8 is maintained as it is. On the other hand, if all of the extracted delay times do not match the currently selected delay time, the selector 8 is switched to select one of the extracted delay times.

  A signal instructing switching of the selector output from the control circuit 6 is output to the selector 8 in synchronization with the clock CK by the D flip-flop 7. The clock of the flip-flop 7 is input later than the clock CK through the clock delay circuit 4-3. The clock delay circuit 4-3 adjusts the latch timing of the latch circuit 2 and the switching timing of the selector 8.

  The control circuit 6 described above stores in advance a relationship between the delay time and the allowable operating environment range in a table. Instead of this table, it can also be stored as a reference voltage for comparison in a voltage generation circuit (for example, a programmable voltage generation circuit) or a voltage comparison circuit. For example, the observation data input as a voltage is compared with a plurality of internally generated reference voltages, and the range of the observation data is classified by the reference voltage.

  A circuit for temperature observation is formed on the chip of the semiconductor device according to the present embodiment, and the chip temperature is input to the control circuit 6 as observation data Dob of a voltage or digital signal. If necessary, observation data of the temperature of other parts, for example, the temperature of the junction between the circuit board and the lead, the package temperature, or the atmospheric temperature can be input from outside the chip.

  Further, the chip of the semiconductor device according to the present embodiment can be provided with a monitor circuit including a ring oscillator and a measurement circuit for the transmission frequency. This monitor circuit observes the delay time of the gate constituting the ring transmitter from the observation data of the transmission frequency of the ring transmitter. Based on the delay time of the gate, the delay times of the latch circuits 1 and 2, the logic circuit 5, the variable delay circuit 10, and the clock delay circuits 4-1 to 4-3 of the semiconductor device actually manufactured through the wafer process are obtained. calculate. In consideration of the delay time of the circuit elements, the control circuit 6 reflects the timing of the operating environment, for example, in a table storing the operating environment, and adjusts the timing. As a result, it is possible to adjust so as to absorb the timing shift caused by the variation of the delay time of the circuit element caused by the variation of the process condition. For this reason, a manufacturing yield improves.

  Hereinafter, the present invention will be described in more detail with reference to the manufacturing process of the semiconductor device according to the first embodiment.

  FIG. 2 is a timing chart according to the first embodiment of the present invention, showing the timing at which the latch circuit 2 latches the output data of the logic circuit 5. Data D2 (1) min, D2 (1) max, D2 (2) min, and D2 (2) max in the figure represent data input to the input terminal D of the latch circuit 2. Here, (1) and (2) represent data passing through the delay circuit 3-1 having the minimum delay time or the delay circuit 3-2 having the maximum delay time, respectively, constituting the variable delay circuit 10. Suffixes min and max represent data passing through the shortest path P1 and the longest path P4 of the logic circuit 5, respectively. Note that hatched portions of the data D2 (1) and D2 (2) represent data that the latch circuit 2 should latch at time t1.

  First, after the temporary layout of the semiconductor device, the setup margin and hold margin of the latch circuit 2 are analyzed using a static timing analysis tool, and the circuit design is corrected. This static timing analysis is performed according to the following procedure for the best condition and worst condition of the operating environment range required for the semiconductor device.

  First, the variable delay circuit 10 is corrected so that a setup error does not occur under worst conditions. Referring to the delay (2) in FIG. 2, when the delay circuit 3-2 having the maximum delay time is selected, the data D2 (2) max is latched via the longest path P4 of the logic circuit 5 under the worst condition. The delay time of the delay circuit 3-2 is corrected so that the setup time ts is secured. This correction is made, for example, by deleting the delay element constituting the delay circuit 3-2 or replacing the delay element constituting the delay circuit 3-2 with a buffer having a large driving capability. At this time, if the delay time of the delay circuit 3-2 cannot be further shortened, the delay time of the clock delay circuit 4-2 is increased.

  Next, the variable delay circuit 10 is corrected so that a hold error does not occur under the Best condition. Referring to delay (1) in FIG. 2, when the delay circuit 3-1 having the shortest delay time is selected, the latch of data D2 (1) min that passes through the shortest path P1 of the logic circuit 5 under the best condition. The delay time of the delay circuit 3-1 is corrected so that the hold time th is secured. This correction is made, for example, by inserting a gate serving as a delay element into the delay circuit 3-1.

  In the present embodiment, as will be described later, the environmental conditions (environmental ranges) for using the delay circuits 3-1 and 3-2 are set so as to partially overlap. For this reason, if the setup condition is satisfied under the worst condition, the timing of the best condition is satisfied. If the setup condition is satisfied under the worst condition, the timing of the best condition is satisfied. If the planned environmental condition cannot be satisfied by the two delay circuits 3-1 and 3-2, the entire range of the planned environmental conditions can be achieved by using the variable delay circuit 10 having more delay circuits. Cover.

As described above, the semiconductor device according to the present embodiment is designed in a narrow operating range for each of the plurality of delay circuits 3-1 and 3-2, and a wide range including these operating ranges is set as a design operating environment. It can be. For this reason, the convergence property of the static timing analysis is good, and a wide operation range of the semiconductor device is ensured.

The semiconductor device of this embodiment designed as described above is manufactured through a wafer process. Hereinafter, the latch timing and the operating environment of the semiconductor device manufactured in this way will be described.

  FIG. 3 is an explanatory diagram of the operation range of the logic circuit according to the first embodiment of the present invention, and represents the range of the operating environment in which the output data of the logic circuit 5 is correctly latched by the latch circuit 2. In FIG. 3, D2 (1) max and D2 (2) max pass through the longest path P4 of the logic circuit 5, and the delay circuit 3-1 having the minimum delay time and the delay circuit 3-2 having the maximum delay time, respectively. Represents the output data of the logic circuit 5 output to the latch circuit 2 via. In FIG. 3, D2 (1) min and D2 (2) min pass through the shortest path P1 of the logic circuit 5, respectively, and the delay circuit 3-1 having the minimum delay time and the delay circuit 3-2 having the maximum delay time, respectively. Represents the output data of the logic circuit 5 output through the above. For simplicity, FIG. 3 shows only the data that should be latched in the latch circuit 2 at time t1.

Referring to FIG. 3, the output data that has passed through longest path P4 of logic circuit 5 is input to input terminal D of latch circuit 2 as data D2 (1) max when passing through delay circuit 3-1 having the minimum delay time. When the signal passes through the delay circuit 3-2 having the maximum delay time, the data is input as data D2 (2) max later. In FIG. 3, straight lines C and G respectively indicate the rising edges of data D2 (1) max and data D2 (2) max, and straight lines D and H indicate the rising edges of data D2 (1) max and data D2 (2) max, respectively. Represents the fall time. The rise and fall times of the data D2 (1) max and the data D2 (2) max are faster as the operating environment is in the Best direction, and are later in the Worst direction. As described above, in the worst condition, that is, the condition 1, the setup time ts of data passing through the longest path P4 is a problem. The data D2 (1) max passing through the longest path P4 and passing through the delay circuit 3-1 having the minimum delay time satisfies the setup time in the condition 1 and the best direction. On the other hand, the setup time ts is insufficient for the data D2 (2) max passing through the delay circuit 3-2 having the maximum delay time. The data D2 (2) max satisfies the setup time ts when the operating environment is the condition 3 or the best direction. That is, the setup condition is satisfied in the best operating environment from condition 1 when the delay circuit 3-1 is used, and is satisfied in the best operating environment from condition 3 when the delay circuit 3-2 is used.

  In the Best condition, the hold time th of data passing through the shortest path P1 is a problem as described above. The data D2 (1) min passing through the delay circuit 3-1 having the minimum delay time via the shortest path satisfies the hold time ts in the condition 2 or the operating environment in the worst direction. On the other hand, the data D2 (2) min passing through the delay circuit 3-2 satisfies the hold time th until the condition 4. That is, the hold condition is satisfied in the worst operating environment from condition 2 when the delay circuit 3-1 is used, and is satisfied in the worst operating environment from condition 4 when the delay circuit 3-2 is used.

  In summary, when the delay circuit 3-1 having the minimum delay time is selected, the operation range is the range A (condition 1 to condition 2) shown in FIG. 3, and the delay circuit 3-2 having the maximum delay time is shown. When is selected, the operation range is a range B (condition 3 to condition 4) shown in FIG. Therefore, the operation range of the semiconductor device according to the present embodiment is a range including the range A and the range B (condition 1 to condition 4), and is expanded from the range A or the range B when only one delay circuit is used. .

  In the semiconductor device according to the present embodiment, one of the delay circuits 3-1 and 3-2 is selected according to the observation data Dob of the operating environment. The control circuit 6 compares the observation data Dob with values corresponding to the conditions 1 to 4, and if the delay circuit currently used, for example, the delay circuit 3-1, is in the usable operating environment A, the control circuit 6 delays as it is. Maintain use of circuit 3-1. On the other hand, when the observation data deviates from the operating environment A in the best direction, the delay circuit 3-1 is switched to the delay circuit 3-2 to reduce the delay time of the variable delay circuit 10. As a result, the operating range of the semiconductor device is changed to the operating range B.

  As described above, the semiconductor device after the manufacturing process can be switched automatically by changing the delay time of the variable delay circuit 10 according to the operating environment, so that the semiconductor device having a wide operating range can be obtained. Can be easily realized. In addition, it is possible to observe variations in the operating speed of circuit elements due to the manufacturing process, and use the results as one of the operating environments. Therefore, variations in the manufacturing process that must be expected at the design stage in static timing analysis. Can be made very small.

  In the semiconductor device of the present embodiment described above, with reference to FIG. 3, the delay circuits 3-1 and 3-2 of the variable delay circuit 10 are designed so that the operation range A and the operation range B partially overlap. Then, the control circuit 6 is provided with a hysteresis characteristic when the operating environment enters and exits the overlapping operating range (condition 3 to condition 2). That is, when the delay circuit 3-1 is selected, the condition 1 to the condition 3 is moved to the condition 3 to the condition 2, or when the delay circuit 3-1 is selected, the condition 3 to the condition 2 is selected. When moving to 1 to condition 3, the delay circuit 3-1 is maintained as it is. When the delay circuit 3-1 is selected in the condition 3 to the condition 2 and the process moves to the condition 2 to the condition 4, the delay circuit 3-1 is switched to the delay circuit 3-2. Similarly, when moving from condition 2 to condition 4 selecting delay circuit 3-2 to condition 3 to condition 2 or when selecting delay circuit 3-2, from condition 3 to condition 2 When moving from condition 2 to condition 4, the delay circuit 3-2 is maintained as it is. When the delay circuit 3-2 is selected in the condition 3 to the condition 2 and the process moves to the condition 1 to the condition 3, the delay circuit 3-2 is switched to the delay circuit 3-1. In this way, the switching of the delay circuits 3-1 and 3-2 is provided with a hysteresis characteristic, thereby preventing switching chattering in the vicinity of condition 2 and condition 3.

  The second embodiment of the present invention relates to a mode for switching the delay time of the clock CK of the second latch circuit 2. FIG. 4 is a circuit diagram of a logic circuit and its peripheral circuits according to the second embodiment of the present invention.

  Referring to FIG. 4, in the semiconductor device of the second embodiment, a delay circuit 3 having a fixed delay time is used instead of the variable delay circuit 10 of the semiconductor device of the first embodiment, and further, a second latch circuit is provided. Two clocks CK <b> 2 are supplied via the variable delay circuit 11. The variable delay circuit 11 is controlled by the same control circuit 6 as in the first embodiment.

  As in the first embodiment, the control circuit 6 sends a switching signal to the selector 9 of the variable delay circuit 11 based on the observation data Dob, and is variable by selecting one from the delay circuits 12-1 and 12-2. The delay time of the delay circuit 11 is switched. Note that the delay circuit 12-1 having the minimum delay time may be simply a wiring without providing a delay element such as a gate, as in the variable delay circuit 10 of the first embodiment. The flip-flop 13 is provided to synchronize the output of the variable delay circuit 11 with the clock CK.

  In designing the semiconductor device according to the present embodiment, static timing analysis is performed on a temporary layout.

  First, the clock CK2 passing through the delay circuit 12-2 having the maximum delay time is selected, and the delay circuit 3 is set so that the longest path data D2max via the longest path P4 of the logic circuit 5 does not generate a setup error under the worst condition. Correct it. At this time, if the delay time of the delay circuit 3-2 cannot be shortened, the delay time of the clock delay circuit 4-2 is increased.

  Next, the clock CK2 passing through the delay circuit 12-1 having the minimum delay time is selected, and the delay circuit 12 prevents the shortest path data D2min passing through the shortest path P1 of the logic circuit 5 from causing a hold error under the Best condition. -1 is corrected.

  As a result of the correction, the operation ranges A and D when the delay circuits 12-1 and 12-2 are used are stored in the control circuit 6, and the static timing analysis is completed. The semiconductor device designed in this way is further manufactured through a wafer process. Hereinafter, the operation range of the semiconductor device after the wafer process will be described.

  FIG. 5 is an explanatory diagram of the operation range of the logic circuit according to the second embodiment of the present invention, and represents the range of the operation environment where the output data of the logic circuit 5 is correctly latched by the latch circuit 2. 3, D2max and D2min represent the output data of the logic circuit 5 output to the latch circuit 2 via the longest path P4 and the shortest path of the logic circuit 5, respectively. For simplicity, FIG. 3 shows only the data that should be latched in the latch circuit 2 at time t1.

  When the operating environment is worst, that is, condition 1, the margin of the setup time ts of the longest path data D2max is a problem as described above. The condition 1 satisfying the setup time ts is the rising time t2 of the clock CK2 delayed by the delay circuit 12-2 having the maximum delay time. The rise time t1 of the clock CK2 delayed by the delay circuit 12-1 having the minimum delay time has a short setup margin. The clock CK2 rising at the time t1 satisfies the setup condition in the operating environment in the direction of Best from Condition 3.

  On the other hand, when the operating environment is Best, that is, the condition 4, the margin of the hold time th of the shortest path data D2max is a problem. The rising time t1 of the clock CK2 delayed by the delay circuit 12-1 having the minimum delay time satisfies this hold condition. On the other hand, the rising time t2 of the clock CK2 delayed by the delay circuit 12-2 having the maximum delay time satisfies the hold condition under the operating environment in the worst direction from condition 2.

  To summarize the above results, when the clock CK2 having the rising time t2 delayed by the delay circuit 12-2 having the maximum delay time is used, the semiconductor device operates in the operation range C from Condition 1 to Condition 2. On the other hand, when the clock CK2 at the rising time t1 delayed by the delay circuit 12-1 having the minimum delay time is used, the operation is performed in the operation range D of Condition 3 to Condition 4.

  As in the first embodiment, the control circuit 6 determines whether the operating environment indicated by the observation data corresponds to the operating range C or the operating range D, and switches the delay circuits 12-1 and 12-2. When the operation ranges C and D partially overlap, the same processing as in the first embodiment is performed. Therefore, a semiconductor device having a wide operation range is realized.

  The third embodiment of the present invention includes the variable delay circuit 10 of the first embodiment that delays the output of the logic circuit 5, and the variable delay circuit 11 that generates the clock CK2 of the latch circuit 2 by delaying it from the clock CK. The present invention relates to a semiconductor device.

  FIG. 6 is a circuit diagram of a logic circuit and its peripheral circuits according to the third embodiment of the present invention. Circuits having functions similar to those in FIGS. 1 and 4 are denoted by the same reference numerals.

  The semiconductor device according to the third embodiment includes a variable delay including latch circuits 1 and 2, a logic circuit 5, a clock delay circuit 4-1, delay circuits 3-1 and 3-2, and a selector 8 as in the first embodiment. A circuit 10 and a flip-flop 7 are provided. Further, it has a delay circuit 12-1, 12-2 similar to the second embodiment, a variable delay circuit 11 including a selector 9, and a flip-flop circuit 13. These circuits operate in the same manner as already described in the first and second embodiments.

  The control circuit 6 of the third embodiment has a table in which the delay time of the variable delay circuit 10 that delays data is the first variable, and the delay time of the variable delay circuit 11 that delays the clock CK is the second variable. Each column of this table includes a range of operating environments (specifically satisfying timing conditions) that can be handled when the first and second variables corresponding to the column are the delay times of the variable delay circuits 10 and 11 (specifically, Is the range of the value of the observation data Dob).

  The control circuit searches the column including the observation data Dob input from the table, compares the first and second variables in the searched column with the delay time currently used, and varies based on the comparison result. It is determined which of the delay circuits 10 and 11 is to be switched.

  In this embodiment, the delay times of the variable delay circuits 10 and 11 that can be correctly latched under the observed operating environment are expressed on a two-dimensional table based on the first and second variables. It can be easily determined which of the first and second variables is changed and how much the operating environment can be most appropriately handled. For example, in order to obtain the fastest operation, a condition in which the clock CK is the shortest is selected in the vicinity of the periphery of the two-dimensional pattern drawn by the extracted column. As described above, according to the present embodiment, since two variables can be used for adapting to the observed operating environment, more appropriate control is possible.

  The invention described in the following supplementary notes is disclosed in the above description.

(Supplementary Note 1) A first latch circuit that latches and outputs data in synchronization with the first clock, a second latch circuit that latches data in synchronization with the second clock, and output data of the first latch circuit is input And a logic circuit that outputs an operation result to the second latch circuit,
A variable delay circuit that delays output data of the logic circuit and outputs the delayed data to the second latch circuit;
The observation data of the operation environment that affects the operation speed of the logic circuit or the first or second latch circuit is input, and the output data of the logic circuit is correct under the operation environment indicated by the input observation data. A semiconductor device comprising: a control circuit that controls a delay time of the variable delay circuit so as to be latched.

(Supplementary Note 2) A first latch circuit that latches and outputs data in synchronization with the first clock, a second latch circuit that latches data in synchronization with the second clock, and output data of the first latch circuit is input. And a logic circuit that outputs an operation result to the second latch circuit,
A variable delay circuit for delaying the second clock;
The observation data of the operation environment that affects the operation speed of the logic circuit or the first or second latch circuit is input, and the output data of the logic circuit is correctly latched under the operation environment indicated by the observation data. And a control circuit for controlling the delay time of the variable delay circuit.

 (Supplementary Note 3) The variable delay circuit includes a plurality of delay circuits having different delay times, and a selector that selects one of the outputs from the plurality of delay circuits and outputs the selected one to the second latch circuit. In the control circuit, a range of the operating environment in which the output data of the logic circuit is correctly latched for each delay time of the delay circuit is set in advance, and the operating environment indicated by the observation data is set. 3. The semiconductor according to claim 1, wherein the selector is controlled so as to select the delay circuit having a delay time in which the output data of the logic circuit is correctly latched by comparing with a range of an operating environment. apparatus.

(Supplementary Note 4) The variable delay circuit includes a plurality of delay circuits having different delay times, and a selector that selects one of the output data of the plurality of delay circuits and outputs the selected data to the second latch circuit. ,
3. The semiconductor device according to claim 1, wherein the control circuit controls the selector so as to select the delay circuit having a delay time in which output data of the logic circuit is correctly latched.

 (Supplementary Note 5) The operating environment includes a chip temperature of the semiconductor device, a package temperature of the semiconductor device, a temperature around the chip or package of the semiconductor device, and a connection point between the lead of the semiconductor device and the circuit board. 5. The semiconductor device according to appendix 1, 2, 3 or 4 including one or a plurality of temperatures selected from the temperatures.

(Additional remark 6) It has the monitor circuit which measures the gate delay provided in the said semiconductor device,
6. The semiconductor device according to appendix 1, 2, 3, 4 or 5, wherein the operating environment includes a gate delay time measured by the monitor circuit.

(Supplementary Note 7) A first latch circuit that latches and outputs data in synchronization with the first clock, a second latch circuit that latches data in synchronization with the second clock, and output data of the first latch circuit is input. And a logic circuit that outputs an operation result to the second latch circuit,
A first variable delay circuit that delays output data of the logic circuit and outputs the delayed data to the second latch circuit;
A second variable delay circuit for delaying the second clock;
The observation data of the operation environment that affects the operation speed of the logic circuit or the first or second latch circuit is input, and the output data of the logic circuit is correctly latched under the operation environment indicated by the observation data. And a control circuit for controlling the delay times of the first and second variable delay circuits.

  The present invention can be applied to a semiconductor device having a synchronous logic circuit to realize a semiconductor device that has a wide use environment and converges quickly in static timing analysis.

1 is a circuit diagram of a first embodiment of the present invention. Timing chart in the first embodiment of the present invention Operational range explanatory diagram of the logic circuit of the first embodiment of the present invention Circuit diagram of logic circuit and peripheral circuit thereof according to second embodiment of the present invention Operating range explanatory diagram of the logic circuit of the second embodiment of the present invention Circuit diagram of logic circuit and peripheral circuit thereof according to third embodiment of the present invention Circuit diagram of conventional logic circuit and its peripheral circuits Conventional logic circuit timing chart Operating range explanatory diagram of conventional logic circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Latch circuit 3, 3-1, 3-2, 12-1, 12-2 Delay circuit 4-1, 4-2 Clock delay circuit 5 Logic circuit 6 Control circuit 7, 13 Flip-flop 8, 9 Selector 10 , 11 Variable delay circuit D1, D2 Data Din Input data Dout Output data CK, CK1, CK2 Clock P1-P4 Path t0, t1, t2 Time (latch timing)
ts setup time th hold time

Claims (5)

A first latch circuit that latches and outputs data in synchronization with a first clock; a second latch circuit that latches data in synchronization with a second clock; and the output data of the first latch circuit is input to the second latch circuit. In a semiconductor device including a logic circuit that outputs an operation result to a latch circuit,
A variable delay circuit that delays output data of the logic circuit and outputs the delayed data to the second latch circuit;
The observation data of the operation environment that affects the operation speed of the logic circuit or the first or second latch circuit is input, and the output data of the logic circuit is correct under the operation environment indicated by the input observation data. A semiconductor device comprising: a control circuit that controls a delay time of the variable delay circuit so as to be latched. A first latch circuit that latches and outputs data in synchronization with a first clock; a second latch circuit that latches data in synchronization with a second clock; and the output data of the first latch circuit is input to the second latch circuit. In a semiconductor device including a logic circuit that outputs an operation result to a latch circuit,
A variable delay circuit for delaying the second clock;
The observation data of the operation environment that affects the operation speed of the logic circuit or the first or second latch circuit is input, and the output data of the logic circuit is correctly latched under the operation environment indicated by the observation data. And a control circuit for controlling the delay time of the variable delay circuit. The variable delay circuit includes a plurality of delay circuits having different delay times, and a selector that selects one of the outputs from the plurality of delay circuits and outputs the selected one to the second latch circuit. A range of the operating environment in which the output data of the logic circuit is correctly latched for each delay time of the delay circuit is preset, and the operating environment range indicated by the observation data is set. 3. The semiconductor device according to claim 1, wherein the selector is controlled so as to select the delay circuit having a delay time in which the output data of the logic circuit is correctly latched. The operating environment includes a chip temperature of the semiconductor device, a package temperature of the semiconductor device, a temperature around the chip or package of the semiconductor device, and a temperature of a connection point between the lead of the semiconductor device and the circuit board. 4. The semiconductor device according to claim 1, comprising one or a plurality of selected temperatures. A first latch circuit that latches and outputs data in synchronization with a first clock; a second latch circuit that latches data in synchronization with a second clock; and the output data of the first latch circuit is input to the second latch circuit. In a semiconductor device including a logic circuit that outputs an operation result to a latch circuit,
A first variable delay circuit that delays output data of the logic circuit and outputs the delayed data to the second latch circuit;
A second variable delay circuit for delaying the second clock;
The observation data of the operation environment that affects the operation speed of the logic circuit or the first or second latch circuit is input, and the output data of the logic circuit is correctly latched under the operation environment indicated by the observation data. And a control circuit for controlling the delay times of the first and second variable delay circuits.

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