JP2007074002A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve IGBT having a high withstand voltage, a low on-voltage, and a wide area of safe operation. <P>SOLUTION: In IGBT having at least a p+n-pn+ structure from a collector side to an emitter side, and an n layer having high concentration compared with an n- layer between the n- layer and a p layer, an n layer having the further high concentration compared with the n layer is formed between the n- layer and the p layer. Since an avalanche is induced in the n layer having the high concentration, an area of safe operation is expanded. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  A semiconductor device that controls a high voltage is required to have a small loss. In order to reduce the switching loss, it is necessary that the voltage drop in the semiconductor device is small and the on-voltage is small at the time of on, and that the switching operation is fast.

  Even if switching is performed at high speed, the jumping voltage is small and the noise is required to be low. Further, there is a demand for reliability such as the ability to reliably block high voltage, a large controllable current, and a wide safe operation area. In addition, it is an important issue to reduce the manufacturing cost.

  Under such circumstances, various insulated gate bipolar transistors (hereinafter abbreviated as IGBTs), which are semiconductor devices in which MOS gates and transistors are combined, have been proposed. Among these, storage type IGBTs that can reduce the on-state voltage have attracted attention in recent years.

  FIG. 11 is a diagram for explaining a conventional carrier storage type IGBT, and is a cross-sectional view of an IGBT having a groove-shaped trench gate. The feature of this element 201 is that the emitter electrode of a normal trench gate type IGBT is thinned out with an insulating film 60. This element is called IEGT (Injection Enhanced IGBT) and is disclosed in Non-Patent Document 1.

  In the element 201, the n buffer layer 21 is formed on the p + layer 10, and the n− layer 22 is provided thereon. A trench is dug in the silicon from the upper surface, and a gate insulating film 500 and gate electrodes 300 and 301 are formed. The emitter electrode 2 is in contact with the n + layer 400 and the p + layer 320 between the gate electrodes 300.

  The gate electrodes 300 and 301 are covered with the insulating film 60, and the p layer adjacent to the gate electrode 301 is insulated from the emitter electrode 2 by the insulating film 60. The p + layer 10 is in contact with the collector electrode 1.

  The difference between the element 201 and an IGBT having a normal trench gate is that the p layer adjacent to the gate electrode 301 is insulated from the emitter electrode 2 by the insulating film 60. As a result, positive charges (holes) injected from the p + layer 10 can be accumulated in the n− layer 22, conductivity modulation can be increased, and the on-voltage can be reduced.

  FIG. 12 is also a cross-sectional view of an IGBT having a trench gate. It is called a CSTBT (Carrier Stored Trench-Gate Bipolar Transistor) and is an element announced in Non-Patent Document 2.

  In the element 202, the n buffer layer 21 is formed on the p + layer 10, and the n− layer 22 is provided thereon. A trench is dug in the silicon from the upper surface to form a gate insulating film 500 and a gate electrode 300, and the emitter electrode 2 is in contact with the n + layer 400 and the p + layer 320 between the gate electrodes 300.

  A p layer 310 is formed between the underlying gate electrodes 300, and an n layer 230 is formed below the p layer 310. The gate electrode 300 is covered with an insulating film 60. On the other hand, the p + layer is in contact with the collector electrode 1.

  The difference between this element 202 and an IGBT having a normal trench gate is that an n layer 230 is added. As a result, positive charges (holes) injected from the p + layer 10 can be accumulated in the n− layer 22, conductivity modulation can be increased, and the on-voltage can be reduced.

  FIG. 13 is a cross section of an IGBT having a planar gate structure. It is called HiGT (High-Conductivity IGBT) and is shown in Patent Document 1. In the element 203, the n buffer layer 21 is formed on the p + layer 10, and the n− layer 22 is provided thereon.

  From the upper surface, n layer 23 having a carrier concentration higher than that of n − layer 22 is diffused in n − layer 22. Further, the p layer 31 is diffused so as to be surrounded by the n layer 23.

  An n + layer 40 is introduced into the P layer 31. A gate insulating film 51 is formed on the surface of the P layer 31 and the n layer 23 so as to straddle the n + layer 40 and the n− layer 22, and the gate electrode 1 is in contact therewith.

  On the other hand, the p + layer is in contact with the collector electrode 1. The emitter electrode 2 is formed in the n + layer 40 and in the p layer 31 and is in contact with the p + layer 32 reaching under the n + layer 40.

And IGBT with normal planar gate structure, the difference between this device 203 is n layer 23 higher carrier concentration than the n- layer 22 is formed, in that the sheet carrier concentration is 1 × 10 ¹² cm- ² or less is there. Accordingly, positive charges (holes) injected from the p + layer 10 can be accumulated in the n− layer 22 without lowering the breakdown voltage, conductivity modulation can be increased, and the on-voltage can be reduced.

  FIG. 14 is a cross-sectional view of an IGBT having a planar gate structure. This is shown in Patent Document 1. The difference between the element 204 and the above-described element 203 is located between the virtual perpendiculars drawn from the inner ends of the n + layers 40 adjacent to each other in the n layer 23 in one p layer 31. A region 231 having an impurity concentration higher than that of the region is partially formed. In the region 231, avalanche breakdown is more likely to occur than in other regions of the n layer 23. This makes it difficult to latch up and widens the safe operating area.

  FIG. 15 is a cross section of an IGBT having a planar gate structure. This is shown in Patent Document 1. The difference between the element 205 and the element 203 described above is that the distance between the gate electrodes 3 is reduced to the depth of the n layer 23, and the n layer 23 is rounded at the bottom. In this case, since the electric field is strongest at the lower part of the n layer 23, the avalanche breakdown is likely to occur at a lower part than the other regions of the n layer 23. Therefore, the safe operation area is widened.

JP-A-10-178174 ISPSD (International Symposium on Power Semiconductor Devices and Ics, ISPSD2000, p.221-p.224) International Symposium on Power Semiconductor Devices and Ics (ISPSD1996, p.349-p.352)

  However, in the semiconductor device 201 of FIG. 11, since the emitter electrode 2 is in contact only between some of the insulated gates 300, current is concentrated there, and latch-up is likely to occur. That is, there is a problem that the controllable current is small and the safe operation area is narrowed, and the reliability is lowered.

  Further, there is a problem that the manufacturing cost increases due to the complexity of the process inherent in the trench gate type IGBT, such as dry etching of silicon to form the gate electrode 300.

  In the semiconductor device 202 of FIG. 12, the emitter electrode 2 is in contact between almost all the insulated gates 300. Although no current is concentrated, the provision of the n layer 230 has a problem that the electric field is more easily concentrated at the bottom corner of the insulated gate 300 and the reliability of the gate insulating film is lowered. In addition, the manufacturing cost increases due to the trench gate type.

In the semiconductor device 203 of FIG. 13, the insulated gate 300 is a planar type and has an advantage that the manufacturing cost is low. However, A-A 'line of n layer 23, i.e. the longitudinal direction of the sheet carrier concentration when the _{N A} was defined as 1 × ¹⁰ 12 ^{cm -2} or less, the horizontal direction of the sheet carrier concentration 1 × ^{10 12} of the n layer 23 It is lower than cm ⁻² , hole accumulation is not sufficient, and conductivity is not sufficiently modulated.

  That is, there is a problem that the on-voltage is not lowered to the original physical limit value and the on-loss is large. In addition, since the electric field tends to concentrate on the corners of the n layer 23, avalanche breakdown occurs here, and it is difficult to increase the maximum controllable current. As a result, the safe operation area is not widened, and it is difficult to further improve the reliability.

  In the semiconductor device 204 of FIG. 14, since the electric field is likely to concentrate on the n layer 231 at the center of the n layer 23, avalanche breakdown occurs here, and the maximization control current increases.

Safe operating region is enlarged, A-A 'line of n layer 23, i.e. the longitudinal direction of the sheet carrier concentration when the _{N A} was defined as 1 × ¹⁰ 12 ^{cm -2} or less, the lateral n layer 23 sheet carrier The concentration is lower than 1 × 10 ¹² cm ⁻² . Therefore, hole accumulation is not sufficient and the conductivity is not sufficiently modulated. That is, the same problem that the on-voltage does not decrease to the original physical limit value and the on-loss is large occurs.

  Since the electric field of the semiconductor device 205 in FIG. 15 is likely to be concentrated in the lower part of the n layer 23, the avalanche breakdown occurs here, and the maximization control current increases. However, the distance between the gate electrodes 3 must be reduced to the depth of the n layer 23.

  In that case, the n + layer 40 and the p + layer 32, the gate electrode 3 and the emitter electrode 2 must be positioned with high precision, which requires an expensive lithography apparatus and increases the manufacturing cost.

  The present invention provides a semiconductor substrate having a pair of main surfaces, a first semiconductor region of a first conductivity type located in the semiconductor substrate, and a second conductor type of second adjacent to the first semiconductor region. A semiconductor region; a third semiconductor region of a second conductivity type extending from one main surface of the semiconductor substrate into the second semiconductor region and having a carrier concentration higher than the carrier concentration of the second semiconductor region; A first conductive type fourth semiconductor region extending from one main surface of the semiconductor substrate and positioned in the third semiconductor region; and extending from one main surface of the semiconductor substrate and positioned in the fourth semiconductor region A second conductive type fifth semiconductor region, and a gate insulating film formed to face an exposed surface of the second, third, fourth, and fifth semiconductor regions on the one main surface; A gate electrode formed adjacent to the gate insulating film; An emitter electrode in low resistance contact with the fourth semiconductor region and the fifth semiconductor region; and a collector electrode in low resistance contact with the first semiconductor region, wherein the gate electrode of the third semiconductor region This is a semiconductor device in which a seventh semiconductor region located between them and having a carrier concentration higher than that of the third semiconductor region is formed.

  According to the present invention, the on-voltage is low, the switching is fast, the withstand voltage is easily increased, the feedback capacitance causing noise is small, the manufacturing cost is low, the maximum controllable current is large, and the safe operation area is wide. An excellent semiconductor device can be provided.

Example 1
An embodiment of the present invention will be described in detail with reference to FIG. Semiconductor device 100 has substantially parallel and flat one and other main surfaces 120 and 122. N buffer layer 21 is formed on p + layer 10 exposed at the other main surface 122, and n − layer 22 having an impurity concentration lower than that of buffer layer 21 is formed thereon. N− layer 22 is exposed at one main surface 120.

  An n layer 23 having a carrier concentration higher than that of n − layer 22 is diffused from one main surface 120 into n − layer 22. Further, a p layer 31 is diffused inside so as to be surrounded by the n layer 23. Further, n + layers 40 are formed side by side at intervals in the plurality of P layers 31.

  A gate insulating film 51 is formed across the exposed surface of one of main surfaces 120 of n− layer 22, p layer 31, n layer 23, and n + layer 40, and gate electrode 3 is provided thereon.

  On the other main surface 122, collector electrode 1 is in low resistance contact with p + layer 10. On one main surface 120, emitter electrode 2 is in low resistance contact with n + layer 40 and p + layer 32. The p + layer 32 is formed in the p layer 31 and straddles the plurality of n + layers 40 and is located thereunder.

  In order to turn on such a semiconductor device 100, a negative potential is applied to the emitter electrode 2 and a positive potential is applied to the collector electrode 1, and a positive potential is applied to the gate electrode 3 from the emitter potential.

  At this time, an n-type inversion layer is formed on the surface of the p layer 31 located under the gate electrode 3, and electrons pass through the n + layer 40, the inversion layer, the n layer 23, the n− layer 22, and the n buffer layer 21. Then, it is injected into the p + layer 10. Holes are injected from the p + layer 10 into the n buffer layer 21 and the n− layer 22 by the injected electrons.

  As a result, the conductivity of the n− layer 22 is modulated and the resistance is reduced, and the semiconductor device 100 exhibits a low on-voltage. At this time, the n layer 23 has an effect of suppressing the injected holes from diffusing into the p layer 31 and accumulating the holes in the n − layer 22. As a result, conductivity modulation increases and the on-voltage decreases.

The present inventors have, 'rather than sheet carrier concentration N _A along the line, B-B shown in FIG. 1' A-A shown in FIG. 13 determine the breakdown voltage is essentially a sheet carrier concentration NB along the line I found out that

  In this case, when the p layer 31 and the n layer 23 are formed by diffusion, impurities near the center of these layers diffuse one-dimensionally downward, but below the corners and the gate electrode 3, This is due to diffusion not only in the direction but also in the horizontal direction in two dimensions.

As a result, the sheet carrier concentration N _B of the corner portion of the n layer 23 is lower unlike sheet carrier concentration N _A of the central portion. The breakdown voltage is determined by the avalanche breakdown at the place where the electric field is the strongest. Here, the electric field is the strongest because it becomes the boundary between the corners of the p layer 31 and the n layer 23.

Figure 2 is a result of the studies, shows the relationship between sheet carrier concentration N _B and the breakdown voltage along the line B-B 'of the n-layer 23 shown in FIG. FIG As is clear from, B-B 'is sheet carrier concentration _{N B} along the line drops significantly and the breakdown voltage becomes 1 × ¹⁰ 12 cm- ² or more.

The sheet carrier concentration _{N B} taken along line B-B 'of the n layer 23 since, it is desirable to 1 × ¹⁰ 12 cm- ² or less. On the other hand, as shown in JP-A-10-178174, the ON voltage decreases monotonously as the sheet carrier concentration increases.

'If the sheet carrier concentration _{N B} along line ^{1 × 10 12 cm- 2, A} -A' if B-B sheet carrier concentration _{N A} along the line can be higher than that. Thereby than when the sheet carrier concentration N _A taken along line A-A 'and 1 × 10 ¹² cm- ² or less, the result of the n layer 23 can be most effectively formed, lowering the on-voltage to the physical limits I can do it.

  On the other hand, in the semiconductor device 100 according to the embodiment of the present invention, the n layer 23 is depleted during turn-off in which a reverse bias is applied to the p layer 31 and the n layer 23. As a result, holes accumulated in the n− layer 22 can flow directly into the p layer 31 and can be turned off at high speed. Furthermore, the feedback capacitance can be reduced by forming a gate insulating film 52 in which a part of the center of the gate oxide film 50 is thicker than the gate insulating film 51.

  A region 231 is partially formed substantially at the center of the n layer 23. Of this region 231, the portion with the highest impurity concentration is located between virtual perpendiculars CC taken from the inner ends of adjacent n + layers 40 in one p layer 31. In this embodiment, the p + layer 10 can be made thinner than the diffusion length of electrons as in the p + layer 11 indicated by a dotted line.

  As a result, the injection of holes can be suppressed and the ratio of the electron current to the total current can be further increased, so that the hole current for latch-up is reduced, the maximum controllable current is increased, and the safe operation area is further expanded. To do.

  Further, when the P + layer 11 is positioned as shown in the figure, the on-voltage is not increased, so that the thickness of the n− layer of the semiconductor element 100 is 0.9 times or less that when the p + layer 10 is positioned. It is preferable. In terms of the expression using the withstand voltage Vb, it is preferable that Vb / 8 μm or less. Further, in order to increase the maximum controllable current, it is desirable that the thickness of the p + layer 11 is 1 μm or less.

FIG. 3 shows the ratio N _C / N _B between the sheet carrier concentration N _B along the line BB ′ and the sheet carrier concentration N _C of the partial CC ′ line having the highest concentration in the region 231, and the breakdown voltage. The maximum controllable current relationship is shown.

It can be seen that the maximum controllable current increases monotonically as N _C / N _B increases. This As the N _{C /} N _B becomes large and the dynamic avalanche point that occurs upon turn-off of transition from the ON state to the OFF state is concentrated at the highest impurity concentration position of the n layer 231.

However, the breakdown voltage decreases abruptly when the _N C / _{N B} becomes 5 or higher. When N _C / N _B is 5 or less, when the static avalanche position that has occurred at the corners of the n layer 23 and the p layer 30 becomes 5 or more, it moves and is determined at the position of the n layer 231 where the impurity concentration is the highest. Because. Therefore, it is desirable that N _C / N _B is 5 or less.

  On the other hand, a conventional example similar to the present embodiment is shown in the conventional semiconductor device 204 shown in FIG. However, in this embodiment, the position Pk having the highest impurity concentration of the n layer 231 is located between the virtual perpendiculars CC taken down from the inner ends of the adjacent n + layers 40 in one p layer 31. . That is, the position Pk having the highest impurity concentration is not necessarily located at the center of the virtual perpendicular line CC ′.

  On the other hand, in the conventional semiconductor device 204, the impurity concentration in the n layer 231 which is a high concentration region must be higher than any place in the n layer 23 excluding the n layer 231. For this purpose, the position Pk having the highest impurity concentration must be located at the center between the virtual perpendicular lines CC ′ as shown in FIG. 14, and is different in that expensive photolithography is required. In the present embodiment, the point Pk at which the concentration is maximum needs to be within the region of the n layer 231.

  In addition, as described above, it is a novel finding discovered by the present inventors that there are suitable conditions for the n layer 23 and the n layer 231 in order to maintain the withstand voltage and increase the maximum controllable current.

  Here, a manufacturing method of the semiconductor device 100 of the present embodiment will be described with reference to FIGS. First, the n buffer layer 21 and the p + layer 10 are formed on the substrate to be the n− layer. A thick gate oxide film 52 is formed in a planar shape on the emitter side and patterned into a desired shape.

  Further, an oxide film to be a thin gate insulating film 51 is formed on the surface where the n− layer 22 is exposed. Polycrystalline silicon is deposited as the gate electrode 3 on the oxide film to be the thick gate insulating film 52 and the thin gate insulating film 51. Here, the opening is opened together with the gate electrode 3 on the thin gate insulating 51 so that the thick gate insulating film 52 is substantially symmetrical.

  At this time, the lengths in the planar direction of the thin gate oxide films 51 on the left and right of the opening are set to be substantially equal. Also, as shown in FIG. 4, phosphorus is ion-implanted as an impurity of the n layer 23 from the opening using the gate electrode 3 as a mask.

  Next, as shown in FIG. 5, phosphorus is ion-implanted as an impurity of the n layer 231 using a photoresist pattern 1000 narrower than the opening, and FIG. 6 http://www6.ipdl.ncipi.go.jp/Tokujitu /tjitemdrw.ipdl?N0000=234&N0500=4E_N/;>9?69?:>///&N0001=133&N0552=9&N0553=000008.

  Next, boron is ion-implanted as an impurity of the n layer 31 from the same opening using the gate electrode 3 as a mask, and thermal diffusion is performed as shown in FIG.

  Further, in order to reduce the lateral resistance of the p layer 31 below the n + layer, impurity boron in the p + layer 32 is ion-implanted and diffused using a photoresist so as to reach the bottom of the n + layer. Next, arsenic or phosphorus, which is an impurity of the n + layer 40, is ion-implanted and thermally diffused using a photoresist pattern.

  Thereafter, an insulating film 60 is deposited, an opening is opened in the insulating film 60 using a photoresist so as to cover the gate electrode 3, and the p + layer 32 and the n + layer 40 are short-circuited by the emitter electrode 2 to be in electrical contact.

Further, the collector electrode 1 is also formed on the p + layer 10 and is electrically coupled. The p + layer 10 may be formed immediately before the collector electrode 1 is formed and electrically coupled.
(Example 2)
FIG. 8 is a sectional view showing another embodiment of the present invention. In the semiconductor device 105 of this embodiment, the gate electrode 3 has a trench structure, and the p layer 31 is formed in the wider gate interval, and the n + layer 40, the p + layer 32, and the p layer 31 are formed in the narrower one. N layer 23 is formed.

An n layer 231 having a carrier concentration higher than that of the n layer 23 is formed almost at the center of the n layer 23. As a result, since the avalanche occurs in the n layer 231, the safe operation area is widened. Further, since the gate electrode 3 is formed more roughly than the conventional trench IGBT, the feedback capacitance can be reduced.
(Example 3)
FIG. 9 is a sectional view showing another embodiment using the present invention. In the semiconductor device 106 of this embodiment, the gate electrode 3 has a trench structure, and the p layer 31 is formed in the wider gate interval, and the n + layer 40, the p + layer 32, and the p layer 31 are formed in the narrower one. N layer 23 is formed.

  An n layer 231 having a carrier concentration higher than that of the n layer 23 is formed almost at the center of the n layer 23. As a result, since the avalanche occurs in the n layer 231, the safe operation area is widened. Further, since the gate electrode 3 is formed more roughly than the conventional trench IGBT, the feedback capacitance can be reduced. In this embodiment, by making the p + layer 11 thinner than the diffusion length of electrons, the injection of holes from the p + layer 11 can be suppressed.

  As a result, the ratio of the electron current to the total current can be further increased, so that the Hall current for latch-up is reduced, the maximum controllable current is increased, and the safe operation area is further expanded.

At this time, the thickness of the n − layer 24 is preferably 0.9 times or less that of the semiconductor element 105 in order not to increase the on-voltage. In terms of the expression using the withstand voltage Vb, it is preferable that Vb / 8 μm or less. Further, in order to increase the maximum controllable current, it is desirable that the thickness of the p + layer 11 is 1 μm or less.
Example 4
FIG. 10 shows an application example in which the semiconductor device of the present invention is applied to an inverter device which is one of power converters. By using the semiconductor device of the present invention, low loss and high speed control can be performed without impairing the breakdown voltage characteristics, and gate noise through the feedback capacitance can be reduced, and the inverter device is highly efficient and highly reliable. Can be realized.

  By using the low-loss and high-reliability power conversion device of the present invention, for example, a vehicle cooling device driven with electric power as a power source can be simplified, reduced in size, reduced in weight, and thus reduced in cost. Furthermore, the conventional Shinkansen that used the blower for cooling can be made blower-free, and the vehicle can be reduced in weight, noise and loss.

It is sectional drawing explaining the structure of one Example of this invention semiconductor device. It is a figure showing the relationship between the sheet carrier density | concentration of the n layer corner | angular part of FIG. 1, and a characteristic. It is a figure showing the ratio of the sheet carrier density | concentration of n layer corner | angular part of FIG. It is sectional drawing explaining the manufacturing method of this invention semiconductor device. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing explaining the structure of the Example of this invention semiconductor device. It is sectional drawing explaining the structure of the Example of this invention semiconductor device. It is an example of the power converter device which uses this invention semiconductor device. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Collector electrode, 2 ... Emitter electrode, 3 ... Gate electrode, 10, 32 ... p + layer, 21 ... n buffer layer, 22 ... n- layer, 23 ... n layer, 31 ... p layer, 40 ... n + layer, 50 ... Gate insulating film, 60 ... Insulating film, 1000 ... Photoresist pattern.

Claims (6)

A semiconductor substrate having a pair of main surfaces, a first semiconductor region of a first conductivity type located in the substrate, and a second semiconductor region of a second conductivity type located adjacent to the first semiconductor region A third semiconductor region of a second conductivity type extending from one main surface of the semiconductor substrate into the second semiconductor region and having a carrier concentration higher than that of the second semiconductor region, and the semiconductor A fourth semiconductor region of a first conductivity type extending from one main surface of the substrate and positioned in the third semiconductor region; and extending from one main surface of the semiconductor substrate and positioned in the fourth semiconductor region A gate insulating film formed opposite to the exposed surface of the second conductive type fifth semiconductor region and the second, third, fourth, and fifth semiconductor regions on one main surface of the semiconductor substrate. And a gate electrode formed on the gate insulating film. An emitter electrode in low resistance contact with the fourth semiconductor region and the fifth semiconductor region, and a collector electrode in low resistance contact with the first semiconductor region, wherein a sheet carrier concentration of the sixth semiconductor regions is a major part of the curvature is 1 × 10 ¹² cm- ² or less. A semiconductor substrate having a pair of main surfaces, a first semiconductor region of a first conductivity type located in the substrate, and a second semiconductor region of a second conductivity type located adjacent to the first semiconductor region A third semiconductor region of a second conductivity type extending from one main surface of the semiconductor substrate into the second semiconductor region and having a carrier concentration higher than that of the second semiconductor region, and the semiconductor A first conductivity type fourth semiconductor region extending from one main surface of the substrate and located in the third semiconductor region; and extending from one main surface of the semiconductor substrate and positioned in the fourth semiconductor region And a second insulating type fifth semiconductor region and a gate insulation formed opposite to the exposed surface of the second, third, fourth and fifth semiconductor regions on one main surface of the semiconductor substrate. And a gate formed on the gate insulating film A pole, an emitter electrode in low resistance contact with the fourth semiconductor region and the fifth semiconductor region, and a collector electrode in low resistance contact with the first semiconductor region, most sheet carrier concentration of the sixth semiconductor regions is a major part of the curvature is at 1 × 10 ¹² cm- ² or less, of the third semiconductor region located between the gate electrode, the third A semiconductor device comprising a seventh semiconductor region having a carrier concentration higher than that of the semiconductor region.   3. The eighth semiconductor region of the second conductivity type according to claim 1, wherein the eighth semiconductor region is a second conductivity type sandwiched between the first semiconductor region and the second semiconductor region and having a carrier concentration higher than a carrier concentration of the second semiconductor region. A semiconductor device having the same.   4. The semiconductor device according to claim 1, wherein a thickness of the first semiconductor region is shorter than an electron diffusion length.   5. The semiconductor device according to claim 1, wherein the thickness of the first semiconductor region is 1 μm or less.   6. The semiconductor device according to claim 1, wherein the thickness of the second semiconductor region is Vb / 8 [mu] m or less when the breakdown voltage of the semiconductor device is Vb.

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