JP2007073641A - Method of manufacturing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor substrate having an impurity-doped polycrystalline semiconductor layer having little variation in impurity concentration on an insulation substrate. <P>SOLUTION: The method of manufacturing the semiconductor substrate having a polycrystalline semiconductor layer containing impurities on the surface of the insulation substrate includes: a process of forming an impurity-doped amorphous semiconductor layer which is more highly doped than the polycrystalline semiconductor layer; a process of forming an impurity-doped amorphous semiconductor layer which is more lightly doped than the polycrystalline semiconductor layer, or an impurity-undoped amorphous semiconductor layer; and a process of crystallizing the amorphous semiconductor layers. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a method for manufacturing a semiconductor substrate. More specifically, a polycrystalline semiconductor layer is provided on an insulating surface, and a semiconductor substrate suitable for a manufacturing method such as an active matrix substrate or a solar cell substrate used in a display device such as a liquid crystal display device or an organic electroluminescence display device. The present invention relates to a manufacturing method, and an active matrix substrate, a liquid crystal display device, and a solar cell substrate obtained by using the manufacturing method.

A semiconductor substrate is a circuit board provided with a semiconductor element, which is an active element utilizing the electrical characteristics of a semiconductor, on a substrate, and is widely applied to electronic devices such as audio equipment, communication equipment, computers, and home appliances. . In particular, a semiconductor substrate used in a thin display device such as a liquid crystal display device (hereinafter also referred to as “LCD”) or an organic electroluminescence display device (hereinafter also referred to as “organic EL display”) is switched as an active matrix substrate. It is used as a thin film transistor (hereinafter also referred to as “TFT”) that is an element, a control circuit for controlling each pixel, and the like, and enables high definition and high speed moving image display of a display device. Here, examples of a semiconductor used for a semiconductor element such as a TFT include silicon and germanium. However, such an intrinsic semiconductor cannot be used as a semiconductor element because its electrical insulation is too large. Therefore, the intrinsic semiconductor is imparted with conductivity by doping the intrinsic semiconductor with a P-type impurity such as boron or an N-type impurity such as phosphorus, and generating a small number of electrons or holes that are carriers of charge (carriers). It can function as an active element.

In recent years, in a semiconductor substrate provided with TFTs used in a display device, downsizing and high performance of each TFT are required as the display device is increased in size and definition. Accordingly, there is a demand for further thinning and high speed operation of the semiconductor in the TFT, and reduction in variation in characteristics of each TFT. Here, as a method for forming a semiconductor layer on a substrate, generally, a raw material gas such as silicon is formed by a CVD (Chemical Vapor Deposition) method. Further, as a method for doping impurities into the semiconductor layer, amorphous silicon doped with impurities on the substrate (hereinafter referred to as “a−”) is formed by CVD using a mixed gas in which impurity gas is mixed with silicon gas. A technique for forming a film (also referred to as “Si”) is disclosed (for example, see Patent Document 1). However, it is difficult to control the flow rate due to the small amount of impurity gas mixed in, resulting in variations in the impurity concentration of the semiconductor layer within the substrate surface. As a result, the semiconductor substrate is caused by nonuniform impurity concentration. The defect characteristics of the product were likely to increase.

In recent years, a technique for manufacturing a polycrystalline silicon TFT having a polycrystallized silicon layer by irradiating an excimer laser on an amorphous silicon film on a semiconductor substrate provided with a TFT has been disclosed (for example, Patent Documents). 2-5). This makes it possible to improve the performance of the TFT by adopting a self-aligned structure of the semiconductor layer in the polycrystalline silicon TFT. In addition, since the mobility of polycrystalline silicon is larger than that of amorphous silicon, when a polycrystalline silicon TFT is used as an active matrix substrate, a driving circuit can be integrally formed on the same substrate. Thus, the space of the display device can be saved. Furthermore, since crystallization by laser irradiation can be performed at a temperature below the strain point of the glass substrate, there is an advantage that it is not necessary to use an expensive quartz substrate. However, even if laser irradiation is performed on an amorphous semiconductor film doped with impurities using the above-described CVD method, the variation in impurity concentration in the polycrystalline semiconductor is not eliminated, and the polycrystalline semiconductor layer has a uniform impurity concentration. It was difficult to get.
As described above, regarding the semiconductor substrate manufacturing method using the CVD method, since the impurity gas mixed in the reaction gas is extremely small and the flow rate control is difficult, the impurity concentration in the amorphous semiconductor due to the flow rate variation is small. As a result, there is room for improvement in that the impurity concentration varies even in a polycrystalline semiconductor polycrystallized by laser irradiation.
JP-A-4-348533 JP-A-6-45607 JP-A-6-97196 JP 2001-60551 A JP 2002-367905 A

The present invention has been made in view of the above-described situation, and an object of the present invention is to provide a method for manufacturing a semiconductor substrate having an impurity-doped polycrystalline semiconductor layer with little variation in impurity concentration on an insulating surface.

The inventors of the present invention have studied various methods for manufacturing a semiconductor substrate having a polycrystalline semiconductor layer on an insulating surface with little variation in impurity concentration in a method for manufacturing a semiconductor substrate using a CVD method. We focused on the process of forming the semiconductor layer. A step of forming an impurity-doped amorphous semiconductor layer having a higher concentration than the polycrystalline semiconductor layer; and an impurity-doped amorphous semiconductor layer or an impurity-undoped amorphous semiconductor layer having a lower concentration than the polycrystalline semiconductor layer. It has been found that by including the step of forming and the step of crystallizing the amorphous semiconductor layer, a semiconductor substrate having a polycrystalline semiconductor layer with little variation in impurity concentration on the insulating surface can be manufactured. The inventors have arrived at the present invention by conceiving that the problem can be solved.

That is, the present invention is a method for manufacturing a semiconductor substrate having a polycrystalline semiconductor layer containing an impurity on an insulating surface, and the manufacturing method includes an impurity-doped amorphous semiconductor having a higher concentration than the polycrystalline semiconductor layer. A step of forming a layer, a step of forming an impurity-doped amorphous semiconductor layer or an impurity-undoped amorphous semiconductor layer having a lower concentration than the polycrystalline semiconductor layer, and a step of crystallizing the amorphous semiconductor layer The manufacturing method of the semiconductor substrate containing this.
Here, the impurity-doped amorphous semiconductor layer having a higher concentration than the polycrystalline semiconductor layer (hereinafter also referred to as “impurity highly-doped amorphous semiconductor layer”) refers to the polycrystalline semiconductor layer of the final product of the present invention. Means an amorphous semiconductor layer having a higher impurity concentration than the impurity concentration in the semiconductor layer, and an impurity-doped amorphous semiconductor layer having a lower concentration than the polycrystalline semiconductor layer (hereinafter referred to as “impurity lightly-doped amorphous semiconductor layer”). "Also" means an amorphous semiconductor layer having an impurity concentration lower than that of the polycrystalline semiconductor layer. The impurity-undoped amorphous semiconductor layer means an amorphous semiconductor layer to which no impurity is added. Furthermore, the amorphous semiconductor layer includes one or more impurity heavily doped amorphous semiconductor layers, one or more impurity undoped amorphous semiconductor layers, and / or one or more impurity lightly doped amorphous semiconductor layers. Are laminated. The material of the semiconductor is not particularly limited as long as the effects of the present invention can be achieved. For example, germanium (Ge), selenium (Se), or the like, cadmium sulfide (CdS), gallium arsenide (GaAs) ) And the like, and silicon (Si) is particularly preferable. The insulating surface may be anything that can be evaluated as insulating in a semiconductor substrate.

According to the method for manufacturing a semiconductor substrate of the present invention, a CVD method using a mixed gas in which an impurity gas is mixed in a source gas containing a semiconductor element by performing the impurity highly doped amorphous semiconductor layer forming step. This makes it possible to form an impurity highly doped amorphous semiconductor layer on the insulating surface. At this time, since the amorphous semiconductor layer can be formed by increasing the flow rate of the impurity gas, the controllability of the flow rate of the impurity gas can be improved. Also, the impurity lightly doped or impurity-undoped amorphous semiconductor layer is formed on the impurity highly-doped amorphous semiconductor layer by performing the impurity lightly-doped or impurity-undoped amorphous semiconductor layer forming step. be able to. Furthermore, an impurity-doped polycrystalline semiconductor layer can be formed on the insulating surface by including the amorphous semiconductor layer crystallization step. At this time, as shown in FIG. 7, when the amorphous semiconductor is melted and recrystallized to be polycrystallized, impurities are doped from the impurity high-concentration doped amorphous semiconductor layer 23 into a lightly doped or non-doped impurity. Since it diffuses into the crystalline semiconductor layer 22, the polycrystalline semiconductor layer 6 having a uniform impurity concentration can be formed. Therefore, according to the present invention, it is possible to reduce the defect characteristics caused by the non-uniformity of the impurity concentration in the polycrystalline semiconductor layer of the semiconductor substrate, and to improve the yield.

The component of the source gas is not particularly limited as long as it is a gas containing a semiconductor element, but silane (SiH ₄ ), disilane (Si ₂ H ₆ ) and the like are particularly preferable when the semiconductor is silicon. The component of the impurity gas is not particularly limited, but is preferably a gas containing an impurity element described later. Further, the CVD method is not particularly limited, and examples thereof include an atmospheric pressure CVD method, a low pressure CVD method, a remote plasma CVD method, and the like, and it is particularly preferable to use the plasma CVD method.

The method for producing a semiconductor substrate of the present invention includes the step of forming an impurity heavily doped amorphous semiconductor layer, the step of forming an impurity lightly doped or impurity undoped amorphous semiconductor layer, and the step of crystallizing the amorphous semiconductor layer. As long as it is included as an essential step, other steps may or may not be included, and there is no particular limitation. Therefore, for example, as shown in FIGS. 2A to 2C, an embodiment in which the following steps (a) to (c) are performed is also included in the method for manufacturing a semiconductor substrate of the present invention.
(A) First impurity lightly doped or impurity undoped amorphous semiconductor layer forming step / second impurity heavily doped amorphous semiconductor layer forming step / third impurity lightly doped or impurity undoped amorphous The quality semiconductor layer forming step / first, second and third amorphous semiconductor layer crystallization steps are performed in this order.
(B) First impurity lightly doped or impurity-undoped amorphous semiconductor layer forming step / second impurity heavily doped amorphous semiconductor layer forming step / first and second amorphous semiconductor layer crystallization The aspect which performs a process in this order.
(C) First impurity lightly doped or impurity undoped amorphous semiconductor layer forming step / second impurity heavily doped amorphous semiconductor layer forming step / third impurity lightly doped or impurity undoped amorphous Semiconductor layer forming step / fourth impurity highly doped amorphous semiconductor layer forming step / fifth impurity lightly doped or impurity undoped amorphous semiconductor layer forming step / first, second, third, first A mode in which the fourth and fifth amorphous semiconductor layer crystallization steps are performed in this order.
The present invention may also include an impurity high-concentration doping, impurity low-concentration doping, and impurity undoped amorphous semiconductor layer forming step. For example, the first impurity undoped amorphous semiconductor layer forming step / Second impurity lightly doped amorphous semiconductor layer forming step / third impurity heavily doped amorphous semiconductor layer forming step / first, second and third amorphous semiconductor layer crystallization steps in this order The mode to perform is also included in the manufacturing method of the semiconductor substrate of the present invention.

In the step of forming an impurity lightly doped or undoped amorphous semiconductor layer of the present invention, it is preferable that no impurity is added to the amorphous semiconductor layer. As a result, the impurity concentration of the heavily doped amorphous semiconductor layer can be set higher than the desired impurity concentration of the polycrystalline semiconductor layer, so that the flow rate of the impurity gas can be increased. Controllability can be improved. In addition, from the same viewpoint, it is preferable that the thickness of the heavily doped amorphous semiconductor layer is small. Specifically, the thickness of the amorphous semiconductor layer is more than 1/50 and 1/2. Or less, more preferably 1/20 or more and 1/5 or less. Here, the preferable lower limit is set for each because the film thickness ratio is difficult to control when the film thickness of the heavily doped amorphous semiconductor layer is too small. If the film thickness ratio is less than 1/50, the film thickness of the heavily doped amorphous semiconductor layer may vary when the film thickness of the entire amorphous semiconductor layer is reduced. is there. When the film thickness ratio exceeds 1/2, when obtaining a polycrystalline semiconductor layer having an extremely small amount of impurities, the flow rate of the impurity gas when forming the heavily doped amorphous semiconductor layer is too small. Variations in impurity concentration in the heavily doped amorphous semiconductor due to variations may occur.

It is preferable that no impurity is added to the uppermost layer of the amorphous semiconductor layer formed according to the present invention. This is because when the impurity highly doped or lightly doped amorphous semiconductor layer is the uppermost layer, the uppermost layer of the deposit in the CVD chamber is also an impurity doped amorphous semiconductor. Then, there is a possibility that impurities are diffused into the amorphous semiconductor layer of the next substrate and the impurity concentration is deviated. In order to avoid this, the impurity-doped amorphous semiconductor layer forming chamber and the undoped amorphous semiconductor layer forming chamber are separated, or chamber dry cleaning is performed for each one to remove deposits in the CVD chamber. Etc. are considered. However, it is not preferable because the processing capability of CVD is lowered. Therefore, if the uppermost layer of the amorphous semiconductor layer is a layer to which no impurity is added, the uppermost layer of the deposit in the CVD chamber is also an undoped amorphous semiconductor layer, and the impurity in the chamber deposit is undoped. Since it is contained in the crystalline semiconductor layer and the diffusion of impurities can be reduced, the next substrate is not adversely affected by the impurity diffusion.

Here, an example of a chamber structure for film formation according to the present invention will be described with reference to FIG. FIG. 8 is a schematic configuration diagram of a CVD chamber according to the present invention. The CVD chamber according to the present invention includes a first reaction chamber 31, a second reaction chamber 32, a third reaction chamber 33, a fourth reaction chamber 34, an introduction chamber 35, and a preheating chamber 36 connected to the transfer chamber 30. ing. Thus, silicon nitride, silicon oxide, impurity-doped a-Si layer, and undoped a-Si layer can be continuously formed on the glass substrate in a clean environment. The assignment of each reaction chamber is not particularly limited. For example, (1) the silicon nitride film and the silicon oxide film are continuously formed in the first reaction chamber 31 and the second reaction chamber 32, and thereafter A mode in which the impurity-doped a-Si layer 4 and the undoped a-Si layer 5 are continuously formed in the three reaction chambers 33 and the fourth reaction chamber 34. (2) Each first reaction chamber 31 and second reaction chamber 32, a mode in which silicon nitride 2, silicon oxide 3, an impurity-doped a-Si layer and an undoped a-Si layer are continuously formed in the third reaction chamber 33 and the fourth reaction chamber 34, (3) In one reaction chamber 31 and the second reaction chamber 32, silicon nitride and silicon oxide are continuously formed, and in the third reaction chamber 33, an impurity-doped a-Si layer is formed. An embodiment in which an undoped a-Si layer is formed in the fourth reaction chamber 34 is exemplified.

The impurity doped in the amorphous semiconductor layer forming step of the present invention is a substance added to the semiconductor in order to reduce the resistance of the intrinsic semiconductor, and may be a group 13 element or a group 15 element. preferable. When the group 13 element is doped, holes are generated between the semiconductor atoms, and the semiconductor becomes a P-type semiconductor. When the group 15 element is doped, free electrons are supplied between the semiconductor atoms, and the semiconductor is an N-type semiconductor. Therefore, conductivity is imparted to the semiconductor, and the semiconductor element can function as an active element. Further, each element is not particularly limited, but boron is preferable for a group 13 element and phosphorus is preferable for a group 15 element.

In the amorphous semiconductor layer crystallization process of the present invention, it is preferable to perform laser irradiation, and in particular, laser annealing that irradiates a sample with high-energy pulsed light such as excimer laser to instantaneously melt and crystallize the material. It is preferable to use a method. According to this, since the amorphous semiconductor layer can be selectively melted and polycrystallized, the temperature rise of the insulating substrate can be kept low, and as a result, a low temperature process can be realized in the semiconductor substrate manufacturing process. .

The semiconductor substrate is preferably an active matrix substrate. According to this, it is possible to reduce characteristic defects such as active elements caused by non-uniformity of the impurity concentration, so that it is possible to improve the yield in the manufacturing process of the active matrix substrate. The present invention is also an active matrix substrate manufactured using the method for manufacturing a semiconductor substrate. According to this active matrix substrate, since the characteristic variation of each active element in the substrate surface is reduced, it can be suitably used for a display device such as an LCD or an organic EL display.

The semiconductor substrate is preferably a solar cell substrate. According to the method for manufacturing a semiconductor substrate of the present invention, since a uniform polycrystalline semiconductor layer can be easily formed on an insulating substrate having a large area, it can be suitably used for a method for manufacturing a solar cell substrate. The present invention is also a solar cell substrate manufactured using the method for manufacturing a solar cell substrate of the present invention.

According to the method for manufacturing a semiconductor substrate of the present invention, a step of forming an impurity highly doped amorphous semiconductor layer, a step of forming an impurity lightly doped or undoped amorphous semiconductor layer, and an amorphous semiconductor By performing the step of crystallizing the layer, a semiconductor substrate having a polycrystalline semiconductor layer with little variation in impurity concentration on the insulating surface can be manufactured. As a result, the defect characteristics of the semiconductor substrate due to the non-uniformity of the impurity concentration in the polycrystalline semiconductor layer can be reduced, so that the yield can be improved.

EXAMPLES Although an Example is hung up below and this invention is demonstrated still in detail with reference to drawings, this invention is not limited only to these Examples.

Example 1
A method for manufacturing an active matrix substrate using the method for manufacturing a semiconductor substrate of the present invention will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view showing a manufacturing process flow of the active matrix substrate of this embodiment. As shown in FIG. 1A, first, a silicon nitride layer 2 (thickness: 50 nm) / silicon oxide layer 3 (100 nm) was formed on a substrate 1 by plasma CVD. Thereafter, impurity doped a-Si layer 4 (5 nm) / undoped a-Si layer 5 (45 nm) were formed by plasma CVD. That is, the film thickness of the impurity-doped a-Si layer 4 is 1/10 of the entire a-Si layer (50 nm), but is not limited thereto. At this time, the undoped a-Si layer 5 is formed using a SiH ₄ / H ₂ mixed gas, and the impurity-doped a-Si layer 4 is formed by adding a small amount of B ₂ H ₆ gas to the SiH ₄ / H ₂ mixed gas. Formed by mixing. Thereby, the impurity-doped a-Si layer 4 becomes a P-type a-Si layer. In this embodiment, the silicon nitride layer 2 / silicon oxide layer 3 / impurity doped a-Si layer 4 / undoped a-Si layer 5 can be formed continuously in the same chamber. In this embodiment, impurity doped a-Si / undoped a-Si are formed in this order. For example, undoped a-Si / impurity doped a-Si, undoped a-Si / impurity doped a- You may form in order of Si / undoped a-Si or undoped a-Si / impurity doped a-Si / undoped a-Si / impurity doped a-Si / undoped a-Si. Furthermore, an a-Si layer with a reduced impurity doping amount may be formed instead of the undoped a-Si layer.

Next, the a-Si layer forming process of the present embodiment will be described in further detail. First, a SiH ₄ / H ₂ mixed gas and a small amount of B ₂ H ₆ gas were flowed into the a-Si formation chamber. At this time, the flow rates of the respective gases were SiH ₄ : 200 sccm and H ₂ : 1720 sccm, and diluted with H ₂ to make B ₂ H ₆ gas with a concentration of 100 ppm 80 sccm. After the flow rate of each gas was stabilized, plasma was applied to form the impurity-doped a-Si layer 4. Thereafter, the chamber was purged with H ₂ gas, N ₂ gas, or the like. This is for purging the B ₂ H ₆ gas in the chamber. Thereafter, a mixed gas of SiH ₄ (200 sccm) / H ₂ (1800 sccm) is flowed. At this time, B ₂ H ₆ gas is not flowed. After the flow rate was stabilized, plasma was applied to form an undoped a-Si layer 5.

Next, the formation process of the polycrystalline semiconductor layer of the present embodiment will be described in more detail. As shown in FIG. 1B, the impurity-doped a-Si layer 4 and the undoped a-Si layer 5 were irradiated with an excimer laser to polycrystallize the a-Si layer. At this time, boron, which is an impurity element, diffuses from the impurity-doped a-Si layer 4 to the undoped a-Si layer 5 to form a P-type polycrystalline semiconductor layer 6 in which impurities are uniformly dispersed. Thereafter, as shown in FIG. 1C, the polycrystalline semiconductor layer 6 was patterned and then a gate insulating film 7 was formed on the polycrystalline semiconductor layer 6. Further, a gate electrode layer was formed on the gate insulating film 7 and patterned to form the gate electrode film 8. Thereafter, as shown in FIG. 1D, by using the gate electrode film 8 as a mask, phosphorus or the like is implanted into the polycrystalline semiconductor layer 6 by an ion implantation apparatus or the like, and heat treatment is performed. A source region 9 and a drain region 10 are formed. As a result, an N-ch TFT was formed. Thereafter, as shown in FIG. 1E, formation / patterning of the interlayer insulating film 11, formation / patterning of the source electrode 12 and drain electrode 13, formation / patterning of the organic interlayer insulating film 14, formation / patterning of the pixel electrode 15 The active matrix substrate of this example was manufactured.

(Example 2)
Next, a method for manufacturing the active matrix substrate of Example 2 will be described. In this example, a silicon nitride layer (thickness: 50 nm) / silicon oxide layer (100 nm) was first formed on a substrate by plasma CVD. Thereafter, an impurity-doped a-Si layer (5 nm) / undoped a-Si layer (45 nm) were formed by plasma CVD. That is, the film thickness of the impurity-doped a-Si layer is 1/10 the film thickness of the entire a-Si layer (50 nm), but is not limited thereto. At this time, the undoped a-Si layer is formed using a SiH ₄ / H ₂ mixed gas, and the impurity-doped a-Si layer is formed by mixing a small amount of PH ₃ gas into the SiH ₄ / H ₂ mixed gas. did. Thereby, the impurity-doped a-Si layer becomes an N-type a-Si layer. In this embodiment, the silicon nitride layer / silicon oxide layer / impurity doped a-Si layer / undoped a-Si layer can be continuously formed in the same chamber. In this embodiment, impurity doped a-Si / undoped a-Si are formed in this order. For example, undoped a-Si / impurity doped a-Si, undoped a-Si / impurity doped a- You may form in order of Si / undoped a-Si or undoped a-Si / impurity doped a-Si / undoped a-Si / impurity doped a-Si / undoped a-Si. Furthermore, an a-Si layer with a reduced impurity doping amount may be formed instead of the undoped a-Si layer.

Next, the a-Si layer forming process of the present embodiment will be described in further detail. First, a SiH ₄ / H ₂ mixed gas and a small amount of PH ₃ gas were flowed into the a-Si formation chamber. At this time, the flow rate of each gas was SiH ₄ : 200 sccm, H ₂ : 1720 sccm, and diluted with H ₂ to make PH ₃ gas having a concentration of 100 ppm 80 sccm. After the flow rate of each gas was stabilized, plasma was applied to form an impurity-doped a-Si layer. Thereafter, the chamber was purged with H ₂ gas, N ₂ gas, or the like. This is for purging PH ₃ gas in the chamber. Thereafter, a mixed gas of SiH ₄ (200 sccm) / H ₂ (1800 sccm) is flowed. At this time, PH ₃ gas is not flowed. After the flow rate was stabilized, plasma was applied to form an undoped a-Si layer.

Next, the formation process of the polycrystalline semiconductor layer of the present embodiment will be described in more detail. The impurity-doped a-Si layer and the undoped a-Si layer were irradiated with an excimer laser to crystallize the a-Si layer. At this time, phosphorus, which is an impurity element, diffuses from the impurity-doped a-Si layer to the undoped a-Si layer, and an N-type polycrystalline semiconductor layer in which impurities are uniformly dispersed is formed. Thereafter, the polycrystalline semiconductor layer was patterned and formed, and then a gate insulating film was formed on the polycrystalline semiconductor layer. Further, a gate electrode layer was formed on the gate insulating film and patterned to form a gate electrode film. Thereafter, using the gate electrode film as a mask, boron or the like is implanted into the polycrystalline semiconductor layer with an ion implantation apparatus or the like, and heat treatment is performed, thereby forming a source region and a drain region which are P-type polycrystalline semiconductor layers. As a result, a P-ch TFT was formed. Thereafter, formation and patterning of an interlayer insulating film, formation and patterning of a source electrode and a drain electrode, formation and patterning of an organic interlayer insulating film, and formation and patterning of a pixel electrode were performed, and an active matrix substrate of this example was manufactured.

(Comparative Example 1)
Next, a method for manufacturing the active matrix substrate of Comparative Example 1 will be described. In this comparative example, first, silicon nitride (50 nm) / silicon oxide (100 nm) was formed on a substrate by plasma CVD. Thereafter, impurity-doped a-Si (50 nm) was formed by plasma CVD. The gas type and gas flow rate at this time were SiH ₄ : 200 sccm and H ₂ : 1792 sccm, and the flow rate of B ₂ H ₆ gas was 8 sccm, which is 1/10 of the flow rate of Example 1. On the other hand, the concentration of B ₂ H ₆ gas was diluted to 100 ppm by being diluted with H ₂ gas so as to be the same as in Example 1. Thereafter, an active matrix substrate of this comparative example was produced in the same manner as in Example 1.

Here, the results of comparing the sheet resistance and TFT characteristics of Example 1 and Comparative Example 1 are shown in FIGS. FIG. 3 shows the sheet resistance of the P-type polycrystalline semiconductor film of Example 1 and Comparative Example 1, and FIG. 4 shows the Vth value of the N-ch TFT. In Example 1, since the flow rate of the B ₂ H ₆ gas can be easily controlled, good sheet resistance and TFT characteristics without variation are shown. On the other hand, in Comparative Example 1, since the flow rate of B ₂ H ₆ gas is as very small as 1/10/10 sccm of Example 1, it is difficult to control the flow rate, and B ₂ H ₆ gas makes the substrate surface uniform. Flow did not flow and flow rate variation occurred, resulting in variations in sheet resistance and TFT characteristics.

(Comparative Example 2)
Next, a method for manufacturing the active matrix substrate of Comparative Example 2 will be described. In this comparative example, first, silicon nitride (50 nm) / silicon oxide (100 nm) is formed on a substrate by plasma CVD. Thereafter, impurity-doped a-Si (50 nm) is formed by plasma CVD. The gas type and gas flow rate at this time were SiH ₄ : 200 sccm and H ₂ : 1720 sccm, and the flow rate of B ₂ H ₆ gas was 80 sccm, the same flow rate as in Example 1. On the other hand, the concentration of B ₂ H ₆ gas was diluted with H ₂ gas to 10 ppm, which is 1/10 of Example 1. Thereafter, an active matrix substrate of this comparative example was prepared in the same manner as in Example 1.

Here, the results of comparing the resistance and TFT characteristics of Example 1 and Comparative Example 2 are shown in FIGS. FIG. 5 shows the sheet resistance of the P-type polycrystalline semiconductor film of Example 1 and Comparative Example 2, and FIG. 6 shows the Vth value of the N-ch TFT. In Comparative Example 2, since the flow rate of B ₂ H ₆ is the same as that in Example 1, flow rate control is easy, and thus flow rate variation within the same substrate surface was suppressed. However, since the concentration of B ₂ H ₆ is as low as 10 ppm, which is 1/10 of that of Example 1, the influence of B ₂ H ₆ adsorption on the gas piping of the chamber becomes significant, and as a result, the substrate Variation in sheet resistance and TFT characteristics.

FIG. 3 is a schematic cross-sectional view showing a manufacturing process flow of the active matrix substrate of Example 1. It is a cross-sectional schematic diagram of the semiconductor substrate obtained by the form of another manufacturing method which concerns on this invention. It is the figure which compared the sheet resistance of Example 1 and Comparative Example 1. FIG. 2 is a diagram comparing TFT characteristics of Example 1 and Comparative Example 1. FIG. It is the figure which compared the sheet resistance of Example 1 and Comparative Example 2. FIG. 6 is a diagram comparing TFT characteristics of Example 1 and Comparative Example 3. FIG. It is a cross-sectional schematic diagram which shows a part of manufacturing process flow of this invention. It is a structure schematic diagram of the CVD chamber which concerns on this invention.

Explanation of symbols

1: Substrate 2: Silicon nitride layer 3: Silicon oxide layer 4: Impurity doped a-Si layer 5: Undoped a-Si layer 6: Polycrystalline semiconductor layer 7: Gate insulating film 8: Gate electrode film 9: Source region 10 : Drain region 11: interlayer insulating film 12: source electrode 13: drain electrode 14: organic interlayer insulating film 15: pixel electrode 20: first base coat layer 21: second base coat layer 22: impurity low concentration doped or impurity undoped Amorphous semiconductor layer 23: highly doped impurity amorphous semiconductor layer 30: transfer chamber 31: first reaction chamber 32: second reaction chamber 33: third reaction chamber 34: fourth reaction chamber 35: introduction chamber 36: Preheating chamber

Claims (12)

A method of manufacturing a semiconductor substrate having a polycrystalline semiconductor layer containing impurities on an insulating surface,
The manufacturing method includes a step of forming an impurity-doped amorphous semiconductor layer having a concentration higher than that of the polycrystalline semiconductor layer;
Forming an impurity-doped amorphous semiconductor layer or an impurity-undoped amorphous semiconductor layer having a lower concentration than the polycrystalline semiconductor layer;
And a step of crystallizing the amorphous semiconductor layer. 2. The semiconductor according to claim 1, wherein a film thickness of the heavily doped impurity amorphous semiconductor layer is 1/50 or more and 1/2 or less with respect to a film thickness of the entire amorphous semiconductor layer. A method for manufacturing a substrate. 3. The film thickness of the impurity-doped amorphous semiconductor layer is 1/20 or more and 1/5 or less with respect to the film thickness of the entire amorphous semiconductor layer. A method for manufacturing a semiconductor substrate. The method for manufacturing a semiconductor substrate according to claim 1, wherein an impurity is not added to the uppermost layer of the amorphous semiconductor layer. The method of manufacturing a semiconductor substrate according to claim 1, wherein the impurity is a group 13 element. The method for manufacturing a semiconductor substrate according to claim 1, wherein the impurity is a group 15 element. The method for manufacturing a semiconductor substrate according to claim 1, wherein the amorphous semiconductor layer crystallization step performs laser irradiation. The method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is an active matrix substrate. An active matrix substrate manufactured using the method for manufacturing a semiconductor substrate according to claim 1. A liquid crystal display device comprising the active matrix substrate according to claim 9. The method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is a solar cell substrate. A solar cell substrate manufactured using the method for manufacturing a semiconductor substrate according to claim 11.

Images