JP2007072832A - Method and system for designing power supply wiring in integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply wiring design method and a power supply wiring design system that can reduce a workload of power line preprocessing before timing closure. <P>SOLUTION: Power line processing is divided into power line preprocessing S23 before timing closure S24 and power line postprocessing S25 after the timing closure S24. The power line preprocessing S23 comprises branch power line generation and main power line generation, and the power line postprocessing S25 comprises usable area extraction S25-1, wiring graphic generation S25-2 and connection relationship generation S25-3. Operations related to the power line preprocessing S23 before the timing closure S24 are the branch power line generation and main power line generation, and the usable area extraction S25-1, wiring graphic generation S25-2 and connection relationship generation S25-3 are after the timing closure S24. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method and system for designing power supply wiring in layout design of an integrated circuit, and more particularly, a method and system for designing power supply wiring in a core region of an LSI (Large Scale Integrated Circuit), and an I / O ring power supply. The present invention relates to a method and system for drawing power from a computer.

  Various methods relating to the layout method of the power supply wiring are known. For example, in Patent Document 1, when designing a power supply wiring in a layout design of a chip including a macroblock, a subset of the macroblock is found on the chip, and a trunk line of the power supply wiring and It is disclosed that the branch line wiring process is performed independently. For this reason, processing can be performed in parallel, and processing time can be shortened.

  Further, Patent Document 2 discloses that a power supply bus is wired, then the number of power supply lines and the wiring width are calculated, and then the power supply lines are wired.

  Conventionally, as disclosed in Patent Literature 1 and Patent Literature 2, power supply wiring is designed in a series of continuous processes. A general LSI layout design flow will be described below. Input the data into the dedicated layout software, and then execute the floor plan. In the floor plan, a chip size, a hard macro arrangement position, and a standard cell arrangement area are determined. The hard macro may be a known one, and may include, for example, RAM, IP, and the like. Following the floor plan process, a power supply wiring process is performed. In the power supply wiring process, the power supply line width is determined in consideration of the macro and the number of elements to be mounted, and ring-shaped power supply wiring is performed on the outer periphery of the core region. Thereafter, an optimum power supply trunk line is generated for connection to each macro and standard cell. Further, following the creation of the power supply trunk line, wiring to the power supply terminals of each hard macro and the power supply branch line in the standard cell area are connected to the power supply trunk line.

  After the power supply wiring process, a timing / close process is performed. The term “timing close” is also referred to as “timing closure”, but in this application “timing close” is used. Standard cells are placed in the timing / close process. Further, timing violation removal necessary for operating the LSI, such as drive capability change and clock synthesis, is performed. Further, as necessary, as a wiring convergence check, it is checked whether all signal lines can be connected without any problem. If the wiring does not converge, the power supply wiring is adjusted or the floor plan is changed according to the failure status, and the timing / closing operation is performed again. This operation is performed until it can be confirmed that the wiring converges.

After the timing / close operation is completed and all the signal lines are connected, layout verification is performed.
JP 2003-58592 A (paragraph number 0019, FIG. 1) Japanese Patent Laid-Open No. 06-029501 (paragraph numbers 0071 and 0072, FIG. 2)

  However, in the above LSI layout method, if the power supply wiring becomes impossible due to a partial change after execution or after completion of the layout during the timing / close operation, the chip size is increased or the generated power supply wiring It is necessary to redo the ground wiring. In other words, when power wiring becomes impossible, it is necessary to start over from the floor plan process. For this reason, the design period was prolonged. If a floor plan in which sufficient wiring resources are provided in advance is employed, an increase in chip size is caused, which results in an increase in manufacturing cost.

  Accordingly, an object of the present invention is to provide a power supply wiring design method for an integrated circuit without the above-mentioned problems.

  A further object of the present invention is to provide an integrated circuit power supply wiring design system which does not have the above-mentioned problems.

  A first aspect of the present invention is a first power line processing step for performing a part of the power line processing in the multilayer wiring structure, a timing / close processing step performed after the first power line processing step, A power supply wiring design method including at least a second power supply line processing step for performing the remaining processing of the power supply line processing after the timing / close processing step.

  According to a second aspect of the present invention, there is provided a first power supply line processing unit for performing a part of the power supply line processing in the multilayer wiring structure, and a timing close for performing a timing close processing after the first power supply line processing. To provide a power supply wiring design system including at least a processing unit and a second power supply line processing unit that performs the remaining processing of the power supply line processing after the timing / close processing.

According to the present invention, the power line processing is divided into power line pre-processing performed before the timing / close operation and power line post-processing performed after the timing / close operation. The power line pre-processing includes power branch generation and power trunk generation, while the power line post-processing includes available area extraction, wiring graphic generation, and connection relationship generation. The work related to the power line pre-processing performed before the timing and closing work is power branch generation and power trunk generation. Usable area extraction, wiring figure generation, and connection relation generation are the timing closing work. To do later. This means that the amount of work related to the power line pre-processing performed before the timing / close work is reduced. Reduction in the amount of work related to power line pre-processing greatly increases the degree of freedom for signal wiring. The large increase in the degree of freedom greatly reduces the possibility of floor plan correction for the purpose of wiring convergence.

(1) First Embodiment A first embodiment of the present invention provides a power supply wiring design method and a power supply wiring design system for an integrated circuit. FIG. 1 is a block diagram showing the configuration of the power supply wiring design system according to the first embodiment of the present invention.

(Configuration of power supply wiring design system)
The power supply wiring design system 1000 according to the first embodiment of the present invention includes a circuit information storage unit 110, a region information storage unit 120, a floor plan creation unit 130, a power supply line generation unit 140, and pattern wiring / timing control. Unit 150, usable area extraction unit 160, wiring pattern generation unit 170, connection relationship generation unit 180, and layout verification unit 190.

  The circuit information storage unit 110 stores data relating to circuit information of the integrated circuit. Data related to the circuit information of the integrated circuit is input by layout-dedicated software. The area information storage unit 120 stores data relating to an area that can be used for wiring of the power supply wiring in the core area. Each of the circuit information storage unit 110 and the region information storage unit 120 may be a known and usable storage device, and need not be limited to a specific storage device, but is typically configured by a library. Is possible.

  The floor plan creation unit 130 reads the circuit information from the circuit information storage unit 110, determines the hard macro and the core area of the chip on which the standard cell is arranged based on the circuit information, and then places the hard macro in the core area. At the same time, a standard cell arrangement region and a power supply trunk region are defined. FIG. 3 is a plan view showing the relationship between the core region and the I / O ring region before the floor plan process in the power supply wiring design method according to the first embodiment of the present invention. As shown in FIG. 3, the core region 210 is surrounded by the I / O ring region 220. The core region 210 is separated from the I / O ring region 220 via a margin 222. A plurality of I / O cells 221 are arranged in the I / O ring region 220. The plurality of I / O cells 221 are typically arranged at regular intervals. Each of the plurality of I / O cells 221 has a known configuration. The distance between the outer periphery 223 of the core region 210 and the inner periphery 224 of the I / O ring region 220 corresponds to the margin 222. The margin 222 is a margin for connecting the I / O cell 221 and the signal wiring. Therefore, the margin 222 is typically desirably 50 μm or more, but is not necessarily required to be 50 μm or more.

  FIG. 4 is a plan view showing the standard cell arrangement area and the hard macro arrangement area after the floor plan process in the power supply wiring design method according to the first embodiment of the present invention. The floor plan creation unit 130 determines the core region 210 in consideration of the margin 222 for connecting the signal wiring to the I / O cell 221, arranges the hard macro 240 in the core region 210, and A standard cell arrangement region 230 and a power supply trunk region 250 are defined in the region 210. The power supply main line region 250 extends so as to further divide the region of the core region 210 into a plurality of sections. A plurality of sections defined by the power supply main line area 250 are composed of a hard macro 240 and a standard cell arrangement area 230. The function and configuration of the floor plan creation unit 130 are known techniques. The floor plan shown in FIG. 4 is an example, and the present invention is not limited to this plan.

  The power supply line generation unit 140 receives information on the standard cell arrangement region 230 and the power supply main line region 250 from the floor plan creation unit 130, and in the standard cell arrangement region 230, the lowest layer or the lower two layers of the multilayer wiring layers Are used to generate a signal line, a power supply branch line 310, and a power supply trunk line. Furthermore, as shown in FIG. 4, the power supply line generation unit 140 generates a protrusion 320 corresponding to the end of the power supply branch line 310 outside the standard cell arrangement region 230.

  The power supply branch generation and the power supply trunk generation described above correspond to power supply wiring preprocessing. That is, while the power supply wiring process is performed in a series of continuous processes in the prior art, the power supply wiring process is performed separately in a power supply wiring pre-processing process and a power supply wiring post-processing process in the present invention. Therefore, the power supply line generation unit 140 performs a power supply wiring pretreatment process.

  The pattern wiring / timing control unit 150 performs timing and closing based on the power supply branch line generated by the power supply line generation unit 140, and further performs wiring convergence confirmation. Timing close and wiring convergence confirmation are performed in the same manner as in the prior art. In timing close, in addition to placing standard cells in the standard cell placement area 230, timing violations necessary to operate the LSI, such as driving capability change and clock synthesis, are removed. Check if all the wires can be connected without problems. If the wiring does not converge, after adjusting the power supply wiring by the power supply line generation unit 140 or changing the floor plan by the floor plan creation unit 130, the pattern wiring / timing control unit The timing is closed again by 150. These series of steps are performed until it is confirmed that all signal lines can be connected without any problem.

  After the timing / close work and the wiring convergence confirmation work by the pattern wiring / timing control unit 150 are completed, the power supply wiring post-processing step described above is performed. In the present invention, it is important to separate the power wiring process into a power wiring pre-processing process and a power wiring post-processing process. The power supply wiring post-processing step is performed by the available area extracting unit 160, the wiring figure generating unit 170, and the connection relationship generating unit 180.

  The available area extraction unit 160 extracts an available area in the core area 210. Specifically, the available area extraction unit 160 reads the area information from the area information storage unit 120, and uses the used area that has been used as the power supply branch line and the signal wiring for each wiring layer in the multilayer wiring structure. An extended area expanded from the completed area by the minimum wiring interval is extracted, and the used area and the extended area are subjected to exclusion processing on the core area to specify the available area.

  The wiring graphic generation unit 170 generates a wiring graphic based on the usable area specified by the usable area extracting unit 160 when the pattern wiring / timing control unit 150 confirms that all signal lines can be connected without any problem. I do. Specifically, the wiring graphic generation unit 170 generates a wiring graphic in which the width of the power supply line is changed for the portion extracted as the usable area. For example, the width of the power supply line may be twice the width of the power supply branch line. FIG. 5 is a partial plan view showing the I / O cell 221 and the power supply wiring region 330 in the vicinity of the I / O cell 221. FIG. 6 is a partial plan view showing the I / O cell 221 and the power supply wiring region 330 in the vicinity of the I / O cell 221. FIG. 7 is a partial plan view showing an example of a wiring pattern generated by changing the width of the power supply line with respect to the portion extracted as the usable area. By changing the width of the power supply line in the usable area, it is possible to recognize that the power supply line can be easily used visually. 5 and 6, the used power supply branch line 310 is shown in the power supply wiring region 330, but the available power supply line is not shown. On the other hand, in FIG. 7, not only the used power supply branch line 310 but also the available power supply line 340 is shown in the power supply wiring region 330. Since the usable power supply line 340 is changed to be wider than the used power supply branch line 310, it is easy to distinguish between the usable power supply line 340 and the used power supply branch line 310.

  When generating the wiring graphic, the wiring graphic generation unit 170 generates the wiring graphic so that the power wiring of the same wiring layer as the signal wiring extends in the same direction at the minimum line width interval, and at the same time, Thus, the power supply (VDD) and ground (GND) attributes are alternately applied. Further, the wiring pattern generation unit 170 uses the uppermost two layers in the boundary region between the core region 210 and the I / O cell 221 and has the same width as the line width used in the core region 210 and the minimum line spacing. In MD, a power supply wiring extension to the ring wiring on the I / O ring region 220 is generated. Specifically, the extension unit includes a top power supply layer 350, a top ground layer 360, a second upper power supply layer 370, and a second upper ground layer 380. FIG. 8 is a partial plan view showing the power supply wiring extension extending from the core region 210 to the ring wiring on the I / O ring region 220.

  As shown in FIG. 8, the wiring pattern generation unit 170 includes a plurality of power supply ring wirings 390 and a plurality of ground ring wirings extending along the first direction with the minimum line spacing MD in the I / O ring region 220. 394. The plurality of power supply ring wirings 390 and the plurality of ground ring wirings 394 extend above the I / O cell 221. Further, the wiring pattern generation unit 170 generates a plurality of power supply ring wirings 392 and a plurality of ground ring wirings 396 extending in the second direction with the minimum line spacing MD in the I / O ring region 220. . Here, the second direction is orthogonal to the first direction. The plurality of power supply ring wirings 392 and the plurality of ground ring wirings 396 extend above the I / O cell 221.

  Further, the wiring pattern generation unit 170 generates a plurality of second upper power supply layer expansion units 370 and a plurality of second upper ground layer expansion units 380. The plurality of second upper power supply layer extensions 370 and the plurality of second upper ground layer extensions 380 extend from the power supply wiring region 330 to above the plurality of power supply ring wirings 392 and the plurality of ground ring wirings 396. It extends along the second direction. The plurality of second upper power supply layer expansion units 370 and the plurality of second upper ground layer expansion units 380 are layers higher than the plurality of power supply ring wirings 392 and the plurality of ground ring wirings 396, The power supply ring wiring 390 and the plurality of ground ring wirings 394 are formed of the same layer. The plurality of second upper power supply layer extensions 370 and the plurality of second upper ground layer extensions 380 extend in the second direction, and include a plurality of power supply ring wirings 392 and a plurality of ground rings. It intersects the wiring 396 three-dimensionally. The plurality of second upper power supply layer extensions 370 and the plurality of second upper ground layer extensions 380 are alternately arranged in the first direction at the minimum line interval MD.

  Further, the wiring graphic generation unit 170 generates a plurality of uppermost power supply layer expansion units 350 and a plurality of uppermost ground layer expansion units 360. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 extend along the first direction from the power supply wiring region 330 to above the plurality of power supply ring wirings 390 and the plurality of ground ring wirings 394. Extend. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 include a plurality of power ring wires 390, a plurality of ground ring wires 394, a plurality of second upper power supply layer extensions 370, and a plurality of The second upper ground layer expansion unit 380 is a layer higher than the second upper ground layer expansion unit 380. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 extend along the first direction, and include a plurality of second upper power supply layer extensions 370 and a plurality of second power supply layers. The third upper ground layer extension 380, the plurality of power supply ring wirings 390, and the plurality of ground ring wirings 394 intersect three-dimensionally. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 are alternately arranged in the second direction at the minimum line interval MD.

  For example, in the case of a multilayer wiring structure including five layers, the power supply ring wiring 392 and the ground ring wiring 396 are configured by the third layer. The second upper power supply layer expansion unit 370, the second upper ground layer expansion unit 380, the power supply ring wiring 390, and the ground ring wiring 394 are configured in the fourth layer. The uppermost power supply layer extension 350 and the uppermost ground layer extension 360 are configured by the fifth layer.

  The connection relationship generation unit 180 generates the connection relationship of the power supply wiring after the wiring graphic generation by the wiring graphic generation unit 170 is completed. The connection relationship generation unit 180 considers the attribute 500 given to the generated wiring pattern, the power supply potentials of the power supply ring wirings 390 and 392 in the I / O ring region 220, and the ground potential of the ground ring wirings 394 and 396. A through hole is generated at the selected cross point among the cross points of the wiring figure. Specifically, as shown in FIG. 8, a through hole 400 is generated at a cross point between the uppermost power supply layer extension unit 350 and the second upper power supply layer extension unit 370. A through hole 410 is generated at the cross point between the uppermost power supply layer extension 350 and the power supply ring wiring 390. A through hole 420 is generated at a cross point between the uppermost ground layer extension 360 and the second upper ground layer extension 380. A through hole 430 is generated at the cross point between the uppermost ground layer extension 360 and the ground ring wiring 394. A through hole 440 is generated at the cross point between the second upper power supply layer extension 370 and the power supply ring wiring 392. A through hole 450 is generated at the cross point between the second upper ground layer extension 380 and the ground ring wiring 396. A through hole 460 is generated at a cross point between the power supply ring wiring 390 and the power supply ring wiring 392. A through hole 470 is generated at the cross point between the ground ring wiring 394 and the ground ring wiring 396. When the generation of the through holes 400, 410, 420, 430, 440, 450, 460, and 470 by the connection relation generation unit 180 is completed, the power supply wiring post-processing is completed.

  After the power supply wiring post-processing is completed, the layout verification unit 190 performs layout verification. This layout verification is the same as the conventional layout verification, and includes a design rule check and circuit equivalent verification for the layout.

  As described above, the power line processing is divided into power line pre-processing performed before the timing / close operation by the pattern wiring / timing control unit 150 and power line post-processing performed after the timing / close operation. The power line pre-processing includes power branch generation by the power line generation unit 140, while the power line post-processing includes use area extraction by the available area extraction unit 160 and wiring figure generation by the wiring figure generation unit 170. And connection relationship generation by the connection relationship generation unit 180. By dividing power line processing into power line pre-processing and power line post-processing, most of the power wiring that becomes an obstacle at the time of signal wiring is generated after timing and closing work, so the degree of freedom for signal wiring is greatly increased The possibility of floor plan correction for the purpose of wiring convergence can be greatly reduced.

  Further, as described above with reference to FIG. 8, the power supply ring wirings 390 and 392 and the ground ring wirings 394 and 396 are generated in the I / O ring region 220 so as to extend above the I / O cell 221. Furthermore, the uppermost power supply layer extension 350, the uppermost ground layer extension 360, the second upper power supply layer extension 370, and the second upper ground layer extension 380 are connected to the power supply ring wirings 390 and 392 and the ground. By extending to the upper side of the ring wirings 394 and 396, the power supply ring wirings 390 and 392 and the ground ring wirings 394 and 396 on the I / O ring region 220 can be used as a core ring, so that the core region 210 is made smaller accordingly. As a result, the chip size can be reduced.

  Hereinafter, the power supply wiring design method according to the present embodiment will be described. FIG. 2 is a flowchart showing the power supply wiring design method according to the first embodiment of the present invention.

(Power supply wiring design method)
In step S21, data related to the circuit information and area information of the integrated circuit is input by the dedicated software for layout, and the input data related to the circuit information is stored in the circuit information storage unit 110. On the other hand, data related to region information is stored in the region information storage unit 120.

  In step S22, the circuit information is read from the circuit information storage unit 110 by the floor plan creation unit 130, and based on the circuit information, the core area of the chip on which the hard macro and the standard cell are arranged is determined. A hard macro is arranged in the area, and a standard cell arrangement area and a power supply main line area are defined. As described above with reference to FIG. 3, the core region 210 is surrounded by the I / O ring region 220 in which a plurality of I / O cells 221 are arranged. The core region 210 is separated from the I / O ring region 220 via a margin 222. The floor plan creation unit 130 determines the core region 210 in consideration of the margin 222 for connecting the I / O cell 221 and the signal wiring, and the hard macro 240 is arranged in the core region 210, and the core A standard cell arrangement region 230 and a power supply trunk region 250 are defined in the region 210.

  In step S23, the power supply line generation unit 140 performs a power supply wiring pretreatment process. The power supply wiring pretreatment process includes the following two processes S23-1 and S23-2.

  In step S23-1, based on the information of the standard cell arrangement region 230 and the power supply main line region 250 defined by the floor plan creation unit 130, the power line generation unit 140 causes the multilayer wiring layer to be included in the standard cell arrangement region 230. The signal line, the power supply branch line 310, and the power supply trunk line are generated using the lowest layer or the lower two layers.

  In step S <b> 23-2, the power supply line generation unit 140 generates a protrusion 320 corresponding to the end of the power supply branch line 310 outside the standard cell arrangement region 230.

  In step S <b> 24, the timing and closing is performed by the pattern wiring / timing control unit 150 based on the power supply branch line generated by the power supply line generation unit 140. In timing close, in addition to placing standard cells in the standard cell placement region 230, timing violations necessary for operating the LSI, such as drive capability change and clock synthesis, are removed.

  In step S 24-1, a wiring convergence check is performed by the pattern wiring / timing control unit 150. If the wiring does not converge, after adjusting the power supply wiring by the power supply line generation unit 140 or changing the floor plan by the floor plan creation unit 130, the pattern wiring / timing control unit The timing is closed again by 150. These series of steps are performed until it is confirmed that all signal lines can be connected without any problem. These series of steps are performed until it is confirmed that all signal lines can be connected without any problem.

  In step S <b> 25, the power supply wiring post-processing step is performed by the available area extraction unit 160, the wiring pattern generation unit 170, and the connection relationship generation unit 180.

  In step S25-1, the available area extraction unit 160 extracts an available area in the core area 210. Specifically, the available area extraction unit 160 reads the area information from the area information storage unit 120, and for each wiring layer in the multilayer wiring structure, a used area that has been used as a power supply branch line and a signal wiring; An extended area expanded from the used area by the minimum wiring interval is extracted, and the used area and the extended area are excluded from the core area, and an available area is specified.

  In step S25-2, when it is confirmed by the pattern wiring / timing control unit 150 that all the signal lines can be connected without any problem, the wiring graphic generation unit is based on the usable area specified by the usable area extracting unit 160. In 170, a wiring figure is generated. Specifically, as shown in FIG. 7, the wiring graphic generation unit 170 generates a wiring graphic in which the width of the power supply line is changed for the portion extracted as the usable area. For example, the width of the power supply line may be twice the width of the power supply branch line. When generating a wiring graphic, the wiring graphic generation unit 170 generates a wiring graphic so that power wirings in the same wiring layer as the signal wiring extend in the same direction with a minimum line width interval, and at the same time, for the generated power wiring Thus, the attributes of the power supply (VDD) and the ground (GND) are alternately given. Further, in the boundary region between the core region 210 and the I / O cell 221, the uppermost two layers are used, and the I / O ring has the same width as that used in the core region 210 and the minimum line spacing MD. The power supply wiring extension part to the ring wiring on the region 220 is generated by the wiring figure generation part 170. Specifically, the extension section includes the uppermost power supply layer 350, the uppermost ground layer 360, the second upper power supply layer 370, and the second upper ground layer 380 shown in FIG.

  In step S <b> 25-3, after the wiring graphic generation by the wiring graphic generation unit 170 is completed, the connection relationship generation unit 180 generates a power supply wiring connection relationship. The connection relationship generation unit 180 considers the attribute 500 given to the generated wiring pattern, the power supply potentials of the power supply ring wirings 390 and 392 in the I / O ring region 220, and the ground potential of the ground ring wirings 394 and 396, As shown in FIG. 8, through holes 400, 410, 420, 430, 440, 450, 460, and 470 are generated at selected cross points among the cross points of the wiring pattern.

  In step S26, the layout verification unit 190 performs layout verification. This layout verification is the same as the conventional layout verification, and includes a design rule check and circuit equivalent verification for the layout.

  Although the width of the power supply line is twice that of the power supply branch line, this line width can be changed. In addition, this power supply wiring is connected in core size with wiring and through-holes in advance, then covered with signal lines, and the signal line and signal line minimum line spacing area and the signal line part are deleted by post-processing processing. Next, it is possible to connect the power supply system.

(effect)
As described above, the power line processing is divided into power line pre-processing performed before the timing / close operation by the pattern wiring / timing control unit 150 and power line post-processing performed after the timing / close operation. The power supply line preprocessing includes power supply branch generation and power supply trunk generation by the power supply line generation unit 140, while the power supply line postprocessing includes useable area extraction by the available area extraction unit 160 and wiring pattern generation unit 170. And a connection relation generation by the connection relation generation unit 180. The work related to the power line pre-processing performed before the timing / close work is the power branch generation and power trunk generation by the power line generation unit 140, the available area extraction by the available area extraction unit 160, and the wiring figure generation unit. The wiring graphic generation by 170 and the connection relation generation by the connection relation generation unit 180 are performed after the timing / close operation. This means that the amount of work related to the power line pre-processing performed before the timing and closing work is reduced. The reduction in the amount of work related to power line pre-processing greatly increases the degree of freedom for signal wiring. The large increase in the degree of freedom greatly reduces the possibility of floor plan correction for the purpose of wiring convergence.

  Further, as described above with reference to FIG. 8, the power supply ring wirings 390 and 392 and the ground ring wirings 394 and 396 are generated in the I / O ring region 220 so as to extend above the I / O cell 221. Furthermore, the uppermost power supply layer extension 350, the uppermost ground layer extension 360, the second upper power supply layer extension 370, and the second upper ground layer extension 380 are connected to the power supply ring wirings 390 and 392 and the ground. By extending to the upper side of the ring wirings 394 and 396, the power supply ring wirings 390 and 392 and the ground ring wirings 394 and 396 on the I / O ring region 220 can be used as a core ring, so that the core region 210 is made smaller accordingly. As a result, the chip size can be reduced.

  Furthermore, since the process (dummy metal generation process) for satisfying the pattern ratio in the wiring layer currently being carried out becomes unnecessary, the processing process is reduced.

(2) Second Embodiment A second embodiment of the present invention provides a power supply wiring design method and a power supply wiring design system for an integrated circuit having a plurality of power supply systems. In the first embodiment described above, a system and method for designing power supply wiring in an integrated circuit having a single power supply system are provided. In a second embodiment of the present invention, a system and method for designing power supply wiring in an integrated circuit having a plurality of different power supply systems is provided. FIG. 9 is a block diagram showing a configuration of a power supply wiring design system according to the second embodiment of the present invention.

(Configuration of power supply wiring design system)
A power supply wiring design system 1000 according to the second exemplary embodiment of the present invention includes a circuit information storage unit 110, a region information storage unit 120, a floor plan creation unit 130, a separated power attribute assignment dummy power supply wiring generation unit 132, A power line generation unit 140, a pattern wiring / timing control unit 150, an available area extraction unit 160, a wiring figure generation unit 170, a connection relationship generation unit 180, a separated power attribute assignment dummy power supply wiring deletion unit 182; A layout verification unit 190.

  The circuit information storage unit 110 stores data relating to circuit information of the integrated circuit. Data related to the circuit information of the integrated circuit is input by layout-dedicated software. The area information storage unit 120 stores data relating to an area that can be used for wiring of the power supply wiring in the core area. Each of the circuit information storage unit 110 and the region information storage unit 120 may be a known and usable storage device, and need not be limited to a specific storage device, but is typically configured by a library. Is possible.

  The floor plan creation unit 130 reads circuit information from the circuit information storage unit 110, and determines a core area of a chip in which a hard macro and a standard cell are arranged based on the circuit information. Furthermore, the floor plan creation unit 130 determines a separation region for separating a part of the core region. This separation region and the other core regions belong to different power supply systems. In other words, the power supply system to which the core region belongs and the power supply system to which the isolation region belongs are different from each other. Thereafter, a hard macro is arranged in the core region, and a standard cell arrangement region and a power supply trunk region are defined.

  FIG. 11 is a plan view showing the relationship among the core region, the I / O ring region, and the separation region before the floor plan process in the power supply wiring design method according to the second embodiment of the present invention. As shown in FIG. 11, the core region 210 is surrounded by the I / O ring region 220. The core region 210 is separated from the I / O ring region 220 via a margin 222. A plurality of I / O cells 221 are arranged in the I / O ring region 220. The plurality of I / O cells 221 are typically arranged at regular intervals. Each of the plurality of I / O cells 221 has a known configuration. Further, a part of the core region 210 is separated as a separation region 600. This isolation region belongs to a power supply system different from the power supply system to which the core region 210 belongs.

  FIG. 12 is a plan view showing a standard cell arrangement area, a hard macro arrangement area, and a different power supply system area after the floor plan process in the power supply wiring design method according to the second embodiment of the present invention. The floor plan creation unit 130 arranges the hard macro 240 in the core region 210 in consideration of a margin for connecting the I / O cell 221 and the signal wiring, and the standard cell arrangement region 230 and the core region 210 in the core region 210. A power trunk region 250 is defined. The power supply main line region 250 extends so as to further divide the region of the core region 210 into a plurality of sections. A plurality of sections defined by the power supply main line area 250 are composed of a hard macro 240 and a standard cell arrangement area 230. The function and configuration of the floor plan creation unit 130 are known techniques. The floor plan shown in FIG. 4 is an example, and the present invention is not limited to this plan. Performing a floor plan is a well-known technique.

  Further, the separated power attribute imparting dummy power wiring generation unit 132 generates a dummy power wiring 500 extending along the boundary between the separation region 600 and the core region 210, and the separated power attribute (SPLIT_POWER attribute) is assigned to the dummy power wiring 500. ). The width of the dummy power supply wiring 500 may be thicker than the width of a power supply branch line to be generated later, and may be, for example, twice the width of the power supply branch line. The separated power attribute imparting dummy power supply wiring 500 is a dummy wiring that is not finally used as a power supply line, so there is no problem even if it is short-circuited with a signal line.

  The power line generation unit 140 receives the information of the standard cell arrangement area 230 from the floor plan creation unit 130 and uses the lowest layer or the lower two layers of the multilayer wiring layer in the standard cell arrangement area 230 to supply the power branch line. 310 is generated.

  The power supply branch generation described above corresponds to power supply wiring preprocessing. That is, while the power supply wiring process is performed in a series of continuous processes in the prior art, the power supply wiring process is performed separately in a power supply wiring pre-processing process and a power supply wiring post-processing process in the present invention. Therefore, the power supply line generation unit 140 performs a power supply wiring pretreatment process.

  The pattern wiring / timing control unit 150 performs timing and closing based on the power supply branch line generated by the power supply line generation unit 140, and further performs wiring convergence confirmation. Timing close and wiring convergence confirmation are performed in the same manner as in the prior art. In timing close, in addition to placing standard cells in the standard cell placement area 230, timing violations necessary to operate the LSI, such as driving capability change and clock synthesis, are removed. Check if all the wires can be connected without problems. If the wiring does not converge, after adjusting the power supply wiring by the power supply line generation unit 140 or changing the floor plan by the floor plan creation unit 130, the pattern wiring / timing control unit The timing is closed again by 150. These series of steps are performed until it is confirmed that all signal lines can be connected without any problem.

  After the timing / close work and the wiring convergence confirmation work by the pattern wiring / timing control unit 150 are completed, the power supply wiring post-processing step described above is performed. In the present invention, it is important to separate the power wiring process into a power wiring pre-processing process and a power wiring post-processing process. The power supply wiring post-processing step is performed by the available area extracting unit 160, the wiring figure generating unit 170, and the connection relationship generating unit 180.

  The available area extraction unit 160 extracts an available area in the core area 210. Specifically, the available area extraction unit 160 reads the area information from the area information storage unit 120, and uses the used area that has been used as the power supply branch line and the signal wiring for each wiring layer in the multilayer wiring structure. An extended area expanded from the completed area by the minimum wiring interval is extracted, and the used area and the extended area are subjected to exclusion processing on the core area to specify the available area.

  The wiring graphic generation unit 170 generates a wiring graphic based on the usable area specified by the usable area extracting unit 160 when the pattern wiring / timing control unit 150 confirms that all signal lines can be connected without any problem. I do. Specifically, the wiring graphic generation unit 170 generates a wiring graphic in which the width of the power supply line is changed for the portion extracted as the usable area. For example, the width of the power supply line may be twice the width of the power supply branch line.

  When generating the wiring graphic, the wiring graphic generation unit 170 generates the wiring graphic so that the power wiring of the same wiring layer as the signal wiring extends in the same direction at the minimum line width interval, and at the same time, Thus, the power supply (VDD) and ground (GND) attributes are alternately applied. Further, the wiring pattern generation unit 170 uses the uppermost two layers in the boundary region between the core region 210 and the I / O cell 221 and has the same width as the line width used in the core region 210 and the minimum line spacing. In MD, a power supply wiring extension to the ring wiring on the I / O ring region 220 is generated. Specifically, the extension unit includes a top power supply layer 350, a top ground layer 360, a second upper power supply layer 370, and a second upper ground layer 380.

  The wiring pattern generation unit 170 generates a plurality of power supply ring wirings 390 and a plurality of ground ring wirings 394 extending along the first direction with the minimum line spacing MD in the I / O ring region 220. The plurality of power supply ring wirings 390 and the plurality of ground ring wirings 394 extend above the I / O cell 221. Further, the wiring pattern generation unit 170 generates a plurality of power supply ring wirings 392 and a plurality of ground ring wirings 396 extending in the second direction with the minimum line spacing MD in the I / O ring region 220. . Here, the second direction is orthogonal to the first direction. The plurality of power supply ring wirings 392 and the plurality of ground ring wirings 396 extend above the I / O cell 221.

  Further, the wiring pattern generation unit 170 generates a plurality of second upper power supply layer expansion units 370 and a plurality of second upper ground layer expansion units 380. The plurality of second upper power supply layer extensions 370 and the plurality of second upper ground layer extensions 380 extend from the power supply wiring region 330 to above the plurality of power supply ring wirings 392 and the plurality of ground ring wirings 396. It extends along the second direction. The plurality of second upper power supply layer expansion units 370 and the plurality of second upper ground layer expansion units 380 are layers higher than the plurality of power supply ring wirings 392 and the plurality of ground ring wirings 396, The power supply ring wiring 390 and the plurality of ground ring wirings 394 are formed of the same layer. The plurality of second upper power supply layer extensions 370 and the plurality of second upper ground layer extensions 380 extend in the second direction, and include a plurality of power supply ring wirings 392 and a plurality of ground rings. It intersects the wiring 396 three-dimensionally. The plurality of second upper power supply layer extensions 370 and the plurality of second upper ground layer extensions 380 are alternately arranged in the first direction at the minimum line interval MD.

  Further, the wiring graphic generation unit 170 generates a plurality of uppermost power supply layer expansion units 350 and a plurality of uppermost ground layer expansion units 360. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 extend along the first direction from the power supply wiring region 330 to above the plurality of power supply ring wirings 390 and the plurality of ground ring wirings 394. Extend. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 include a plurality of power ring wires 390, a plurality of ground ring wires 394, a plurality of second upper power supply layer extensions 370, and a plurality of The second upper ground layer expansion unit 380 is a layer higher than the second upper ground layer expansion unit 380. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 extend along the first direction, and include a plurality of second upper power supply layer extensions 370 and a plurality of second power supply layers. The third upper ground layer extension 380, the plurality of power supply ring wirings 390, and the plurality of ground ring wirings 394 intersect three-dimensionally. The plurality of uppermost power supply layer extensions 350 and the plurality of uppermost ground layer extensions 360 are alternately arranged in the second direction at the minimum line interval MD.

  The connection relationship generation unit 180 generates the connection relationship of the power supply wiring after the wiring graphic generation by the wiring graphic generation unit 170 is completed. The connection relationship generation unit 180 considers the attribute 500 given to the generated wiring pattern, the power supply potentials of the power supply ring wirings 390 and 392 in the I / O ring region 220, and the ground potential of the ground ring wirings 394 and 396. A through hole is generated at the selected cross point among the cross points of the wiring figure. Specifically, a through hole 400 is generated at a cross point between the highest power supply layer extension 350 and the second upper power supply layer extension 370. A through hole 410 is generated at the cross point between the uppermost power supply layer extension 350 and the power supply ring wiring 390. A through hole 420 is generated at a cross point between the uppermost ground layer extension 360 and the second upper ground layer extension 380. A through hole 430 is generated at the cross point between the uppermost ground layer extension 360 and the ground ring wiring 394. A through hole 440 is generated at the cross point between the second upper power supply layer extension 370 and the power supply ring wiring 392. A through hole 450 is generated at the cross point between the second upper ground layer extension 380 and the ground ring wiring 396. A through hole 460 is generated at a cross point between the power supply ring wiring 390 and the power supply ring wiring 392. A through hole 470 is generated at the cross point between the ground ring wiring 394 and the ground ring wiring 396. When the generation of the through holes 400, 410, 420, 430, 440, 450, 460, and 470 by the connection relation generation unit 180 is completed, the power supply wiring post-processing is completed.

  After the power supply wiring post-processing is completed, the separated power attribute assignment dummy power supply wiring deletion unit 182 finally deletes the separated power attribute assignment dummy power supply wiring 500 as a dummy wiring that is not used as a power supply line.

  Thereafter, the layout verification unit 190 performs layout verification. This layout verification is the same as the conventional layout verification, and includes a design rule check and circuit equivalent verification for the layout.

  Hereinafter, the power supply wiring design method according to the present embodiment will be described. FIG. 10 is a flowchart showing a power supply wiring design method according to the second embodiment of the present invention.

(Power supply wiring design method)
In step S21, data related to the circuit information and area information of the integrated circuit is input by the dedicated software for layout, and the input data related to the circuit information is stored in the circuit information storage unit 110. On the other hand, data related to region information is stored in the region information storage unit 120.

  In step S22, the circuit information is read from the circuit information storage unit 110 by the floor plan creation unit 130, and based on the circuit information, the core area of the chip on which the hard macro and the standard cell are arranged is determined. A hard macro is arranged in the area, and a standard cell arrangement area and a power supply main line area are defined. As described above with reference to FIG. 3, the core region 210 is surrounded by the I / O ring region 220 in which a plurality of I / O cells 221 are arranged. The core region 210 is separated from the I / O ring region 220 via a margin 222. The floor plan creation unit 130 determines the core region 210 in consideration of the margin 222 for connecting the I / O cell 221 and the signal wiring, and the hard macro 240 is arranged in the core region 210, and the core A standard cell arrangement region 230 and a power supply trunk region 250 are defined in the region 210.

  In step S22-1, the dummy power supply wiring generation unit 132 generates a dummy power supply wiring 500 that extends along the boundary between the isolation region 600 and the core region 210, and the dummy power supply wiring 500 receives the separated power supply. An attribute (SPLIT_POWER attribute) is given.

  In step S23, the power supply line generation unit 140 performs a power supply wiring pretreatment process. The power supply wiring pretreatment process includes the following two processes S23-1 and S23-2.

  In step S23-1, based on the information of the standard cell arrangement region 230 and the power supply main line region 250 defined by the floor plan creation unit 130, the power line generation unit 140 causes the multilayer wiring layer to be included in the standard cell arrangement region 230. The signal line, the power supply branch line 310, and the power supply trunk line are generated using the lowest layer or the lower two layers.

  In step S <b> 23-2, the power supply line generation unit 140 generates a protrusion 320 corresponding to the end of the power supply branch line 310 outside the standard cell arrangement region 230.

  In step S <b> 24, the timing and closing is performed by the pattern wiring / timing control unit 150 based on the power supply branch line generated by the power supply line generation unit 140. In timing close, in addition to placing standard cells in the standard cell placement region 230, timing violations necessary for operating the LSI, such as drive capability change and clock synthesis, are removed.

  In step S 24-1, a wiring convergence check is performed by the pattern wiring / timing control unit 150. If the wiring does not converge, after adjusting the power supply wiring by the power supply line generation unit 140 or changing the floor plan by the floor plan creation unit 130, the pattern wiring / timing control unit The timing is closed again by 150. These series of steps are performed until it is confirmed that all signal lines can be connected without any problem. These series of steps are performed until it is confirmed that all signal lines can be connected without any problem.

  In step S <b> 25, the power supply wiring post-processing step is performed by the available area extraction unit 160, the wiring pattern generation unit 170, and the connection relationship generation unit 180.

  In step S25-1, the available area extraction unit 160 extracts an available area in the core area 210. Specifically, the available area extraction unit 160 reads the area information from the area information storage unit 120, and for each wiring layer in the multilayer wiring structure, a used area that has been used as a power supply branch line and a signal wiring; An extended area expanded from the used area by the minimum wiring interval is extracted, and the used area and the extended area are excluded from the core area, and an available area is specified.

  In step S25-2, when it is confirmed by the pattern wiring / timing control unit 150 that all the signal lines can be connected without any problem, the wiring graphic generation unit is based on the usable area specified by the usable area extracting unit 160. In 170, a wiring figure is generated. Specifically, as shown in FIG. 7, the wiring graphic generation unit 170 generates a wiring graphic in which the width of the power supply line is changed for the portion extracted as the usable area. For example, the width of the power supply line may be twice the width of the power supply branch line. When generating a wiring graphic, the wiring graphic generation unit 170 generates a wiring graphic so that power wirings in the same wiring layer as the signal wiring extend in the same direction with a minimum line width interval, and at the same time, for the generated power wiring Thus, the attributes of the power supply (VDD) and the ground (GND) are alternately given. Further, in the boundary region between the core region 210 and the I / O cell 221, the uppermost two layers are used, and the I / O ring has the same width as that used in the core region 210 and the minimum line spacing MD. The power supply wiring extension part to the ring wiring on the region 220 is generated by the wiring figure generation part 170. Specifically, the extension section includes the uppermost power supply layer 350, the uppermost ground layer 360, the second upper power supply layer 370, and the second upper ground layer 380 shown in FIG.

  In step S <b> 25-3, after the wiring graphic generation by the wiring graphic generation unit 170 is completed, the connection relationship generation unit 180 generates a power supply wiring connection relationship. The connection relationship generation unit 180 considers the attribute 500 given to the generated wiring pattern, the power supply potentials of the power supply ring wirings 390 and 392 in the I / O ring region 220, and the ground potential of the ground ring wirings 394 and 396, As shown in FIG. 8, through holes 400, 410, 420, 430, 440, 450, 460, and 470 are generated at selected cross points among the cross points of the wiring pattern.

  In step S27, after the power supply wiring post-processing is completed, the separated power attribute assignment dummy power supply wiring deletion unit 182 deletes the separated power attribute assignment dummy power supply wiring 500 as a dummy wiring that is not finally used as a power supply line.

  In step S26, the layout verification unit 190 performs layout verification. This layout verification is the same as the conventional layout verification, and includes a design rule check and circuit equivalent verification for the layout.

  Although the width of the power supply line is twice that of the power supply branch line, this line width can be changed. In addition, this power supply wiring is connected in core size with wiring and through-holes in advance, then covered with signal lines, and the signal line and signal line minimum line spacing area and the signal line part are deleted by post-processing processing. Next, it is possible to connect the power supply system.

(effect)
According to the second embodiment described above, the following effects can be obtained in addition to the effects described in the first embodiment. In order to form a power source line after the isolated power source attribute imparting dummy power source wiring generation unit 132 forms the separated power source attribute imparting dummy power source wiring 500, the power source line in the core region 210 is assigned the separated power source attribute from the core region 210. There is no possibility of short-circuiting with the power supply line of the different power supply system region 700 separated by the dummy power supply wiring 500. For this reason, the analysis which generate | occur | produces by the short analysis between different power supplies becomes unnecessary. Furthermore, layout correction is not required. Therefore, the analysis time and the layout correction time that occur due to the short analysis between different power sources do not occur. This makes it possible to shorten the development TAT (Turn Around Time). Furthermore, even when designing a circuit having a plurality of different power supply systems, it is easy to carry out power supply wiring without any mistakes.

1 is a block diagram showing a configuration of a power supply wiring design system according to a first embodiment of the present invention. It is a flowchart which shows the power supply wiring design method which concerns on the 1st Embodiment of this invention. It is a top view which shows the relationship between the core area | region before a floor plan process in the power supply wiring design method which concerns on the 1st Embodiment of this invention, and an I / O ring area | region. It is a top view which shows the standard cell arrangement | positioning area | region and hard macro arrangement | positioning area | region after the floor plan process in the power supply wiring design method which concerns on the 1st Embodiment of this invention. It is a partial top view which shows an I / O cell and the power supply wiring area | region of this I / O cell vicinity. It is a partial top view which shows an I / O cell and the power supply wiring area | region of this I / O cell vicinity. In the power supply wiring design method according to the first embodiment of the present invention, it is a partial plan view showing an example of a wiring pattern generated by changing the width of the power supply line for the portion extracted as an available area. In the power supply wiring design method according to the first embodiment of the present invention, it is a partial plan view showing a power supply wiring extension extending from the core region to the ring wiring on the I / O ring region. It is a block diagram which shows the structure of the power supply wiring design system which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the power supply wiring design method which concerns on the 2nd Embodiment of this invention. It is a top view which shows the relationship between the core area | region before a floor plan process, an I / O ring area | region, and an isolation | separation area | region in the power supply wiring design method regarding the integrated circuit which has several different power supply systems which concern on the 2nd Embodiment of this invention. . FIG. 6 is a plan view showing a standard cell arrangement area, a hard macro arrangement area, and a different power supply system area after a floor plan process in a power supply wiring design method for an integrated circuit having a plurality of different power supply systems according to a second embodiment of the present invention. is there.

Explanation of symbols

1000 Power supply wiring design system 110 Circuit information storage unit 120 Area information storage unit 130 Floor plan creation unit 132 Separate power supply attribute assignment dummy power supply line generation unit 140 Power supply branch line generation unit 150 Pattern wiring / timing control unit 160 Available area extraction unit 170 Wiring Graphic generation unit 180 Connection relationship generation unit 182 Separate power supply attribute assignment dummy power supply wiring deletion unit 190 Layout verification unit 210 Core region 220 I / O ring region 221 I / O cell 222 Margin 223 Core region outer periphery 224 I / O ring region inner periphery 230 Standard cell placement area 240 Hard macro 250 Power trunk area 310 Power branch 320 Protrusion 330 Power wiring area 340 Available power branch 350 Top power layer extension 360 Top ground layer extension 370 Second upper power layer extension Part 38 0 Second upper ground layer extension 390 Power ring wiring 392 Power ring wiring 394 Ground ring wiring 396 Ground ring wiring 400 Through hole 410 Through hole 420 Through hole 430 Through hole 440 Through hole 450 Through hole 460 Through hole 470 Through hole 500 Isolated power supply attribute imparting dummy power supply wiring 600 Isolation region 700 Different power supply system region MD Minimum line spacing

Claims (16)

A first power line processing step for performing a part of the power line processing in the multilayer wiring structure;
A timing / close process performed after the first power line process;
A second power line processing step for performing the remaining processing of the power line processing after the timing / close processing step;
A power supply wiring design method including at least.   The power supply wiring design method according to claim 1, wherein the first power supply line processing step includes at least one of power supply branch line generation and power supply main line generation.   2. The power supply wiring design method according to claim 1, wherein the first power supply line processing step includes signal line generation, power supply branch line generation, and power supply trunk line generation using lower two layers in the multilayer wiring structure.   The power supply wiring design method according to claim 1, wherein the second power supply line processing step includes a step of extracting a region that can be used as a power supply line.   The usable area extracting step includes, for each wiring layer in the multilayer wiring structure, a used area that has been used in the first power supply line processing step, and a predetermined minimum wiring interval from the used area. The power supply wiring design according to claim 4, comprising: a step of extracting an extended region, and a step of specifying an available region by performing an exclusive process on the used region and the extended region with respect to the core region. Method.   6. The power supply wiring design according to claim 5, wherein the second power supply line processing step further includes a step of generating a wiring figure in which the width of the power supply line is changed with respect to the available area extracted by the available area extraction step. Method.   The power wiring design method according to claim 6, wherein the wiring graphic generation step is performed using upper two layers in the multilayer wiring structure.   The power supply wiring according to claim 6 or 7, wherein the second power supply line processing step further includes a step of generating a through hole at a selected cross point among the cross points of the wiring graphic generated by the wiring graphic generation step. Design method. A first power line processing unit for performing a part of the power line processing in the multilayer wiring structure;
A timing / close processing unit for performing timing / close processing after the first power line processing;
A second power line processing unit for performing the remaining processing of the power line processing after the timing and closing processing;
Including at least power wiring design system.   The power supply wiring design system according to claim 9, wherein the first power supply line processing unit performs at least one of power supply branch line generation and power supply main line generation.   The power supply wiring design system according to claim 9, wherein the first power supply line processing unit performs signal line generation, power supply branch line generation, and power supply trunk line generation using lower two layers in the multilayer wiring structure.   The power supply wiring design system according to claim 9, wherein the second power supply line processing unit includes a usable area extracting unit that extracts a usable area as a power supply line.   The usable area extracting unit is configured to use a used area that has been used in the first power supply line processing unit for each wiring layer in the multilayer wiring structure, and a predetermined minimum wiring interval from the used area. The power supply wiring design system according to claim 12, wherein an extended area is extracted, and an available area is specified by performing exclusive processing of the used area and the extended area with respect to the core area.   The power supply wiring design system according to claim 13, wherein the second power supply line processing unit generates a wiring pattern in which a width of a power supply line is changed with respect to the available area extracted by the available area extraction unit.   The power wiring design system according to claim 14, wherein the wiring graphic generation unit generates a wiring graphic using upper two layers in the multilayer wiring structure.   The power supply wiring design system according to claim 14 or 15, wherein the second power supply line processing unit generates a through hole at a selected cross point among the cross points of the wiring graphic generated by the wiring graphic generation unit.

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