JP2007067992A - Amplitude deviation modulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplitude deviation modulator in which power is saved and a matching circuit is unnecessary. <P>SOLUTION: An amplitude deviation modulator 100 includes an analog multiplier using npn transistors Q<SB>3</SB>and Q<SB>6</SB>for a constant current circuit and constituted by two pairs of npn transistors Q<SB>1</SB>and Q<SB>2</SB>and npn transistors Q<SB>4</SB>and Q<SB>5</SB>. A high frequency RF as a carrier wave is input to an emitter of the transistor Q<SB>3</SB>. A modulation signal V<SB>mod</SB>is input through a current mirror circuit 10 to bases of the transistors Q<SB>2</SB>and Q<SB>4</SB>. Furthermore, a modulated high frequency is output from a collector of the transistor Q<SB>2</SB>(Q<SB>5</SB>) by operating a transistor Q<SB>7</SB>as an emitter follower. In such a case, the current mirror circuit 10 forms a current mirror circuit from two p-channel MOSFETs Q<SB>8</SB>and Q<SB>9</SB>. In one terminal thereof, an n-channel MOSFET Q<SB>10</SB>of a fixed gate potential is connected in series and in another terminal thereof, a p-channel MOSFET Q<SB>11</SB>with the modulation signal V<SB>mod</SB>as a gate potential is connected in series. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an amplitude shift keying modulator using a high frequency as a carrier wave.

  The direct modulation type amplitude shift keying modulator (ASK) has an advantage that the modulation hardware is simple. However, in the system in which the baseband signal is modulated in a low frequency band and then up-converted, a local oscillator for that purpose is used. And a filter is required, and the hardware is usually complicated.

  Since signals are transmitted “by electric power” between the high frequency circuits, a matching circuit is required between the high frequency circuits. On the other hand, since a signal is transmitted “by voltage” in the low frequency circuit, a matching circuit is not required. Therefore, the present invention was completed by conceiving a high-frequency amplitude shift modulator that transmits a signal "by voltage" and confirming its characteristics. An object of the present invention is to provide a low-power consumption and small-sized amplitude shift modulator using a high frequency in the GHz band as a carrier wave.

  The invention according to claim 1 is an amplitude shift modulator, comprising: a first differential amplifying unit comprising a first transistor and a second transistor; an emitter / source of the first transistor; A first constant current circuit unit including a third transistor having a collector / drain connected to the emitter / source of the transistor and a first resistor connected to the emitter / source of the third transistor; A second differential amplifying unit composed of the first transistor and the fifth transistor; a sixth transistor having a collector / drain connected to the emitter / source of the fourth transistor and the emitter / source of the fifth transistor; A second constant current circuit unit comprising a second resistor connected to the emitter / source of the sixth transistor, and outputs a signal from the second transistor; The base / gate of the first transistor and the base / gate of the fifth transistor are connected, and the base / gate of the second transistor and the base / gate of the fourth transistor are connected. The collector / drain of the first transistor and the collector / drain of the fourth transistor are connected, the collector / drain of the second transistor and the collector / drain of the fifth transistor are connected, and the high frequency as the carrier wave is the third. The modulation signal is input to the base / gate of the second transistor via a current mirror circuit capable of current injection and extraction, and the collector / drain of the second transistor is connected to the seventh transistor's collector / drain. Connected to the base / gate of the transistor, Wherein the high frequency from the emitter / source is amplitude-shift keying is output. When bipolar transistors are used, the terms emitter, base, and collector are used, and for FETs, the terms source, gate, and drain are used.

  According to a second aspect of the present invention, the current mirror circuit includes the eighth and ninth transistors, which are the main components of the current mirror circuit, and the tenth transistor connected in series to the eighth transistor and having a fixed base / gate potential. And an eleventh transistor connected in series to the ninth transistor and having a modulation signal as a base / gate potential, and the emitter / source of the eleventh transistor is connected to the base / gate of the second transistor. It is connected. The invention according to claim 3 is characterized in that the high frequency is 0.5 GHz or more and the modulation signal is lower than the frequency of the high frequency.

  An analog multiplier is formed by the first to sixth transistors. If these transistors are small and have a small parasitic capacitance, an amplitude shift modulator with low power consumption and high frequency leakage can be obtained. Further, an emitter follower / source follower is formed by the seventh transistor. The seventh transistor can be larger than the first to sixth transistors forming the analog multiplier. The current mirror circuit enables current injection and current extraction by a modulation signal, and can be formed from four transistors.

  The high frequency (carrier wave) input to the emitter of the third transistor has a small phase rotation by using a transistor with low leakage of high frequency, input matching is achieved, and thereafter voltage transmission. Therefore, direct coupling to the next-stage emitter follower / source follower is possible. Further, power consumption can be reduced as compared with a double balance type such as a so-called Gilbert type multiplier. Even if the modulation operation is performed, the DC bias current from the constant voltage power source does not change, and the input impedance does not change. In addition, the on / off ratio can be increased, and high-speed modulation of about 100 MHz can be handled using a high frequency of 20 GHz as a carrier wave.

  Hereinafter, a specific circuit configuration of the present invention will be described with reference to circuit diagrams. In addition, this invention is not limited to a following example.

FIG. 1 is a circuit diagram showing the configuration of an amplitude shift key modulator 100 according to a specific embodiment of the present invention. The configuration of the amplitude shift keying modulator 100 is as follows. The seven npn transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ and Q ₇ are the first, second, third, fourth, fifth, This corresponds to 6th and 7th transistors, respectively. Further, the MOSFETs Q ₈ , Q ₉ , Q ₁₀ and Q ₁₁ correspond to the eighth, ninth, tenth and eleventh transistors, respectively, in the claims.

Six npn transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ and Q ₆ form an analog multiplier Mx. The four npn transistors Q ₁ , Q ₂ , Q _4, and Q ₅ have the same characteristics, and the two npn transistors Q ₃ and Q ₆ have the same characteristics. Six npn transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ and Q ₆ are respectively connected to the first, second, third, fourth, fifth and sixth transistors in the claims. Correspond.

Specifically, the collector of the npn transistor Q _{1 and} the collector of the npn transistor Q ₄ are connected to the constant voltage power supply V _CC . The collector of the npn transistor Q _{2 and} the collector of the npn transistor Q ₅ are connected to the fixed voltage V _CC via the resistor R _2C . The base of the npn transistor Q _{1 and} the base of the npn transistor Q ₅ are connected, and a base potential is applied from the constant voltage power supply V _CC via the resistor R _1B . Note that the source of the p-channel MOSFET 15 is also connected to the base of the npn transistor Q ₁ . A third bias (BIAS3) is applied to the gate of the p-channel MOSFET 15, and the drain is grounded. In addition, the base of the npn transistor Q _{2 and} the base of the npn transistor Q ₄ are connected, and the modulation signal V _mod is input through the current mirror circuit 10. The bases of npn transistor Q ₅ of the npn transistor Q _4, each capacitor C _4B and C _5B which the other end is grounded is connected.

The emitter of npn transistor Q _{1 and} the emitter of npn transistor Q ₂ are connected, and npn transistors Q ₁ and Q ₂ form a first differential amplifier. The collector of npn transistor Q ₃ is connected to the emitter of npn transistor Q ₁ . The base of the npn transistor Q _3, a first and a bias (BIAS1) is applied through a resistor R _3B, The capacitor C _3B other end of which is grounded is connected. Further, a resistor R _3E having the other end grounded is connected to the emitter of the npn transistor Q ₃ . an npn transistor Q ₃ and the resistor R _3E forms a first constant current circuit unit. A high frequency (RF) as a carrier wave is input to the emitter of the npn transistor Q ₃ through the input inductor L _i and the input capacitor C _i .

In exactly the same manner, the emitter of npn transistor Q _{4 and} the emitter of npn transistor Q ₅ are connected, npn transistors Q ₄ and Q ₅ form a second differential amplifier, and the npn transistor Q _{4 has} an emitter connected to npn the collector of the transistor Q ₆ is connected. The base of the npn transistor Q _6, the first and bias (BIAS1) is applied through a resistor R _6B, The capacitor C _6B whose other end is grounded is connected. Further, a resistor R _6E having the other end grounded is connected to the emitter of the npn transistor Q ₆ . The npn transistor Q ₆ and the resistor R _6E form a second constant current circuit portion.

The collector of the npn transistor Q ₂ is connected to the emitter follower unit 20. Emitter follower section 20 is configured npn transistors Q ₇ and Q _gc, inductor L ₇₈ and capacitor C _78, resistor R _GCE and R _GCB, an output capacitor C _o. The connection of each element of the emitter follower unit 20 is as follows. That is, the collector of the npn transistor Q ₂ is connected to the base of the npn transistor Q ₇ . The collector of the npn transistor Q ₇ is connected to the constant pressure power supply V _CC. The collector of the npn transistor Q _gc is connected to the emitter of the npn transistor Q ₇ via a parallel circuit of an inductor L ₇₈ and a capacitor C ₇₈ , and the other end of the resistor R _gcE is grounded to the emitter of the npn transistor Q _gc. Is connected. the base of the npn transistor Q _gc via a resistor R _GCB are applied gain control voltage V _gc is, high-frequency modulated via an output capacitor C _o from the emitter of the npn transistor Q ₇ is output.

The configuration of the current mirror circuit 10 is as follows. The sources of the p-channel MOSFETs Q ₈ and Q ₉ are connected to the constant voltage power supply V _cc , the gates are connected to each other, and are connected to the drain of the p-channel MOSFET Q ₈ . The drain of the n-channel MOSFET Q ₁₀ is connected to the drain of the p-channel MOSFET Q ₈ . The gate of the n-channel MOSFET Q ₁₀ is applied a second bias (BIAS2) is, and the source is grounded. On the other hand, the source of the p-channel MOSFET Q ₁₁ is connected to the drain of the p-channel MOSFET Q _9, the modulation signal V _mod is applied to the gate of the p-channel MOSFET Q ₁₁ , and the drain is grounded.

Apart from the above, a bias circuit 30 for generating first, second and third biases (BIAS1, BIAS2, BIAS3) from the constant voltage power supply V _CC is formed.

The current mirror circuit 10 of the amplitude shift modulator 100 is a circuit that performs “current injection and current extraction”. This will be described in comparison with other circuit configurations in FIG. FIG. FIG. 2A is a partial view of the current mirror circuit 10 and the first differential amplifier unit and the first constant current circuit unit of the amplitude shift modulator 100, FIG. B is a circuit diagram of an input circuit in which the current mirror circuit 10 is replaced with only an n-channel MOSFET ₉₀ and one resistor R ₉₀ , FIG. C is a circuit diagram of an input circuit in which a current mirror circuit is constituted by two p-channel MOSFETs 91 and 92 and a modulation signal V _mod is inputted by an n-channel MOSFET 93.

When the analog multiplier as described above is used, as an input circuit connected to the base of the second (and fourth) npn transistor Q ₂ (and Q ₄ ), for example, FIG. An input signal is applied to the gate, such as B, the constant voltage power supply V _CC is connected to the drain via the resistor R ₉₀ , the drain is connected to the base of the npn transistor Q ₂ (and Q ₄ ), and the source is grounded. A case where the configuration of the n-channel MOSFET 90 is used is assumed. However, FIG. In the configuration of B, it is “voltage injection”. Therefore, if the resistance R ₉₀ is decreased in order to cope with high-speed modulation such as the modulation signal V _{mod in} the MHz band, current consumption increases. On the contrary, when the resistance R ₉₀ is increased, the time constant increases, and a distorted modulated wave is generated as an output with respect to the modulated signal V _mod .

In addition, FIG. C connects the sources of the two p-channel MOSFETs 91 and 92 to the constant voltage power supply V _CC , connects the gates of the p-channel MOSFETs 91 and 92 to each other, and connects to the drain of the p-channel MOSFET 91 to form a current mirror circuit. The drain of the channel MOSFET 91 is connected to the drain of the n-channel MOSFET 93 whose modulation signal V _mod is applied to the gate, the source of the n-channel MOSFET 93 is grounded, and the drain of the p-channel MOSFET 92 is connected to the npn transistor Q ₂ (and Q ₄ ). It is a thing. FIG. In the configuration of C, “current injection” is possible, but since there is no “current extraction” path, a distorted modulated wave is output.

FIG. Configuration of A, the second (and fourth) to the drain of the p-channel MOSFET Q ₉ is connected to the base of the npn transistor Q ₂ (and Q ₄₎ of, the p-channel MOSFET Q _11, which modulation signal V _mod is applied to the gate Since the source is connected, a path for “current extraction” can be provided, and “current injection” and “current extraction” are possible. Thereby, it is possible to obtain an amplitude shift modulator that suppresses current consumption (power consumption) and does not smooth the modulated high frequency (carrier wave) that is output with respect to the modulation signal V _mod .

The advantages of the emitter follower unit 20 of the amplitude shift key modulator 100 are as follows. Analog multiplier Mx moiety, it can be directly coupled without matching circuit consisting of a capacitor, an inductor, and a transistor Q as a npn transistor Q ₇ by suppressing the leakage of high frequency by providing a parallel circuit of an inductor L ₇₈ and capacitor C _{78 1} to Q ₆ that can be used for larger size than is provided with the npn transistor Q _gc for the current control to the emitter of the npn transistor Q ₇ (the load side of the emitter follower section 20), the gain control voltage V that it can be made variable output power by _gc.

In FIG. 1, when the collector bias currents of the npn transistors Q _{1 to} Q ₆ are I _{c1 to} I _c6 , I _c3 = I _c6 , I _c3 = I _c1 + I _c2 , I _c6 = I _c4 + I _c5 . . Since the npn transistors Q _{1 to} Q ₆ have the same electrical characteristics, the operation is such that I _c5 decreases as I _c2 increases. The base bias potential (DC potential component) of the npn transistor Q ₇ of the emitter follower unit 20 is V _cc −R _2c (I _c2 + I _c5 ), and is constant as I _c2 + I _c5 = I _c1 + I _c2 = I _c3. Become.

[Characteristics of prototype]
In order to prototype the amplitude shift modulator 100, a 0.75 mm × 0.85 mm IC chip is formed by using 0.35 μm SiGeBiCMOS as an IC process, and this is formed into a 6-layer B ² it (Buried Bump Interconnection Technology). ) Mounted on a substrate and obtained the following characteristics.

When the constant voltage power supply V _CC is changed as follows, the corresponding consumption current I _CC is as follows.
V _CC (V) I _CC (mA)
1.8 3.75
2.0 6.45
2.5 7.68
3.3 7.74

The analog multiplier Mx does not change I _CC even when the modulation signal V _mod is changed. FIG. A, FIG. B, FIG. C shows the measurement results with a network analyzer 8510C manufactured by Agilent Technologies. Each of FIG. A is the input reflection coefficient with respect to the carrier frequency, FIG. B is the output reflection coefficient with respect to the carrier frequency, FIG. C is a graph showing the voltage dependence of the transfer coefficient with respect to the frequency of the carrier wave with respect to the modulation signal V _mod , and in each case, the constant voltage power supply V _CC is 2.0 V, the gain control voltage V _{gc is} 0.95 V, and the modulation signal the V _mod shows a case of changing at 0.05V intervals until 0 to 0.5 V.

FIG. A and FIG. From B, the reflection coefficient in the GHz band was not sufficiently small due to a slight misalignment, but the fluctuation of the input / output reflection coefficient with respect to the modulation signal V _mod was small, and the amplitude shift modulator 100 A circuit characteristic with a small change in impedance viewed from the circuit block before and after the pin was obtained.

FIG. From C, it was found that, for example, at 5.8 GHz, the difference between when the modulation signal V _mod is 0 V and 0.5 V is 38.2 dB, and a good on / off ratio can be obtained.

FIG. D is a graph obtained by measuring the transfer coefficient with respect to frequency while switching the gain control voltage V _gc . FIG. In the measurement and D, and the constant pressure supply V _CC 2.0 V, and 0.5V modulated signal V _mod, showing a case the gain control voltage V _gc was the case with 0.75V which was 0.95 V. For example, at 5.8 GHz, it was found that the difference between the gain control voltage V _gc of 0.95V and 0.75V was 12.1 dB, and a good variable width was obtained.

FIG. E is a graph showing input / output power characteristics of the amplitude shift modulator 100 when the constant-voltage power supply V _CC is switched to the above-described 1.8V, 2.0V, 2.5V, and 3.3V. The constant power supply V _CC was 2.0 V or higher, the input power Pin was −10 dBm or higher, and the output power Pout exceeded −10 dBm. When used as a modulator, it does not matter that the output power Pout with respect to the input power Pin is saturated.

On the other hand, the waveform of the output of the amplitude shift key modulator 100 was observed with an oscilloscope to determine whether it followed the modulation signal V _mod . Incidentally, as obtained by modulating the carrier wave of 5.8GHz amplitude shift which is the output of the modulator 100 at a modulation signal V _mod, and waveform observation for signals 40MHz is the difference in frequency of 5.84GHz which is not modulated. As a result, it was found that the high-speed modulation of 15 MHz was sufficiently followed.

  The present invention is compatible with ARIB STD-T75 standard of narrowband communication (DSRC), and can be applied to communication between a radio device installed on the roadside and a radio device mounted on a vehicle.

1 is a circuit diagram showing a configuration of an amplitude shift key modulator 100 according to an embodiment of the present invention. 2. A is a partial diagram of an input circuit for inputting the modulation signal V _mod of the amplitude shift modulator 100; B is a circuit diagram in which only an n-channel MOSFET ₉₀ and one resistor R ₉₀ are replaced; C is a circuit diagram of an input circuit in which a current mirror circuit is constituted by two p-channel MOSFETs 91 and 92 and a modulation signal V _mod is inputted by an n-channel MOSFET 93. The graph which shows the fluctuation | variation of the input reflection coefficient at the time of changing the modulation signal _Vmod of the amplitude shift modulator 100. FIG. The graph which shows the fluctuation | variation of the output reflection coefficient at the time of changing the modulation signal _Vmod of the amplitude shift modulator 100. FIG. The graph which shows the fluctuation | variation of the transmission coefficient at the time of changing the modulation signal _Vmod of the amplitude shift modulator 100 The graph figure which shows the fluctuation _| variation of the transmission coefficient at the time of changing the gain control voltage _Vgc of the amplitude shift modulator 100. FIG. 4 is a graph showing input / output power characteristics of the amplitude shift key modulator 100. FIG.

Explanation of symbols

100: amplitude shift keying (ASK) device 100
10: current mirror circuit Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₇ , Q _gc : npn transistor Q ₈ , Q ₉ , Q ₁₁ , 15, 91, 92: p-channel MOSFET
Q ₁₀ , 90, 93: n-channel MOSFET
20: Emitter follower unit 20

Claims (3)

An amplitude shift modulator,
A first differential amplifying section comprising a first transistor and a second transistor;
A third transistor having a collector / drain connected to the emitter / source of the first transistor and the emitter / source of the second transistor, and a first resistor connected to the emitter / source of the third transistor A first constant current circuit unit comprising:
A second differential amplifying unit comprising a fourth transistor and a fifth transistor;
A sixth transistor having a collector / drain connected to the emitter / source of the fourth transistor and the emitter / source of the fifth transistor, and a second resistor connected to the emitter / source of the sixth transistor A second constant current circuit unit comprising:
A seventh transistor that outputs a signal from the second transistor;
The base / gate of the first transistor and the base / gate of the fifth transistor are connected;
The base / gate of the second transistor and the base / gate of the fourth transistor are connected;
The collector / drain of the first transistor and the collector / drain of the fourth transistor are connected;
The collector / drain of the second transistor and the collector / drain of the fifth transistor are connected;
A high frequency which is a carrier wave is input to the emitter / source of the third transistor,
A modulation signal is input to the base / gate of the second transistor through a current mirror circuit capable of current injection and extraction,
The collector / drain of the second transistor is connected to the base / gate of the seventh transistor, and an amplitude shift modulated high frequency is output from the emitter / source of the seventh transistor. Amplitude shift modulator. The current mirror circuit is:
Eighth and ninth transistors which are main components of the current mirror circuit;
A tenth transistor connected in series to the eighth transistor and having a fixed base / gate potential;
An eleventh transistor connected in series to a ninth transistor and having the modulation signal as a base / gate potential;
The amplitude shift modulator according to claim 1, wherein the emitter / source of the eleventh transistor is connected to the base / gate of the second transistor. 3. The amplitude shift modulator according to claim 1, wherein the high frequency is 0.5 GHz or more, and the modulation signal is lower than the frequency of the high frequency.

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