JP2007067585A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver which breaks from a pseudo synchronizing state and reduces a processing time required for the breaking. <P>SOLUTION: A tentative synchronization discrimination section 24 calculates a relative phase difference between partial signals acquired by a partial signal acquisition section 22 to acquire a partial signal that is to correspond to a known signal, and estimate a position of a signal sequence to which the known signal is inserted. A pseudo synchronization discrimination section 26 discriminates whether the synchronization discriminated by the tentative synchronization discrimination section 24 is pseudo synchronization or normal synchronization. A frequency correction section 28 corrects a carrier frequency according to the notice from the pseudo synchronization discrimination section 26. A demodulation section 20 gives a frequency signal generated by the frequency correction section 28 to one of mixers (not shown) to correct the carrier frequency. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal processing technique, and more particularly to a receiving apparatus that determines synchronization of radio signals.

In a wireless communication system, a frequency offset occurs due to instability of a signal oscillated from a crystal or the like used in a transmission device and a reception device. In order to reduce the influence of the generated frequency offset, the phase error of the known signal included in the transmitted signal is estimated, and the phase of the signal is shifted by the estimated phase error. However, when the frequency offset is greater than or equal to ± 1 / 2M of the symbol rate (M is the number of phases in PSK (Phase Shift Keying) modulation), normal synchronization is not established and ± There may be a so-called pseudo-synchronization state where the synchronization state is fixed at a position shifted by 2π / M × symbol rate / 2π. Conventionally, in order to escape from this pseudo-synchronized state, error correction is performed, and whether or not pseudo-synchronization is achieved is determined based on the result. Further, when it is determined that the pseudo-synchronization is detected, the frequency shift is repeated until the pseudo-synchronization state is lost. (For example, see Patent Document 1)
Japanese Patent Laid-Open No. 11-308288 (FIG. 1)

  Under such circumstances, the present inventor has come to recognize the following problems. That is, a state in which a signal with very weak reception power is received at a terminal, as in a satellite communication system, and the reference phase in the carrier recovery loop is unnecessarily shifted due to the influence of the fading phenomenon and the Doppler phenomenon, That is, when a phase slip occurs, it takes a long time to make an accurate determination based on the reliability after error correction decoding.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a receiving apparatus capable of exiting the pseudo-synchronized state and reducing the processing time required for the exit.

  In order to solve the above problems, a receiving apparatus according to an aspect of the present invention includes an input unit that inputs a signal sequence in which a known signal is inserted at a constant period, and a carrier wave that is reproduced from the signal sequence that is input at the input unit In accordance with the reproduced carrier wave, a demodulator that demodulates the signal sequence, a partial signal acquisition unit that acquires a plurality of partial signals included in the signal sequence demodulated by the demodulator in the same cycle as the cycle, and acquired by the partial signal acquisition unit By calculating the relative phase difference between the partial signals, and estimating the position where the known signal was inserted, and the signal sequence demodulated by the demodulator was estimated by the temporary synchronization determiner Pseudo-synchronous determination that determines whether the frequency of the carrier wave reproduced by the demodulator is correct by integrating the absolute phase difference between the partial signal present at the position and the known signal that should correspond to the partial signal And the Obtain.

  Here, the “input unit for inputting a signal sequence” includes a configuration for transmitting the signal sequence input to the receiving apparatus, and includes, for example, a memory in which the signal sequence is stored. In addition, the “known signal” includes signals arranged according to a predetermined rule, and may be configured by the same symbol or may be configured by different symbols. That is, any information that is known on the receiving side may be used. In addition, the “partial signal” includes a portion that should correspond to a known signal in a signal series received through a wireless line. In other words, the partial signal is a known signal at the time of reception. In addition, the “relative phase” includes a phase difference between a plurality of phases, for example, a difference obtained by calculating a differential of the phases of known signals before and after. The “absolute phase” includes a phase in which a frequency offset is added to the phase of a reference carrier wave signal. “Determining whether or not the frequency of the regenerated carrier wave is correct” includes determining whether or not synchronization can be normally acquired, determining whether or not the state is a pseudo-synchronization state, and the like.

  According to this aspect, the synchronization processing is roughly established using the relative phase difference, and further, the strict synchronization is established using the absolute phase difference, so that the determination processing time of the pseudo synchronization state can be reduced.

  The temporary synchronization determination unit calculates the relative phase difference between the partial signals by calculating the differential of the phases of the front and rear partial signals among the plurality of partial signals acquired by the partial signal acquisition unit. A correlation calculation unit that calculates a correlation value between each phase difference calculated by the differential calculation unit and a relative phase difference between the known signals that should correspond to each phase difference, and a correlation calculation When the correlation value calculated in the section is larger than the threshold value related to temporary synchronization, the partial signal is acquired as a signal corresponding to the known signal, and the position where the partial signal exists is determined as the position where the known signal is inserted. And a known signal determination unit.

  Here, the “front and rear partial signals” include two partial signals arranged at positions separated from the signal sequence by the same length as the period. The “relative phase difference between known signals to be associated with each phase difference” includes the phase difference between the known signals before and after the known signal, which is the ideal value of the partial signal. "The correlation value between the phase difference and the relative phase difference between the known signals to be associated with each phase difference" includes a value indicating the relationship between the actual phase difference and the ideal phase difference, etc. For example, a difference between an actual phase difference and an ideal phase difference is included.

  According to this aspect, by calculating the phase difference between the partial signals, synchronization can be accurately acquired even when a phase slip occurs.

  When the correlation value calculated by the correlation calculation unit is smaller than the threshold value related to temporary synchronization, the temporary synchronization determination unit again performs a differential calculation unit on a partial signal different from a plurality of partial signals in the signal sequence. May calculate the differential. According to this aspect, the position of the known signal inserted on the transmission side can be accurately captured by repeating predetermined processing until provisional synchronization is established.

  The pseudo-synchronization determination unit includes a first measurement unit that measures a phase difference between a plurality of partial signals acquired by the temporary synchronization determination unit, and a phase difference between known signals corresponding to each of the plurality of partial signals. A difference between the measured phase differences is calculated, and the result is added together, and the sum measured by the second measurer is greater than the first threshold value for normal synchronization, or When the phase difference is smaller than the second threshold value smaller than the first threshold value, it is determined that the phase of the carrier wave reproduced by the demodulator is correct, while the total value is smaller than the first threshold value, and And a control unit that determines that the phase of the carrier wave reproduced by the demodulation unit is incorrect when it is larger than the second threshold value. According to this aspect, the pseudo synchronization can be accurately determined in a short time by calculating the difference between the known signal and the partial signal.

  The pseudo synchronization determination unit may further include a frequency correction unit that corrects the frequency of the carrier wave by shifting the frequency of the carrier wave when it is determined that the phase of the carrier wave reproduced by the demodulation unit is incorrect. . Here, “correcting the frequency” includes shifting the center frequency of the carrier wave. According to this aspect, it is possible to escape from the pseudo-synchronized state by correcting the phase.

  According to another aspect of the present invention, a receiving method reproduces a carrier wave from a signal sequence in which a known signal is inserted at a constant period, and demodulates the signal sequence according to the reproduced carrier wave, and demodulates the demodulating step. By acquiring a plurality of partial signals included in the signal sequence at the same period as the period, and calculating a relative phase difference between the partial signals acquired in the acquiring step, a partial signal corresponding to the known signal is obtained. A temporary synchronization determination step for obtaining a position at which a known signal is inserted and a partial signal existing at a position estimated by a temporary synchronization determination unit in the signal sequence demodulated in the demodulation step; and the partial signal Determining whether or not the phase of the carrier wave reproduced by the demodulator is correct by integrating the absolute phase difference with the known signal that should correspond to. According to this aspect, the pseudo-synchronous state determination processing time can be reduced by using both the relative phase difference and the absolute phase difference indicators.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  According to the present invention, it is possible to reduce the processing time required to escape from the pseudo-synchronized state and to escape.

  Before describing the present invention in detail, an outline will be described. Embodiments described herein relate generally to a terminal device that receives a low CNR (Carrier to Noise power Ratio) radio signal. In general, in a terminal device, when receiving a signal modulated by the M-phase PSK method, if a frequency offset occurs more than ± 1 / 2M of a symbol rate, normal synchronization is not secured. There may be a so-called pseudo-synchronization state where the synchronization state is fixed at a position shifted from the normal synchronization by ± 2π / M × symbol rate / 2π. Furthermore, there may be a phase slip state in which the reference phase in the carrier recovery loop is unnecessarily shifted due to the influence of the fading phenomenon and the Doppler phenomenon. In such a case, it is difficult to identify a known signal and acquire accurate synchronization.

  Assuming the case as described above, the terminal apparatus according to the present embodiment executes the synchronization process in two stages in order to capture the synchronization of the received radio signal. As a first step, the terminal device according to the present invention first uses the relative phase difference of known signals to remove the effect of phase slip and identifies the position where the known signal is inserted in the radio signal sequence. That is, the timing synchronization of the known signal is captured. Next, as a second stage, it is determined whether the captured synchronization is normal synchronization or pseudo-synchronization using the absolute phase difference of the known signal. In the present embodiment, in order to simplify the description, the radio signal modulation method is assumed to be BPSK (Binary Phase Shift Keying). Further, it is assumed that all known signals included in the radio signal sequence are composed of the same symbols. Details will be described later.

  FIG. 1 is a diagram illustrating a configuration example of a terminal device 200 according to an embodiment of the present invention. The terminal device 200 includes an antenna 1, an RF unit 2, an orthogonal detection unit 3, a signal processing unit 100, and a decoding unit 6. The antenna 1 receives a signal sequence transmitted from a partner that is performing communication. The RF unit 2 performs processing for converting a signal sequence received by the antenna 1 from an RF band to an intermediate frequency band signal using a filter or the like. The quadrature detection unit 3 performs frequency conversion processing from the intermediate frequency band to the baseband band on the signal sequence processed by the RF unit 2. As will be described in detail later, the signal processing unit 100 performs analog / digital conversion, synchronization processing, and the like on the signal sequence processed by the quadrature detection unit 3, and sends the signal sequence in which synchronization is captured to the decoding unit 6. Output.

  The decoding unit 6 performs a decoding process corresponding to the error correction encoding process executed on the transmission side on a sequence excluding the known signal among the signal sequences whose synchronization is captured by the signal processing unit 100. For example, when an interleaving process for rearranging the order of signal sequences is performed on the transmission signal sequence on the transmission side, the decoding unit 6 executes a rearrangement process opposite to the interleaving process for the received signal sequence. The deinterleaving process is executed. On the transmission side, when convolutional coding is performed on the signal sequence, the decoding unit 6 performs Viterbi decoding on the received signal sequence to estimate the transmitted signal.

  FIG. 2 is a diagram illustrating a configuration example of the signal processing unit 100 of FIG. The signal processing unit 100 includes a demodulation unit 20, a partial signal acquisition unit 22, a temporary synchronization determination unit 24, a pseudo synchronization determination unit 26, a frequency correction unit 28, and a buffer 40.

  Here, the signal series 50 processed by the signal processing unit 100 is configured as shown in FIG. FIG. 3 is a diagram illustrating a configuration example of a signal sequence received by the signal processing unit 100 in FIG. The horizontal axis represents time. The receiving unit 10 receives the reception signal shown in FIG. 3, that is, the signal sequence. This signal series includes a known signal 52 and a data signal 54. The known signal 52 is inserted into the signal series for each period L. FIG. 3 shows a case where one known signal 52 is composed of a plurality of symbols, but is not limited to this, and may be composed of one symbol. Note that the number of symbols included in the known signal 52 and the data signal 54 is L. A signal sequence composed of an integral multiple of L is expressed as a frame.

  Further, the known signal 52 received by the signal processing unit 100 is generally different from the transmitted known signal due to a continuous error generated in the transmission path or thermal noise generated in the RF unit 2 or the like. Therefore, in the following description, “known signal 52” will be described as “partial signal corresponding to known signal 52” or simply “partial signal”.

  Returning to FIG. The demodulator 20 reproduces a carrier wave from the signal sequence 50 and demodulates the signal sequence 50 according to the reproduced carrier wave. Specifically, synchronous detection using a Costas loop or the like is performed on the signal sequence 50 input from the quadrature detection unit 3 to reproduce the carrier wave. Further, processing such as band limitation processing, automatic gain control processing, DC offset correction, phase estimation, and the like is executed on the signal sequence 50 and output to the partial signal acquisition unit 22.

  Here, with reference to FIGS. 4A to 4C, a symbol point arrangement of a signal sequence subjected to BPSK modulation after reproducing a carrier wave will be described. 4A to 4C are diagrams showing examples of signal point arrangement of the signal sequence output from the demodulator 20 of FIG. FIG. 4A is a diagram showing a signal point arrangement when ideal carrier wave reproduction is performed. FIG. 4B is a diagram showing the signal point arrangement when the phase error θ resulting from the frequency offset remains. FIG. 4C is a diagram showing the signal point arrangement when the signal points A and B are shifted from each other by π. In other words, it shows that the phase error θ due to the frequency offset remains in the carrier wave reproduced by an integral multiple of ± π.

  Even in the case of the signal point arrangement as shown in FIG. 4B, the state shown in FIG. 4A can be corrected by using the demodulator 20 or the like. However, in the case of the signal point arrangement as shown in FIG. 4C, the demodulator 20 itself cannot recover. Correction is performed by the decoding unit 6. In addition, the state of FIG.4 (c) is generally called a phase slip or cycle slip. The phase slip is a phenomenon in which the reference phase rotates in a short time. In the case of BPSK modulation, the phase slip rotates by an integral multiple of 180 degrees. That is, the sign is repeatedly inverted. In such a case, even if error correction decoding is used, correct decoding cannot be performed, and it is necessary to relieve by differential processing described later.

  Returning to FIG. The partial signal acquisition unit 22 acquires a plurality of partial signals included in the signal series 50 demodulated by the demodulation unit 20 at the same cycle as the cycle. Specifically, a signal sequence is acquired over one frame and written into the buffer 40. At this time, the data signal is also written into the buffer 40 together with the partial signal. The partial signal acquisition unit 22 writes all the signal sequences to the buffer 40 and then notifies the provisional synchronization determination unit 24 that the writing has been completed.

  Here, the buffer 40 into which the partial signal acquisition unit 22 writes the signal series has a configuration as shown in FIG. FIG. 5 is a diagram illustrating a configuration example of the buffer 40 of FIG. The partial signal acquisition unit 22 writes the signal sequence from the upper left of the buffer 40 to the right when writing the signal series into the buffer 40. The partial signal acquisition unit 22 writes to the end of a certain row of the buffer 40 and then writes to the next row in the same manner. In addition, the decoding unit 6 reads a signal sequence other than the partial signal corresponding to the known signal from the buffer 40 after receiving notification that the normal synchronization has been acquired by the pseudo synchronization determination unit 26 described later. When reading the signal sequence from the buffer 40, the decoding unit 6 reads the signal sequence from the upper left of the buffer 40 downward. The partial signal acquisition unit 22 reads the next column in the same manner after reading a certain column of the buffer 40 to the end. By using the buffer 40 in this way, deinterleaving processing can be realized efficiently.

  By setting the size of one row of the buffer 40 to the same L as the known signal insertion period in the signal sequence, the known signals 52 can be positioned in the same column as shown in FIG. In FIG. 5, since it is assumed that the frame is synchronized, the partial signal corresponding to the known signal appears at the head of the column. When frame synchronization is not achieved, the partial signal does not exist in the first column as shown in FIG. 5, but does not change in that it is located in the same column. Here, the frame synchronization includes, for example, determining the position of the partial signal sequence in the temporary synchronization determination unit 24.

  Here, in order to simplify the description, the configuration example of the buffer 40 in FIG. 5 has been described as being two-dimensionally arranged, but the actual buffer 40 may have a one-dimensional configuration. . Each row may be stored in a physically separated memory as long as each row is associated with a pointer or the like.

  Returning to FIG. The temporary synchronization determination unit 24 calculates a relative phase difference between the partial signals acquired by the partial signal acquisition unit 22, thereby acquiring a partial signal that should correspond to the known signal and a position where the known signal is inserted. And the pseudo-synchronization determination unit 26 is notified of the position as a synchronization position. Specifically, it is estimated in which column of the buffer 40 the partial signal exists in the signal sequence written in the buffer by the partial signal acquisition unit 22. In the estimation, a relative phase difference between the previous and next rows is calculated for each column. Further, the relative phase difference of the known signal that is the ideal value of the partial signal is calculated in the same manner. Further, the correlation of the phase difference between the two is obtained for each partial signal and summed. Finally, the timing synchronization of the partial signals is estimated by comparing the sum and the threshold value. Details will be described later.

  The pseudo synchronization determination unit 26 determines whether the synchronization determined by the temporary synchronization determination unit 24 is pseudo synchronization or normal synchronization. The determination is performed by integrating the absolute phase difference between the partial signal existing in the position estimated by the temporary synchronization determination unit 24 and the known signal corresponding to the partial signal in the signal sequence 50 in the buffer 40. Executed. Specifically, the difference between the phase of the partial signal and the phase of the known signal is calculated for each row in the buffer 40. Further, the differences for all the rows are added together, and the result is compared with a threshold value to determine whether the synchronization is normal synchronization or normal synchronization. When it is determined that it is pseudo-synchronization, the frequency correction unit 28 is notified of pseudo-synchronization and the frequency offset amount to be corrected. On the other hand, when it is determined that the synchronization is normal, the fact is notified to the decoding unit 6 and execution of decoding processing such as interleaving processing is started.

  The frequency correction unit 28 corrects the frequency of the carrier according to the notification from the pseudo synchronization determination unit 26. Specifically, a frequency signal corresponding to the amount of frequency to be corrected is generated and output to the demodulator 20. The demodulator 20 corrects the frequency of the carrier wave by inputting the frequency signal generated by the frequency corrector 28 to one of frequency converters such as a mixer (not shown).

  The buffer 40 is a memory space that holds a signal sequence written by the partial signal acquisition unit 22 or the like. The buffer 40 is also used as a temporary memory when the temporary synchronization determination unit 24 and the pseudo synchronization determination unit 26 determine the synchronization of the partial signals. The buffer 40 may have a different start address for writing for each target to be written. Further, the buffer 40 may not be configured from a single memory.

  FIG. 6 is a diagram illustrating a configuration example of the partial signal acquisition unit 22 of FIG. The partial signal acquisition unit 22 includes a writing unit 62 and a reliability acquisition unit 64. The writing unit 62 writes the signal series demodulated by the demodulating unit 20 into the buffer 40.

  The reliability acquisition unit 64 acquires the reliability of partial signals corresponding to known signals included in the signal sequence demodulated by the demodulation unit 20 and sequentially writes them in the buffer 40. Here, the reliability includes a value indicating the probability of the partial signal, and includes, for example, a soft decision value of the partial signal, a value indicating a correlation between the partial signal and the known signal, and the like. Further, it may be a value indicating the certainty of the phase of the partial signal. When one partial signal is composed of a plurality of symbols, the reliability of the partial signal may be acquired by adding the reliability of the plurality of symbols included in the partial signal.

FIG. 7 is a diagram illustrating a configuration example of the temporary synchronization determination unit 24 of FIG. The provisional synchronization determination unit 24 includes a differential calculation unit 30, a correlation calculation unit 32, and a known signal determination unit 36. The differential calculation unit 30 calculates the relative phase difference between the partial signals by calculating the differential of the phases of the front and rear partial signals among the plurality of partial signals acquired by the partial signal acquisition unit 22. To do. The phase θ is calculated as follows using the I component and Q component of the symbol included in the partial signal. When the signal sequence is modulated by BPSK and no noise or the like is included, the phase θ of the partial signal is 0 or π.
θ = tan ⁻¹ (Q / I) (1)

  Here, “calculate the difference between the front and rear partial signals” means the difference between the phase of a certain partial signal in the buffer 40 and the phase existing in the upper row or the lower row of the partial signal. It means calculating.

  The correlation calculation unit 32 calculates a correlation value between each phase difference calculated by the differential calculation unit 30 and a relative phase difference between known signals that should correspond to each phase difference. The “relative phase difference between the known signals to be associated with the respective phase differences” includes the phase difference between the known signals before and after the known signals corresponding to the respective partial signals. Specifically, in all the rows in the buffer 40, the phase differences between the partial signals existing in the preceding and succeeding rows or between the known signals are calculated. Further, the correlation value is obtained by adding the calculated phase differences in all rows. When the partial signals corresponding to the known signal are all composed of the same symbol “0”, the calculated phase θ becomes the correlation value as it is. Specific examples will be described later.

  The known signal determination unit 36 acquires the partial signal as a signal corresponding to the known signal when the correlation value calculated by the correlation calculation unit 32 is larger than the threshold value related to temporary synchronization, and determines the position where the partial signal exists. It is determined as a position where a known signal is inserted. When the correlation value calculated by the correlation calculation unit 32 is smaller than the threshold value related to temporary synchronization, the temporary synchronization determination unit 24 again applies a difference to a partial signal different from a plurality of partial signals in the signal sequence 50. The dynamic calculation unit 30 calculates the differential. Here, “different partial signals” include other columns in the buffer 40. In other words, if the column determined by the known signal determination unit 36 is not a partial signal that should correspond to a known signal, whether or not the column is a partial signal that should correspond to a known signal for another column. Determine. The “different partial signal” when the partial signal that should correspond to the known signal is composed of a plurality of symbols is a part of the partial signal that has already been determined and a signal that has not been determined. Including. For example, when it is determined that the first column and the second column are not partial signals, the columns to be determined next are the second column and the third column. At this time, the second and subsequent processes can be shortened by holding the differential result for the second column in which the determination is made first.

  FIG. 8 is a diagram illustrating a configuration example of the pseudo-synchronization determination unit 26 of FIG. The pseudo synchronization determination unit 26 includes a measurement unit 38 and a control unit 42. The measurement unit 38 measures the phase difference between the plurality of partial signals acquired by the temporary synchronization determination unit 24 and the known signals corresponding to each of the plurality of partial signals. As a result of the measurement by the measurement unit 38, the control unit 42 has a phase difference larger than the first threshold value related to normal synchronization or smaller than the second threshold value smaller than the first threshold value. If it is smaller, it is determined that the phase of the carrier wave reproduced by the demodulator 20 is correct. On the other hand, when the phase difference is smaller than the first threshold value and larger than the second threshold value, it is determined that the frequency of the carrier wave reproduced by the demodulator 20 is incorrect, that is, pseudo synchronization.

  In general, when there is no noise or the like, the phase of the partial signal matches the phase of the known signal. However, in a situation where noise or the like occurs, the phases of the partial signal and the known signal do not completely match. Further, when the synchronization captured by the temporary synchronization determination unit 24 is pseudo-synchronization, the phases of both are remarkably different. Therefore, the phase difference between the two is added up, and if the result is within the range of the first threshold value and the second threshold value, it is determined that it is pseudo-synchronous. If it is larger than the second threshold value, it can be solved by sign inversion processing.

  For example, it is assumed that the number of partial signals measured by the measurement unit is 8. Further, it is assumed that the first threshold is “3” and the second threshold is “6”. At this time, it is assumed that the phase difference between the eight partial signals and the known signal corresponding to each partial signal is two different. In this case, since it is smaller than the first threshold “3”, it is determined that the synchronization is normal. On the other hand, when five are different, since it is larger than the first threshold “3” and smaller than the second threshold “6”, it is determined to be pseudo-synchronization. Further, if there are nine differences, it is larger than the second threshold value “6”, so that it is regarded as normal synchronization after the process of inverting the sign of all the partial signals.

  Here, the operation of the signal processing unit 100 will be described with reference to FIGS. 9 and 10A to 10D. FIG. 9 is a flowchart showing an operation example of the signal processing unit 100 of FIG. First, the demodulator 20 performs demodulation processing such as carrier wave recovery processing on the signal sequence sent from the quadrature detector 3 (S10). Next, the partial signal acquisition unit 22 writes the signal series in the buffer 40 (S12). Next, the temporary synchronization determination unit 24 calculates a differential for a certain column in the buffer 40 (S14). The differential is similarly calculated for the known signal. Further, the temporary synchronization determination unit 24 calculates the calculated correlation between the two differentials (S16). Further, the provisional synchronization determination unit 24 adds the correlation results by the number of columns for which the differential is calculated (S18). Further, the provisional synchronization determination unit 24 compares the threshold value related to provisional synchronization with the correlation result to determine whether or not the column for which the differential is calculated is a partial signal corresponding to a known signal, that is, frame synchronization ( S20).

  If the threshold value is not exceeded as a result of the determination (N in S20), the temporary synchronization determination unit 24 shifts the column in the buffer 40 (S22), and again calculates the differential (S14). . As a result of the determination, when the threshold value is exceeded (Y in S20), it can be regarded as temporary synchronization. In this case, the pseudo synchronization determination unit 26 calculates an absolute phase difference (S24). Next, the pseudo-synchronization determination unit 26 determines whether or not the sum of the absolute phase differences is within a certain threshold range (S26). If it is determined that it is within the range, it is determined that the synchronization is false (N in S26), and the pseudo synchronization determination unit 26 causes the frequency correction unit 28 to perform frequency correction. If it is determined to be out of the range, it is determined to be normal synchronization (Y in S26). Although not shown in FIG. 9, after normal synchronization is established, the decoding unit 6 performs decoding processing such as interleaving processing and Viterbi decoding processing.

  10A to 10D are diagrams showing examples of the phase of the partial signal stored in the buffer 40 and the differential result. Here, it is assumed that the partial signal is composed of two symbols of x and y. In order to simplify the description, it is assumed that there are no components such as noise. FIGS. 10A and 10B show a case where the signal processing unit 100 receives a known signal composed of symbols having the same x and y in the same row and stores them in the buffer 40. Here, FIG. 10A is a diagram showing a case of normal synchronization. FIG. 10B is a diagram showing a case of pseudo synchronization.

  First, in order to remove the influence of the phase slip, in FIG. 10A, the differential is calculated for each of the first to fourth rows. For x, the difference between “0” in the first row and “π” in the second row is calculated to be “1”. Here, in the differential calculation, the phase of one row is subtracted from the phase of the other row and then divided by π. Further, the absolute value of the result is calculated. In the case of modulation by QPSK (Quadrature Phase Shift Keying), it may be divided by π / 2.

  Further, the difference between “π” in the second row and “π” in the third row is calculated to be “0”. Similarly, the differential is calculated for the third row. When the results are arranged in order, {1, 0, 1} is obtained. Here, assuming that the known signal corresponding to the partial signal is the same as that in FIG. 10A, the relative differential in the known signal, that is, the relative phase difference is also {1, 0, 1}. Since the phase difference between the two coincides, the correlation value is maximized. In FIG. 10A, the differential results are the same for x and y because x and y are equal.

  On the other hand, when the differential is similarly calculated in FIG. 10B, {1, 0, 1} for x and {1, 0, 1} for y are obtained. Then, it turns out that the differential result in a known signal and the differential in FIG.10 (b) are equal. Therefore, also in this case, the correlation value is maximized. In other words, depending on the differential, it is not affected by the phase slip, but it cannot be determined whether it is pseudo-synchronous.

  Therefore, the calculation is performed using the partial phases of FIGS. 10A and 10B and the absolute phase of the known signal. Further, the eight phase differences obtained for each figure are added together. As a result, the partial signal shown in FIG. 10A matches the known signal, so that the total result is zero. On the other hand, for the partial signal shown in FIG. 10B, each of the four phases {π, 0, 0, π} of y is completely different from {0, π, π, 0} in the case of normal synchronization. Therefore, the total result is 4. Here, when the first threshold value is 3 and the second threshold value is 6, FIG. 10B is determined to be pseudo-synchronous. In this way, it is possible to determine whether or not pseudo synchronization is achieved by using an absolute phase difference.

  FIGS. 10C to 10D show a case where partial signals are composed of different symbols, that is, x and y in the same row are different. Here, FIG. 10C is a diagram showing a case of normal synchronization. FIG. 10D is a diagram showing a case of pseudo synchronization.

  First, in order to remove the influence of the phase slip, in FIG. 10C, when the differential is calculated for each of the first to fourth rows, {1, 0, 1} for x, {0, 1, 0}. Here, assuming that the known signal corresponding to the partial signal is the same as that in FIG. 10C, the relative differential in the known signal, that is, the relative phase difference is also {1, 0, 1} for x. For y, {0, 1, 0}.

  On the other hand, when the differential is similarly calculated in FIG. 10D, {1, 0, 1} for x and {0, 1, 0} for y are obtained. Then, it turns out that the differential result in a known signal and the differential in FIG.10 (b) are equal. In other words, depending on the differential, it is not affected by the phase slip, but it cannot be determined whether it is pseudo-synchronous.

  Therefore, the calculation is performed using the respective partial signals of FIGS. 10C and 10D and the absolute phase of the known signal. Further, the eight phase differences obtained for each figure are added together. Then, since the partial signal shown in FIG. 10C matches the known signal, the total result is 0. On the other hand, for the partial signal shown in FIG. 10D, each of the four phases {π, π, 0, 0} of y is completely different from {0, 0, π, π} in the case of normal synchronization. Therefore, the total result is 4. Here, when the first threshold value is 3 and the second threshold value is 6, FIG. 10D is determined to be pseudo-synchronous. In this way, it is possible to determine whether or not pseudo synchronization is achieved by using an absolute phase difference.

  According to the present embodiment, since the result of error correction decoding is not required for the determination of pseudo synchronization, the processing time required for exiting the pseudo synchronization state can be reduced. By using both the relative phase difference and the absolute phase difference indicators, it is possible to reduce the determination processing time of the pseudo synchronization state. By calculating the phase differential between the partial signals, synchronization can be accurately captured even if a phase slip occurs. The position of the known signal inserted on the transmission side in the signal sequence can be accurately captured. By calculating the difference between the known signal and the partial signal, pseudo-synchronization can be accurately determined in a short time.

  In the above, this invention was demonstrated based on the Example. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are also within the scope of the present invention. .

  In the present embodiment, it has been described that the signal sequence is written in the buffer 40 on one side. However, the present invention is not limited to this, and a two-surface buffer 40 may be used. Further, it has been described that the upper and lower sides written in the buffer 40 are executed in the differential processing. However, the present invention is not limited to this, and every second and third rows may be differentially executed. In the present embodiment, the modulation scheme of the transmitted signal sequence is described as being BPSK. However, the present invention is not limited to this, and a modulation method for M-phase PSK (M is a power of 2) such as QPSK and 8PSK may be used. In FIG. 1, the RF unit 2 and the quadrature detection unit 3 have been described as separate circuits. However, the present invention is not limited to this, and the quadrature detection unit 3 may be provided inside the RF unit 2 to perform direct conversion. It goes without saying that the same effects as described above can be obtained even in such a configuration.

It is a figure which shows the structural example of the terminal device concerning the Example of this invention. It is a figure which shows the structural example of the signal processing part of FIG. It is a figure which shows the structural example of the signal series which the signal processing part of FIG. 2 receives. 4A to 4C are diagrams showing examples of signal point arrangement of the signal sequence output from the demodulator in FIG. It is a figure which shows the structural example of the buffer of FIG. It is a figure which shows the structural example of the partial signal acquisition part of FIG. It is a figure which shows the structural example of the temporary synchronization determination part of FIG. It is a figure which shows the structural example of the pseudo-synchronization determination part of FIG. It is a flowchart which shows the operation example of the signal processing part of FIG. 10A to 10D are diagrams illustrating examples of the phase of the partial signal stored in the buffer and the differential result.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Antenna, 2 RF part, 3 Quadrature detection part, 6 Decoding part, 20 Demodulation part, 22 Partial signal acquisition part, 24 Temporary synchronization determination part, 26 Pseudo synchronization determination part, 28 Frequency correction part, 30 Differential calculation part, 32 Correlation calculation unit 36 known signal determination unit 38 measurement unit 40 buffer 42 control unit 50 signal series 52 known signal 54 data signal 62 writing unit 64 reliability acquisition unit 100 signal processing unit 200 Terminal device.

Claims (5)

An input unit for inputting a signal sequence in which a known signal is inserted at a constant period;
A demodulator that reproduces a carrier wave from the signal sequence input at the input unit, and demodulates the signal sequence according to the reproduced carrier wave;
A partial signal acquisition unit for acquiring a plurality of partial signals included in the signal sequence demodulated by the demodulation unit at the same cycle as the cycle;
A temporary synchronization determination unit that estimates the position where the known signal is inserted by calculating a relative phase difference between the partial signals acquired by the partial signal acquisition unit;
Of the signal series demodulated by the demodulator, by integrating the absolute phase difference between the partial signal existing at the position estimated by the provisional synchronization determination unit and the known signal to correspond to the partial signal, A pseudo-synchronization determination unit that determines whether the frequency of the carrier wave reproduced by the demodulation unit is correct;
A receiving apparatus comprising: The temporary synchronization determination unit
A differential calculation unit that calculates a relative phase difference between the partial signals by calculating a differential of the phases of the front and rear partial signals among a plurality of partial signals acquired by the partial signal acquisition unit; ,
A correlation calculation unit for calculating a correlation value between each phase difference calculated by the differential calculation unit and a relative phase difference between known signals to be associated with the respective phase differences;
When the correlation value calculated by the correlation calculation unit is larger than a threshold value related to temporary synchronization, the partial signal is acquired as a signal corresponding to the known signal, and the position where the partial signal exists is determined by the known signal. A known signal determination unit that determines the inserted position;
The receiving apparatus according to claim 1, comprising:   When the correlation value calculated by the correlation calculation unit is smaller than a threshold value related to temporary synchronization, the temporary synchronization determination unit targets again a partial signal different from the plurality of partial signals in the signal sequence, The receiving apparatus according to claim 2, wherein a differential calculation unit is configured to calculate a differential. The pseudo-synchronization determination unit
A first measurement unit that measures a phase difference of a plurality of partial signals acquired in the temporary synchronization determination unit and a phase difference of a known signal corresponding to each of the plurality of partial signals;
A second measurement unit that calculates a difference between the phase differences measured by the measurement unit and adds up the results;
When the sum value measured by the second measuring unit is larger than a first threshold value regarding normal synchronization or smaller than a second threshold value smaller than the first threshold value, While determining that the phase of the carrier wave reproduced by the demodulator is correct, if the sum is smaller than the first threshold and larger than the second threshold, the carrier is reproduced by the demodulator. A controller that determines that the phase of the detected carrier wave is incorrect;
The receiving apparatus according to claim 1, comprising:   The pseudo-synchronization determination unit further includes a frequency correction unit that corrects the frequency of the carrier wave by shifting the frequency of the carrier wave when it is determined that the phase of the carrier wave reproduced by the demodulation unit is incorrect. The receiving apparatus according to claim 1.

Images