JP2007067460A - High-frequency power amplifying electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency power amplifying electronic component capable of highly accurately detecting the capacity of power. <P>SOLUTION: The electronic component is provided with, for example, an NMOS transistor MN1 for receiving a bias voltage VREF and a high-frequency input signal from an input node RFin, and generating a current corresponding to the same; PMOS transistors MP1, MP2 for transferring the current of MN1; and an NMOS transistor MN2v for converting the transferred current into a voltage VDT by diode connection. The component is further provided with a differential amplifier circuit DIFAMP for subtracting the bias voltage VREF from the voltage VDT and amplifying a resulted voltage, and then, adding an offset voltage VOS to generate a detection voltage VDET. In such a configuration, a value of VREF, a value of VOS and an element size of MN2v can be adjusted by control signals SW1, SW3 and SW2, respectively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic component for high frequency power amplification, and more particularly to a technique that is effective when applied to an electronic component including a power detection circuit required for controlling transmission power of a mobile phone or the like.

  In general, a high-frequency power amplification circuit that amplifies a modulated signal is incorporated in a transmission-side output unit in a wireless communication device (mobile communication device) such as a mobile phone. In such a wireless communication apparatus, it is necessary to control the amplification factor of the high-frequency power amplifier circuit in accordance with the transmission level required from a control circuit such as a baseband circuit or a microprocessor. Therefore, feedback is performed by detecting the output level of the high frequency power amplifier circuit.

  For example, Patent Document 1 discloses means for detecting the output level of such a high-frequency power amplifier circuit. The configuration is such that an output signal of the high frequency power amplifier circuit is taken out from an intermediate node of the impedance matching circuit connected to the final stage transistor of the high frequency power amplifier circuit through a resistor and a capacitive element. The power detection circuit generates a voltage proportional to the extracted signal level.

As a specific example of the power detection circuit, a transistor using the extracted signal as a gate input, a current mirror circuit that transfers a current flowing through the transistor, a circuit that converts the transferred current into a voltage, and a converted voltage A configuration including an amplifier circuit that performs amplification by removing a DC bias component from is shown. If the technique of this patent document 1 is used, it becomes possible to realize downsizing, low insertion loss, and the like of the power detection means.
JP 2004-328555 A

  In recent cellular phones, in addition to a system called GSM (Global System for Mobile Communication) using a frequency of 880 to 915 MHz, a system such as DCS (Digital Cellular System) using a frequency of 1710 to 1785 MHz is used. Dual-band mobile phones that can handle these signals have been proposed. In such a high-frequency power amplifier circuit used for a mobile phone, an output power amplifier is provided for each band, so a coupler and a power detection circuit for detecting the output level are also required for each band. . Therefore, further miniaturization is required for each circuit and each component.

  Under such circumstances, in the power detection circuit, in addition to downsizing, it is necessary to control detection characteristics such as sensitivity with high accuracy in accordance with each of these bands. However, in the technique of Patent Document 1 described above, the specific configuration of the power detection circuit corresponding to the dual band system is not particularly shown. If two power detection circuits having the above-described configuration are simply used corresponding to two bands, the circuit area becomes large. Further, in the technique disclosed in Patent Document 1 described above, when variations occur in circuit element characteristics in the power detection circuit due to manufacturing reasons such as processes, the detection characteristics of each power detection circuit may vary. There is. Further, in the case of the dual band method, there is a possibility that each detection characteristic varies for each band in the power detection circuit.

  Accordingly, an object of the present invention is to provide an electronic component for high frequency power amplification capable of detecting the magnitude of power with high accuracy. Another object of the present invention is to realize miniaturization and high accuracy in a power detection circuit corresponding to a plurality of communication methods.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  An electronic component for high frequency power amplification according to the present invention receives a high frequency power signal and an input signal including a bias voltage, outputs a voltage reflecting the magnitude of the input signal, and a voltage output from the detection circuit. An amplifier circuit that subtracts the bias voltage, amplifies the subtracted voltage, and further adds and outputs an offset voltage. The detection circuit includes a first transistor that generates a current according to the input signal, a current mirror circuit that transfers a current generated by the first transistor, and a current transferred by the current mirror circuit that is converted into a voltage by diode connection. And a second transistor for conversion and output. And with respect to such a configuration, the magnitudes of the bias voltage and the offset voltage can be adjusted in accordance with predetermined set values.

  That is, when the first transistor is, for example, a MOS transistor, it is desirable that the bias voltage is set to the threshold voltage of the MOS transistor, and the first transistor is subjected to a class B amplification operation in response to a high frequency power signal. This makes it possible to realize highly accurate and stable power detection even with a minute high frequency power signal. However, since the threshold voltage of the MOS transistor fluctuates due to process variations or the like, the power detection characteristics fluctuate accordingly. Therefore, by making the bias voltage adjustable, variation in power detection characteristics can be reduced, and highly accurate and stable power detection can be realized. In addition, even when the offset voltage varies, offset variations occur in the power detection characteristics. Accordingly, by making this adjustable, highly accurate and stable power detection can be realized.

  In addition to the adjustment of the bias voltage and offset voltage described above, the element size of the second transistor may be adjustable. In other words, there is a possibility that the detection sensitivity varies depending on the frequency band of the high-frequency power signal, the modulation method, and the like. Such variation in detection sensitivity is absorbed by adjusting the element size of the second transistor. be able to. Therefore, it is possible to obtain the target detection sensitivity in actual use with high accuracy.

  The electronic component for high-frequency power amplification according to the present invention includes a plurality of detection circuits as described above, and has the amplifier circuit as described above in common with the plurality of detection circuits. That is, for example, when high-frequency power signals of different frequency bands corresponding to different communication methods are input, each high-frequency power signal is detected by a separately provided detection circuit, and one of the detection circuits is selected. The bias voltage and the output voltage are input to the amplifier circuit. For such a configuration, the bias voltage for each detection circuit, the element size of the second transistor for each detection circuit, and the offset voltage input to the common amplifier circuit are set according to predetermined setting values, respectively. It is adjustable.

  As a result, even when a high frequency power signal of a different communication method is input, the power detection characteristics can be individually adjusted for each communication method, so that highly accurate and stable power detection can be realized. Furthermore, the area can be reduced by using the amplifier circuit in common.

  To briefly explain the effects obtained by typical inventions among the inventions disclosed in the present application, it is possible to detect the magnitude of power with high accuracy in an electronic component for high frequency power amplification provided with a power detection circuit. It becomes possible. In addition, the power detection circuit corresponding to a plurality of communication methods can be reduced in size and increased in accuracy.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a circuit diagram showing an example of the configuration of a power detection circuit included in an electronic component for high-frequency power amplification according to an embodiment of the present invention. The power detection circuit shown in FIG. 1 receives a high-frequency power signal input from the input node RFin, and amplifies the detection unit DET that generates a voltage VDT reflecting the magnitude of the power signal by subtracting the bias voltage from the voltage VDT. It comprises a differential amplifier circuit DIFFAMP for performing the above.

  The detection unit DET includes, for example, NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, and resistance elements R3 and R4 for supplying a bias voltage VREF to the NMOS transistor MN1. The gate of MN1 is supplied with a voltage V1 signal obtained by adding an input signal from the input node RFin via the capacitive element Ci to the bias voltage VREF generated from the node N1 between R3 and R4. The source of MN1 is a ground voltage, and a current reflecting the signal of the voltage V1 is generated between the source and drain of MN1. The resistor element R7 provided between the gate of the MN1 and the node N1 is for preventing a signal from RFin from wrapping around to the node N1 side.

  MP1 has a source connected to the power supply voltage VDD, a drain connected to the drain of MN1, and a gate connected to the gate of MP2. MP2 has a source connected to the power supply voltage VDD and a drain connected to the drain of MN2. Thus, MP1 and MP2 constitute a current mirror circuit, and transfer the current generated in MN1 to MN2. The source of MN2 is connected to the ground voltage, and the gate and drain are commonly connected to the drain of MP2. MN2 is diode-connected and converts a current generated by MN1 input through a current mirror circuit into a voltage VDT. The voltage VDT is output to the differential amplifier circuit DIFFAMP.

  The differential amplifier circuit DIFAMP determines, for example, two amplifier circuits AMP1 and AMP2, resistance elements R1 and R2 (and R1 ′ and R2 ′) that determine amplification factors of AMP1 and AMP2, and an offset voltage VOS of AMP1 and AMP2. Resistor elements R5 and R6 are included. In AMP1, the bias voltage VREF of the node N1 is input to one input node ((+) side), and the negative feedback signal from the output node N3 is input to the other input node ((−) side). That is, the resistance elements R2 and R1 are connected in series from the N3 side between the node N2 that generates the offset voltage VOS between the resistance elements R5 and R6 and the output node N3, and the node between R2 and R1 is negative. It is an input node for feedback.

  In AMP2, the voltage VDT of the gate (drain) of MN2 is input to one input node, and the negative feedback signal from the output node (detection voltage) VDET is input to the other input node with the output of AMP1 as an offset. That is, R1 ′ and R2 ′ are connected in series from the VDET side between the output node VDET of AMP2 and the output node N3 of AMP1, and the node between R1 ′ and R2 ′ is an input node for negative feedback. . The detection voltage VDET is a voltage representing the magnitude of input power at the input node RFin.

  In such a configuration, the main feature of the configuration of FIG. 1 is that the circuit for generating the bias voltage VREF and the circuit for generating the offset voltage VOS each include trimming means. In FIG. 1, for example, between the power supply voltage VDD and the ground voltage, VREF is generated from a node N1 divided by resistors R3 and R4, and VOS is generated from a node N2 divided by resistors R5 and R6. ing. Here, the resistance elements R4 and R6 are variable resistances as shown in FIG. 2, thereby realizing trimming means.

  FIG. 2 is a circuit diagram showing an example of the trimming means in the power detection circuit of FIG. 1, wherein (a) is a bias voltage adjustment circuit, and (b) is an offset voltage adjustment circuit. In FIG. 2A, the resistance element R4 of FIG. 1 is realized by four resistance elements R41, R42, R43, R44 connected in parallel and four switch elements connected in series to the resistance elements R41 to R44, respectively. ing. The four switch elements are controlled by control signals SW1 [1], [2], [3], [4] (SW1 [4: 1]), respectively. Further, as shown in FIG. 2B, the resistance element R6 of FIG. 1 is similarly realized by four resistance elements R61 to R64 and four switch elements, and these switch elements are respectively controlled by the control signal SW3. Controlled by [4: 1].

  Therefore, for example, by setting R41 to R44 (R61 to R64) to the same resistance value and controlling the number of switch elements to be turned on, the resistance values of the resistance elements R4 and R6 in FIG. 1 can be changed, and the bias voltage VREF In addition, the offset voltage VOS can be adjusted. Of course, the number of resistance elements is not limited to four, and is determined according to the required adjustment accuracy of the resistance value. Further, the trimming means is not particularly limited to a parallel-connected resistance element. For example, a method for selecting a node for extracting a voltage from among nodes between resistance elements using a series-connected resistance element, a method for using a drain voltage when a current is passed through the drain of a diode-connected MOS transistor, etc. But you can. In this case, the current flowing through the drain or the size of the MOS transistor is variable.

  Next, the operation of the power detection circuit of FIG. 1 will be described. First, the detection voltage VDET of the power detection circuit is given by the differential amplifier circuit DIFFAMP as shown in Expression (1).

VDET = (1 + R1 ′ / R2 ′) VDT− (R1 ′ / R2 ′) (1 + R2 / R1) VREF + (R1 ′ / R2 ′) (R2 / R1) VOS (1)
Here, when R1 = R1 ′ and R2 = R2 ′, the equation (2) is obtained.

VDET = (1 + R1 / R2) (VDT−VREF) + VOS (2)
From this equation (2), the power detection circuit of FIG. 1 extracts the net input power from RFin as a voltage value by subtracting the bias voltage VREF from the voltage VDT, and amplifies the extracted voltage value to offset it. The voltage VOS is applied. As will be described later, the voltage VDT has a value such that a voltage ΔV reflecting the input power of RFin is added to the bias voltage VREF. How to obtain this ΔV with high accuracy is important. Further, when the voltage VOS varies due to process variations or the like, the value of VDET is shifted by VOS, so that this voltage also requires accuracy.

  Under such circumstances, the voltage VDT is generated as follows. First, the bias voltage VREF input to the NMOS transistor MN1 is adjusted so that the MN1 performs the class B amplification operation. That is, the threshold voltage Vth is adjusted to be near MN1 so that the signal can be detected even if the input signal from RFin is weak. MN1 operates with a half-wave portion of the AC signal from RFin, and generates a drain current corresponding thereto. This drain current is transferred by a current mirror circuit of MP1 and MP2, and converted to a voltage VDT by MN2. Although MN1 operates for half a wave, the voltage VDT is applied to the delay and parasitic capacitance of each MOS transistor when a current is generated at MN1 or when the current is input to MN2 via MP1 and MP2. Is rectified and smoothed by the input capacity of the AMP2. This is schematically shown in FIG.

  FIG. 3 is a schematic diagram illustrating a process until a voltage is generated by the detection unit in the power detection circuit of FIG. 1. When the bias voltage VREF is equal to the threshold voltage Vth of MN1 (in the case of Vth1), MN1 operates at a voltage higher than VREF with respect to the input waveform from RFin. If the element sizes of MN1 and MN2 are equal, the current and voltage associated therewith are rectified and smoothed as described above, so that VREF + ΔV1 is obtained as voltage VDT.

  However, in practice, the threshold voltage Vth of MN1 varies due to process variations. Therefore, since the conventional technique does not include trimming means for the bias voltage VREF, there is a case where the threshold voltage Vth of MN1 becomes larger than the bias voltage VREF (in the case of Vth2) as shown in FIG. Could happen. As a result, the magnitude of the voltage VDT becomes VREF + ΔV2 which is smaller than the above-described value, and the voltage VDT also varies as the threshold voltage of the MN1 varies. Further, in this case, if the input signal from RFin is weak, it may be difficult to detect the power itself.

  Therefore, the variation in ΔV can be reduced by adjusting the bias voltage VREF so that it can be adjusted to the threshold voltage Vth of MN1. In addition, the variation of the offset voltage VOS can be reduced by adjusting the resistance element R6. As a result, it is possible to obtain a voltage that accurately reflects the magnitude of the input power to the input node RFin as the detection voltage VDET. The offset voltage VOS is the initial value of the detection voltage VDET when the input power to RFin is zero. The initial value of the detection voltage VDET may vary depending on the system to which the power detection circuit is applied, and is set to an optimal value according to each system.

  FIG. 4 is a circuit diagram showing an example of a modified configuration of the power detection circuit of FIG. The power detection circuit shown in FIG. 4 differs from the configuration example of FIG. 1 in that the NMOS transistor MN2 is an NMOS transistor MN2v whose element size is variable. Since other configurations are the same as those in FIG. The power detection circuit of FIG. 4 includes trimming means for detection sensitivity by MN2v in addition to trimming means for the bias voltage VREF and the offset voltage VOS.

  FIG. 5 is a circuit diagram showing an example of the trimming means in the power detection circuit of FIG. In FIG. 5, the NMOS transistor MN2v of FIG. 4 is realized by four NMOS transistors MN2v1, MN2v2, MN2v3, and MN2v4 connected in parallel and four switch elements connected in series to these NMOS transistors MN2v1 to MN4, respectively. ing. Each of the MNs 2v1 to 4 has a diode connection. The four switch elements are controlled by control signals SW2 [1], [2], [3], [4] (SW2 [4: 1]), respectively. Note that the number of transistors is not limited to four, and is appropriately determined according to an adjustment range to be obtained.

  When the element size (gate width W) of the NMOS transistor MN2v can be adjusted in this way, the detection sensitivity (change in voltage VDT (VDET) relative to change in RFin) can be adjusted accordingly. Therefore, the trimming means of MN2v sets a desired detection sensitivity according to the system to which the power detection circuit is applied, or reduces variations in detection sensitivity due to process variations for each power detection circuit, etc. Will also be possible.

  The detection sensitivity can be adjusted by making the resistance elements R1 (R1 ') and R2 (R2') variable as can be seen from the equation (2). However, for example, it is generally possible to obtain high accuracy with a small area by making the MOS transistor element size variable as shown in FIG. 5, rather than making the resistance elements R1 and R2 variable by the same method as in FIG. Therefore, it is desirable to adjust the detection sensitivity by the NMOS transistor MN2v.

  FIG. 6 is a block diagram showing a configuration example of a wireless communication system using the high frequency power amplification electronic component according to the embodiment of the present invention. Here, a configuration example of a mobile phone having two communication methods such as GSM (Global System for Mobile Communications) and DCS (Digital Cellular System) or PCS (Personal Communication Services) is shown. The system shown in FIG. 6 includes, for example, a baseband module 100, a power amplifier module 200, a front end module 300, and the like. These modules are not particularly limited. For example, two modules can be realized by implementing three IC devices corresponding to each module, or by integrating the power amplifier module 200 and the front end module 300 into one IC device. There are cases where it consists of devices.

  The baseband module 100 includes a baseband circuit 110, bandpass filters BPF1 and BPF2 that remove harmonic components from the transmission signal, low noise amplifiers LNA1 and LNA2 that amplify the reception signal to the baseband circuit 110, and It is composed of bandpass filters BPF3 and BPF4 that remove unnecessary waves from the output. The baseband circuit 110 has a function of performing GMSK modulation / demodulation in a GSM or DCS system or PSK modulation / demodulation in an EDGE mode, or generates I and Q signals based on transmission data (baseband signals) or I I extracted from a received signal. , Q signal processing function and the like.

  The transmission circuit includes, for example, variable gain amplifiers GCA1 and GCA2 that amplify GSM and DCS transmission signals, respectively, and mixers Tx-MIX1 that upconvert these outputs using oscillation signals generated by the oscillators VCO1 and VCO2, respectively. Tx-MIX2 is included. In addition, the reception system circuit includes, for example, mixers Rx-MIX1 and Rx-MIX2 that downconvert the received signals of GSM and DCS by the oscillation signals generated by the oscillators VCO1 and VCO2, respectively. The gains of the variable gain amplifiers GCA1 and GCA2 are controlled by the gain control circuit 111.

  The power amplifier module 200 corresponds to the electronic component of the present embodiment, and the power detection circuit 220 therein has a configuration as described above. Here, an amplifier circuit (power amplifier unit) 210a for GSM and an amplifier circuit 210b for DCS are provided, and each amplifier circuit is an LD-MOSFET (Lateral Diffusion Metal Oxide) having, for example, a two-stage configuration or a three-stage configuration. Semiconductor Field Effect Effect Transistor). Output power POUT1, POUT2 of the amplifier circuits 210a, 210b is controlled by the bias circuit 230. A mode selection signal VBAND indicating GSM or DCS and a constant current Icont are supplied from the baseband module 100 to the bias circuit 230. The bias circuit 230 generates a bias current corresponding to each mode based on VBAND and Icont, and supplies the bias current to either the power amplifier unit 210a or 210b.

  The output powers POUT1 and POUT2 of the amplifier circuits 210a and 210b are taken out by the directional couplers 242a and 242b and input to the input nodes RFin1 and RFin2 of the power detection circuit 220. The power detection circuit 220 is controlled by a mode selection signal VBAND or the like, and outputs a detection voltage VDET reflecting the output power of any mode to the gain control circuit 111 in the baseband module 100. The gain control circuit 111 compares the detection voltage VDET with the internal output level instruction signal Vramp, generates a power control signal PCS for the variable gain amplifiers GCA1 and GCA2, and controls their gains. By this control, the amplitude of the high-frequency signal input to the power amplifier units 210a and 210b is controlled, and the output power of the power amplifier units 210a and 210b is also controlled accordingly.

  The front-end module 300 includes low-pass filters LPF1 and LPF2 that remove noise such as harmonics from transmission outputs of the power amplifier units 210a and 210b, and a duplexer that synthesizes and separates GSM signals and DCS signals. DPX1 and DPX2 and transmission / reception changeover switch T / R-SW are included. An antenna ANT is connected to the changeover switch T / R-SW. Although not particularly limited, the power amplifier units 210a and 210b, the bias circuit 230, and the power detection circuit 220 in the power amplifier module 200 are formed on one semiconductor chip.

  FIG. 7 is a block diagram showing another configuration example of the wireless communication system using the high frequency power amplification electronic component according to the embodiment of the present invention. While the system described in FIG. 6 controls output power by the gain control circuit 111, the system in FIG. 7 includes an APC circuit 250 in the power amplifier module 200 to control output power. It has become. Other configurations are the same as those in FIG.

  In the system of FIG. 7, the detection voltage VDET from the power detection circuit 220 and the output level instruction signal Vramp from the baseband module 100 are input to the APC circuit 250. The APC circuit 250 compares these two inputs and outputs an output control signal Vapc to the bias circuit 230. The bias circuit 230 controls the gains of the power amplifier units 210a and 210b according to the output control signal Vapc, and controls the output power of the power amplifier units 210a and 210b to change accordingly.

  6 and 7, the mixers Tx-MIX1 and Tx-MIX2 are provided at the subsequent stage of the variable gain amplifiers GCA1 and GCA2. However, the mixers Tx-MIX1, at the previous stage of the variable gain amplifiers GCA1 and GCA2 are provided. Tx-MIX2 may be provided. Although not shown in FIGS. 6 and 7, in addition to the module, a microprocessor that generates an output level instruction signal that is a basis of a control signal and a power control signal for the baseband module 100 and controls the entire system. (CPU) may be provided.

  Since the wireless communication system as described above supports two communication methods, the size of each module becomes large. Under such circumstances, the power amplifier module 200 requires a power detection circuit 220 that detects the output powers POUT1 and POUT2 of the two power amplifier units 210a and 210b in a small size and with high accuracy. Therefore, when using the trimming means as described with reference to FIGS. 1 to 5 and further supporting two communication systems, for example, the configuration shown in FIG. 8 may be used.

  FIG. 8 is a circuit diagram showing a configuration example of a power detection circuit in the power amplifier module in the wireless communication system of FIGS. 6 and 7. The power detection circuit shown in FIG. 8 includes, for example, two detection units DET1 and DET2 for low band (GSM) and high band (DCS), and a common differential amplifier that amplifies the results detected by the detection units DET1 and DET2. The circuit is composed of DIFFAMP. Each of the detectors DET1 and DET2 has the same configuration as that of the detector DET in FIG. 4, and DIFFAMP provided in common to the two detectors DET1 and DET2 has the same configuration as in FIG. It has become.

  In the detection unit DET1, a bias voltage VREF1 is generated by the resistance elements R13 and R14, and a voltage V1 obtained by adding an AC signal from the input node RFin1 to the VREF1 is applied to the NMOS transistor MN11. The current generated in MN11 is supplied to the NMOS transistor MN12 via the PMOS transistors MP11 and MP12 serving as a current mirror circuit, and is converted into the voltage VDT1 by the MN12.

  On the other hand, in the detection unit DET2, a bias voltage VREF2 is generated by the resistance elements R23 and R24, and a voltage V2 obtained by adding an AC signal from the input node RFin2 to the VREF2 is applied to the NMOS transistor MN21. The current generated in MN21 is supplied to the NMOS transistor MN22 via the PMOS transistors MP21 and MP22 serving as a current mirror circuit, and is converted into the voltage VDT2 by the MN22.

  The differential amplifier circuit DIFFAMP includes amplifier circuits AMP1 and AMP2 similar to those in FIG. 4 and resistance elements R1 (R1 ') and R2 (R2'), and an offset voltage VOS is supplied by the resistance elements R5 and R6. Here, the input node ((+) side) which is not on the negative feedback side in AMP1 can be connected to either the bias voltage VREF1 or VREF2 by the switch element SW_A. Further, the input node ((+) side) which is not on the negative feedback side in AMP2 can be connected to either the voltage VDT1 or VDT2 by the switch element SW_B.

  Therefore, in the low band mode, the output power POUT1 in the low band mode can be detected by selecting the input to AMP1 on the VREF1 side and the input to AMP2 on the VDT1 side by the switch elements SW_A and SW_B. Similarly, in the high band mode, the output power POUT2 in the high band mode can be detected by selecting the input to AMP1 on the VREF2 side and the input to AMP2 on the VDT2 side by the switch elements SW_A and SW_B. As described above, by using the switch elements SW_A and SW_B, the two detection units DET1 and DET2 can be handled by one differential amplifier circuit DIFFAMP, so that the circuit area can be reduced. The switch elements SW_A and SW_B can contribute to rectification and smoothing of the voltages VDT1 and VDT2 by their capacitance components.

  Further, in the power detection circuit of FIG. 8, as in FIG. 4, resistance elements R14 and R24 that determine bias voltages VREF1 and VREF2 for each mode, NMOS transistors MN12 and MN22 that determine detection sensitivity and the like for each mode, A trimming means is provided in the resistance element R6 that determines the offset voltage VOS of DIFFAMP in common with each mode. Here, with the same configuration as in FIG. 2, the resistance values of R14, R24 and R6 are determined by the control signals SW11 [4: 1], SW21 [4: 1] and SW3 [4: 1] of the switch elements. 5, the element sizes of MN12 and MN22 are determined by control signals SW12 [4: 1] and SW22 [4: 1].

  These control signals are generated by a method as shown in FIG. 9, for example. FIG. 9 is a schematic diagram showing an example of a method of generating each control signal for the power detection circuit of FIG. 8, and (a) and (b) show examples of different methods.

  In FIG. 9A, for example, the power detection circuit shown in FIG. 8 is used as a power detection unit 220a, and a storage unit 90, a decoder 91, a control unit 92, and the like are provided on the same semiconductor chip. . The storage unit 90 is a non-volatile storage unit such as a non-volatile memory, for example, and the set values of the control signals SW11, SW21, SW3, SW12, and SW22 are set via an adjustment terminal A that is an external terminal of the semiconductor chip. Stored. In this case, for example, the setting value can be stored in the storage unit 90 at the inspection stage after manufacturing the power amplifier module 200 including the power detection circuit 220. In some cases, for example, after assembling a mobile phone system or the like, it is also possible to change the power detection characteristics in accordance with a user request or the like.

  For practical use, for example, the value stored in the storage unit 90 is read when the power amplifier module 200 is turned on, and is set in the resistance element and the NMOS transistor in FIG. At this time, the value read from the storage unit 90 may be set via the decoder 91 as shown in FIG. This is useful, for example, in the case of a trimming method in which only one of a plurality of switch elements is turned on to set a resistance value and an element size, thereby reducing the area of the storage unit 90. It becomes possible. In the example of FIG. 9, the decoder 91 expands, for example, 2 bits “00”,..., “11” into 4 bits “0001”,.

  Further, the mode switching switch elements SW_A and SW_B in FIG. 8 receive the mode selection signal VBAND in FIGS. 6 and 7 and are set via the control unit 92 as shown in FIG. 9A, for example. The control unit 92 includes, for example, a latch circuit that holds the states of the switch elements SW_A and SW_B. Note that the storage unit 90 may use a fuse or the like instead of the nonvolatile memory. In this case, the adjustment terminal A is unnecessary and cannot be changed after once set, but there is an advantage in terms of ease and certainty.

  In FIG. 9B, for example, the power detection circuit shown in FIG. 8 is used as a power detection unit 220a, and a holding unit 93, a control unit 92, and the like are provided on the same semiconductor chip. Here, unlike FIG. 9A, a non-volatile storage unit 90 that stores set values of the control signals SW11, SW21, SW3, SW12, and SW22 is formed on a semiconductor chip different from the power detection unit 220a. ing. That is, a cellular phone system or the like normally includes a nonvolatile memory chip inside, and uses this, for example. In this case, the set value is stored in the storage unit 90 at the inspection stage after the assembly of the mobile phone system or the like.

  For practical use, the value stored in the storage unit 90 is read, for example, when a mobile phone system or the like is turned on, and is transferred to and held in the holding unit 93 via the adjustment terminal B serving as an external terminal of the semiconductor chip. The The holding unit 93 includes, for example, a latch circuit inside. If the number of control signals is large, the number of adjustment terminals B may increase drastically. For example, a latch circuit may be configured by a shift register, and values can be transferred by serial transfer via the adjustment terminals B. It is good to do so.

  As described above, by using the power detection circuit as shown in FIG. 8, trimming is performed for each of the detection units DET1 and DET2 corresponding to each communication method even when the power amplifier module supports a plurality of communication methods. Therefore, highly accurate power detection can be realized for each communication method. That is, if the communication method (frequency band and modulation method) is different, even if the input power to RFin1 and RFin2 in FIG. 8 is the same, the detection sensitivity when converting it to the detection voltage VDET can be different. Sex is conceivable. In this case, these detection sensitivity shifts are absorbed by individual trimming of the NMOS transistors MN12 and MN22.

  Further, by using the power detection circuit as shown in FIG. 8, it is possible to reduce the characteristic variation for each power detection circuit due to the process variation as described above. Furthermore, such a highly accurate power detection circuit can be realized with a small area. Therefore, the manufacturing yield can be improved and the manufacturing cost can be reduced.

  FIG. 10 is a graph showing an example of the relationship between input power and detection voltage in the power detection circuit of FIG. FIG. 11 is a graph showing an example of the relationship between input power and detection sensitivity in the power detection circuit of FIG. The dotted line in FIGS. 10 and 11 shows an example of the specification of the detection characteristic. FIG. 10 shows the relationship between the output power POUT of the power amplifier 210a or 210b in FIGS. 6 and 7 and the detected voltage VDET of the power detection circuit 220 corresponding thereto. FIG. 11 shows the output power POUT similar to that in FIG. 10 and the detection sensitivity at that output power. That is, FIG. 11 corresponds to the slope at each output power in the graph characteristics of FIG.

  In FIG. 10, it is assumed that the specification of the detection voltage VDET must be, for example, 150 mV ± 30 mV when POUT <−5 dBm, and VDET = 2V ± 0.2 V when POUT = 33 dBm. In FIG. 11, it is assumed that the specification of the detection sensitivity should be 0.05 V / V to 0.22 V / V with −5 dBm ≦ POUT ≦ 33 dBm.

  Normally, even if such a specification is satisfied at the design stage, there may be variations in element characteristics during manufacturing, or the specification may not be satisfied if the frequency is changed by band switching. That is, it is a case like the characteristic A and the characteristic B shown in FIGS. In such a case, for example, by adjusting the bias voltages VREF1 and VREF2 in FIG. 8 within the test process of the power amplifier module 200, and further adjusting the element sizes and offset voltages VOS of MN12 and MN22 as necessary, The specification can be satisfied as shown by the characteristic C in FIGS. That is, even when there are two types of communication systems (frequency bands), adjustment can be made for each of the detection units DET1 and DET2 so as to satisfy the above-described detection characteristic specifications in any frequency band. it can.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in FIG. 8 and the like, the configuration of the power detection circuit corresponding to two types of communication systems is shown, but similarly, the three types of detection units and the common differential amplifier circuit are used to support the three types of communication systems. Etc. are also possible. In this embodiment, a MOS (Metal Oxide Semiconductor) type is used as each transistor element constituting the detection unit. However, the present invention is not limited to this, and any MIS (Metal Insulator Semiconductor) type transistor can be similarly applied. . In some cases, the present invention can be applied even when a bipolar transistor is used. In this case, the detection sensitivity is adjusted by adjusting the base-emitter voltage VBE by trimming the bias voltage VREF and adjusting the number of diode-connected bipolar transistors (diode area) connected in parallel. .

  The semiconductor device of the present invention is a particularly useful technique when applied to a power amplifier module which is an electronic component for generating transmission power and detecting transmission power in a mobile phone system. Further, the present invention is not limited to this, and can be widely applied as an electronic component for detecting transmission power of various wireless communication systems such as a wireless LAN and RFID (Radio Frequency Identification).

1 is a circuit diagram illustrating an example of a configuration of a power detection circuit included in an electronic component for high-frequency power amplification according to an embodiment of the present invention. FIG. FIG. 2 is a circuit diagram showing an example of the trimming means in the power detection circuit of FIG. 1, wherein (a) is a bias voltage adjustment circuit, and (b) is an offset voltage adjustment circuit. FIG. 2 is a schematic diagram illustrating a process until a voltage is generated by the detection unit in the power detection circuit of FIG. 1. It is a circuit diagram which shows an example of the structure which deform | transformed the electric power detection circuit of FIG. FIG. 5 is a circuit diagram showing an example of the trimming means in the power detection circuit of FIG. 4. It is a block diagram which shows the structural example of the radio | wireless communications system using the electronic component for high frequency power amplification by one embodiment of this invention. It is a block diagram which shows the other structural example of the radio | wireless communications system using the electronic component for high frequency power amplification by one embodiment of this invention. FIG. 8 is a circuit diagram showing a configuration example of a power detection circuit in the power amplifier module in the wireless communication system of FIGS. 6 and 7. FIG. 9 is a schematic diagram illustrating an example of a method for generating each control signal for the power detection circuit of FIG. 8, and (a) and (b) illustrate examples of different methods. 9 is a graph showing an example of the relationship between input power and detection voltage in the power detection circuit of FIG. 8. 9 is a graph showing an example of the relationship between input power and detection sensitivity in the power detection circuit of FIG. 8.

Explanation of symbols

AMP amplifier circuit ANT antenna BPF bandpass filter Ci capacitive element DET detection unit DIFFAMP differential amplifier circuit DPX duplexer GCA variable gain amplifier LPF lowpass filter LNA low noise amplifier MN NMOS transistor MP PMOS transistor R resistor element RFin input node SW control signal SW_A, SW_B Switch element Tx-MIX, Rx-MIX Mixer T / R-SW changeover switch VBAND Mode selection signal VCO Oscillator VDD Power supply voltage VDET Detection voltage VREF Bias voltage VOS Offset voltage 90 Storage unit 91 Decoder 92 Control unit 93 Holding unit 100 Baseband module 110 Baseband circuit 111 Gain control circuit 200 Power amplifier module 210a , 210b Power amplifier unit 220 Power detection circuit 220a Power detection unit 230 Bias circuit 242a, 242b Directional coupler 250 APC circuit 300 Front end module

Claims (10)

A first transistor that receives an input signal including a high-frequency power signal and a bias voltage, and generates a current corresponding to the input signal;
A current mirror circuit for transferring the current generated by the first transistor;
A second transistor for converting the current transferred by the current mirror circuit into a voltage by diode connection;
An amplifier circuit that subtracts the bias voltage from the voltage converted by the second transistor, amplifies the subtracted voltage, and outputs a voltage obtained by adding an offset voltage to the amplified voltage;
A voltage reflecting the magnitude of the high-frequency power signal is an electronic component for high-frequency power amplification obtained by the output of the amplifier circuit,
The set value is determined in advance,
Means for adjusting the magnitude of the bias voltage based on the set value;
And a means for adjusting the magnitude of the offset voltage based on the set value. The electronic component for high frequency power amplification according to claim 1, further comprising:
An electronic component for high frequency power amplification comprising means for adjusting an element size of the second transistor based on the set value. In the electronic component for high frequency power amplification according to claim 1,
The bias voltage and the offset voltage are each generated by dividing a power supply voltage by resistance, and the ratio of the resistance division can be changed based on the set value. . In the electronic component for high frequency power amplification according to claim 1,
The first transistor is a MOS transistor;
The electronic component for high frequency power amplification, wherein the bias voltage is adjusted to be equal to a threshold voltage of the MOS transistor. In the electronic component for high frequency power amplification according to claim 1,
The amplifier circuit is
A first amplifier circuit to which the bias voltage is input to one input node;
A second amplifier circuit in which the voltage converted by the second transistor is input to one input node;
A first resistance element connected between the other input node of the first amplifier circuit and an output node of the offset voltage;
A second resistance element connected between the other input node of the first amplifier circuit and an output node of the first amplifier circuit;
A third resistance element connected between the other input node of the second amplifier circuit and an output node of the first amplifier circuit;
A fourth resistance element connected between the other input node of the second amplifier circuit and an output node of the second amplifier circuit;
The first resistance element and the fourth resistance element have the same resistance value,
The second resistance element and the third resistance element have the same resistance value,
An electronic component for high-frequency power amplification, wherein a voltage reflecting the magnitude of the high-frequency power signal is obtained by an output node of the second amplifier circuit. In the electronic component for high frequency power amplification according to claim 2,
The means for adjusting the second transistor is realized by a configuration in which a switch element is connected in series to a diode-connected transistor, and a plurality of the circuits connected in series are connected in parallel. An electronic component for high-frequency power amplification, wherein the element size is adjusted by determining on / off of. A first detection circuit that receives a first input signal including a first high-frequency power signal and a first bias voltage and outputs a voltage reflecting the magnitude of the first input signal;
A second detection circuit that receives a second input signal including a second high-frequency power signal and a second bias voltage and outputs a voltage reflecting the magnitude of the second input signal;
Means for selecting a combination of the first bias voltage and the output voltage of the first detection circuit, or a combination of the second bias voltage and the output voltage of the second detection circuit;
Based on one combination selected by the means for selecting provided in common to the first detection circuit and the second detection circuit, the corresponding bias voltage is subtracted from the corresponding output voltage, and the subtracted voltage is amplified. And an amplifier circuit that outputs a voltage obtained by adding an offset voltage to the amplified voltage,
The first detection circuit includes:
A first transistor that generates a current according to the first input signal;
A first current mirror circuit for transferring a current generated by the first transistor;
A second transistor that converts the current transferred by the first current mirror circuit into a voltage by diode connection and outputs the voltage;
The second detection circuit includes:
A third transistor that generates a current according to the second input signal;
A second current mirror circuit for transferring the current generated by the third transistor;
A high frequency power amplification electronic component comprising: a fourth transistor for converting the current transferred by the second current mirror circuit into a voltage by diode connection and outputting the voltage;
The set value is determined in advance,
Means for adjusting the magnitude of the first bias voltage based on the set value;
Means for adjusting the magnitude of the second bias voltage based on the set value;
Means for adjusting the element size of the second transistor based on the set value;
Means for adjusting the element size of the fourth transistor based on the set value;
And a means for adjusting the magnitude of the offset voltage based on the set value. The electronic component for high frequency power amplification according to claim 7,
The first detection circuit, the second detection circuit, the amplifier circuit, and the adjusting means are formed on the same semiconductor chip,
An electronic component for high-frequency power amplification, wherein a non-volatile storage means for holding the set value used by the adjusting means is further formed on the semiconductor chip. The electronic component for high frequency power amplification according to claim 7,
The first detection circuit, the second detection circuit, the amplifier circuit, and the adjusting means are formed on the same semiconductor chip,
An electronic component for high frequency power amplification, wherein a non-volatile storage means for holding the set value used by the adjusting means is formed on a semiconductor chip different from the semiconductor chip. The electronic component for high frequency power amplification according to claim 8,
The nonvolatile storage means is realized by a nonvolatile memory,
The electronic component for high frequency power amplification, wherein the semiconductor chip is provided with an external terminal for storing the set value in the nonvolatile memory.

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