JP2007066959A - Process for fabricating silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a silicon carbide semiconductor device in which the problems of aggregation of impurities, and the like, are eliminated in a silicon carbide layer, etching of a base contact portion is suppressed in activated annealing, or the like, and low resistivity ohmic contact is established between the source-base common electrode and the base contact portion. <P>SOLUTION: A base contact portion 15 is formed by implanting Al ions at an impurity concentration of 2e20 cm<SP>-3</SP>while holding the substrate temperature between 400-800°C. When ions are implanted while holding the substrate temperature between 400-800°C, crystallinity aggravation of a silicon carbide layer is suppressed when ions are implanted, problems of aggregation of impurities, and the like, are eliminated in a silicon carbide layer and etching of the base contact portion 15 is suppressed in activated annealing, or the like. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  Silicon carbide (SiC) has a high breakdown electric field. Therefore, a vertical insulated gate field effect transistor (silicon carbide MOSFET) using silicon carbide has a switching performance with high withstand voltage and low loss as compared with the case using silicon (Si).

  Further, by forming an epitaxial channel layer made of silicon carbide in the channel portion of the silicon carbide MOSFET, channel mobility can be improved, and a switching element with lower loss characteristics can be obtained.

  Here, in the n-channel silicon carbide MOSFET, when performing a switching operation, the base region and the source region are connected by connecting the p-type base region and the n-type source region with a metal electrode (source / base common electrode). Operating at the same potential. This is necessary to prevent the silicon carbide MOSFET from performing a bipolar operation during the OFF operation and to quickly perform the OFF operation.

In order to minimize the switching loss due to the OFF operation, the base region and the source / base common electrode need to be ohmic contacts having a contact resistivity of 1e-3 Ωcm ² or less.

  Therefore, when a nickel (Ni) electrode is used for the source-base common electrode, p-type carbonization in which ions containing any of aluminum (Al), boron (B), or gallium (Ga) are implanted at a high concentration. It is necessary to form a silicon layer (base contact portion) at the junction between the base region and the source / base common electrode.

Therefore, in Non-Patent Document 1, Al ions having a concentration of 2e20 cm ⁻³ are implanted into the base region to form a base contact portion, and the base contact portion and the Ni electrode are brought into contact with each other, whereby the contact resistivity is 5e−3 Ωcm ² . Get ohmic contact.

  In addition, in the manufacturing process of silicon carbide MOSFETs, a technique is known in which ion implantation is performed with the silicon carbide substrate (silicon carbide wafer) held at a high temperature in order to increase the activation rate of the ion-implanted impurities by annealing. ing.

  Patent Document 1 discloses an invention in which a base region and a source region that are part of a silicon carbide MOSFET are formed by performing ion implantation with a silicon carbide substrate held at 1000 ° C. or higher.

S. Tanimoto, N.A. Kiritani, M .; Hoshi, and H.H. Okushi “Ohmic contact structure and Fabrication process applied to practical SiC devices”, Materials Science Forum, 389-393 (2001) 879. Japanese Patent No. 3206727

However, in the silicon carbide MOSFET, an ohmic contact having a contact resistivity of 1e-3 Ωcm ² or less is required for the contact between the source / base common electrode and the base contact portion in order to reduce the loss.

  Therefore, an ohmic contact having a lower contact resistivity than that disclosed in Non-Patent Document 1 is required.

  Furthermore, the crystallinity of the base contact portion is deteriorated due to high concentration ion implantation. Then, after forming the base contact portion, it is necessary to keep the silicon carbide substrate at a high temperature in the process of forming the activated annealing layer and the epitaxial channel layer.

  When the temperature of the silicon carbide substrate is maintained at a high temperature, a part of the base contact portion whose crystallinity has deteriorated due to ion implantation is sublimated, and the base contact portion is etched. That is, the thickness of the base contact portion is reduced by activation annealing or formation of an epitaxial channel layer.

  As a result, a step y (μm) is generated between the base contact portion and a region adjacent to the base contact portion (see FIG. 19 described later). Here, the level difference y is an index indicating how much the base contact portion has been etched by the activation annealing or the epitaxial channel layer manufacturing process.

  In addition, the base contact portion includes an epitaxial channel layer etching step (see FIG. 21 described later), a sacrificial oxidation and gate oxidation step (see FIG. 23 described later), and RTA (Rapid Thermal Annealing) at the time of source / base common electrode formation. Etching is further performed by about 0.1 to 0.2 μm by processing (see FIG. 26 described later).

  Therefore, the base contact portion is etched from the substrate surface to a depth of y + 0.1 to y + 0.2 μm when the entire manufacturing process of the silicon carbide MOSFET is performed.

  Therefore, assuming that the depth of the base contact portion is x, in order to effectively leave the base contact portion after the entire manufacturing process of the silicon carbide MOSFET, the step y and the depth x are at least y + 0.1 <x. It is necessary to satisfy.

  On the other hand, the level difference y is increased by increasing the depth x of the base contact portion or by increasing the thickness of the epitaxial channel layer. Therefore, it is difficult to design the depth x so as to satisfy the above conditions.

  As described above, the generation of the step y affects the design margin of the silicon carbide MOSFET manufacturing process, the contact failure between the base contact portion and the source / base common electrode, and the breakdown voltage drop when the silicon carbide MOSFET is OFF. Invite.

  Therefore, it is necessary to suppress the etching of the base contact portion due to the formation of the activated anneal or the epitaxial channel layer and to sufficiently reduce the step difference y.

  Further, when the manufacturing method of the base region and the source region disclosed in Patent Document 1 is applied to the manufacturing process of the base contact portion, the ion implantation is performed while maintaining the substrate temperature at a high temperature of 1000 ° C. or higher. Deterioration of crystallinity of the silicon carbide layer is prevented.

  Further, since deterioration of crystallinity due to ion implantation is prevented, there is a possibility that etching of the base contact portion during activation annealing or epitaxial channel layer formation can be suppressed.

  However, when the base contact portion is formed with the substrate temperature kept at 1000 ° C. or higher, the ion-implanted impurities are aggregated in the silicon carbide layer, and the electrical activation by the subsequent annealing process occurs in the ion-implanted region There is a risk that it will not be possible.

  Further, when the substrate temperature is set to 800 ° C. or higher, ion implantation into the silicon carbide layer may be hindered due to, for example, shielding of thermoelectrons emitted from the ion implantation apparatus or the silicon carbide substrate itself.

  Therefore, the object of the present invention is to suppress the etching of the base contact part in activation annealing or the like without problems such as aggregation of impurity ions in the silicon carbide layer, and the source-base common electrode and the base contact part are A method of manufacturing a silicon carbide semiconductor device that provides an ohmic contact with a low resistivity is provided.

  The invention according to claim 1 includes a silicon carbide underlayer, a p-type region formed in a surface layer portion of the silicon carbide underlayer, and a contact portion formed in a surface layer portion of the p-type region. A method for manufacturing a silicon semiconductor device, wherein the silicon carbide underlayer is maintained at 400 ° C. or higher and 800 ° C. or lower while implanting ions containing any of Al, B, or Ga into the p-type region. A step of forming a contact portion is provided.

  According to the first aspect of the present invention, the contact portion is formed by implanting ions containing any of Al, B, or Ga into the p-type region while holding the silicon carbide underlayer at 400 ° C. or higher and 800 ° C. or lower. Is forming.

  Since the ion implantation is performed while maintaining the temperature of the silicon carbide underlayer at 400 ° C. or higher and 800 ° C. or lower, the crystallinity of the contact portion can be prevented from deteriorating.

  Therefore, etching of the contact portion due to activation annealing or formation of an epitaxial channel layer can be suppressed.

  Further, since the silicon carbide underlayer is held at 800 ° C. or lower, there is no problem that impurity ions aggregate in the contact portion.

  As a result, when the present invention is applied to a silicon carbide MOSFET, a silicon carbide MOSFET in which the source / base common electrode and the base contact portion have an ohmic contact with a low resistivity without problems such as aggregation of impurity ions in the base contact portion. Can be manufactured.

<Embodiment 1>
<A. Ion implantation concentration of base contact portion and manufacturing method>
Before describing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, the base contact portion required for setting the contact resistivity between the base contact portion and the source / base common electrode to 1e-3 Ωcm ² or less. The ion implantation concentration and the base contact part manufacturing method will be described.

<A-1. Investigation of ion implantation concentration>
First, the silicon carbide semiconductor device 100 for resistivity evaluation shown in FIG. 1 is manufactured, and the resistivity of the ohmic contact is evaluated by TLM (Transmission Line Method). Then, the ion implantation concentration of Al ions necessary for obtaining the ohmic contact resistivity of 1e- ³ Ωcm ⁻³ or less is examined.

<A-1-1. Configuration of Silicon Carbide Semiconductor Device for Resistivity Evaluation>
FIG. 1 is a cross-sectional view showing a configuration of the silicon carbide semiconductor device 100 for resistivity evaluation described above.

  A silicon carbide epitaxial layer 2 made of n-type silicon carbide is formed on n-type silicon carbide substrate 1. A p-type hole conductive layer 3 is formed on silicon carbide epitaxial layer 2.

  Two base contact portions 4 are formed on the surface layer portion of the hole conductive layer 3 at a predetermined interval. An Ni electrode 5 is formed on the base contact portion 4.

  Hereinafter, a method for manufacturing silicon carbide semiconductor device 100 for resistivity evaluation will be described.

<A-1-2. Method for Manufacturing Silicon Carbide Semiconductor Device 100 for Resistivity Evaluation>
First, silicon carbide epitaxial layer 2 is formed on silicon carbide substrate 1 by a thermal CVD (Chemical Vapor Deposition) method.

Silicon carbide epitaxial layer 2 is formed so that the doping concentration of n-type impurities is 5e15 to 1.5e16 cm ⁻³ and the film thickness is 7 to 15 μm.

The silicon carbide epitaxial layer 2 has a substrate temperature of 1500 to 1600 ° C., an atmospheric pressure of 250 mbar, a carrier gas flow rate: H ₂ = 50 lm, and a generated gas flow rate: SiH ₄ / C ₃ H ₈ / N ₂ = 9 / 4.5 / 1. It is formed under the condition of 5 ccm.

Next, Al ions having a concentration of 5e18 cm ⁻³ are implanted into the entire surface of the silicon carbide epitaxial layer 2 to a depth of 0.7 to 1.0 μm to form the hole conductive layer 3.

Next, a mask (not shown) is formed on silicon carbide epitaxial layer 2 and Al ions having a concentration of 2e19 to 2e20 cm ⁻³ are implanted to a depth of 0.25 μm to form base contact portion 4.

  Next, Al ions in the base contact portion 4 and the hole conductive layer 3 are electrically activated by annealing at 1300 to 1900 ° C.

  Next, the Ni electrode 5 is formed on the base contact portion 4. Thereafter, the Ni electrode 5 and the base contact portion 4 are alloyed at the portion where they are in contact.

  Alloying is performed by RTA treatment at a temperature of 950 to 1000 ° C., a treatment time of 20 to 60 seconds, and a heating rate of 10 to 25 ° C./second.

  Thereby, silicon carbide semiconductor device 100 for resistivity evaluation shown in FIG. 1 is completed.

<A-1-3. Evaluation of ohmic contact resistivity>
Next, the contact resistivity between base contact portion 4 and Ni electrode 5 of silicon carbide semiconductor device 100 in FIG. 1 is evaluated by TLM.

  FIG. 2 shows IV characteristics measured in the range of applied voltage −1 to +1 V, with the distance between the electrodes (distance between the Ni electrodes 5) being 5 μm.

FIG. 2 shows I when the Al concentration of the base contact portion 4 is 2 × 10 ¹⁹ cm ⁻³ , 5 × 10 ¹⁹ cm ⁻³ , 8 × 10 ¹⁹ cm ⁻³ , and 2 × 10 ²⁰ cm ^−3. The -V characteristic is illustrated.

  As shown in FIG. 2, as the Al concentration of the base contact portion 4 becomes higher, the IV characteristics show better ohmic properties, and the resistance value between the electrodes becomes lower.

  This is because, as the Al concentration of the base contact portion 4 increases, the hole density generated in the base contact portion 4 increases, and the tunnel current of the holes flowing between the base contact portion 4 and the Ni electrode 5 increases. is there.

  Further, the same IV characteristic evaluation was performed with the distance between the electrodes set to 50 to 3 μm, and the contact resistivity (vertical axis) calculated by TLM for each Al concentration (horizontal axis) is shown in FIG.

As shown in FIG. 3, by the Al concentration in the base contact portion 4 1.5E20cm ^-3, the contact resistivity of 1e-3Ωcm ^-3 is obtained. When the Al concentration of the base contact portion 4 is further increased, the rate of decrease in contact resistivity tends to saturate.

  This is because the number of holes tunneling between the region of the base contact portion 4 and the Ni electrode 5 is saturated as the Al concentration increases.

Therefore, it is shown that an ohmic contact having a contact resistivity of 1e- ³ Ωcm- ³ or less can be obtained by implanting Al ions having a concentration of 1.5e20 cm- ³ or more to form the base contact portion 4.

<A-2. Manufacturing method of base contact part 4>
Next, a method for manufacturing the base contact portion 4 will be described.

<A-2-1. Condition of depth x of base contact portion 4>
First, the condition of the depth x of the base contact portion 4 will be described.

  As will be described later, in the silicon carbide MOSFET manufacturing process, the base contact portion 4 is etched due to the formation of the activation annealing at 1300 to 1900 ° C. and the epitaxial channel layer, and a step y is formed between adjacent regions. .

  Then, an etching process of the epitaxial channel layer (see FIG. 20), a sacrificial oxidation and gate oxidation process (see FIG. 22), and an alloying process of silicon carbide by RTA treatment when forming the source / base common electrode 20 (see FIG. 25). Thus, the base contact portion 4 is further etched by about 0.1 to 0.2 μm.

  Therefore, in order for base contact portion 4 to remain effectively after the completion of all the manufacturing steps of the silicon carbide MOSFET, depth x of base contact portion 4 needs to satisfy at least y + 0.1 <x. As a more optimal condition for the base contact portion 4 to remain effectively, it is necessary to satisfy y + 0.2 <x.

  On the other hand, the depth of the base region is 0.7 to 1.0 μm, and the maximum value of the depletion layer extending to the base region side among the depletion layers extending when the silicon carbide MOSFET is OFF is 0.1 μm. Degree.

  Then, the high-concentration Al ions implanted into the base contact portion 4 are distributed to a depth of about 0.1 μm further than the depth x.

  Considering the above, the depth of the base contact portion 4 is set to x <0.5 μm so that the base contact portion 4 does not affect the breakdown voltage when the silicon carbide MOSFET is OFF.

  FIG. 4 is a graph of the values of the level difference y and the depth x that satisfy the above conditions.

  In FIG. 4, a region 1 indicated by hatching is a region satisfying y + 0.1 <x and x <0.5. Further, a region 2 indicated by hatching in FIG. 4 is a region satisfying y + 0.2 <x and x <0.5.

<A-2-2. Production of silicon carbide semiconductor device for level difference y evaluation>
Next, in order to investigate the step y between the base contact portion 4 and the adjacent region, which is caused by the formation of the activated annealing at 1300 to 1900 ° C. and the formation of the silicon carbide epitaxial layer 10 after the formation of the base contact portion 4. Next, the silicon carbide semiconductor device 200 for level difference y evaluation shown in FIG. 5 is produced.

  In FIG. 5, n-type silicon carbide epitaxial layer 2 is formed on n-type silicon carbide substrate 1. Hole conduction layer 3 is formed on silicon carbide epitaxial layer 2. Two base contact portions 4 are formed on the surface layer portion of the hole conductive layer 3 at a predetermined interval. Silicon carbide epitaxial layer 10 is formed on hole conductive layer 3.

  Here, silicon carbide epitaxial layer 10 corresponds to epitaxial channel layer 16 (FIG. 13).

<A-2-3. Method for Manufacturing Silicon Carbide Semiconductor Device for Step Y Evaluation>
Hereinafter, a method of manufacturing silicon carbide semiconductor device 200 for level difference y evaluation shown in FIG. 5 will be described.

First, silicon carbide epitaxial layer 2 is formed on silicon carbide substrate 1 by a thermal CVD method. Silicon carbide epitaxial layer 2 is formed to have an n-type doping concentration of 5e15 to 1.5e16 cm ⁻³ and a film thickness of 7 to 15 μm.

The formation conditions of the silicon carbide epitaxial layer 2 are as follows: temperature 1500-1600 ° C., pressure 250 mbar, carrier gas flow rate: H ₂ = 50 lm, product gas flow rate: SiH ₄ / C ₃ H ₈ / N ₂ = 9 / 4.5 /1.5 ccm.

Next, Al ions having a concentration of 5e18 cm ⁻³ are implanted to a depth of 0.7 to 1.0 μm over the entire surface of the silicon carbide epitaxial layer 2 to form the p-type hole conductive layer 3.

Next, a mask (not shown) is formed on the hole conductive layer 3 and Al ions having a concentration of 2e20 cm ⁻³ are implanted to a depth of 0.25 μm to form the base contact portion 4.

  Here, in order to investigate the difference in etching of the base contact portion 4 that occurs after activation annealing or the formation of the silicon carbide epitaxial layer 10 due to the difference in substrate temperature during ion implantation, the substrate temperature during ion implantation is set to room temperature, 500. Those held at ℃ and 800 ℃ are prepared.

  Next, Al ions implanted into the base contact portion 4 and the hole conductive layer 3 are electrically activated by annealing at 1300 to 1900 ° C.

Next, silicon carbide epitaxial layer 10 having a film thickness of 0.1 to 2.0 μm made of silicon carbide having an n-type doping concentration of 1e15 to 3e17 cm ⁻³ is formed by thermal CVD.

The silicon carbide epitaxial layer 10 has a temperature of 1500 to 1600 ° C., an atmospheric pressure of 250 mbar, a carrier gas flow rate: H ₂ = 50 lm, and a generated gas flow rate: SiH ₄ / C ₃ H ₈ / N ₂ = 9 / 4.5 / 0.15. It is formed under the condition of 30 ccm.

  From the above, silicon carbide semiconductor device 200 for level difference y evaluation shown in FIG. 5 can be obtained.

<A-2-4. Step y measurement>
6 to 8 are diagrams respectively showing measurement results of the step y when the substrate temperature is set to room temperature, 500 ° C., and 800 ° C. during the ion implantation in the silicon carbide semiconductor device 200 for step y evaluation shown in FIG. is there.

  The depth of the base contact portion 4 (corresponding to the p ++ region in the figure) is measured using the surface of the region adjacent to the base contact portion 4 as a reference (Depth (vertical axis) = 0 nm). Therefore, Depth at the base contact portion 4 corresponds to the level difference y.

  As shown in FIG. 6, in silicon carbide semiconductor device 200 in which Al ions are implanted into base contact portion 4 at a substrate temperature of room temperature, level difference y is 200 to 300 nm.

  On the other hand, as shown in FIGS. 7 and 8, in silicon carbide semiconductor device 200 in which Al ion implantation is performed while maintaining the substrate temperature at 500 ° C. or 800 ° C., level difference y is suppressed to 20 nm or less.

  This is considered to be because the crystallinity deterioration of the silicon carbide single crystal due to high concentration ion implantation was suppressed by maintaining the substrate temperature at the time of Al ion implantation at a high temperature.

  In other words, it is considered that the crystallinity deterioration is suppressed, so that the etching due to the sublimation of silicon carbide and the decrease in the growth rate of the silicon carbide epitaxial layer 10 are suppressed in the subsequent high temperature process such as activation annealing.

  FIG. 9 shows the maximum value of the level difference y (vertical axis) after the formation of the silicon carbide epitaxial layer 10 with respect to the substrate temperature at the time of ion implantation (implantation temperature: horizontal axis).

  As shown in FIG. 9, the substrate temperature at the time of ion implantation is 400 ° C. or more, and the level difference y is suppressed to about 20 nm. The value of the level difference y sufficiently satisfies the condition shown in FIG.

  Although detailed data is not shown in FIG. 9, it has been found by experiments of the inventor that the maximum value of the step difference y changes along the line shown in FIG. Therefore, it can be seen from the line shown in FIG. 9 that the step y is suppressed to about 20 nm when the substrate temperature is 400 ° C. or higher.

  On the other hand, even if ion implantation is performed at a substrate temperature of 800 ° C. or higher, the level difference y can be suppressed to about 20 nm. However, the implanted Al aggregates in the silicon carbide, and the electrical ions of Al ions are activated by the subsequent activation annealing. There is a possibility that activation cannot be performed uniformly within the ion implantation region.

  Furthermore, if the substrate temperature is set to 800 ° C. or higher, ion implantation into the silicon carbide substrate may be hindered due to, for example, shielding of thermal electrons emitted from the implantation apparatus or the silicon carbide substrate itself.

  From the above, when Al ion implantation of the base contact portion 4 is performed, the step temperature y and the depth x have the x and y values shown in FIG. The base contact part 4 to be filled can be manufactured.

<A-2-5. Contact resistance evaluation of ohmic contacts>
Next, the contact resistivity of the ohmic contact is evaluated using silicon carbide semiconductor device 200 shown in FIG.

  Therefore, silicon carbide epitaxial layer 10 of silicon carbide semiconductor device 200 shown in FIG. 5 is all removed by etching, and Ni electrode 5 is formed on base contact portion 4.

  Then, RTA treatment is further performed to manufacture silicon carbide semiconductor device 200 having the same structure as that in FIG. Thereafter, the resistivity between the Ni electrodes 5 is evaluated by TLM.

FIGS. 10 to 12 show results obtained by evaluating the contact resistivity between the base contact portion 4 and the Ni electrode 5 formed by Al ion implantation at a concentration of 2e20 cm ⁻³ at a substrate temperature of 500 ° C. and 800 ° C. by TLM. is there.

  As shown in FIG. 10, in the silicon carbide semiconductor device 200 in which the substrate temperature during ion implantation is room temperature, the IV characteristics do not show good ohmic characteristics in the range of applied voltage −1 to 1V.

  This is because the level difference y between the regions generated after the formation of the silicon carbide epitaxial layer 10 is 300 nm at the maximum, so that the base contact portion 4 is all etched in the subsequent etching process of the silicon carbide epitaxial layer 10.

As shown in FIGS. 11 and 12, when the substrate temperature at the time of ion implantation is 500 ° C. and 800 ° C., the IV characteristics show good ohmic characteristics. The contact resistivity is 7.2e-4 Ωcm ^-3 and 9.5e-4 Ωcm ^-3 , respectively. This value sufficiently satisfies the contact resistivity required for the base contact portion 4 of the silicon carbide MOSFET.

  This is because the step y between the above-mentioned regions generated after the formation of the silicon carbide epitaxial layer 10 was 20 nm or less, and therefore the base contact portion 4 remained even after the etching process of the silicon carbide epitaxial layer 10.

  Next, a method for manufacturing a silicon carbide MOSFET to which the above-described method for manufacturing base contact portion 4 is applied will be described.

<B. Application to Silicon Carbide MOSFET>
<B-1. Structure of silicon carbide semiconductor device 300>
FIG. 13 is a cross sectional view showing a configuration of silicon carbide semiconductor device 300 according to the first embodiment. Here, silicon carbide semiconductor device 300 is an n-channel silicon carbide MOSFET.

  In FIG. 13, a drift layer (silicon carbide layer, silicon carbide underlayer) 12 made of n-type silicon carbide is formed on n-type silicon carbide substrate 1. A p-type base region (p-type region) 13 is formed at a predetermined interval in the surface layer portion of the drift layer 12. An n-type source region 14 is formed in the surface layer portion of the base region 13.

  An epitaxial channel layer 16 is formed on the drift layer 12. The epitaxial channel layer 16 is formed so as to cover from one source region 14 end to the other source region 14 end.

  A base contact portion (contact portion, p-type base contact region) 15 is formed in a region not covered with the epitaxial channel layer 16 in the surface layer portion of the base region 13.

  A source / base common electrode 20 is formed on the source region 14 and the base region 13. The base contact portion 15 and the source region 14 are connected by a source / base common electrode 20.

  A gate insulating film 17 is formed on the epitaxial channel layer 16. A gate electrode 18 is formed on the gate insulating film 17. An interlayer insulating film 19 is formed so as to cover the gate electrode 18 and the gate insulating film 17.

  Drain electrode 21 is formed on the surface of silicon carbide substrate 1 opposite to the surface on which drift layer 12 is formed.

<B-2. Method for Manufacturing Silicon Carbide Semiconductor Device 300>
Next, a method for manufacturing silicon carbide semiconductor device 300 according to the first embodiment will be described with reference to FIGS.

  First, drift layer 12 made of silicon carbide is formed on silicon carbide substrate 1 by a thermal CVD method (see FIG. 14).

The drift layer 12 is formed to have an n-type doping concentration of 5e15 to 1.5e16 cm ⁻³ and a film thickness of 7 to 15 μm. The drift layer 12 has a temperature of 1500 to 1600 ° C., an atmospheric pressure of 250 mbar, a carrier gas flow rate: H ₂ = 50 lm, and a generated gas flow rate: SiH ₄ / C ₃ H ₈ / N ₂ = 9 / 4.5 / 1.5 ccm. Form under conditions.

Next, the base region 13 is formed in the surface layer portion of the drift layer 12 (FIG. 15). The base region 13 is formed by forming a mask (not shown) on the drift layer 12 and implanting Al ions having a concentration of 5e17 to 2e18 cm ⁻³ to a depth of 0.7 to 1.0 μm. FIG. 15 shows a cross-sectional view after removing the mask.

Next, the source region 14 is formed in the surface layer portion of the base region 13 (FIG. 16). The source region 14 is formed by forming a mask (not shown) on the base region 13 and implanting N ions having a concentration of 1e19 to 3e19 cm ⁻³ to a depth of 0.2 to 0.5 μm. FIG. 16 shows a cross-sectional view after removing the mask.

Next, a mask (not shown) is formed outside each of the base regions 13 and Al ions having a concentration of 1e17 to 2e17 cm ⁻³ are implanted to a depth of 0.7 to 1.0 μm to form p-type JTE. (Junction Termination Extension) region (not shown) is formed.

  Next, the base contact portion 15 is formed on the surface layer portion of the base region 13 (FIG. 17).

The base contact portion 15 forms Al ions having a concentration of 1.5e20 cm ⁻³ or more at a depth of 0 in a state where the substrate temperature is maintained at 400 ° C. or higher, more preferably 800 ° C. or lower after a mask is formed on each base region 13. Formed by injecting to 1 to 0.5 μm. Here, the manufacturing conditions of the base contact portion 15 were set from the manufacturing conditions of the base contact portion 4 described above. FIG. 13 shows a cross-sectional view after removing the mask.

  Next, annealing is performed at a temperature of 1300 to 1900 ° C. by an annealing apparatus to electrically activate ions implanted in the substrate.

Next, an epitaxial channel layer 16 made of silicon carbide and having an n-type doping concentration of 1e15 to 3e17 cm ⁻³ and a film thickness of 0.1 to 2.0 μm is formed by thermal CVD (FIG. 18).

The epitaxial channel layer 16 has a temperature of 1500 to 1600 ° C., an atmospheric pressure of 250 mbar, a carrier gas flow rate: H ₂ = 50 lm, and a generated gas flow rate: SiH ₄ / C ₃ H ₈ / N ₂ = 9 / 4.5 / 0.15 to 30 ccm. The film is formed under the following conditions.

  Here, for comparison, FIG. 19 shows a cross-sectional view when the base contact portion 15 is formed by ion implantation at a substrate temperature of room temperature. As shown in FIG. 19, the base contact portion 15 is etched by the activation annealing and the manufacturing process of the epitaxial channel layer 16, and a step y is generated.

  Next, the drift layer 12 exposed between the pair of base regions 13 is positioned at the center of the epitaxial channel layer 16 by lithography and etching techniques, and the base region 13 and the source region 14 of the epitaxial channel layer 16 are formed. The shape is positioned at both ends. FIG. 20 shows a cross-sectional view after etching the epitaxial channel layer 16.

  Here, for comparison, FIG. 21 shows a cross-sectional view after etching the epitaxial channel layer 16 when Al ion implantation for forming the base contact portion 15 is performed at room temperature as in the prior art. In the conventional manufacturing method, as shown in FIG. 21, the base contact portion 15 is etched by activation annealing, etching of the epitaxial channel layer 16, etc., and a step y is generated.

  Next, a gate insulating film 17 is formed on the entire surface of the substrate (FIG. 22).

  Next, the drift layer 12 exposed between the pair of base regions 13 is positioned in the center by the lithography technique and the etching technique, and the gate region is formed in such a shape that the base region 13 and the source region 14 are positioned at both ends. The electrode 18 is formed (FIG. 23).

  Next, an interlayer insulating film 19 for electrically insulating the source region 14 and the gate electrode 18 is formed on the entire surface of the device (FIG. 24).

  Next, the gate insulating film 17 and the interlayer insulating film 19 on each source region 14 and the base contact portion 15 are removed by a lithography technique and an etching technique.

  Next, by removing the gate insulating film 17 and the interlayer insulating film 19, the source / base common electrode 20 is formed in a portion where the source region 14 and the base contact portion 15 are exposed on the surface.

  FIG. 25 shows a device cross section after the source / base common electrode 20 is formed.

  Next, drain electrode 21 is formed on the entire back surface side of silicon carbide substrate 1. Thereafter, in order to alloy the source / base common electrode 20 and the drain electrode 21 with the silicon carbide in contact with the silicon carbide element substrate, the temperature is increased from 950 to 1000 ° C., the processing time is from 20 to 60 seconds, and the temperature is increased. RTA treatment is performed at a rate of 10 to 25 ° C./second. Thereby, the silicon carbide semiconductor device shown in FIG. 13 is completed.

  Here, for comparison, FIG. 26 shows a cross-sectional view after forming the source / base common electrode 20 when Al ion implantation for forming the base contact portion 15 is performed at room temperature.

  As shown in FIG. 26, when Al ion implantation is performed at room temperature, the base contact portion 15 is etched away by the RTA process after the source / base common electrode 20 is formed. As a result, the source / base common electrode 20 and the base region 13 do not form an ohmic contact, and the loss during operation of the silicon carbide MOSFET increases.

<C. Effect>
According to the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment, the silicon carbide substrate 1 is maintained at 400 ° C. or higher and 800 ° C. or lower, and the base region contains any of Al, B, or Ga. The base contact portion 15 is formed by injecting.

  Since ion implantation is performed while maintaining the temperature of silicon carbide substrate 1 at 400 ° C. or higher and 800 ° C. or lower, deterioration of the crystallinity of base contact portion 15 can be prevented.

  Therefore, etching of the base contact portion 15 due to activation annealing or formation of the epitaxial channel layer 16 can be suppressed.

  In addition, since the silicon carbide substrate is held at 800 ° C. or lower, there is no problem that impurity ions aggregate in the silicon carbide layer.

  As a result, it is possible to manufacture a silicon carbide MOSFET having a sufficiently low resistance ohmic contact without causing problems such as aggregation of impurity ions in the silicon carbide layer and without causing a decrease in breakdown voltage or an increase in on-resistance of the silicon carbide MOSFET. Can do.

Further, according to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, since base contact portion 15 is formed with an ion implantation concentration of 1.5e20 cm ⁻³ or more, base contact portion 15 and source The contact of the base common electrode 20 can be an ohmic contact of 1e-3 Ωcm ² or less.

  Furthermore, according to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, since the implantation depth of ions implanted into base region 13 is 0.1 μm to 0.5 μm, etching of epitaxial channel layer 16 is performed. The base contact portion 15 can reliably remain even after the process, the sacrificial oxidation and gate oxidation process, and the silicon carbide alloying process by the RTA process when the source / base common electrode 20 is formed.

  Furthermore, since the depth of the base contact portion 4 is set to x <0.5 μm, the breakdown voltage when the silicon carbide MOSFET is OFF is not adversely affected.

  Furthermore, according to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, the method further includes the step of forming epitaxial channel layer 16 on drift layer 12, so that a silicon carbide MOSFET having a lower on-resistance is provided. Can be manufactured.

  In the first embodiment, the base contact portion 15 is formed by implanting Al ions into the base region 13, but may be formed by implanting ions containing any of Al, B, or Ga. Good.

  In the first embodiment, an example in which the present invention is applied to a silicon carbide MOSFET has been described. However, the present invention is not limited to a silicon carbide MOSFET, and contacts a p-type region in a silicon carbide underlayer. Any other structure can be applied as long as it has a portion.

1 is a cross sectional view of a silicon carbide semiconductor device for resistivity evaluation according to a first embodiment. It is a figure which shows the IV characteristic of the silicon carbide semiconductor device for resistivity evaluation which concerns on Embodiment 1. FIG. It is a figure which shows the contact resistivity of the silicon carbide semiconductor device for resistivity evaluation which concerns on Embodiment 1. FIG. It is a figure which shows the conditions of the level | step difference y required for the silicon carbide MOSFET which concerns on Embodiment 1, and ion implantation depth x. 1 is a cross sectional view showing a configuration of a silicon carbide semiconductor device for level difference y evaluation according to a first embodiment. It is a figure which shows the measurement result of the level | step difference y of the silicon carbide semiconductor device for level | step difference y evaluation based on Embodiment 1. FIG. It is a figure which shows the measurement result of the level | step difference y of the silicon carbide semiconductor device for level | step difference y evaluation based on Embodiment 1. FIG. It is a figure which shows the measurement result of the level | step difference y of the silicon carbide semiconductor device for level | step difference y evaluation based on Embodiment 1. FIG. It is a figure which shows the maximum value of the level | step difference y of the silicon carbide semiconductor device for level | step difference y evaluation which concerns on Embodiment 1. FIG. It is a figure which shows the IV characteristic of the silicon carbide semiconductor device for level | step difference y evaluation based on Embodiment 1. FIG. It is a figure which shows the IV characteristic of the silicon carbide semiconductor device for level | step difference y evaluation based on Embodiment 1. FIG. It is a figure which shows the IV characteristic of the silicon carbide semiconductor device for level | step difference y evaluation based on Embodiment 1. FIG. 1 is a cross sectional view showing a configuration of a silicon carbide MOSFET according to a first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide MOSFET according to the first embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon carbide substrate, 2,10 Silicon carbide epitaxial layer, 3 hole conductive layer, 4,15 Base contact part, 5 Ni electrode, 12 Drift layer, 13 Base region, 14 Source region, 16 Epitaxial channel layer, 17 Gate insulating film , 18 gate electrode, 19 interlayer insulating film, 20 source / base common electrode, 21 drain electrode.

Claims (5)

A silicon carbide underlayer;
A p-type region formed in a surface layer portion of the silicon carbide underlayer;
A contact portion formed on a surface layer portion of the p-type region;
A method for manufacturing a silicon carbide semiconductor device comprising:
A step of forming the contact portion by implanting ions containing any of Al, B, or Ga into the p-type region while maintaining the silicon carbide underlayer at 400 ° C. or more and 800 ° C. or less. A method for manufacturing a silicon carbide semiconductor device. The silicon carbide underlayer is a silicon carbide layer formed on a silicon carbide substrate,
The p-type region is a p-type base region of a MOSFET,
The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the contact portion is a p-type base contact region of a MOSFET. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step includes a step in which an ion implantation concentration is 1.5e20 cm ⁻³ or more.   4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step includes a step in which the ion implantation depth is 0.1 μm to 0.5 μm. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of forming an epitaxial channel layer on the silicon carbide underlayer after the step.

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