JP2007066928A - Etching method, etching apparatus and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a kind of gas, a process or a treatment device which has a high selection ratio to a base Si and less change in processing length, and can process a gate at high accuracy when a high dielectric-constant gate insulating film is etched by plasma. <P>SOLUTION: Gas suitable for etching a high dielectric-constant gate insulating film by plasma is a mixed gas of BCl<SB>3</SB>and a carbon fluoride gas. The carbon fluoride gas uses CF<SB>3</SB>Cl, CF<SB>2</SB>Cl<SB>2</SB>, CHF<SB>3</SB>and CH<SB>2</SB>F<SB>2</SB>, or a mixed gas thereof, or a mixed gas of the mixed gas and CF<SB>4</SB>, or a mixed gas of the above mixed gas and Ar. Thus, a selection ratio to a base Si can be made high, and a change in processing length caused by deposition or surface roughness can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an etching method and apparatus in plasma etching for processing an object to be processed using plasma, and a semiconductor device manufactured by them.

  With the progress of miniaturization and high integration of ULSI elements, devices with a gate length of 90 nm have shifted to mass production, and devices of 65 nm, 45 nm, and 32 nm are being developed. For high-speed operation of the LSI, it is necessary to improve the operation speed of the transistor and overcome the propagation delay of the multilayer metal wiring. For high-speed operation of transistors, it is necessary to prevent leakage in the gate insulating film and reduce the resistance of the device. As a solution to this problem, the development of a device using a high dielectric constant gate insulating film and a refractory metal gate electrode is required. It is being advanced. A very stable oxide containing Hf and Zr is used for the high dielectric constant gate insulating film, and a thin oxide film is formed on the Si substrate. Development of a refractory metal gate electrode film on a high dielectric constant gate insulating film is underway using nitride or W containing Ta or Ti in view of electrical characteristics and stability. Japanese Patent Application Laid-Open No. 2004-207481 (Patent Document 1) describes an example in which the above materials are used for a high dielectric constant gate insulating film and a refractory metal gate electrode film.

  Since many elements are mounted on the ULSI and an accurate operation is required, the gate electrode needs to be processed to an accurate gate length. The 90 nm node requires processing accuracy of several nm or less. For this processing, dry etching using a plasma processing apparatus is used. Conventionally, polycrystalline Si has been used for the gate electrode, and an example of using a mixed gas of chlorine and bromine containing gas and oxygen can be seen when etching the gate electrode. Etching of the refractory metal gate electrode film is also performed using a Cl-based gas.

On the other hand, in order to save the number of process steps, it is desirable to remove the high dielectric constant insulating film by dry processing in the same apparatus. Regarding the removal of the high-dielectric-constant insulating film by dry processing, Japanese Patent Application Laid-Open No. 2004-2004
No. 146787, “Cletching gas of high dielectric constant material and cleaning method of high dielectric constant material deposition chamber” (Patent Document 2) uses Cl-based gas such as BCl ₃ , COCl ₂ , C _x H _y Cl _z It is written. When a high dielectric constant insulating layer is dry-etched with a gate structure, a process with a high selectivity is required in order not to scrape the underlying Si substrate. In the above-described prior art, the examination on this point is not described.

In addition, in Japanese Patent Laid-Open No. 2005-045126 “Semiconductor Device Manufacturing Method” (Patent Document 3), in order to etch a high dielectric constant insulating film in a stable state with good reproducibility, the etching rate is too high with BCl ₃ alone. Therefore, it is stated that BCl ₃ is diluted with Ar to lower the etching rate and improve controllability. Due to Ar dilution, the etching rate and the deposition rate decrease.

In Japanese Unexamined Patent Application Publication No. 2004-356575 “Method for Manufacturing Semiconductor Device” (Patent Document 4), in order to increase a process margin when etching a high dielectric constant insulating film, the high dielectric constant insulating film is dry-etched, It is described that a damaged layer is formed while removing a part thereof, and the damaged layer is removed by wet etching. As examples of dry etching gas, BCl ₃ , Cl ₂ , HBr, CF ₄ , O ₂ , Ar, N Mention is made of at least one gas selected from the group consisting of ₂ and He. As a gas capable of forming a damaged layer while removing a part of the high dielectric constant insulating film by dry etching, all gases having no depositability are applicable. On the other hand, here, the purpose is to selectively etch the oxide film with respect to the underlying Si by dry etching, and gas having no depositability as BCl ₃ / CF ₄ is excluded.

In Japanese Patent Laid-Open No. 2004-296477, “Manufacturing Method of Semiconductor Device” (Patent Document 4), BCl ₃ , Cl is used as a dry etching gas for the purpose of selectively etching a high dielectric constant insulating film with respect to a base SiO ₂ film. ₂ , at least one gas selected from the group consisting of HBr, CF ₄ , O ₂ , Ar, N ₂ and He is mentioned. In order to obtain a selective ratio with respect to the underlying SiO ₂ film, CF ₄ is not suitable, and a mixture of chlorine (bromine) and O ₂ is indispensable. In addition, the use of CF ₄ increases the etching rate of the oxide film, so it is necessary to decrease the etching rate by Ar dilution or the like. However, this is a problem that the etching rate of the side wall and the underlying Si is increased at the same time. is there.

JP 2004-207481 A JP 2004-146787 A Japanese Patent Laying-Open No. 2005-045126 JP 2004-356575 A

  When etching is performed using the etching gas disclosed in Patent Documents 1 to 4, the amount of shaving of the underlying Si increases, but the amount of Si shaving is preferably small. The reason is that there is a cleaning process after etching, and Si is further retreated, although it depends on damage and contamination of the Si surface. If the substrate Si is largely missing, the characteristics of the element change. In addition, the size of the defect occurs non-uniformly within the wafer surface due to the non-uniformity of the processing speed of the etching apparatus. Therefore, the variation in device characteristics increases when the underlying surface is greatly removed. Therefore, the smaller the undercoat removal rate, the smaller the device characteristic change and its variation.

  An object of the present invention is to etch a high dielectric constant insulating film layer with a plasma processing apparatus in order to reduce the number of processing steps when etching a device structure having a high dielectric constant insulating film layer and a gate electrode wiring layer on an oxide film. An object of the present invention is to provide a gas type, a process and a processing apparatus which can be processed at a low cost with a high selection ratio with respect to the underlying Si.

One feature of the present invention is that a gas containing BCl ₃ and CH _x F _y or CF _x Cl _y is used when etching a device structure having a high dielectric constant insulating film layer and a gate electrode wiring layer on an oxide film. Is used as an etching gas.

  Other features of the present invention will be described in the best mode section for carrying out the invention of the present specification.

  According to the present invention, when etching a high dielectric constant gate insulating film, an etching gas having a high deposition ratio with respect to the underlying Si and a low deposition property is used. Si machining and machining length change can be reduced, and high precision gate machining can be realized.

  A vacuum chamber having a processing chamber into which a gas is introduced from a gas introduction system and an electrode for supporting a wafer is provided. There is a high-frequency generating means outside the processing chamber, and the gas in the processing chamber is ionized and dissociated to generate plasma. In the plasma processing apparatus that generates the above, a gas that can be used at a low cost and a method for etching the high dielectric constant gate insulating film on the Si substrate with a high selectivity relative to the underlying Si will be described.

Regarding the gas used, it is preferable to use a gas that is relatively easy to react and vaporize with respect to the high dielectric constant insulating film layer, hardly causes a vaporization reaction to the underlying Si, and can be used at low cost. By examining the enthalpy change in the reaction against the expected vaporization reaction, it is possible to know the ease of the reaction. By examining this for each candidate gas, a promising etching gas can be known. For example, when BCl ₃ and HfO ₂ react, a reaction of (4/3) BCl ₃ + HfO ₂ → HfCl ₄ + (2/3) B ₂ O ₃ (g) can be assumed, and the enthalpy at 25 ° C. is 31.
An increase in kcal / mol can be seen from data books such as CRC Handbook of Physics and Chemistry. When the gas products HfCl ₄ and (2/3) B ₂ O ₃ are continuously exhausted while always supplying the gas BCl ₃ as in the case of the plasma etching apparatus, this reaction is gradually increased even if it is disadvantageous in terms of energy. Progress. Rather, it can be understood that the etching rate is suitable for HfO ₂ which is a thin film of several nm. Such examination may be performed for each candidate gas. On the other hand, for Si, it can be seen that the enthalpy is reduced by 28 kcal / mol in the reaction of (4/3) BCl ₃ + Si → SiCl ₄ + (4/3) B (c). For this reason, a thin solid B layer is formed on the Si surface, but since B can be vaporized as BCl ₃ , the surface B layer remains thin, and Si is continuously etched by the effect of ion sputtering. Therefore, only BCl ₃ gas cannot achieve a high selectivity with respect to Si. On the other hand, the gas CH ₂ Cl _2, the HfO ₂ is difficult to vaporize than BCl _3, but for Si is
When a C layer is formed on the surface by vaporizing SiH ₂ Cl ₂ , the enthalpy is reduced by 22 kcal / mol due to the reaction of CH ₂ Cl ₂ → C (s) + 2HCl (g). Protection can be increased. However, a gas containing Cl such as CH _x Cl _y is expensive because it requires a special excluding device from the viewpoint of safety and environmental problems, and is not preferable. In addition, although a selection ratio to the underlying Si is required, if a deposition gas is used for the slow etching of HfO ₂ / SiO ₂ , deposits adhere to the sidewalls of the already processed gate electrode, The problem that the dimension after a process changes from a design value generate | occur | produces. Since this is a trade-off with the selection ratio of Si to the base, it is necessary to carefully select the gas to be used.

First, the effect of CF ₄ and the BCl ₃ mixing effect will be described. In the case of CF ₄ alone, oxide etching is likely to proceed as CF ₄ + HfO ₂ → HfF ₄ + CO ₂ (−60 kcal / mol). In the following, the unit in parentheses, kcal / mol is omitted, and only the numerical value is shown. On the other hand, for Si, initially CF ₄ + Si → SiF ₄ + C (−165), and C is deposited, but thereafter (1) 2F ₂ + C (+221), (2) CF ₄ (0 ), (3) As can be seen from the reaction formula 0.5SiF ₄ + 0.5C ₂ F ₄ (−50), vaporization is more advantageous in energy than deposition on C. Remains very thin and the underlying Si is also etched. Next, in the case of a BCl ₃ / CF ₄ mixed gas, the etching of the oxide film proceeds in the same manner. However, on Si, (1) BF ₃ + FCl + Cl ₂ + C (+33), (2) BF ₃ + CFCl ₃ (−20), (3) BF ₃ + 0.25SiF ₄ + 1.5Cl ₂ + C (−51) As you can see from the equation, it is still on the vaporization side, but it is clear that it has shifted significantly in the direction of deposition. From this, it can be seen that even when the gas is not used individually, a gas with which the selectivity to Si can be obtained can be obtained by mixing BCl ₃ and a halogenated carbon gas. On the other hand, it can be expected that mixing of halogenated carbon gas, which has a strong deposition property with BCl ₃ , further increases the deposition property and adversely affects the shape. Therefore, a gas having a weak deposition property as much as possible is required as a mixed gas of BCl ₃ and a halogenated carbon gas.

Considering a mixed gas of CF ₄ , CF ₃ Cl, CF ₂ Cl ₂ , CHF ₃ , CH ₂ F _2, and BCl _{3 in} the selection of gas that satisfies the progress of the HfO ₂ / SiO ₂ etching and the selection ratio / shape. . These halogenated carbon gases can be used alone or in combination. In addition, since these can be used sufficiently for etching of oxide films, they concentrate on the problems of the selectivity with respect to the underlying Si and the shape caused by deposits such as sidewalls, which are problems in removing the gate insulating oxide film by plasma treatment. To discuss whether it can be used. That is, in the following, the reaction on Si will be discussed. In the reaction with Si, Si is vaporized at the initial stage and the C-based film remains on the surface. However, the deposition property of the gas can be known from the subsequent reaction of the mixed gas on the C-based film. As a result, it is possible to know the deposition gas as weak as possible, which is a request from the shape problem.

BCl ₃ + CF ₄ → (1) BF ₃ + FCl + Cl ₂ + C (+33),
(2) BF ₃ + CFCl ₃ (−20)
BCl ₃ + CF ₃ Cl → (1) BF ₃ + 2Cl ₂ + C (−9),
(2) BCl ₃ + CF ₃ Cl (0)
BCl ₃ + CF ₂ Cl ₂ → (1) BF ₂ Cl + 2Cl ₂ + C (−2),
(2) BCl ₃ + CF ₂ Cl ₂ (0),
BCl ₃ + Cl ₂ + 0.5 * C ₂ F ₄ (+36)
BCl ₃ + CHF ₃ → (1) BF ₃ + HCl + Cl ₂ + C (−33),
(2) BF ₃ + CHCl ₃ (−29),
_{BCl 3 + HF + 0.5 * C} 2 F 4 (+22)
BCl ₃ + CH ₂ F ₂ → (1) BF ₂ Cl + 2HCl + C (−53),
(2) BF ₂ Cl + CH ₂ Cl ₂ (−31),
BCl ₃ + H ₂ + 0.5 * C ₂ F ₄ (+29)
In the above five reaction formulas, (1) is a reaction involving the deposition of a C-based film, (2) is a reaction in which the input gas is vaporized, the numbers in parentheses are enthalpy changes after the reaction, and the unit is kcal / mol. . It can be seen that, except for BCl ₃ + CF ₄ , the deposition reaction is more likely to occur, and in particular, BCl ₃ + CH ₂ F ₂ is clearly stronger in the deposition reaction. Here, when the reactions of (1) and (2) are compared, since the formation molecule of (1) is smaller and the formation reaction is faster, the difference in enthalpy indicates that (1) is more likely to occur than (2). It is necessary to consider in addition to. From this, on the vaporization side, BCl ₃ / CF ₄ is left as a candidate for examination. Further, due to the limitation of the shape problem, the CH ₂ F ₂ mixing ratio needs to be reduced to reduce the deposition property. Further, by mixing CF ₄ with gases CH ₂ F ₂ , CHF ₃ , CF ₂ Cl ₂ , and CF ₃ Cl that exhibit deposition properties when mixed with BCl ₃ , the deposition properties can be further reduced. In the above description, Si is considered. However, the deposition property is the property of the gas itself, and thus the same applies not only to Si but also to the side wall of the gate electrode.

It was confirmed from the above discussion that the gas deposition property and the Si selection ratio with respect to the base were increased by mixing BCl ₃ and CF gas. On the other hand, the addition of C and F increases the etching property for oxide films and nitride films. Japanese Patent Application Laid-Open No. 2005-045126 “Semiconductor Device Manufacturing Method” states that an oxide film of several nm can be removed in a short time with only BCl ₃ and the etching rate is high. For this reason, it is necessary to reduce the amount of radicals that reach the substrate, lengthen the time for removing the oxide film, and make the process stop control sufficiently possible. This means includes low pressure treatment and dilution with an inert gas such as Ar. In this case, the etching rate decreases, but the deposition rate also decreases because the deposition radicals also decrease. Further, since the ratio of ions to radicals is increased, the ratio of vaporization by ion bombardment is increased. For this reason, the gas on the vaporization side, such as BCl ₃ / CF ₄ , BCl ₃ , CF _4, etc., moves to the vaporization side more easily due to Ar dilution or the like, so that the underlying Si can be easily removed, so that it is removed from the gas used. .

From the above, when etching a device structure that has a high dielectric constant insulating film layer and a gate electrode wiring layer on an oxide film, the high dielectric constant insulating film layer is also etched by a plasma processing apparatus to reduce the number of processing steps. The gas species that has a high selectivity with respect to the underlying Si, has a small change in processing dimensions, and can be processed at low cost is a mixed gas of BCl ₃ and fluorinated C-based gas. The fluorinated C-based gas is CH ₂ F ₂ , CHF ₃ , CF ₂ Cl ₂ , CF ₃ Cl, a mixed gas thereof, a mixed gas with CF ₄ , or a mixed gas with an inert gas such as Ar. is there. The high dielectric constant insulating film layer is an insulating layer made of any of HfO ₂ , ZrO ₂ , Hf _x SiO _y , Zr _x SiO _y, a nitride thereof, or a laminated structure thereof.

  An embodiment of the present invention will be described with reference to FIGS.

  Since a large number of elements are mounted on the ULSI and an accurate operation is required, the gate electrode is processed to an accurate gate length. After that, when the high dielectric constant gate insulating film is etched by the plasma processing apparatus, it is necessary to process with a high selection ratio with respect to the underlying Si, and to process the gate insulating film with an accurate gate length. Gas type, process and processing equipment are required. The present embodiment relates to a method of etching gas 6 into plasma, but the main point is in gas component 20 constituting gas 6 and provides a method for processing the high dielectric constant gate insulating film with high accuracy. There is to do. Therefore, first, gas selection guidelines will be described, followed by examples and effects.

As a guideline for gas selection, the means for solving the problems are described. FIG. 1 summarizes the effects on the selectivity and shape of each of BCl ₃ , CF ₃ Cl, CF ₂ Cl ₂ , CHF ₃ , CH ₂ F ₂ , and CF ₄ , and mixed gas. As already described, all of the gases shown in FIG. 1 can etch the oxide film. Further, the gas containing carbon can etch the oxynitride film. Therefore, the selectivity to Si and the depositability on the side wall of the gate electrode are problems, and FIG. 1 collectively shows the effect. Regarding the Si etching property, it is necessary to be smaller than the etching property of BCl ₃ . For this reason, most of the single gas of FIG. 1 is removed from use. Further, the deposition property is related to the Si non-etching property, but if it is large, it will be deposited on the side wall and the processing dimension will change, and if uneven deposition occurs, the surface will become rough. Therefore, the single gas CH ₂ F ₂ is also excluded from use. In addition, since the mixed gas has a high oxide film / nitride film etching property, it is necessary to lengthen the processing time for controlling the etching stop, and low pressure processing and dilution of inert gas such as Ar are necessary. Shift in the direction of vaporization. Therefore, it is desirable that the gas suitable for use does not have the Si etching property of FIG. 1 and the deposition property is very small or small. However, in the case of a mixed gas, the deposition ratio can be adjusted to be weaker by decreasing the mixing ratio of the deposition cause gas, so that it can be used, and BCl ₃ / CH ₂ F ₂ can also be used.

A first embodiment of the present invention will be described using the device structure of FIG. 3 and the etching apparatus of FIG. FIG. 3 shows a target device structure, which includes a high dielectric constant gate insulating film 19 on a silicon substrate 18, a refractory metal film 21 processed into a gate electrode, and a hard mask 22. This gate structure is etched using plasma, and then the gate insulating film is also removed by plasma treatment. An example of the refractory metal film is TiN, which is not limited to a single layer but may be a multilayer film. As the high dielectric gate insulating film, it includes HfO _2, which also may be of two or more layers. An example of an etching apparatus for performing etching is shown in FIG. The plasma processing apparatus includes a vacuum chamber 1 including a processing chamber 3 into which a gas 6 is introduced via a gas introduction system 2 and a support base (electrode) 5 that supports an object (wafer) 4 to be processed. The gas is exhausted by the exhaust system 7. The wafer 4 is configured with the device shown in FIG. The μ wave 9 generated by the μ wave generation source 8 is guided to the cavity 11 surrounded by the metal wall through the waveguide 10 and is guided to the processing chamber 3 through the introduction window 12. A shower plate for supplying gas is arranged under the introduction window. A magnetic field of about 1 kGauss is generated by the magnet / coil 13 outside the processing chamber. The gas 6 introduced into the processing chamber is ionized and dissociated by the interaction between the μ-wave electric field and the magnetic field, and plasma 14 and dissociated species (radicals) 15 are generated. The wafer 4 is disposed on the support 5 and a high frequency from the connected high frequency power supply 16 is applied. A diffusion prevention film (etch stop film) 19 and a low dielectric constant film 18 are formed on the wafer 4. Ions in the plasma are attracted by the high frequency applied to the support 5 to process the wafer.

  In the above, the case of an etching apparatus using a μ wave and a magnetic field is shown, but an apparatus using another plasma generation method may be used. Other methods include a parallel plate type RF device that has upper and lower electrodes arranged in parallel in a vacuum vessel, and applies a high frequency to the upper electrode, the lower electrode, or both, a magnetic field coil and a parallel plate type device. Magnetron type devices with magnets, inductively coupled devices that apply RF to vacuum vessels and coiled antennas made of dielectrics, and devices that use high frequency in the VHF band and UHF band. It may be used.

This embodiment relates to a method for etching gas 6 into plasma. The main point is in gas component 20 constituting gas 6, and BCl ₃ and F are used as etching gas 20a for etching the gate insulating film with plasma. It is characterized by using a mixed gas with a carbonaceous gas. As shown in FIG. 1, these gases selectively etch the gate insulating film with respect to the underlying Si, and because the deposition property is small, deposition on the side wall of the gate electrode is difficult to occur, and the processing length hardly changes. In addition, surface roughness due to uneven deposition on the surface does not occur.

The etching characteristics when BCl ₃ / CF ₃ Cl is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi on it, and a mask thereon. The processing conditions were: plasma source power 500 W, 12-inch wafer electrode RF power 15 W, flow rate BCl ₃ / CF ₃ Cl = 50 sccm / 50 sccm pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 10 seconds. At that time, the amount of the underlying Si was 1 nm, and the amount of change in the processing length of the gate insulating film was 3 nm. Roughness was not observed. BCl ₃ / CF ₃ Cl was confirmed to be a sufficiently usable gas. Here, the reason why the pressure in the reaction vessel is lowered and the processing time is shortened is that the rate of etching the oxide film by the used mixed gas is higher than BCl ₃ . By reducing the pressure, the amount of radicals that etch the oxide film decreases, and the etching rate can be controlled to stop etching. In addition, an inert gas such as Ar can be mixed to reduce the amount of radicals. In this case, the control range can be further expanded. When the amount of radicals decreases due to such low pressure or inert gas dilution, in addition to the etching rate decrease, the ion density relatively increases and physical sputtering increases, so the deposition rate exceeds the radical reduction effect. It is advantageous in terms of shape to the process of the lowered and depositing gas mixture. On the other hand, the increase in physical sputtering is not very advantageous in terms of the etching of the underlying Si, except for the etching rate reduction, for the gas for etching the underlying Si such as BCl ₃ .

As a comparative example, it described etching characteristics when using only BCl ₃ in the apparatus. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions were as follows: plasma source power 500 W, electrode RF power 10 W, flow rate BCl ₃ = 100 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 20 seconds. At that time, the amount of the underlying Si was 4 nm, the processing length change of the gate insulating film was 2 nm or less, and no surface roughness was observed. It was confirmed that BCl ₃ was a gas that was difficult to use because the amount of Si undercutting was too large.

As a second example describes the etching characteristics when using BCl ₃ / CF ₂ Cl ₂ in the apparatus. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions were: plasma source power 500 W, electrode RF power 15 W, flow rate BCl ₃ / CF ₂ Cl ₂ = 55 sccm / 45 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 10 seconds. At that time, the amount of the underlying Si was 1 nm or less, and the amount of change in the processing length of the gate insulating film was 4 nm. Roughness was not observed. BCl ₃ / CF ₂ Cl ₂ was confirmed to be a sufficiently usable gas.

As a third embodiment, etching characteristics when BCl ₃ / CHF ₃ is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions were: plasma source power 500 W, electrode RF power 20 W, flow rate BCl ₃ / CHF ₃ = 70 sccm / 30 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 10 seconds. At that time, the amount of substrate Si shaving is 1
The processing length variation of the gate insulating film was 5 nm. Roughness was not observed. BCl ₃ / CHF ₃ was confirmed to be a sufficiently usable gas.

As a fourth embodiment, etching characteristics when BCl ₃ / CH ₂ F ₂ is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions were: plasma source power 500 W, electrode RF power 20 W, flow rate BCl ₃ / CH ₂ F ₂ = 90 sccm / 10 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 10 seconds. At that time, the amount of underlying Si shaving was 1 nm or less, and the amount of change in the processing length of the gate insulating film was 5 nm. Roughness was not observed. BCl ₃ / CH ₂ F ₂ was confirmed to be a sufficiently usable gas.

As a fifth embodiment, etching characteristics when BCl ₃ / CF ₂ Cl ₂ / CF ₄ is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure is
A laminated gate insulating film Hf _x SiO _y / HfO ₂ is formed on the Si substrate, and a gate electrode film is formed thereon.
A structure with PolySi and a mask thereon was used. The processing conditions are: plasma source power 500 W, electrode RF power 15 W, flow rate BCl ₃ / CF ₂ Cl ₂ / CF ₄ = 50
sccm / 20/30 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., treatment time 10 seconds. At that time, the amount of underlying Si scraping was 1.5 nm, and the processing length variation of the gate insulating film was 2 nm. Roughness was not observed. BCl ₃ / CF ₂ Cl ₂ / CF ₄ was confirmed to be a sufficiently usable gas.

As a sixth embodiment, etching characteristics when BCl ₃ / CHF ₃ / CF ₄ is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions were plasma source power 500 W, electrode RF power 15 W, flow rate BCl ₃ / CHF ₃ / CF ₄ = 50 sccm / 10/40 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 10 seconds. At that time, the amount of underlying Si scraping was 1.5 nm, and the processing length variation of the gate insulating film was 2 nm. Roughness was not observed. BCl ₃ / CHF ₃ / CF ₄ was confirmed to be a sufficiently usable gas.

As a comparative example, the etching characteristics when BCl ₃ / CF ₄ is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions were: plasma source power 500 W, electrode RF power 10 W, flow rate BCl ₃ / CF ₄ = 50 sccm / 50 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 10 seconds. At that time, the amount of underlying Si shaving was 3 nm, and the amount of change in the processing length of the gate insulating film was 1 nm or less. Roughness was not observed. The amount of underlying Si was large, and BCl ₃ / CF ₄ was confirmed to be a difficult gas to use.

As a seventh embodiment, etching characteristics when BCl ₃ / CF ₃ Cl / Ar is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions are: plasma source power 500 W, electrode RF power 10 W, flow rate BCl ₃ / CF ₃ Cl / Ar = 10 sccm / 10
sccm / 80 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., treatment time 30 seconds. At that time, the amount of underlying Si shaving was 1 nm or less, and the processing length variation of the gate insulating film was 1 nm or less. Roughness was not observed. BCl ₃ / CF ₃ Cl / Ar was confirmed to be a sufficiently usable gas.

As a comparative example, the etching characteristics when BCl ₃ / Ar is used in the above apparatus will be described. As for the etching characteristics, the amount of underlying Si shaving after processing and the amount of change in the processing length of the gate insulating film with respect to the side wall of the gate electrode were examined. The etched device structure used was a structure having a laminated gate insulating film Hf _x SiO _y / HfO ₂ on a Si substrate, a gate electrode film PolySi thereon, and a mask thereon. The processing conditions were plasma source power 500 W, electrode RF power 10 W, flow rate BCl ₃ / Ar = 20/80 sccm, pressure 0.2 Pa, electrode temperature 50 ° C., and processing time 50 seconds. At that time, the amount of the underlying Si was 3 nm, the processing length change of the gate insulating film was −1 nm, and no surface roughness was observed. However, it was thought that BCl ₃ / Ar was difficult to use because the amount of Si undercutting was too large.

The figure which shows the gas component by the Example of this invention, and its combination. The figure which shows the plasma processing apparatus used for the Example of this invention. The figure which shows the device structure which consists of Si substrate and the high dielectric constant gate insulating film / gate electrode film / mask concerning the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Vacuum vessel, 2 ... Gas introduction system, 3 ... Processing chamber, 4 ... To-be-processed object, 5 ... Support stand, 6 ... Gas, 7 ... Exhaust system, 8 ... Microwave generation source, 9 ... Microwave, 10 ... Waveguide, 11 ... cavity, 12 ... introduction window,
DESCRIPTION OF SYMBOLS 13 ... Magnet / coil, 14 ... Plasma, 15 ... Radical, 16 ... High frequency power supply, 17 ... Temperature control means, 18 ... Silicon substrate, 19 ... High dielectric constant gate insulating film, 20 ... Gas component, 21 ... High melting point metal film (Nitride containing Ta), 22... Hard mask, 23.

Claims (13)

When etching a device structure having a high dielectric constant insulating film layer and a gate electrode wiring layer on an oxide film, the high dielectric constant insulating film layer is also etched by a plasma processing apparatus, and includes BCl ₃ and CH _x An etching method using a gas containing F _y or CF _x Cl _y as an etching gas. 2. The etching method according to claim 1, wherein BCl ₃ and CF ₃ Cl are used as etching gases. _{2. The} etching method according to claim 1, wherein BCl ₃ and CF ₂ Cl ₂ are used as etching gases. 2. The etching method according to claim 1, wherein BCl ₃ and CHF ₃ are used as etching gases. _{2. The} etching method according to claim 1, wherein BCl ₃ and CH ₂ F ₂ are used as etching gases. The etching method according to claim 2, wherein CF ₄ is further mixed with the etching gas. 4. The etching method according to claim 3, wherein CF ₄ is further mixed with the etching gas. 5. The etching method according to claim 4, wherein CF ₄ is further mixed with the etching gas. 6. The etching method according to claim 5, wherein CF ₄ is further mixed with the etching gas.   The etching method according to claim 2, wherein Ar is further mixed with the etching gas. 2. The high dielectric constant insulating film layer according to claim 1, wherein the high dielectric constant insulating film layer is formed of HfO ₂ , ZrO ₂ , Hf _x SiO _y ,
An etching method comprising any one of Zr _x SiO _y, a nitride thereof, or a laminated structure thereof. An etching apparatus comprising an etching means for etching a device structure having a high dielectric constant insulating film layer and a gate electrode wiring layer on an oxide film, the etching means comprising BCl ₃ and CH _x F _y or CF _x Cl _y An etching apparatus using a gas containing oxygen as an etching gas. A semiconductor device having a high dielectric constant insulating film layer and a gate electrode wiring layer etched using a gas containing BCl ₃ and CH _x F _y or CF _x Cl _y as an etching gas.

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