JP2007066406A - Semiconductor integrated circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. <P>SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank selecting part 19 at the time of erasing bias. Successively, erasing verify is finished, when erasing-verify of an arbitrary bank is passed out of banks Bank 0 to Bank 3, a controller outputs a sub-decoder control signal Csub to a bank selecting part 19 corresponding to a bank in which erasing-verify is passed (e.g. shifting from a Hi level to a Lo level). Thereby, the verify pass signal VP output from the bank selecting part 19 is reversed. Receiving this, a main decoder circuit 20 makes a word line in the bank in which erasing-verify is passed a whole non-selection state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an erasing operation technique in a semiconductor memory, and more particularly to a technique effective when applied to prevention of excessive erasure of memory cells in a nonvolatile semiconductor memory.

  A nonvolatile semiconductor memory exemplified by a flash memory or the like is widely known to have a so-called multi-bank configuration in which a memory array is divided into a plurality of banks.

  In this non-volatile semiconductor memory having a multi-bank configuration, when all banks are simultaneously erased (multi-bank erase), the following erase operation is performed on all banks, and verification of each bank is passed. Until then, the erase operation is repeatedly executed for all banks.

  First, a high voltage (erase bias) that causes an erase operation is applied to a memory that is a target of the memory array for a predetermined time. Next, erase verify is performed. When the electrical state of the memory cell reaches a predetermined value corresponding to each of the erase levels, the erase ends.

  If the electrical state of the memory cell has not reached the predetermined value, the operation of applying the erase bias again for a predetermined time and the erase verify are repeated until the electrical state of the memory cell reaches a predetermined erase level.

  However, the present inventors have found that the multi-bank erase operation in the nonvolatile semiconductor memory as described above has the following problems.

  That is, there may be a difference in erase time due to a difference in electrical characteristics between banks. If an erase operation is completed earlier than other banks, that is, if there is a bank in which erase verify passes earlier than other banks, an unnecessary erase bias is applied to that bank, so-called over-erasure state There is a problem of becoming.

  If the over-erased state is entered, there is a problem that in the depletion (over-erased) check after the erase verify, it takes time to erase and write back from the over-erased state, and the erase time becomes long.

  In addition, the amount of shift of the threshold voltage Vth of the memory cell increases due to excessive erasure, depletion failure of the memory cell, disturb stress on the memory cell of the adjacent word line, and data corruption occurs. There is a risk that.

  It is an object of the present invention to provide a technique capable of preventing excessive erasure of memory cells and greatly reducing deterioration and disturbance of memory cells in multi-bank erasure.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device having a memory array section composed of two or more banks obtained by arbitrarily dividing a plurality of nonvolatile memory cells, and a control section for controlling read / write / erase operations. Thus, the bank selection control means for individually controlling the application of the erase voltage for each bank at the time of multi-bank erase in which all banks are erased is provided.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor integrated circuit device of the present invention, when the bank selection control means performs multi-bank erasing in which all banks are erased, the word line of the bank in which erasing has been completed among the plurality of banks is not selected. It is what.

  In the semiconductor integrated circuit device of the present invention, the bank selection control unit selects a word line of a block in which a plurality of memory cells in the bank are arbitrarily divided based on a control signal, and a row decoder A main decoder unit that decodes an address signal and outputs a control signal to the sub-decoder unit, and a multi-bank erasing operation in which all banks are erased, a plurality of banks are controlled based on the sub-decoder control signal. Among them, it consists of a bank selection control unit that outputs an erase end signal to the main decoder unit corresponding to the bank that has been erased, and the main decoder unit receives the erase end signal output from the bank selection control unit, The word line of the bank corresponding to the main decoder portion is brought into a non-selected state.

  Furthermore, in the semiconductor integrated circuit device of the present invention, the control unit generates a sub-decoder control signal input to the bank selection control unit, and the control unit performs the erase verification every time the nonvolatile memory cell of the bank passes. The subdecoder control signal is output in association with the bank that has passed the erase verify.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the erase time can be significantly shortened, the performance of the semiconductor integrated circuit device can be improved.

  (2) Further, it is possible to prevent depletion failure of the nonvolatile memory cell due to over-erasing and disturb stress to the memory cell, and to improve the reliability of the semiconductor integrated circuit device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram of a nonvolatile semiconductor memory according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of an X decoder unit in a memory circuit provided in the nonvolatile semiconductor memory of FIG. FIG. 4 is an explanatory diagram showing a configuration example of a sub-decoder and a memory array in the sub-decoder circuit provided in the X decoder section of FIG. 2, and FIG. FIG. 5 is an explanatory diagram showing the voltage relationship with the selection, FIG. 5 is an explanatory diagram showing the voltage relationship between the erase verify of the erase operation and the word line non-selection in the sub-decoder of FIG. 3, and FIG. 3 is a timing chart at the time of erasing operation in the conductive semiconductor memory.

  In this embodiment, a nonvolatile semiconductor memory (semiconductor integrated circuit device) 1 exemplified as a flash memory includes a control signal buffer 2, a controller (control unit) 3, a multiplexer 4, and a data input buffer as shown in FIG. 5, page address buffer 6, input data controller 7, column address counter 8, data output buffer 9, and memory circuits 10-13.

  The memory circuits 10 to 13 include an X decoder unit 14, a Y decoder 15, a Y gate 16, a data register 17, and a memory array (memory array unit) 18.

  The memory array 18 has a four-bank configuration in which nonvolatile memory cells, which are the smallest storage units, are regularly arranged in an array, and is divided into four banks Bank0 to Bank3. Each memory array 18 is divided into a plurality of blocks in order to increase the speed of the X decoder unit 14.

  Data is input to and output from the multiplexer 4 through each data input / output terminal I / O. The multiplexer 4 switches input or output. The data input buffer 5 temporarily stores input data via the multiplexer 4 and outputs it to the input data controller 7.

  The control signal buffer 2 has a chip enable / CE, a read enable / RE, a write enable / WE, a write protect / WP, a command latch enable CLE, an address latch enable ALE, and a power-on auto read enable PRE via each input terminal. Each control signal such as reset / RES is input, temporarily stored in the control signal buffer 2, and output to the controller 3.

  A control signal is output directly from the controller 3 through a control signal output terminal R / B (ready / busy). In these control signals, / CE, / RE, / WE, / WP, / RES, / B are inverted signals as indicated by a slash (/) in the figure.

  Control signals from the multiplexer 4 and the controller 3 are input to the page address buffer 6, and page address control signals are output to the X decoder sections 14 of the memory circuits 10 to 13, respectively.

  Data from the data input buffer 5 and a control signal from the controller 3 are input to the input data controller 7, and a control signal for the input data is output to the Y gates 15 of the memory circuits 10 to 13, respectively.

  A control signal is input from the controller 3 to the column address counter 8, and the column address is output to the Y decoder 15 of the memory circuits 10 to 13. Control signals are input to the controller 3 from the multiplexer 4 and the control signal buffer 2, and the control signals are transmitted from the multiplexer 4, the data input buffer 5, the page address buffer 6, the input data controller 7, the column address counter 8, and the control signal. The data is output to the signal buffer 2, the data output buffer 9, and the like.

  In the memory circuits 10 to 13, in the memory array 18, nonvolatile memory cells that store 1-bit data in one memory cell are arranged in an array at intersections of word lines and bit lines. Each memory cell in the memory array 18 is arbitrarily selected by the X decoder unit 14, the Y decoder 15, and the Y gate 16.

  Data reading, data writing, and data erasing are performed on the selected memory cell. These read, write, and erase data are temporarily stored in the data register 17, and the read data are temporarily stored in the data output buffer 9 and output.

  FIG. 2 is a block diagram illustrating a configuration of the X decoder unit 14 provided in each of the memory circuits 10 to 13.

  As shown in the figure, the X decoder section 14 includes a bank selection section (bank selection control means, bank selection control section) 19, a main decoder circuit (bank selection control means) 20, and a sub-decoder circuit (bank selection control means) 21. It is configured.

  Based on a sub-decoder control signal Csub and a bank selection signal SLb, which will be described later, the bank selection unit 19 deselects the memory array 18 that has passed the erase verification, and prevents over-erasure of the memory array 18.

  Based on the control signal from the controller 3 output from the page address buffer 6, the main decoder circuit 20 selects an arbitrary block among a plurality of blocks provided in each memory array 18 (banks Bank 0 to Bank 3). To do.

  The sub decoder circuit 21 connected to the subsequent stage of the main decoder circuit 20 selects a specific word line in the block selected by the main decoder circuit 20.

  The main decoder circuit 20 receives voltages V1 to V4, a verify pass signal (erase end signal) VP, a clock control signal CLK, and the like. The main decoder circuit 20 outputs a sub-decoder output control signal SGJ for controlling the sub-decoder SD (FIG. 3) provided in the sub-decoder circuit 21 based on the verify pass signal VP and the clock control signal CLK.

  The voltage V1 is used as a selection signal when a voltage V4 (for example, about 1.2 V) as a verify voltage is output from the subdecoder SD (FIG. 3) of the subdecoder circuit 21 and applied to the selected word line.

  The voltage V3 is used as a selection signal when outputting the voltage V3 (for example, about −18V) as an erase voltage from the sub-decoder SD (FIG. 3) of the sub-decoder circuit 21.

  The voltage V2 is a voltage applied to the non-selected word line and is, for example, the reference potential VSS. The clock control signal CLK is a signal that controls the output timing of the sub-decoder output control signal SGJ output from the main decoder circuit 20.

  The bank selection unit 19 includes inverters Iv1 to Iv3, and NOR circuits NOR1 and NOR2. One input part of the NOR circuit NOR1 is connected so that the sub-decoder control signal Csub output from the controller 3 is input.

  The sub-decoder control signal Csub is a signal for controlling ON (operation) / OFF (non-operation) of the sub-decoder circuit 21. For example, when the sub-decoder control signal Csub becomes Hi level, the sub-decoder circuit 21 is turned on. When the sub-decoder control signal Csub becomes Lo level, the sub-decoder circuit 21 is turned off.

  The bank selection signal SLb output from the controller 3 is connected to the input part of the inverter Iv1. The bank selection signal SLb is a selection signal for selecting an arbitrary bank among the banks Bank0 to Bank3.

  The other input part of the NOR circuit NOR1 is connected to the output part of the inverter Iv1. The input part of the inverter Iv2 is connected to the output part of the NOR circuit NOR1.

  A main decoder activation signal MDC output from the controller 3 is connected to an input portion of the inverter Iv3. The main decoder activation signal MDC is a signal that controls activation (ON) / inactivation (OFF) of the main decoder circuit 20.

  The output part of the inverter Iv2 is connected to one input part of the NOR circuit NOR2, and the output part of the inverter Iv3 is connected to the other input part of the NOR circuit NOR2. The signal output from the output part of the NOR circuit NOR2 becomes a verify pass signal VP and is connected to be input to the main decoder circuit 20.

  The verify pass signal VP is output to the bank that has passed the erase verify, for example, a Hi level signal is output.

  FIG. 3 is an explanatory diagram showing the correspondence between the sub-decoder SD provided in the sub-decoder circuit 21 and the memory array 18.

  As shown in the figure, the sub-decoder SD is composed of an inverter, and is connected to each word line provided in the memory array 18. A sub decoder output control signal SGJ output from the main decoder circuit 20 is connected to an input portion of the sub decoder SD, and the output portion of the sub decoder SD is provided in the memory array 18. The word line is connected.

  FIG. 4 is an explanatory diagram showing the voltage relationship between the erase bias of the erase operation in the sub-decoder SD and the word line non-selection, and FIG. 5 is the word line non-selection in the erase verify of the erase operation in the sub-decoder SD. It is explanatory drawing which shows the voltage relationship with time.

  As shown in FIG. 4, when the erase voltage (voltage V3) is applied to the word line, the voltage V2 is output as the sub-decoder output control signal SGJ. As a result, the erase voltage (voltage V3) is applied to the word line via the N-channel MOS transistor constituting the inverter.

  When the word line is not selected, the voltage V3 is output as the sub-decoder output control signal SGJ, and the voltage V2 is applied to the word line via the P channel MOS transistor constituting the inverter.

  As shown in FIG. 5, when a verify voltage (voltage V4) is applied to the word line, the voltage V1 is output as the sub-decoder output control signal SGJ. As a result, the verify voltage (voltage V4) is applied to the word line via the N-channel MOS transistor constituting the inverter.

  When the word line is not selected, the voltage V3 is output as the sub-decoder output control signal SGJ as in FIG. 4, and the voltage V2 is applied to the word line via the P-channel MOS transistor constituting the inverter.

  Next, the operation of the bank selection unit 19 in the present embodiment will be described.

  FIG. 6 is a timing chart at the time of erasing operation in the nonvolatile semiconductor memory 1. 6, from the top to the bottom, the main decoder activation signal MDC input to the bank selection unit 19, the bank selection signal SLb input to the bank selection unit 19, the clock control signal CLK input to the main decoder circuit 20, Signal timings of the sub decoder control signal Csub input to the bank selection unit 19, the sub decoder output control signal SGJ output from the main decoder circuit 20, and the word line voltage output from the sub decoder SD are shown.

  First, when multi-bank erasing is started, a high-level main decoder activation signal MDC, a selection signal SLb, and a Lo-level sub-decoder control signal Csub are input to the bank selection unit 19, respectively.

  Therefore, the Hi signal inverted to the inverter Iv2 is output to one input part of the NOR circuit NOR2, and the Lo signal inverted to the inverter Iv3 is output to the other input part of the NOR circuit NOR2. Therefore, a high-level verify pass signal VP is output to the main decoder circuit 20 from the NOR circuit NOR2.

  In response to this, the main decoder circuit 20 outputs a sub-decoder output control signal SGJ having a voltage V 2 synchronized with the clock control signal CLK to the sub-decoder circuit 21. The sub-decoder SD, to which the sub-decoder output control signal SGJ having the voltage V2 is input, applies the erase voltage (erase bias) having the voltage V3 to the selected word line.

  Subsequently, in order to perform erase verify, the main decoder circuit 20 outputs a sub-decoder output control signal SGJ having a voltage V1 to the sub-decoder SD in synchronization with the clock control signal CLK.

  When the sub-decoder output control signal SGJ having the voltage V1 is input, the sub-decoder SD applies the verify voltage having the voltage V4 to the selected word line, and whether the threshold voltage of the nonvolatile memory cell is lower than the determination level. Judgment of whether or not (erase verification) is performed.

  If the erase verify does not pass (determination is NG), the erase voltage application (erase bias) and erase verify are repeated again. These operations are performed until all the blocks in the memory array 18 pass the erase verify.

  Here, of the four memory arrays 18, for example, when the memory array 18 of the bank Bank0 passes the erase verify, the controller 3 outputs the sub decoder control signal Csub to be output to the bank selection unit 19 of the memory circuit 10 to the Lo level. To Hi level (indicated by a thick line in FIG. 6).

  Thereby, in the bank selection unit 19 of the memory circuit 10 (FIG. 1), the Lo signal is output from the NOR circuit NOR1, and the verify pass signal VP output from the NOR circuit NOR2 is the Hi signal. To the Lo signal and output.

  In response to this, the main decoder circuit 20 of the memory circuit 10 (FIG. 1) outputs a sub-decoder output control signal SGJ (shown by a bold line in FIG. 6) of the voltage V3 to the sub-decoder circuit 21. As a result, the word line connected to the sub-decoder SD of the sub-decoder circuit 21 becomes the voltage V2 (shown by a thick line in FIG. 6) which is the reference potential VSS, and the word lines in the bank Bank0 are all unselected.

  At this time, since the sub-decoder control signal Csub at the Lo level is input to the bank selection units 19 of the memory circuits 11 to 13 that have not passed the erase verify, the verify pass signal VP also does not transition. Remain at the Hi level.

  Therefore, the main decoder 20 of the memory circuits 11 to 13 outputs the sub-decoder output control signal SGJ of the voltage V2, respectively. The memory arrays 18 of the banks Bank1 to Bank3 that have not passed the erase verify are An erase voltage is applied (erase bias), and then erase verify is executed.

  Thereafter, for example, when the memory array 18 of the bank Bank1 passes the erase verify, the word line of the bank Bank1 is set to the all unselected state similarly to the case of the bank Bank0, and the bank Bank2 that does not pass the erase verify. Bank3 again executes application of erase voltage (erase bias) and erase verify.

  Then, when all the memory arrays 18 in the banks Bank0 to Bank3 pass the erase verify, the multi-bank erase is completed.

  As described above, in the erasing operation, all the word lines of the memory array 18 that have passed the erasure verification among the banks Bank0 to Bank3 can be brought into a non-selected state, so that excessive erasure of the nonvolatile memory cells can be prevented. it can.

  Thereby, according to the present embodiment, the number of erase write backs in the depletion check after the erase verify is reduced, so that the erase time can be greatly shortened.

  Further, it is possible to prevent depletion failure of the nonvolatile memory cell due to over-erasing and disturb stress to the memory cell.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a multi-bank erasing technique in a semiconductor memory having nonvolatile memory cells.

1 is a block diagram of a nonvolatile semiconductor memory according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of an X decoder unit in a memory circuit provided in the nonvolatile semiconductor memory of FIG. 1. FIG. 3 is an explanatory diagram illustrating a configuration example of a sub-decoder and a memory array in a sub-decoder circuit provided in the X decoder unit of FIG. 2. FIG. 4 is an explanatory diagram showing a voltage relationship between an erase bias and an unselected word line in an erase operation in the sub-decoder of FIG. 3. FIG. 4 is an explanatory diagram showing a voltage relationship between an erase verify and an unselected word line in the erase operation in the sub-decoder of FIG. 3. 2 is a timing chart at the time of erasing operation in the nonvolatile semiconductor memory of FIG. 1.

Explanation of symbols

1 Nonvolatile semiconductor memory (semiconductor integrated circuit device)
2 Control signal buffer 3 Controller (control unit)
4 multiplexer 5 data input buffer 6 page address buffer 7 input data controller 8 column address counter 9 data output buffer 10-13 memory circuit 14 X decoder unit 15 Y decoder 16 Y gate 17 data register 18 memory array (memory array unit)
19 Bank selection section (bank selection control means, bank selection control section)
20 Main decoder circuit (bank selection control means)
21 Sub-decoder circuit (bank selection control means)
SD subdecoder Iv1 to Iv3 inverter NOR1, NOR2 NOR circuit

Claims (4)

A semiconductor integrated circuit device having a memory array unit composed of two or more banks arbitrarily dividing a plurality of nonvolatile memory cells, and a control unit for controlling read / write / erase operations,
A semiconductor integrated circuit device comprising bank selection control means for individually controlling the application of an erase voltage for each bank during multi-bank erase in which all banks are erased. The semiconductor integrated circuit device according to claim 1.
The bank selection control means includes
A semiconductor integrated circuit device, wherein a word line of a bank in which erasure is completed among a plurality of the banks is deselected during multi-bank erasure in which all banks are erased. The semiconductor integrated circuit device according to claim 1 or 2,
The bank selection control means includes
A sub-decoder unit that selects a word line of a block in which a plurality of memory cells in the bank are arbitrarily divided based on a control signal;
A main decoder for decoding a row address signal and outputting a control signal to the sub-decoder;
In multi-bank erasure in which all the banks are erased, an erasure end signal is output to the main decoder corresponding to the bank that has been erased, out of the plurality of banks, based on a sub-decoder control signal And a bank selection control unit to
The main decoder unit, when receiving an erase end signal output from the bank selection control unit, deselects a word line of a bank corresponding to the main decoder unit. . The semiconductor integrated circuit device according to claim 3.
The sub-decoder control signal input to the bank selection control unit is
The control unit generates,
The controller is
Each time a nonvolatile memory cell in the bank passes erase verify, a sub-decoder control signal that associates the bank that has passed erase verify is output.

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