JP2007059982A - Miller capacitance circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a Miller capacitance circuit that has a wide input range, can increase the capacity in a small area, and is suitable for realizing integrated circuit. <P>SOLUTION: The Miller capacity circuit has a comparator 3, and a voltage recovery circuit 2. The comparator 3 compares the output voltage of an inverting amplifier for constituting a Miller capacitance 1 with the maximum and minimum values in the voltage range of the output voltage. The voltage recovery circuit 2 discharges the charge of capacity, provided in between the input and output of the Miller capacitance 1 for setting the output voltage of the inversion amplifier to a prescribed voltage value between the minimum and maximum values, when the minimum and maximum values are reached from the output of the comparator 3; sustains the input voltage of the inverting amplifier at this point of time; and supplies the sustained voltage to the input of the inverting amplifier for stopping a function as the Miller capacitance 1 of the circuit. After the setting of the output voltage is finished, the supply of the holding voltage to the input of the inverting amplifier is stopped for restarting the function as the Miller capacitance to repeat the series of operation. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a mirror capacitance circuit, and more particularly to a wide input range Miller capacitance circuit having a wide input voltage range.

  A capacitive element having a large capacity is essential for a low-frequency signal processing circuit such as a low-frequency filter, a PLL, or a bias circuit. The capacitance of this capacitive element is proportional to the area of the element. Therefore, the capacity mounted on the integrated circuit (IC) is limited to a very small value due to the limited area. As a method for solving this problem and realizing a large-capacity capacitive element that can be used in an IC, a mirror capacitive circuit realized by only a small-capacitance element and an amplifier attracts attention.

FIG. 11 shows a mirror capacitance circuit using an inverting amplifier OP having a gain of -A. In this circuit, the relationship between the input current i _in the input voltage v _in, when the output voltage is v _out, is given by the following equation (1).

また、反転増幅器の利得から出力電圧ｖ_outは下記式（２）で表される。

Further, the output voltage v _out is expressed by the following equation (2) from the gain of the inverting amplifier.

式（２）を式（１）に代入すると、

Substituting equation (2) into equation (1),

これにより、図１２に示すような接地された（１＋Ａ）Ｃの容量（ミラー容量）を得ることができたことになる。したがって、ミラー容量回路は、増幅器の利得に応じて大容量の容量素子を実現することができる。

As a result, a grounded (1 + A) C capacitance (mirror capacitance) as shown in FIG. 12 can be obtained. Therefore, the mirror capacitance circuit can realize a large-capacity capacitive element according to the gain of the amplifier.

Now, _{let us assume} that the allowable range of the output voltage of the amplifier is limited to the range of v _omax to _−vomin . If the output voltage exceeds this range, the amplifier will not operate normally and the gain will be zero. As a result, the capacitance viewed from the input terminal is reduced to C. Therefore, the input signal range of the mirror capacitance must be limited so that the output voltage is within a limited range. The output voltage range of the mirror capacitance is

であり、入力電圧は次式（５）で与えられる。

The input voltage is given by the following equation (5).

これらから、入力信号電圧の許される範囲は

From these, the allowable range of input signal voltage is

大きな容量のミラー容量を実現するためには、大きな電圧利得を有し、結果的に信号入力範囲が極端に制限されたミラー容量となってしまう。一方、受動容量は信号振幅に対してなんらの制限を有してはいない。これがミラー容量と受動容量との間の絶対的な相違である。

In order to realize a large-capacity mirror capacitor, the mirror capacitor has a large voltage gain and, as a result, the signal input range is extremely limited. On the other hand, passive capacitors do not have any restrictions on signal amplitude. This is the absolute difference between mirror capacitance and passive capacitance.

Techniques using a mirror capacitor in an IC circuit have been proposed in Patent Documents 1 and 2, Non-Patent Documents 1 and 2, and the like. However, these documents do not describe a technique for completely solving the problem of the signal input range.
Japanese Patent Laid-Open No. 11-251873 JP-A-8-288793 J.F. Paker, D. Ray: IEEE J. Solid-State Circuits. Vol33, pp.337-343, Mar, 1998 Z.Shu, KLLee and BHLeung: IEEE J. Solid-State Circuits.vol39, pp.452-462, Mar, 2004

  As described above, the mirror capacitance circuit can realize a large-capacity capacitive element. However, the Miller capacitance circuit has a problem in operation characteristics that the signal input range is limited as compared with the operation of the passive capacitance element. In other words, the function of the mirror capacitance circuit depends on the amplifier used to increase the capacitance. By the way, an amplifier generally has a finite signal operating range determined by its power supply voltage. In other words, the allowable signal input range is determined by a value obtained by dividing the maximum output range of the amplifier by the gain of the amplifier. Therefore, the maximum signal input range becomes an extremely small voltage range when the gain of the amplifier is set large so that a large mirror capacitance can be realized, and the Miller capacitance circuit can be used only in a small input signal range. Become.

  The present invention solves such a problem and realizes a mirror capacitance circuit suitable for integration because it has a relatively simple configuration, a wide input range, and a large area with a small area. Let it be an issue.

  In order to solve the above problems, the invention according to claim 1 of the present invention is equivalent to an inverting amplifier having a predetermined negative voltage gain and a capacitor provided between the input and output of the inverting amplifier. In a mirror capacitor circuit including a mirror capacitor that realizes a large capacity, the charge of the capacitor is reached when the output voltage of the inverting amplifier reaches the minimum value or the maximum value of the possible output voltage range determined from the power supply voltage. Output voltage setting means for setting the output voltage of the inverting amplifier to a predetermined voltage value between the minimum value and the maximum value, and the output voltage when the output voltage reaches the minimum value or the maximum value Input voltage holding means for holding the input voltage of the inverting amplifier; and holding input voltage supply means for supplying the holding voltage of the input voltage holding means to the input of the inverting amplifier and stopping the operation as the mirror capacitor. , The holding input voltage supply unit stops the supply of the holding voltage to the input of the inverting amplifier after the setting of the output voltage by the output voltage setting unit is completed, and restarts the operation as the mirror capacitor. These operations are repeated.

  In order to solve the above-mentioned problem, according to a second aspect of the present invention, in the Miller capacitance circuit according to the first aspect, the output voltage of the inverting amplifier is within the voltage range that the output voltage of the inverting amplifier can take. Voltage comparison means for comparing with the minimum value and the maximum value, and the voltage comparison means outputs an operation signal when the output voltage reaches the minimum value or the maximum value, and holds the input voltage. The means holds the input voltage when the output voltage reaches the minimum value or the maximum value according to the operation signal, and the holding input voltage supply means supplies the holding voltage of the input voltage holding means to the input The output voltage setting means starts setting the output voltage.

  In order to solve the above-mentioned problem, according to a third aspect of the present invention, in the Miller capacitance circuit according to the first or second aspect, the predetermined voltage value is a voltage that can be taken by an output voltage of the inverting amplifier. It is an arithmetic mean value of the minimum value and the maximum value of the range.

  In order to solve the above-mentioned problem, according to a fourth aspect of the present invention, in the Miller capacitance circuit according to the first aspect, there is provided a clock oscillating means for generating a clock having a predetermined frequency. The input voltage holding means holds the input voltage at the time of clock generation, the holding input voltage supply means starts supplying the holding voltage of the input voltage holding means to the input, and the output voltage setting means outputs the output voltage It is characterized by starting the setting of.

  The mirror capacitance circuit of the present invention can prevent the amplifier constituting the mirror capacitance from being saturated beyond the allowable range of the output voltage, and a mirror capacitance circuit corresponding to a wide signal input range can be obtained. By using this mirror capacitance circuit, a large capacitance corresponding to a wide signal input range can be made in a small area, so that a low frequency filter circuit or the like can be realized on an integrated circuit without using an external capacitance. An important effect such as being possible is obtained.

Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram of a first embodiment of a Miller capacitance circuit having a wide signal input range according to the present invention. The Miller capacitance circuit shown in FIG. 1 includes a mirror capacitance 1 as shown in FIG. 11, a voltage recovery circuit 2, and a comparator 3. i _in is an input signal current, v _in is an input voltage, and v _out is a mirror. An output voltage Vc of the capacity amplifier is a control signal.

In Miller capacitance circuit shown in FIG. 1, the comparator 3 monitors the output voltage v _out, if when the output voltage v _out is likely to exceed the output range of the formula (4), the voltage recovery circuit 2 Control signal Vc. In response to the control signal Vc, the voltage recovery circuit 2 discharges the electric charge of the mirror capacitor 1 and sets the output voltage v _out of the amplifier Op to a specific value within the range represented by the equation (4), usually v to reset to the arithmetic mean value of the _omax and _-v omin. While resetting the output voltage v _out of the amplifier Op, the voltage recovery circuit 2 keeps the input voltage of the mirror capacitor 1 constant and stops the operation of the circuit as the mirror capacitor.

FIG. 2 shows changes _in the input voltage v _in (FIG. 2 (a)) and the output voltage v _out (FIG. 2 (b)) when a constant direct current is applied to the input of the Miller capacitance circuit shown _in FIG. It is a waveform diagram.
As shown in FIG. 2, _assuming that the input current i _in is sequentially charged and the output voltage v _out reaches the minimum limit value _−vomin at time t = t1, the charge of the capacitor C is reduced during a short time Ts. As a result of the discharge, the output voltage v _out is reset to ( _{vomax− vomin} ) / 2, or 0 when _vomax = _vomin . At time t = t2, the mirror capacitor 1 starts charging the input current i _in again. Thus, the input voltage v _in can be the slide into increased towards its maximum input voltage determined by the structure of the input stage of the Miller capacitance 1. As can be seen from FIG. 2 (a), the input voltage v _in during charging i _in / increases linearly with the slope of {(1 + A) C} , the output voltage v _out is _{-Ai in / {(1 + A} ) C } Is decreasing linearly.

  As shown in FIG. 2, the operation of the mirror capacitance circuit of this embodiment is repeated at a period of T. During the reset time, Tr = t2-t1, the input voltage is held at a constant value, the circuit does not work as a mirror capacitor, and the input current is not charged. As a result, the mirror capacitor 1 can be used for the time of T-Tr. Accordingly, the reset time Tr causes an error in the voltage of the mirror capacitor 1. The shortest value of the reset time Tr is determined by the slew rate of the amplifier Op used in the circuit.

  FIG. 3 shows a specific circuit diagram of the present embodiment excluding the comparator circuit 3. In FIG. 3, OP1, OP2 and OP3 are operational amplifiers, C, C1 and C2 are capacitors, R1 and R2 are resistors having the same resistance value, and Sw1, Sw2 and Sw3 are switches.

  This circuit includes an inverting amplifier composed of a voltage follower composed of an operational amplifier OP1 and an operational amplifier OP2, a capacitor C connecting the input and output of the inverting amplifier, input voltage holding means composed of switches Sw1, Sw3, a capacitor C1, and an operational amplifier OP3. The holding input voltage supply means, the output of the operational amplifier OP3, the output voltage setting means comprising resistors R1, R2, the switch Sw2 and the capacitor C2, and the comparator circuit 3 (voltage comparison means) not shown in FIG.

In a state where the output voltage v _out of the operational amplifier OP2 is within the allowable range represented by the equation (4), the switch SW1 is closed, SW2 and SW3 are open, and the circuit functions as a mirror capacitor, during which the input current i _in is charged, the input voltage v _in increases linearly as shown in FIG. 2 (a).

Operational amplifiers OP1 and OP2 constitute a voltage follower with the amplification circuit, the gain for the input voltage v _in at both constitute an inverting amplifier of -R2 / R1. Therefore, the input capacitance Cin of this circuit is expressed by the following equation (7).

オペアンプＯＰ２の出力に接続されているコンパレータ３が、オペアンプＯＰ２の出力電圧ｖ_outが式（４）で表される範囲を越えたことを検出したとき、コンパレータ３の出力はスイッチＳＷ1を開き、スイッチＳＷ２およびＳＷ３を閉じる制御信号Ｖｃを送る。この状態で容量Ｃ１はその時点での入力電圧ｖ_inに等しい電圧ｖ_bufを保持する。また、容量Ｃ２の電圧ｖ_resetは次式（８）で与えられる。

When the comparator 3 connected to the output of the operational amplifier OP2 detects that the output voltage v _out of the operational amplifier OP2 exceeds the range represented by the equation (4), the output of the comparator 3 opens the switch SW1. A control signal Vc for closing SW2 and SW3 is sent. Capacity in this condition C1 holds a voltage equal v _buf to the input voltage v _in at that time. The voltage v _{reset of the} capacitor C2 is given by the following equation (8).

したがって、オペアンプＯＰ２の出力電圧ｖ_outは、次式（９）の通りになる。

Therefore, the output voltage v _out of the operational amplifier OP2 is expressed by the following equation (9).

ここで、式（８）を式（９）に代入すると、下記式（１０）が得られる。

Here, when Expression (8) is substituted into Expression (9), the following Expression (10) is obtained.

式（１０）は、出力電圧が、常に入力電圧に無関係に２つの供給電圧ｖ_DDと−ｖ_EEの中央値（相加平均値）にリセットされることを示している。

Equation (10) shows that the output voltage is always reset to the median value (arithmetic mean value) of the two supply voltages v _DD and −v _EE regardless of the input voltage.

During the reset period, the input voltage v _in is held as a voltage v _buf by the buffer capacity C1 of the operational amplifier OP3, the voltage is returned to the input via an operational amplifier OP3. The capacitor C is discharged through the operational amplifiers OP2 and OP3 so that the output voltage becomes the value of Expression (10). During this time, the circuit does not operate as a mirror capacitor, charging of the input current is stopped, and the input voltage is held at the voltage v _{buf as} shown in FIG.

After the reset, the switches SW1, SW2, and SW3 return to the closed, open, and open states, respectively, and the circuit operates as a mirror capacitor again.
During operation of the Miller capacitance, the voltage of the capacitor C2 holds the value represented by the formula (8), the voltage of the capacitor C1 follows the input voltage v _in.
By repeating this series of operations, it is possible to realize a Miller capacitance circuit that can use the input full range (rail-to-rail input range) without saturating the output of the inverting amplifier.

FIG. 4 is a block diagram of a second embodiment of the Miller capacitance circuit having a wide signal input range according to the present invention. In FIG. 4, the same parts as those in FIG. Reference numeral 4 denotes a clock oscillation circuit.
Unlike the first embodiment shown in FIG. 1, the second embodiment does not use a comparator that compares the output voltage v _{out of the} amplifier with the maximum value or the minimum value, regardless of the output voltage. The mirror capacitor 1 is discharged and the output voltage is reset using a clock CK having a constant frequency oscillated by the clock oscillation circuit 4.

FIG. 5 shows a clock CK (FIG. 5 (b)), an input voltage v _in (FIG. 5 (a)) and an output voltage v _out (FIG. 5 (c)) when a constant direct current is applied to the input of this circuit. It is a wave form diagram which shows the change of ().

In the circuit shown in FIG. 5, the clock oscillation circuit 4 sends a clock CK having a constant frequency to the voltage recovery circuit 2. In response to the fall of the clock CK, the voltage recovery circuit 2 keeps the input voltage of the mirror capacitor 1 constant, discharges the charge of the mirror capacitor 1, and sets the output voltage v _out of the amplifier Op to a specific value ( Here, it is reset to 0V).

In the second embodiment, while the clock CK is 0 V (low), the reset period of the output voltage v _out of the amplifier Op is set. During this reset period, the voltage recovery circuit 2 changes the input voltage of the mirror capacitor 1. while maintaining the input voltage at the falling edge of the clock CK, the output voltage v arithmetic mean value between the maximum value v _omax and the minimum value -v _Omin voltage range of the output voltage can take _out v _mid (0V in this case Reset to). Further, the period during which the clock CK is v _DD (high) is a charging period, and the mirror capacitor 1 is charged with the input current.

By the way, when a constant direct current is applied to the input as in the second embodiment, the change in the output voltage v _out during the charging period is regular as shown in FIG. It is possible to estimate the time until the output voltage v _out reaches the limit value v _omax or _−vomin after the start of the charging period, and the _fall of the clock CK and the output voltage v _out are limited as shown in FIG. The time when the value is reached can be easily matched.

Thus, for a general input current, the change in the clock CK and the output voltage _vout cannot be matched. However, as long as the clock CK falls earlier than the time when the output voltage v _out reaches the limit value, there is no saturation of the output voltage v _out of the inverting amplifier. Accordingly, if the frequency of the clock CK is set high, the function as a mirror capacitor is maintained, although there are problems such as an increase in the time that the circuit is disconnected from the input, an increase in error, and a longer convergence time.

FIG. 6 shows a specific circuit of the second embodiment.
In FIG. 6, parts having the same functions as those in FIG. Symbol IV is an inverter.
In the circuit shown in FIG. 6, the operational amplifiers OP1 and OP2 and the like are inverting amplifiers, the switches Sw1 and Sw3, the capacitor C1 and the operational amplifier OP3 are the input voltage holding means and the holding input voltage supply means, the output of the operational amplifier OP3 and the resistors R1 and R2 The switch Sw2 constitutes the output voltage setting means as in the case shown in FIG.

In the circuit shown in FIG. 6, the clock oscillation circuit 4 outputs a clock CK having a duty ratio of 50 as shown in FIG. In the present embodiment, a predetermined DC current is given as the input current i _in , and the falling time of the clock CK is set to coincide with the time when the output voltage v _out reaches the lower limit _−vomin of the output voltage. Has been.

The switches SW1, SW2, and SW3 are closed while the applied clock is v _DD (high), and are opened while 0 V (low). Therefore, when the clock CK is v _DD (high), the switch SW1 is closed, and SW2 and SW3 to which an inverted signal of the clock CK is given are open. Thus, the circuit operates as a Miller capacitance, the input current i _in is charged, the input voltage v _in increases linearly as shown in Figure 5 (a).

When the half cycle time of the clock CK elapses and the clock CK becomes 0 V (low), the switch SW1 is opened, and SW2 and SW3 to which an inverted signal of the clock CK is applied are closed. Then, the circuit stops operating as a mirror capacitor. Clock equals v _buf to the input voltage v _in at the time of the reversal is retained in the capacitor C1, together with the voltage is applied to the input voltage v _in, the output voltage v _out is reset to 0V.

Further, when the clock CK becomes v _DD (high), the switch SW1 is closed, the switches SW2 and SW3 are opened to return to the initial state, and the circuit resumes operation as a mirror capacitor.
By repeating this series of operations, it is possible to realize a Miller capacitance circuit that can use the input full range (rail-to-rail input range) without saturating the output of the inverting amplifier.

  Hereinafter, a loop filter used in a phase-locked loop (PLL) circuit will be described as an example of application of the mirror capacitance circuit of the present invention.

  Since the input of the loop filter of the PLL circuit is a current source of the charge pump, the input current is a constant value. Therefore, not only the first embodiment described above but also the mirror capacitance circuit of the second embodiment can be used without any significant trouble.

  A block diagram of the PLL circuit is shown in FIG. The 930 pf capacitor C4 in the circuit shown in FIG. 7 is replaced with the mirror capacitor circuit of the present invention. The mirror capacitance of 930 pf is realized by the first embodiment shown in FIGS. 1 and 3 using a 30 pf passive capacitor and an amplifier with a gain A = 30. In FIG. 7, 5 is a phase detector (PFD), 6 is a 1/2 frequency divider, 7 is a voltage controlled oscillator (VCO), 8 and 9 are current sources, C3 is a capacitor, and R3 is a resistor.

  FIG. 8 shows an example of an operational amplifier circuit used in the mirror capacitance circuit. In order to make it possible to use the input full range of the mirror capacitance (rail-to-rail input range), the input range of the operational amplifier needs to be usable as well, and the input stage is devised.

FIG. 9 shows a comparator circuit used in the mirror capacitance circuit.
V _max and v _min in the comparator circuit of Figure 9 is determined by the output range of the amplifier, corresponding respectively to v _omax and -v _Omin represented by formula (4).

In the comparator circuit of FIG. 9, the output voltage v _out of the amplifier is applied to the terminal v _out . The maximum value comparison unit 10 outputs high when the output voltage v _{out of the} amplifier is larger than v _max . Similarly, the minimum value comparison section 11 when the output voltage v _out of the amplifier is smaller than v _min, outputs a high. Therefore, the output Vnor of the NOR gate section 12 becomes high when v _min <v _out <v _max , and becomes low when v _out <v _min or v _max <v _out .

The monostable multivibrator unit 13 outputs low when the input Vnor is high. Also, high is output at the moment of falling from high to low, high is continuously output for a certain period of time, and then low is output. This fixed time is determined by the time required for setting the output voltage v _out of the inverting amplifier of the mirror capacitance, and is determined by the time constants of Cp and Mr.
As a result, the output voltage of the amplifier is reset to the median value v _mid of v _DD and −v _EE shown in Equation (10) by the voltage recovery circuit, and the output voltage of the amplifier is always set to a value between v _max and v _min. Retained.

  A high-precision circuit simulator (HSPICE, Nippon Synopsys, Inc.) was used to simulate the PLL circuit whose block diagram is shown in FIG. 7 using the 0.18 μm CMOS process parameters given in Table 1. The VCO is configured using a non-inductive ring oscillator having a conversion gain Kvco = 2.65 MHz / V. The power source is a single power source of + 2.5V.

The simulation results are shown in FIGS. 10 (a) to 10 (d).
10A shows the simulation result of the input control voltage of the VCO for the PLL circuit using the mirror capacitor circuit of the present invention, and FIG. 10B shows the input control of the VCO for the PLL circuit using the passive capacitor of 930 pF. The simulation result of a voltage is shown. FIG. 10C shows the output voltage of the Miller capacitance circuit.
From FIG. 10 (c), every time the output voltage v _out reaches its minimum value v _m (= 0.5V) or its maximum value v _max (= 2.0V), the center given by equation (10) is obtained. It can be seen that the value v _mid returns to 1.25V.

From the above simulation results, the difference in response between the two PLL circuits can be seen.
As shown in FIG. 10B, the PLL using the 930 pF passive capacitor reaches the steady state earlier than the PLL circuit shown in FIG. 10A using the mirror capacitor circuit. This is considered to be affected by the time required to reset the output voltage.

When the Miller capacitance circuit of the first embodiment is used, it takes T / (T-Tr) times as long as the passive capacitance is used to reach the same input voltage. Now, in performing the simulation, Tr = T / 2 was set. Therefore, the Miller capacitance circuit of the present invention requires twice as much time as the passive capacitance. This is the same as the response in that the equivalent capacitance C _eq of the Miller capacitance circuit is increased to the value given by the following equation (11). However, the capacity C _in is the initial capacity. Therefore, the response shown in FIG. 10A matches the response shown in FIG. 10D of the PLL circuit using the 1860 pF passive capacitance.

  As described above, according to the present invention, the input allowable range can be improved in the mirror capacitance circuit that shows a large capacitance equivalently by using a small capacitance element. Thus, a large capacity with a wide input range can be realized with a small area, and can be realized on an integrated circuit. Therefore, this Miller capacitance circuit can be used in a wide range of industrial fields where a bypass capacitor, a low frequency filter, and the like that require a large capacitance and a wide dynamic range are used.

1 is a block diagram of a mirror capacitance circuit according to a first embodiment of the present invention. FIG. 2 is a waveform diagram showing changes in input voltage and output voltage when a constant direct current is applied to the input of the mirror capacitance circuit according to the first embodiment of FIG. 1. FIG. 2 is a specific circuit diagram of the mirror capacitance circuit according to the first embodiment of FIG. 1. It is a block diagram of the mirror capacity circuit concerning a 2nd embodiment of the present invention. FIG. 5 is a waveform diagram illustrating changes in a clock, an input voltage, and an output voltage when a constant direct current is applied to the input of the Miller capacitance circuit according to the second embodiment of FIG. 4. FIG. 5 is a specific circuit diagram of a mirror capacitance circuit according to the second embodiment of FIG. 4. It is a block diagram of a PLL circuit using a mirror capacitance circuit of the present invention. It is a circuit diagram of the operational amplifier used for the mirror capacity circuit of the present invention. It is a circuit diagram of the comparator operational amplifier used for the Miller capacity circuit of the present invention. FIG. 7 is a simulation result of the PLL circuit whose block diagram is shown in FIG. It is a circuit diagram of a mirror capacity. This is an equivalent capacity of the mirror capacity shown in FIG.

Explanation of symbols

1 Miller capacitance 2 Voltage recovery circuit 3 Comparator 4 Clock oscillation circuit 5 Phase detector (PFD)
6 1/2 divider 7 Voltage controlled oscillator (VCO)
8,9 Current source C, C1-C4 Capacitance IV Inverter Op Amplifier, operational amplifier R1-R3 Resistor Sw1-Sw5 Switch

Claims (4)

In a mirror capacitance circuit including an inverting amplifier having a predetermined negative voltage gain and a capacitance provided between the input and output of the inverting amplifier and including a mirror capacitance equivalently realizing a large capacitance,
When the output voltage of the inverting amplifier reaches the minimum value or the maximum value of the possible output voltage range determined from the power supply voltage, the charge of the capacitor is discharged, and the output voltage of the inverting amplifier is set to the minimum value. And an output voltage setting means for setting to a predetermined voltage value between the maximum value and
Input voltage holding means for holding the input voltage of the inverting amplifier when the output voltage reaches a minimum value or a maximum value;
Holding input voltage holding means for supplying the holding voltage to the input of the inverting amplifier, and holding input voltage supply means for stopping the operation as the mirror capacitor;
The holding input voltage supply unit stops the supply of the holding voltage to the input of the inverting amplifier after the setting of the output voltage by the output voltage setting unit is completed, and restarts the operation as the mirror capacitor. The Miller capacitance circuit is characterized in that the above operation is repeated.   Voltage comparison means for comparing the output voltage of the inverting amplifier with the minimum value and the maximum value of a voltage range that can be taken by the output voltage of the inverting amplifier, and the voltage comparison means is configured such that the output voltage is the minimum value or the When it is detected that the maximum value has been reached, an operation signal is output, and the input voltage holding means holds the input voltage when the output voltage reaches the minimum value or the maximum value according to the operation signal, 2. The mirror capacitor according to claim 1, wherein the holding input voltage supply unit starts supplying a holding voltage of the input voltage holding unit to an input, and the output voltage setting unit starts setting an output voltage. circuit.   3. The mirror capacitance according to claim 1, wherein the predetermined voltage value is an arithmetic average value of the minimum value and the maximum value in a voltage range that the output voltage of the inverting amplifier can take. circuit.   Clock oscillation means for generating a clock having a predetermined frequency is provided. In response to the clock, the input voltage holding means holds the input voltage at the time of the clock, and the held input voltage supply means is the input voltage holding means. 2. The Miller capacitance circuit according to claim 1, wherein supply of a holding voltage to an input is started, and the output voltage setting unit starts setting an output voltage.

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