JP2007059895A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for manufacturing a highly reliable semiconductor device and a display device with high yield. <P>SOLUTION: An exposure mask provided with a diffraction grating pattern or an auxiliary pattern comprising a translucent film with a light intensity reducing function is used as an exposure mask. Since various light exposures can be more accurately controlled with such an exposure mask, a resist is processed into a more accurate shape. Therefore, when such a mask layer is used, a conductive film and an insulating film can be processed in the same step into different shapes in accordance with desired performances. As a result, thin film transistors with different characteristics, wires in different sizes and shapes, and the like can be manufactured without increasing the number of steps. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

    Thin film transistors used for semiconductor devices, display devices, and the like have different required characteristics depending on the purpose and function of the semiconductor device. In order to satisfy this requirement, it is important to control the characteristics of the thin film transistor, and a technique for manufacturing the thin film transistor so as to have a characteristic suitable for the purpose of use has been studied.

In a thin film transistor, an impurity region having different concentrations in a self-aligned manner is formed in a semiconductor layer by etching a gate electrode layer into a stacked shape having a different shape or a tapered shape by etching and adding an impurity element using the shape. Has been reported (see, for example, Patent Document 1).
JP 2002-203862 A

    However, when the shape of the gate electrode is controlled by the etching as described above, there is a problem that the wiring, the capacitor electrode, and the like formed in the same process also have a shape having a tapered shape similar to that of the gate electrode.

    An object of the present invention is to provide a technique capable of manufacturing a semiconductor device and a display device having high sensitivity and high reliability with high yield without complicating processes and devices.

  Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. A semiconductor device such as a multilayer wiring layer or an ID chip can be manufactured by using the present invention.

    In addition, a display device can be manufactured using the present invention. In a display device to which the present invention can be used, a layer containing an organic substance, an inorganic substance, or a mixture of an organic substance and an inorganic substance that emits light called electroluminescence (hereinafter also referred to as “EL”) is interposed between electrodes. There are a light emitting display device in which a light emitting element and a thin film transistor (hereinafter also referred to as TFT) are connected, and a liquid crystal display device in which a liquid crystal element having a liquid crystal material is used as a display element.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first semiconductor layer and a second semiconductor layer are formed, a gate insulating layer is formed over the first semiconductor layer and the second semiconductor layer, and the gate insulating layer is formed. A first conductive film is formed over the first conductive film, a second conductive film is formed over the first conductive film, and the first conductive film and the second conductive film are formed using an exposure mask that transmits light with a plurality of intensities. Over the conductive film, a first mask layer is formed over the first semiconductor layer and a second mask layer is formed over the second semiconductor layer, and the first mask layer and the second mask layer are used. The first conductive film and the second conductive film are etched, the first mask electrode layer and the second gate electrode layer are formed by the first mask layer, and the third gate electrode layer and the second gate film are formed by the second mask layer. 4 gate electrode layers and the first gate electrode layer and the second gate electrode layer as a mask on the first semiconductor layer. Using the third gate electrode layer and the fourth gate electrode layer as a mask, an impurity element imparting one conductivity type is added to the second semiconductor layer, and the first high-concentration impurity region and the first semiconductor layer are added to the first semiconductor layer. Forming a first low-concentration impurity region overlapping with the first gate electrode layer, and a second high-concentration impurity region overlapping with the third gate electrode layer in the second semiconductor layer. Then, a third mask layer is formed on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer, and the first mask layer is used as a mask by using the third mask layer and the second gate electrode layer as a mask. A region overlapping with the first low-concentration impurity region in the gate electrode layer is removed.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first semiconductor layer and a second semiconductor layer are formed, a gate insulating layer is formed over the first semiconductor layer and the second semiconductor layer, and the gate insulating layer is formed. A first conductive film is formed over the first conductive film, a second conductive film is formed over the first conductive film, and an exposure mask having a light intensity reduction function is used to form the first conductive film and the second conductive film. A first mask layer is formed on the first semiconductor layer and a second mask layer is formed on the second semiconductor layer, and the first mask layer and the second mask layer are used to form the first mask layer. The conductive film and the second conductive film are etched, the first mask electrode layer and the second gate electrode layer are formed by the first mask layer, and the third and fourth gate electrode layers are formed by the second mask layer. Forming a gate electrode layer, and using the first gate electrode layer and the second gate electrode layer as a mask, An impurity element imparting one conductivity type is added to the second semiconductor layer using the third gate electrode layer and the fourth gate electrode layer as a mask, and the first high-concentration impurity region and the first semiconductor layer are added to the first semiconductor layer. Forming a first low-concentration impurity region overlapping with the second gate electrode layer, and a second high-concentration impurity region overlapping with the third gate electrode layer in the second semiconductor layer. Forming a third mask layer on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer, and using the third mask layer and the second gate electrode layer as a mask, A region overlapping with the first low-concentration impurity region in the gate electrode layer is removed.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are formed, and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed. A gate insulating layer is formed thereon, a first conductive film is formed over the gate insulating layer, a second conductive film is formed over the first conductive film, and an exposure mask that transmits light with a plurality of intensities is formed. And a first mask layer is formed over the first semiconductor layer and a second mask layer is formed over the second semiconductor layer over the first conductive film and the second conductive film. A third mask layer is formed over the first semiconductor layer, the first conductive film and the second conductive film are etched using the first mask layer, the second mask layer, and the third mask layer; The first mask electrode layer and the second gate electrode layer are formed by one mask layer, and the third gate electrode layer and the fourth gate electrode layer are formed by a second mask layer. A fifth gate electrode layer and a sixth gate electrode layer are formed by the electrode layer and the third mask layer, and the third gate electrode layer is formed on the third semiconductor layer, the fifth gate electrode layer, and the sixth gate electrode layer. 4 mask layer is formed, and the third gate electrode layer and the fourth gate are formed on the first semiconductor layer using the fourth mask layer, the first gate electrode layer, and the second gate electrode layer as a mask. Using the electrode layer as a mask, an impurity element imparting n-type conductivity is added to the second semiconductor layer, and the first n-type high concentration impurity region and the first gate electrode layer overlap with the first semiconductor layer. Forming a first n-type low-concentration impurity region and a second n-type low-concentration impurity region overlapping the second n-type high-concentration impurity region and the third gate electrode layer in the second semiconductor layer; 1 semiconductor layer, second semiconductor layer, first gate electrode layer, second gate electrode layer, third gate layer A fifth mask layer is formed over the electrode layer and the fourth gate electrode layer, and the fifth mask layer, the fifth gate electrode layer, and the sixth gate electrode layer are used as a mask to form a p-type semiconductor layer. An impurity element imparting a type is added to form a p-type impurity region in the third semiconductor layer, and a sixth mask layer is formed on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer And the region overlapping with the first low-concentration impurity region in the first gate electrode layer is removed using the sixth mask layer and the second gate electrode layer as a mask.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are formed, and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed. A gate insulating layer is formed thereon, a first conductive film is formed over the gate insulating layer, a second conductive film is formed over the first conductive film, and an exposure mask having a light intensity reduction function is used. A first mask layer on the first semiconductor layer and a second mask layer on the second semiconductor layer are formed over the first conductive film and the second conductive film; A third mask layer is formed over the first layer; the first conductive film and the second conductive film are etched using the first mask layer, the second mask layer, and the third mask layer; The first gate electrode layer and the second gate electrode layer are formed by the mask layer, and the third gate electrode layer and the fourth gate are formed by the second mask layer. A fifth gate electrode layer and a sixth gate electrode layer are formed by the polar layer and the third mask layer, and the third gate electrode layer is formed on the third semiconductor layer, the fifth gate electrode layer, and the sixth gate electrode layer. 4 mask layer is formed, and the third gate electrode layer and the fourth gate are formed on the first semiconductor layer using the fourth mask layer, the first gate electrode layer, and the second gate electrode layer as a mask. Using the electrode layer as a mask, an impurity element imparting n-type conductivity is added to the second semiconductor layer, and the first n-type high concentration impurity region and the first gate electrode layer overlap with the first semiconductor layer. Forming a first n-type low-concentration impurity region and a second n-type low-concentration impurity region overlapping the second n-type high-concentration impurity region and the third gate electrode layer in the second semiconductor layer; 1 semiconductor layer, second semiconductor layer, first gate electrode layer, second gate electrode layer, third gate A fifth mask layer is formed on the polar layer and the fourth gate electrode layer, and the fifth semiconductor layer is formed on the third semiconductor layer using the fifth mask layer, the fifth gate electrode layer, and the sixth gate electrode layer as a mask. An impurity element imparting a type is added to form a p-type impurity region in the third semiconductor layer, and a sixth mask layer is formed on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer And the region overlapping with the first low-concentration impurity region in the first gate electrode layer is removed using the sixth mask layer and the second gate electrode layer as a mask.

    In the above structure, an exposure mask that transmits light at a plurality of intensities and an exposure mask that has a light intensity reducing function may use a semi-transmissive film (also referred to as a semi-permeable film) that reduces the intensity of light passing through, or exposure. A diffraction grating pattern having an opening and a non-opening with a width less than the resolution (resolution limit) of the apparatus may be used. Such an exposure mask is an exposure mask in which a resist (photosensitive material) as a mask layer forming material is exposed at a plurality of intensities as a result of light transmission and diffraction, and the resist (photosensitive material) has two or more levels of intensity. It is the exposure mask exposed by.

    By using the present invention, a highly reliable semiconductor device and display device can be manufactured through a simplified process. Therefore, a high-definition and high-performance semiconductor device and display device can be manufactured at a low cost and with a high yield.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
A method for manufacturing the thin film transistor in this embodiment will be described in detail with reference to FIGS. Note that in this embodiment, description is made by focusing on one thin film transistor, but it is needless to say that a plurality of thin film transistors can be simultaneously formed over the same substrate.

    An insulating layer 301 is formed as a base film over the substrate 300, and a semiconductor layer 302 is formed over the insulating layer 301. In this embodiment, a crystalline semiconductor layer is used as the semiconductor layer 302. A gate insulating layer 303 is formed over the semiconductor layer 302, and a first conductive film 304 and a second conductive film 305 are stacked. In this embodiment, the first conductive film 304 and the second conductive film 305 are stacked in order to form a gate electrode layer formed over the gate insulating layer with a stacked structure. The semiconductor layer 302 may be doped with a trace amount of an impurity element (boron or phosphorus) in order to control the threshold voltage of the thin film transistor.

    A mask layer 306 for etching the first conductive film 304 and the second conductive film 305 into a desired shape is formed (see FIG. 1A). The mask layer 306 is a resist pattern obtained by etching a resist into a desired shape using an exposure mask. The exposure mask used in the present embodiment is an exposure mask provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film. The diffraction grating pattern is a pattern in which at least one opening pattern such as a slit or a dot is provided. In the case of having a plurality of openings, the openings may be ordered and arranged regularly (periodically), or may be arranged randomly (non-periodically). By using a fine diffraction grating pattern having an opening with a width less than the resolution of the exposure apparatus and a non-opening portion, it is possible to modulate a substantial exposure amount, and a film after development of the exposed resist film The thickness can be adjusted, and the resist can be processed into a more precise shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in different shapes according to desired performance in the same process. Thus, different types of thin film transistors, wirings with different sizes, and the like can be manufactured without increasing the number of steps.

    Such an exposure mask is an exposure mask in which a resist (photosensitive material) as a mask layer forming material is exposed at a plurality of intensities as a result of light transmission and diffraction, and the resist (photosensitive material) has two or more levels of intensity. It is the exposure mask exposed by.

    The first conductive film 304 and the second conductive film 305 are each etched using the mask layer 306 to form a first gate electrode layer 307 and a second gate electrode layer 308 (see FIG. 1B). ). The shapes of the first gate electrode layer 307 and the second gate electrode layer 308 are formed reflecting the shape of the mask layer 306. In this embodiment, the width of the first gate electrode layer 307 is larger than the width of the second gate electrode layer 308, and the first gate electrode layer 307 includes the second gate electrode layer 307. It extends outward from the side edge of the layer 308. Further, part of the gate insulating layer is etched (also referred to as film reduction) in some cases due to the etching step in forming the gate electrode layer. Therefore, in this embodiment, the gate of the region that is not covered with the first gate electrode layer 307 or the second gate electrode layer 308 by the etching process of the first conductive film 304 and the second conductive film 305 is used. The insulating layer 303 is partially etched to reduce the film thickness. Etching can be dry etching, wet etching, or the like. Note that in the step of etching the first conductive film and the second conductive film, the mask layer 306 is also etched to become the mask layer 309.

    Further, in the same step as the step of forming the first gate electrode layer 307 and the second gate electrode layer 308, the wiring layer is formed by etching the first conductive film 304 and the second conductive film 305 into a desired shape. It can also be formed. In this case, the wiring layer can also be shaped freely according to the location and function by using a mask formed using an exposure mask provided with an auxiliary pattern having a light intensity reducing function such as the mask layer 306. A set wiring layer can be formed. In order to improve the covering property of an insulating layer or the like laminated on the upper part of the wiring layer, the wiring layer may be formed with a step (or taper shape) at the side end portion similarly to the gate electrode layer 307 and the gate electrode layer 308. In addition, the first wiring layer and the second wiring layer can be finely stacked with substantially the same width. When the stacking width is the same, the inter-wiring capacitance with other wiring layers stacked via the insulating layer decreases.

    An impurity element imparting one conductivity type is introduced into the semiconductor layer 302 to form an impurity region. In this embodiment, an n-channel thin film transistor is formed; therefore, an impurity element imparting n-type conductivity (phosphorus (P) in this embodiment) is used as the impurity element imparting one conductivity type. An impurity element 312 imparting n-type conductivity is added to the semiconductor layer 302 provided with the mask layer 309, the first gate electrode layer 307, and the second gate electrode layer 308, and the first n-type impurity region 314a, One n-type impurity region 314b, a second n-type impurity region 313a, and a second n-type impurity region 313b are formed (see FIG. 1C). In addition, the region of the semiconductor layer 302 to which the impurity element 312 is not added becomes a channel formation region 315.

    The impurity element 312 imparting n-type conductivity can be added to the semiconductor layer 302 by an ion doping method or an ion implantation method. An n-type impurity element 312 is added to a region of the semiconductor layer 302 that is not covered with the first gate electrode layer 307, the second gate electrode layer 308, and the mask layer 309. The impurity region 313a and the second n-type impurity region 313b are high-concentration n-type impurity regions. On the other hand, an n-type impurity element 312 is added to the semiconductor layer 302 through the region of the first gate electrode layer 307 that is not covered with the second gate electrode layer 308. The type impurity region 314a and the first n-type impurity region 314b are low-concentration n-type impurity regions.

    In this embodiment, the gate electrode layer has a stacked structure, and the impurity element imparting one n-type conductivity is formed using the shapes of the first gate electrode layer 307 and the second gate electrode layer 308 having different shapes. The first n-type impurity region 314a, the first n-type impurity region 314b, the second n-type impurity region 313a, and the second n-type impurity region 313b are formed in a self-aligned manner by adding 312. In this embodiment, the second n-type impurity region 313a, the second n-type impurity region 313b, the first n-type impurity region 314a, and the first n-type impurity region 314b are added to the impurity element once. The first gate electrode layer 307, the second gate electrode layer 308, and the gate insulating layer 303 are formed several times by controlling the thicknesses of the first gate electrode layer 307, the second gate electrode layer 308, and the gate insulating layer 303 and the impurity element addition conditions. The impurity region can be formed in the addition step.

    The second n-type impurity region 313a and the second n-type impurity region 313b are high-concentration n-type impurity regions and function as a source and a drain. On the other hand, the first n-type impurity region 314a and the first n-type impurity region 314b are low-concentration n-type impurity regions and become LDD (Lightly Doped Drain) regions. In this specification, a region where the impurity region overlaps with the gate electrode layer through the gate insulating layer is referred to as a Lov region, and a region where the impurity region does not overlap with the gate electrode layer through the gate insulating layer is referred to as a Loff region.

Further, in FIG. 1C, the impurity region is indicated by hatching and white background, but this does not indicate that the impurity element is not added to the white background portion, but the concentration of the impurity element in this region. This is because it is possible to intuitively understand that the distribution reflects the mask and doping conditions. This also applies to other drawings in this specification.

    The first gate electrode layer 307 is etched using the second gate electrode layer 308 as a mask to form a first gate electrode layer 316 (see FIG. 1D). The first gate electrode layer 316 reflects the shape of the second gate electrode layer 308, and removes the region of the first gate electrode layer 307 that extends outward from the second gate electrode layer 308. It becomes the shape made. Therefore, the side end portion of the first gate electrode layer 316 and the side end portion of the second gate electrode layer 308 substantially coincide with each other. In this embodiment mode, the mask layer 309 is removed in the etching step of the first gate electrode layer 307. Although the mask layer 309 may be removed after the first gate electrode layer 307 and the second gate electrode layer 308 are formed, the formation of the first gate electrode layer 316 is performed as in this embodiment mode. Sometimes the process can be simplified if performed in the same process.

    Since the first gate electrode layer 307 is processed like the first gate electrode layer 316, the first n-type impurity region 314 a and the first n-type impurity region 314 b are the first gate electrode layer 316 and the second gate electrode layer 316. The gate electrode layer 308 is formed as a Loff region that is not covered with the gate insulating layer 303 interposed therebetween. The first n-type impurity region 314a or the first n-type impurity region 314b formed as a Loff region on the drain side relaxes the electric field in the vicinity of the drain to prevent deterioration due to hot carrier injection and reduce off current. There is an effect to. As a result, a semiconductor device with high reliability and low power consumption can be manufactured.

    A wiring layer (also referred to as a source electrode layer or a drain electrode layer, not shown in FIG. 1, which is electrically connected to the second n-type impurity region 313a and the second n-type impurity region 313b functioning as a source region and a drain region. ) To form an n-channel thin film transistor.

    When impurity regions having different concentrations are usually formed in a semiconductor layer that is not self-aligned, the length and area of the desired impurity region may be reduced due to misalignment during processing of the mask layer used for forming the impurity region. It may not be obtained. If the impurity region as set cannot be formed, desired device characteristics of the thin film transistor cannot be obtained, and device characteristics vary among the plurality of thin film transistors. Therefore, the reliability of the obtained semiconductor device is also lowered.

    If the mask layer 309 is removed, the semiconductor layer 302 may not be protected by doping with an impurity element.

    By using the present invention, a highly reliable semiconductor device can be manufactured through a simplified process. Therefore, high-definition and high-quality semiconductor devices and display devices can be manufactured with low cost and high yield.

(Embodiment 2)
A method for manufacturing the thin film transistor in this embodiment will be described in detail with reference to FIGS. In this embodiment, an example in which two types of thin film transistors having different gate electrode layer structures are manufactured in the same step will be described.

    As in Embodiment 1, an insulating layer 321 serving as a base film is formed over the substrate 320, and a gate insulating layer 323 covering the semiconductor layer 322a, the semiconductor layer 322b, the semiconductor layer 322a, and the semiconductor layer 322b is formed (FIG. 2 (A).) The semiconductor layer 322a and the semiconductor layer 322b may be doped with a slight amount of an impurity element (boron (B) or phosphorus (P)) in order to control the threshold voltage of the thin film transistor.

    A first conductive film 324 and a second conductive film 325 are formed over the gate insulating layer 323, and a mask layer 326a and a mask layer 326b made of resist for processing into a desired shape are formed (FIG. 2 ( See B). Similarly to the mask layer 306 shown in Embodiment Mode 1, the mask layer 326a and the mask layer 326b are also formed using an exposure mask provided with an auxiliary pattern having a light intensity reducing function including a diffraction grating pattern or a semi-transmissive film. With such an exposure mask, various exposure controls can be performed more accurately, so that the resist can be processed into a more precise shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed into different shapes in accordance with desired performance in the same process. Accordingly, thin film transistors having different characteristics, wirings having different sizes and shapes, and the like can be manufactured without increasing the number of steps.

    The first conductive film 324 and the second conductive film 325 are etched using the mask layer 326a and the mask layer 326b, respectively, so that the first gate electrode layer 327a, the first gate electrode layer 327b, and the second gate electrode are etched. A layer 328a and a second gate electrode layer 328b are formed (see FIG. 2C). Note that in the step of etching the first conductive film 324 and the second conductive film 325, the mask layer 326a and the mask layer 326b are also etched to be the mask layer 329a and the mask layer 329b. The shapes of the first gate electrode layer 327a, the first gate electrode layer 327b, the second gate electrode layer 328a, and the second gate electrode layer 328b are formed reflecting the shapes of the mask layer 326a and the mask layer 326b. Is done. In this embodiment, the width of the first gate electrode layer 327a and the first gate electrode layer 327b is larger than the width of the second gate electrode layer 328a and the second gate electrode layer 328b. The first gate electrode layer 327a and the first gate electrode layer 327b extend outward from the side end portions of the second gate electrode layer 328a and the second gate electrode layer 328b, respectively. Yes. Etching can be dry etching, wet etching, or the like.

    A mask layer 397a is formed to cover the semiconductor layer 322a, the first gate electrode layer 327a, and the second gate electrode layer 328a, and an impurity element imparting one conductivity type is introduced into the semiconductor layer 322b to form an impurity region. In the step of FIG. 2D, in order to form an n-channel thin film transistor, an impurity element imparting n-type conductivity (phosphorus (P) in this embodiment) is used as an impurity element imparting one conductivity type.

    An impurity element 330 imparting n-type conductivity is added to the semiconductor layer 322b provided with the first gate electrode layer 327b, the second gate electrode layer 328b, and the mask layer 329b, whereby the first n-type impurity region 334a, the first The n-type impurity region 334b, the second n-type impurity region 333a, and the second n-type impurity region 333b are formed (see FIG. 2D). In addition, a region of the semiconductor layer 322b to which the impurity element 330 is not added becomes a channel formation region 335. Note that the semiconductor layer 322a is masked by the impurity element 330 by the mask layer 397a.

    An n-type impurity element 330 is added to a region of the semiconductor layer 322b which is not covered with the first gate electrode layer 327b, the second gate electrode layer 328b, and the mask layer 329b. The impurity region 333a and the second n-type impurity region 333b are high-concentration n-type impurity regions. On the other hand, an impurity element 330 imparting n-type conductivity is added to the semiconductor layer 322b through the region of the first gate electrode layer 327b that is not covered with the second gate electrode layer 328b. The type impurity region 334a and the first n-type impurity region 334b are low-concentration n-type impurity regions. In this embodiment, the gate electrode layer has a stacked structure, and an impurity element imparting a single n-type by using the shapes of the first gate electrode layer 327b and the second gate electrode layer 328b having different shapes By adding 330, a first n-type impurity region 334a, a first n-type impurity region 334b, a second n-type impurity region 333a, and a second n-type impurity region 333b are formed.

    The addition of the impurity element 330 imparting n-type conductivity may be performed a plurality of times, or each impurity region may be formed by a single addition step. By controlling the doping conditions when the impurity element is added, the first n-type impurity region 334a, the first n-type impurity region 334b, the second n-type impurity region 333a, the first n-type impurity region 333a, It is possible to select whether to form the second n-type impurity region 333b or to form the impurity region by performing a plurality of times.

    The second n-type impurity region 333a and the second n-type impurity region 333b are high-concentration n-type impurity regions and function as a source region and a drain region. On the other hand, the first n-type impurity region 334a and the first n-type impurity region 334b are low-concentration n-type impurity regions and serve as LDD regions. In this embodiment, the first n-type impurity region 334a and the first n-type impurity region 334b are Lov regions because they are covered with the first gate electrode layer 327b with the gate insulating layer 323 interposed therebetween. It is possible to alleviate the electric field in the vicinity of the drain region and suppress deterioration of on-current due to hot carriers.

    In this embodiment, after the mask layer 397a and the mask layer 329b are removed, a mask layer 397b that covers the first gate electrode layer 327b, the second gate electrode layer 328b, and the semiconductor layer 322b is formed. An impurity element imparting p-type conductivity (using boron (B) in this embodiment) is added to the semiconductor layer 322a as an impurity element imparting one conductivity type, so that an impurity region is formed. In this embodiment, an impurity element 332 that imparts p-type conductivity is added to the semiconductor layer 322a over which the first gate electrode layer 327a and the second gate electrode layer 328a are provided, so that the first p-type impurity region 387a, A first p-type impurity region 387b, a second p-type impurity region 386a, and a second p-type impurity region 386b are formed (see FIG. 2E). The region of the semiconductor layer 322a to which the impurity element 332 is not added becomes a channel formation region 388. Note that the semiconductor layer 322b is masked with the impurity element 332 by the mask layer 397b.

    a second p-type impurity region 386a formed by adding an impurity element 332 imparting p-type conductivity to a region of the semiconductor layer 322a not covered with the first gate electrode layer 327a and the second gate electrode layer 328a; The second p-type impurity region 386b is a high-concentration p-type impurity region. On the other hand, a first p formed by adding an impurity element 332 imparting p-type to the semiconductor layer 322a through the region of the first gate electrode layer 327a not covered with the second gate electrode layer 328a. The type impurity region 387a and the first p-type impurity region 387b are low-concentration p-type impurity regions.

    The addition of the impurity element 332 imparting p-type to the semiconductor layer 322a may be performed a plurality of times, or each impurity region may be formed by a single addition step. In this embodiment mode, the first p-type impurity region 387a and the first p-type impurity region 387b have p-type conductivity more than the second p-type impurity region 386a and the second p-type impurity region 386b. Although the case where the concentration of the impurity element to be applied is low is shown, depending on the impurity addition conditions, the impurity region under the first gate electrode layer 327a is not covered with the first gate electrode layer 327a. The impurity concentration may be higher than the region. Therefore, the first p-type impurity region 387a and the first p-type impurity region 387b have an impurity element imparting p-type more than the second p-type impurity region 386a and the second p-type impurity region 386b. In some cases, the concentration of is high or similar.

    Using the second gate electrode layer 328a as a mask, the first gate electrode layer 327a is etched to form the first gate electrode layer 336. The first gate electrode layer 336 reflects the shape of the second gate electrode layer 328a, and removes the region of the first gate electrode layer 327a that extends outward from the second gate electrode layer 328a. It becomes the shape made. Therefore, the side end portion of the first gate electrode layer 336 and the side end portion of the second gate electrode layer 328a substantially coincide with each other.

    The second p-type impurity region 386a and the second p-type impurity region 386b are high-concentration p-type impurity regions and function as a source and a drain. On the other hand, the first p-type impurity region 387a and the first p-type impurity region 387b are low-concentration p-type impurity regions and serve as LDD regions. Since the first gate electrode layer 327a is processed like the first gate electrode layer 336, the first p-type impurity region 387a and the first p-type impurity region 387b are the first gate electrode layer 336 and the second gate electrode layer 336b. The gate electrode layer 328a is formed as a Loff region that is not covered with the gate insulating layer 323 interposed therebetween. The first p-type impurity region 387a or the first p-type impurity region 387b formed as a Loff region on the drain side has an effect of reducing off-state current.

    After the insulating layer 331 is formed and an opening reaching each source region drain region is formed in the insulating layer 331, the second p-type impurity region 386a and the second p-type impurity region 386b functioning as the source region and the drain region are formed. A source or drain electrode layer 369a, a source or drain electrode layer 369b that are electrically connected to each other, a second n-type impurity region 333a that functions as a source region and a drain region, and a second n-type impurity region 333b, respectively A source or drain electrode layer 369c and a source or drain electrode layer 369d which are electrically connected to each other are formed (see FIG. 2F). Through the above steps, a p-channel thin film transistor 339a and an n-channel thin film transistor 339b are manufactured. A CMOS structure can be manufactured by electrically connecting the p-channel thin film transistor 339a and the n-channel thin film transistor 339b.

    By using the present invention, a highly reliable semiconductor device can be manufactured through a simplified process. Therefore, high-definition and high-quality semiconductor devices and display devices can be manufactured with low cost and high yield.

(Embodiment 3)
A method for manufacturing the thin film transistor in this embodiment will be described in detail with reference to FIGS. In this embodiment, an example in which two types of thin film transistors having different gate electrode layer structures are manufactured in the same step will be described.

    As in Embodiment 1, an insulating layer 341 serving as a base film is formed over the substrate 340, and a gate insulating layer 343 covering the semiconductor layer 342a, the semiconductor layer 342b, the semiconductor layer 342a, and the semiconductor layer 342b is formed. The semiconductor layer 342a and the semiconductor layer 342b may be doped with a slight amount of an impurity element (boron (B) or phosphorus (P)) in order to control the threshold voltage of the thin film transistor.

    A first conductive film 344 and a second conductive film 345 are formed over the gate insulating layer 343, and a mask layer 346a and a mask layer 346b made of resist for processing into a desired shape are formed (FIG. 3 ( See A). Similarly to the mask layer 306 shown in Embodiment Mode 1, the mask layer 346a and the mask layer 346b are also formed using an exposure mask provided with an auxiliary pattern having a light intensity reducing function made of a diffraction grating pattern or a semi-transmissive film. With such an exposure mask, various exposure controls can be performed more accurately, so that the resist can be processed into a more precise shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in different shapes according to desired performance in the same process. Accordingly, thin film transistors having different characteristics, wirings having different sizes and shapes, and the like can be manufactured without increasing the number of steps.

    The first conductive film 344 and the second conductive film 345 are processed by etching using the mask layer 346a and the mask layer 346b, respectively, so that the first gate electrode layer 347a, the first gate electrode layer 347b, and the second gate are formed. An electrode layer 348a and a second gate electrode layer 348b are formed (see FIG. 3B). Note that in the step of etching the first conductive film 344 and the second conductive film 345, the mask layer 346a and the mask layer 346b are also etched to be the mask layer 349a and the mask layer 349b. The shapes of the first gate electrode layer 347a, the first gate electrode layer 347b, the second gate electrode layer 348a, and the second gate electrode layer 348b are formed reflecting the shapes of the mask layer 346a and the mask layer 346b. Is done. In this embodiment, the widths of the first gate electrode layer 347a and the first gate electrode layer 347b are larger than the widths of the second gate electrode layer 348a and the second gate electrode layer 348b. The first gate electrode layer 347a and the first gate electrode layer 347b extend outside the side end portions of the second gate electrode layer 348a and the second gate electrode layer 348b, respectively. Yes. For the etching of the first conductive film 344 and the second conductive film 345, dry etching, wet etching, or the like can be used.

    An impurity element imparting one conductivity type is introduced into the semiconductor layers 342a and 342b, so that impurity regions are formed. In this embodiment, an n-type impurity element (phosphorus (P) in this embodiment) is used as an impurity element imparting one conductivity type in order to form an n-channel thin film transistor. Impurities imparting n-type conductivity to the semiconductor layer 342a and the semiconductor layer 342b in which the first gate electrode layer 347a, the first gate electrode layer 347b, the second gate electrode layer 348a, and the second gate electrode layer 348b are provided An element 352 is added, and the first n-type impurity region 354a, the first n-type impurity region 354b, the first n-type impurity region 354c, the first n-type impurity region 354d, and the second n-type impurity region 353a are added. A second n-type impurity region 353b, a second n-type impurity region 353c, and a second n-type impurity region 353d are formed (see FIG. 3C). The regions of the semiconductor layer 342a and the semiconductor layer 342b to which the impurity element 352 is not added serve as a channel formation region 355a or a channel formation region 355b.

    The impurity element 352 imparting n-type conductivity is added to the first gate electrode layer 347a, the first gate electrode layer 347b, the second gate electrode layer 348a, the second gate electrode layer 348b, the mask layer 349a, and the mask layer 349b. The second n-type impurity region 353a, the second n-type impurity region 353b, the second n-type impurity region 353c, the second n-type impurity region 353c, and the second n-type impurity region 353c formed in the regions of the semiconductor layer 342a and the semiconductor layer 342b which are not covered with The n-type impurity region 353d is a high-concentration n-type impurity region. On the other hand, the impurity element 352 imparting n-type conductivity is applied to the region of the first gate electrode layer 347a or the first gate electrode layer 347b which is not covered with the second gate electrode layer 348a or the second gate electrode layer 348b. A first n-type impurity region 354a, a first n-type impurity region 354b, a first n-type impurity region 354c, and a first n-type impurity region which are formed to be added to the semiconductor layer 342a or the semiconductor layer 342b. 354d is a low-concentration n-type impurity region. In this embodiment, the gate electrode layer has a stacked structure, and the first gate electrode layer 347a, the first gate electrode layer 347b, the second gate electrode layer 348a, and the second gate electrode layer 348b having different shapes are used. The first n-type impurity region 354a, the first n-type impurity region 354b, and the first n-type impurity are self-aligned by adding the impurity element 352 imparting n-type once. A region 354c, a first n-type impurity region 354d, a second n-type impurity region 353a, a second n-type impurity region 353b, a second n-type impurity region 353c, and a second n-type impurity region 353d are formed. .

    The addition of the impurity element 352 imparting n-type conductivity may be performed a plurality of times, or each impurity region may be formed by a single addition step. By controlling the doping conditions when the impurity element is added, the first n-type impurity region 354a, the first n-type impurity region 354b, the first n-type impurity region 354c, N-type impurity region 354d, second n-type impurity region 353a, second n-type impurity region 353b, second n-type impurity region 353c, and second n-type impurity region 353d are formed or performed a plurality of times. Thus, it is possible to select whether to form the impurity region.

    A mask layer 357 is formed to cover the first gate electrode layer 347b, the second gate electrode layer 348b, and the semiconductor layer 342b, and the first gate electrode layer 347a is etched using the second gate electrode layer 348a as a mask. A first gate electrode layer 356 is formed (see FIG. 3D). The first gate electrode layer 356 reflects the shape of the second gate electrode layer 348a, and removes the region of the first gate electrode layer 347a that extends outward from the second gate electrode layer 348a. It becomes the shape made. Accordingly, the side end portion of the first gate electrode layer 356 and the side end portion of the second gate electrode layer 348a substantially coincide with each other.

    In this embodiment, the mask layer 349a and the mask layer 349b are used as protective layers for the second gate electrode layer 348a and the second gate electrode layer 348b in the step of adding the impurity element 352, and after the step of adding the impurity element 352. Remove.

    The second n-type impurity region 353a, the second n-type impurity region 353b, the second n-type impurity region 353c, and the second n-type impurity region 353d are high-concentration n-type impurity regions, which are a source region and a drain region. Act as a region. On the other hand, the first n-type impurity region 354a, the first n-type impurity region 354b, the first n-type impurity region 354c, and the first n-type impurity region 354d are low-concentration n-type impurity regions. Become.

    Since the first gate electrode layer 347a is processed like the first gate electrode layer 356, the first n-type impurity region 354a and the first n-type impurity region 354b are the first gate electrode layer 356 and the second gate electrode layer 356b. A Loff region that is not covered with the gate insulating layer 343 is formed in the gate electrode layer 348a. The first n-type impurity region 354a or the first n-type impurity region 354b formed as a Loff region on the drain side relaxes the electric field in the vicinity of the drain region to prevent deterioration due to hot carrier injection and reduce off-current. There is an effect to. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

    On the other hand, since the first n-type impurity region 354c and the first n-type impurity region 354d are covered with the first gate electrode layer 347b via the gate insulating layer 343, they are Lov regions and in the vicinity of the drain region. It is possible to alleviate the electric field and suppress deterioration of on-current due to hot carriers.

    After the insulating layer 398 is formed and an opening reaching each source region drain region is formed in the insulating layer 398, the second n-type impurity region 353a and the second n-type impurity region 353b functioning as the source region and the drain region are formed. A source or drain electrode layer 358a, a source or drain electrode layer 358b that are electrically connected to each other, a second n-type impurity region 353c and a second n-type impurity region 353d that function as a source region and a drain region, respectively. A source electrode layer or a drain electrode layer 358c and a source electrode layer or a drain electrode layer 358d that are electrically connected to each other are formed. Through the above steps, an n-channel thin film transistor 359a and an n-channel thin film transistor 359b are manufactured (see FIG. 3E). A circuit having an NMOS structure can be manufactured by electrically connecting the n-channel thin film transistor 359a and the n-channel thin film transistor 359b.

    In addition, when an impurity element imparting n-type conductivity (for example, phosphorus (P)) is used as the impurity element imparting one conductivity type to be added as in this embodiment mode, an n-channel thin film transistor having an impurity region having n-type conductivity If an impurity element imparting p-type (for example, boron (B)) is used as the impurity element imparting one conductivity type to be added, a p-channel thin film transistor having an impurity region having p-type similarly Can be produced.

    By using the present invention, a highly reliable semiconductor device can be manufactured through a simplified process. Therefore, high-definition and high-quality semiconductor devices and display devices can be manufactured with low cost and high yield.

(Embodiment 4)
A method for manufacturing the thin film transistor in this embodiment will be described in detail with reference to FIGS. In this embodiment, an example in which two types of thin film transistors having different gate electrode layer structures and a capacitor are formed in the same step is described.

    As in Embodiment 1, an insulating layer 361 serving as a base film is formed over the substrate 360, and a gate covering the semiconductor layer 362a, the semiconductor layer 362b, the semiconductor layer 362c, the semiconductor layer 362a, the semiconductor layer 362b, and the semiconductor layer 362c. The insulating layer 363 is formed (see FIG. 4A). The semiconductor layer 362a and the semiconductor layer 362b may be doped with a slight amount of an impurity element (boron (B) or phosphorus (P)) in order to control the threshold voltage of the thin film transistor.

    A first conductive film 364 and a second conductive film 365 are formed over the gate insulating layer 363, and a mask layer 366a, a mask layer 366b, and a mask layer 366c made of resist for processing into a desired shape are formed ( (See FIG. 4A). The mask layer 366a, the mask layer 366b, and the mask layer 366c also use an exposure mask provided with an auxiliary pattern having a function of reducing the light intensity made of a diffraction grating pattern or a semi-transmissive film, similarly to the mask layer 306 described in Embodiment 1. Form.

  An exposure mask provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film used in this embodiment will be described with reference to FIG. Due to the light intensity reducing function made of a semipermeable membrane, the light intensity passing therethrough can be 10 to 70%.

  FIG. 19A is a cross-sectional view of an exposure step for forming the mask layer 366a, the mask layer 366b, and the mask layer 366c. 19A and 19B correspond to FIG. 4A, in which a semiconductor layer 362a, a semiconductor layer 362b, and a semiconductor layer 362c are provided over a substrate 360 and an insulating layer 361, and the semiconductor layer 362a and the semiconductor layer 362b are provided. A gate insulating layer 363, a first conductive film 364, a second conductive film 365, and a resist film 760 are formed so as to cover the semiconductor layer 362c. In this embodiment mode, a case where a positive resist from which an exposure region is removed is used is shown.

    An exposure mask is disposed on the resist film 760 via an optical system. The exposure mask is a light-shielding portion 752a, a light-shielding portion 752b, a light-shielding portion 752c made of a metal film such as Cr, and a semi-transmissive as an auxiliary pattern. A portion provided with the membrane 751a, the semipermeable membrane 751b, and the semipermeable membrane 751c is provided.

    19A, the exposure mask is provided with a translucent substrate 750 provided with a semi-permeable film 751a, a semi-permeable film 751b, and a semi-permeable film 751c made of MoSiN. A light shielding portion 752a, a light shielding portion 752b, and a light shielding portion 752c made of a metal film such as Cr are provided so as to be laminated on the film 751c. In addition, the semipermeable membrane 751a, the semipermeable membrane 751b, and the semipermeable membrane 751c can be formed using MoSi, MoSiO, MoSiON, CrSi, or the like.

  When the resist film is exposed using the exposure mask shown in FIG. 19A, an exposed region 762, a non-exposed region 761a, a non-exposed region 761b, and a non-exposed region 761c are formed. At the time of exposure, an exposure region 762 shown in FIG. 19A is formed by light passing around the light shielding portion and passing through the semipermeable membrane.

  When development is performed, the exposed region 762 is removed, and a mask layer 366a, a mask layer 366b, and a mask layer 366c which are resist patterns shown in FIG. 19B (corresponding to FIG. 4A) are obtained.

  As another example of an exposure mask, an exposure mask in which a diffraction grating pattern having a plurality of slits is provided between a light shielding part and a light shielding part may be used. The diffraction grating pattern is a pattern in which at least one opening pattern such as a slit or a dot is provided. In the case of having a plurality of openings, the openings may be ordered and arranged regularly (periodically), or may be arranged randomly (non-periodically). By using a diffraction grating pattern having a non-opening portion (line) and an opening (space) with a fine width less than the resolution of the exposure apparatus, it is possible to modulate the substantial exposure amount, and the exposed resist The film thickness after development of the film can be adjusted. The resolution is the minimum line width that can be formed by the exposure apparatus. In the projection exposure apparatus, the resolution R is represented by R = Kλ / NA. K is a constant, λ is the wavelength of light used for exposure, and NA is the numerical aperture of the projection lens. Therefore, when the resist film is processed by the method shown in FIG. 19, selective fine processing can be performed without increasing the number of steps, and various resist patterns (mask layers) can be obtained. In this embodiment mode, a capacitor and two types of thin film transistors having different gate electrode layer shapes are formed using such a resist pattern (mask layer).

In addition, a diffraction grating having a light intensity reduction function of an exposure mask has an aperture of a / b × 0.8 or less and a non-opening portion of a / b × or less, where a is the resolution and b is the reduction ratio of the exposure apparatus. preferable. Specifically, when a = 1.5 μm and b = 1, opening / non-opening = 0.5 μm / 0.5 μm, 0.75 μm / 0.75 μm, 1 μm / 0.5 μm, 0.75 μm / 0 .5 μm.

    In FIG. 4A, a first conductive film 364 and a second conductive film 365 are formed, and a mask layer 366a, a mask layer 366b, and a mask layer 366c having different shapes formed as shown in FIG. 19 are formed. Has been.

    The mask layer 366a has a shape close to a rectangular parallelepiped with no steps and unevenness, the mask layer 366b has a shape having a gentle step at the side end, and the mask layer 366c has a shape having a protrusion near the side end. It is.

    The first gate electrode layer 367a, the second gate electrode layer 368a, the first gate electrode layer 367b, and the second gate electrode are processed by etching using the mask layer 366a, the mask layer 366b, and the mask layer 366c. A layer 368b, a first conductive layer 765, and a second conductive layer 766 are formed (see FIG. 4B). The side end portion of the first gate electrode layer 367a and the side end portion of the second gate electrode layer 368a substantially coincide with each other and are continuous. On the other hand, the first gate electrode layer 367b and the second gate electrode layer 368b have a shape in which the width of the first gate electrode layer 367b is larger than the width of the second gate electrode layer 368b. One gate electrode layer 367b extends outward from the side end of the second gate electrode layer 368b. The first conductive layer 765 and the second conductive layer 766 that reflect the shape of the mask layer 366c are similar to the first gate electrode layer 367b and the second gate electrode layer 367b in the first conductive layer 765. The width of the second conductive layer 766 is larger than that of the second conductive layer 766, and the second conductive layer 766 has a shape extending outward from one side end portion of the second conductive layer 766. One upper end portion of the first conductive layer 765 and one lower end portion of the second conductive layer substantially coincide with each other. As shown in FIG. 4B, the second conductive layer 766 is narrower than the first gate electrode layer 368b and has a narrow area covering the first conductive layer 765; The exposed area is widened.

    A semiconductor layer in which a mask layer 396a is formed to cover the semiconductor layer 362a, the first gate electrode layer 367a, and the second gate electrode layer 368a, and the first gate electrode layer 367b and the second gate electrode layer 368b are provided. An impurity element imparting one conductivity type is introduced into the semiconductor layer 362c provided with the 362b and the first conductive layer 765 and the second conductive layer 766, and an impurity region is formed. 4C, an impurity element imparting n-type conductivity (phosphorus (P) in this embodiment) is used as the impurity element imparting one conductivity type.

    The semiconductor layer 362b in which the first gate electrode layer 367b and the second gate electrode layer 368b are provided, and the semiconductor layer 362c in which the first conductive layer 765 and the second conductive layer 766 are provided are n-type. An impurity element 380 to be added is added, and the first n-type impurity region 374a, the first n-type impurity region 374b, the second n-type impurity region 373a, the second n-type impurity region 373b, and the first n-type impurity region are added. An impurity region 394 and a second n-type impurity region 393 are formed (see FIG. 4C). The region of the semiconductor layer 362b to which the impurity element 380 is not added becomes a channel formation region 377. Similarly, a region to which the impurity element 380 of the semiconductor layer 362c is not added becomes a non-added region 319. Note that the semiconductor layer 362a is masked with the impurity element 380 by the mask layer 396a.

    The semiconductor layer 362b and the semiconductor layer which are not covered with the first gate electrode layer 367b, the second gate electrode layer 368b, the first conductive layer 765, and the second conductive layer 766 are doped with the impurity element 380 imparting n-type conductivity. The second n-type impurity region 373a, the second n-type impurity region 373b, and the second n-type impurity region 393 formed by adding to the region 362c are high-concentration n-type impurity regions. On the other hand, the impurity element 380 imparting n-type conductivity is allowed to pass through the region of the first gate electrode layer 367b or the first conductive layer 765 that is not covered with the second gate electrode layer 368b or the second conductive layer 766. The first n-type impurity region 374a, the first n-type impurity region 374b, and the first n-type impurity region 394 which are formed by adding to the semiconductor layer 362b or the semiconductor layer 362c are a low-concentration n-type impurity region and Become. In this embodiment, the gate electrode layer has a stacked structure, and the first gate electrode layer 367b, the second gate electrode layer 368b, the first conductive layer 765, and the second conductive layer 766 having different shapes have different shapes. The first n-type impurity region 374a, the first n-type impurity region 374b, the first n-type impurity region 394, and the first n-type impurity region 374b are self-aligned by adding the impurity element 380 imparting n-type once. A second n-type impurity region 373a, a second n-type impurity region 373b, and a second n-type impurity region 393 are formed.

    The addition of the impurity element 380 imparting n-type conductivity may be performed a plurality of times, or each impurity region may be formed by a single addition step. By controlling the doping conditions when the impurity element is added, the first n-type impurity region 374a, the first n-type impurity region 374b, the first n-type impurity region 394, and the second n It is possible to select whether the n-type impurity region 373a, the second n-type impurity region 373b, and the second n-type impurity region 393 are formed, or the impurity region is formed by performing a plurality of times.

    The second n-type impurity region 373a and the second n-type impurity region 373b are high-concentration n-type impurity regions and function as a source region and a drain region. On the other hand, the first n-type impurity region 374a and the first n-type impurity region 374b are low-concentration n-type impurity regions and serve as LDD regions.

    A mask layer 396b is formed to cover the semiconductor layers 362b and 362c, and an impurity element 382 imparting p-type conductivity (boron (B) in this embodiment) is added to the semiconductor layer 362a as an impurity element imparting one conductivity type. Then, a p-type impurity region 381a and a p-type impurity region 381b are formed (see FIG. 4D). In this embodiment mode, the p-type impurity region 381a and the p-type impurity region 381b are formed in a self-aligning manner using the first gate electrode layer 367a and the second gate electrode layer 368a as masks. Therefore, the semiconductor layer 362a The low concentration impurity regions are not intentionally formed, and all impurity regions can be made high concentration impurity regions.

    A mask layer 396d covering the semiconductor layer 362a, the first gate electrode layer 367a, and the second gate electrode layer 368a, and a mask layer 396c covering the semiconductor layer 362c, the first conductive layer 765, and the second conductive layer 766 are formed. The first gate electrode layer 367b is etched using the second gate electrode layer 368b as a mask to form a first gate electrode layer 376 (see FIG. 4E). In the first gate electrode layer 376, the shape of the second gate electrode layer 368b is reflected, and the region of the first gate electrode layer 367b extending outside the second gate electrode layer 368b is removed. It becomes the shape made. Therefore, the side end portion of the first gate electrode layer 376 and the side end portion of the second gate electrode layer 368b substantially coincide with each other.

    Since the first gate electrode layer 367b is processed like the first gate electrode layer 376, the first n-type impurity region 374a and the first n-type impurity region 374b are the first gate electrode layer 376 and the second gate electrode layer 376b. A Loff region that is not covered with the gate insulating layer 363 is formed in the gate electrode layer 368b. The first n-type impurity region 374a or the first n-type impurity region 374b formed as a Loff region on the drain side relaxes the electric field in the vicinity of the drain region to prevent deterioration due to hot carrier injection and reduce off-current. There is an effect to. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

    After the insulating layer 399 is formed and an opening reaching each source region drain region and an opening reaching the second n-type impurity region 393 are formed in the insulating layer 399, a p-type impurity region 381a functioning as a source region and a drain region is formed. And a source or drain electrode layer 383a electrically connected to the p-type impurity region 381b, a source or drain electrode layer 383b, a second n-type impurity region 373a that functions as a source region and a drain region, and a second A source or drain electrode layer 383c, a source or drain electrode layer 383d, and a wiring layer 767 that are electrically connected to the n-type impurity region 373b and the second n-type impurity region 393 are formed. Through the above steps, a p-channel thin film transistor 385 having no LDD region (a so-called single drain type), an n-channel thin film transistor 375 having an LDD region in a Loff region, and a capacitor 395 are manufactured (see FIG. 4F). ).

    When an impurity element imparting n-type conductivity (for example, phosphorus (P)) is used as the impurity element imparting one conductivity type to be added, an n-channel thin film transistor having an n-type impurity region can be manufactured and added. When an impurity element imparting p-type conductivity (eg, boron (B)) is used as the impurity element imparting one conductivity type, a p-channel thin film transistor having a p-type impurity region can be manufactured.

    Further, by controlling the doping conditions for adding an impurity element imparting one conductivity type, the low concentration impurity region is not formed, and all impurity regions can be made high concentration impurity regions.

    Through the same process, thin film transistors with different gate electrode layer and impurity region structures can be manufactured. In addition, when a wiring or the like is manufactured in the same process, a wiring aiming at lower resistance or a wiring having a small size can be manufactured. Therefore, miniaturization is possible, and it is possible to achieve the precision, performance, and weight reduction of the semiconductor device.

    Since the capacitor 395 can form the first conductive layer 765 in a wider shape than the second conductive layer 766, the region of the first n-type impurity region 394 can be formed wider. Since the capacitance formed between the impurity region and the gate electrode is larger than the capacitance formed between the non-doped region 319 to which no impurity element is added and the gate electrode, the first n under the first conductive layer 765 is used. When the type impurity region 394 is formed wide, a large capacity can be obtained.

    As described above, when this embodiment mode is used, a conductive film or an insulating film can be processed in different shapes according to desired performance in the same process. Accordingly, thin film transistors having different characteristics, wirings having different sizes and shapes, and the like can be manufactured without increasing the number of steps. This embodiment mode can be freely combined with each of Embodiment Modes 1 to 3.

    By using the present invention, a highly reliable semiconductor device can be manufactured through a simplified process. Therefore, high-definition and high-quality semiconductor devices and display devices can be manufactured with low cost and high yield.

(Embodiment 5)
A method for manufacturing the display device in this embodiment will be described in detail with reference to FIGS.

    FIG. 20A is a top view illustrating a structure of a display panel according to the present invention. A pixel portion 2701 in which pixels 2702 are arranged in a matrix over a substrate 2700 having an insulating surface, a scan line side input terminal 2703, a signal A line side input terminal 2704 is formed. The number of pixels may be provided in accordance with various standards. For XGA, 1024 × 768 × 3 (RGB), for UXGA, 1600 × 1200 × 3 (RGB), and for full spec high vision, 1920 × 1080. X3 (RGB) may be used.

    The pixels 2702 are arranged in a matrix by a scan line extending from the scan line side input terminal 2703 and a signal line extending from the signal line side input terminal 2704 intersecting. Each of the pixels 2702 includes a switching element and a pixel electrode layer connected to the switching element. A typical example of a switching element is a TFT, and the gate electrode layer side of the TFT is connected to a scanning line, and the source or drain side is connected to a signal line, so that each pixel can be controlled independently by a signal input from the outside. It is said.

    FIG. 20A shows the structure of a display panel in which signals input to the scan lines and signal lines are controlled by an external driver circuit. As shown in FIG. 21A, COG (Chip on The driver IC 2751 may be mounted on the substrate 2700 by a glass method. As another mounting mode, a TAB (Tape Automated Bonding) method as shown in FIG. 21B may be used. The driver IC may be formed on a single crystal semiconductor substrate or may be a circuit in which a TFT is formed on a glass substrate. In FIG. 21, the driver IC 2751 is connected to an FPC (Flexible Printed Circuit) 2750.

    In the case where a TFT provided for a pixel is formed using a crystalline semiconductor, a scan line driver circuit 3702 can be formed over a substrate 3700 as shown in FIG. In FIG. 20B, the pixel portion 3701 is controlled by an external driver circuit as in FIG. 20A connected to the signal line side input terminal 3704. In the case where a TFT provided for a pixel is formed using a polycrystalline (microcrystalline) semiconductor, a single crystal semiconductor, or the like with high mobility, FIG. 20C illustrates a pixel portion 4701, a scan line driver circuit 4702, and a signal line driver circuit. 4704 can be integrally formed on the substrate 4700.

    Silicon nitride oxide by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a CVD method (Chemical Vapor Deposition) such as a plasma CVD method as a base film over the substrate 100 having an insulating surface. A base film 101a is formed to a thickness of 10 to 200 nm (preferably 50 to 150 nm) using a film (SiNO), and a base film 101b is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm) using a silicon oxynitride film (SiON). . Alternatively, heat-resistant polymers such as acrylic acid, methacrylic acid and derivatives thereof, polyimide, aromatic polyamide, polybenzimidazole, or siloxane resin may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, epoxy resins, phenol resins, novolac resins, acrylic resins, melamine resins, and urethane resins may be used. Alternatively, an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, or polyimide, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. Moreover, an oxazole resin can also be used, for example, photosensitive polybenzoxazole can be used. Photosensitive polybenzoxazole has a low dielectric constant (dielectric constant 2.9 at room temperature of 1 MHz) and high heat resistance (differential thermal analysis (TGA) thermal decomposition temperature 550 ° C. at a temperature increase of 5 ° C./min). The material has a low water absorption rate (0.3% at room temperature for 24 hours). The water absorption is a percentage of the ratio between the weight increase and the original weight obtained by immersing a sample of a certain size in distilled water for a certain time.

    Further, a droplet discharge method, a printing method (a method for forming a pattern such as screen printing or offset printing), a coating method such as a spin coating method, a dipping method, or the like can also be used. In this embodiment, the base film 101a and the base film 101b are formed by a plasma CVD method. As the substrate 100, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. In addition, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. As the plastic substrate, a substrate made of PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PES (polyethersulfone) can be used, and as the flexible substrate, a synthetic resin such as acrylic can be used. Since the display device manufactured in this embodiment has a structure in which light from the light-emitting element is extracted through the substrate 100, the substrate 100 needs to have a light-transmitting property.

As the base film, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a laminated structure of two layers or three layers may be used. Note that in this specification, silicon oxynitride is a substance in which the oxygen composition ratio is higher than the nitrogen composition ratio, and can also be referred to as silicon oxide containing nitrogen. Similarly, silicon nitride oxide is a substance in which the composition ratio of nitrogen is higher than the composition ratio of oxygen, and can be said to be silicon nitride containing oxygen. In this embodiment, a silicon nitride oxide film is formed to a thickness of 50 nm on a substrate using SiH ₄ , NH ₃ , N ₂ O, N _2, and H ₂ as reactive gases, and oxidized using SiH ₄ and N ₂ O as reactive gases. A silicon nitride film is formed with a thickness of 100 nm. The thickness of the silicon nitride oxide film may be 140 nm, and the thickness of the stacked silicon oxynitride film may be 100 nm.

    Next, a semiconductor film is formed over the base film. The semiconductor film may be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). In this embodiment mode, it is preferable to use a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by laser crystallization.

    As a material for forming the semiconductor film, an amorphous semiconductor (hereinafter also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane, the non-material is used. A polycrystalline semiconductor obtained by crystallizing a crystalline semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter, also referred to as “SAS”) semiconductor can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. SAS is formed by glow discharge decomposition (plasma CVD) of a gas containing silicon. As a gas containing silicon, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used. Further, F ₂ and GeF ₄ may be mixed. The gas containing silicon may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. Alternatively, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor film.

    A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Needless to say, as described above, a semi-amorphous semiconductor or a semiconductor containing a crystal phase in part of a semiconductor film can also be used.

In the case where a crystalline semiconductor film is used as the semiconductor film, a method for manufacturing the crystalline semiconductor film can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the concentration of hydrogen contained in the amorphous semiconductor film is set to 1 × by heating at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous semiconductor film with laser light. Release to 10 ²⁰ atoms / cm ³ or less. This is because when an amorphous semiconductor film containing a large amount of hydrogen is irradiated with laser light, the amorphous semiconductor film is destroyed. As the heat treatment for crystallization, a heating furnace, laser irradiation, irradiation with light emitted from a lamp (also referred to as lamp annealing), or the like can be used. There are RTA methods such as a GRTA (Gas Rapid Thermal Anneal) method and an LRTA (Lamp Rapid Thermal Anneal) method as heating methods. GRTA is a method for performing heat treatment using a high-temperature gas, and LRTA is a method for performing heat treatment with lamp light.

Further, in the crystallization step of crystallizing the amorphous semiconductor layer to form the crystalline semiconductor layer, an element for promoting crystallization (also referred to as a catalyst element or a metal element) is added to the amorphous semiconductor layer, and heat treatment ( Crystallization may be carried out at 550 ° C. to 750 ° C. for 3 minutes to 24 hours. The metal elements that promote the crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir ), Platinum (Pt), copper (Cu) and gold (Au) can be used.

    The method of introducing the metal element into the amorphous semiconductor film is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor film or inside the amorphous semiconductor film. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor film and to spread the aqueous solution over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

In order to remove or reduce the element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. A semiconductor layer containing a rare gas element is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer containing a rare gas element, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. After that, the semiconductor layer containing a rare gas element that has become a gettering sink is removed.

    Laser irradiation can be performed by relatively scanning the laser and the semiconductor film. In laser irradiation, it is also possible to form a marker in order to accurately superimpose beams and to control the laser irradiation start position and laser irradiation end position. The marker may be formed on the substrate simultaneously with the amorphous semiconductor film.

When laser irradiation is used, a continuous wave laser beam (CW (continuous-wave) laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. This laser can be emitted by CW or pulsed oscillation. When injected at a CW, the power density 0.01 to 100 MW / cm ² of about laser (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, a great improvement in output can be expected.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction. Further, the laser may be irradiated with an incident angle θ (0 <θ <90 degrees) with respect to the semiconductor film. This is because laser interference can be prevented.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

  When a semiconductor film is annealed using a linear beam with uniform intensity obtained in this manner and a semiconductor device is manufactured using this semiconductor film, the characteristics of the semiconductor device are good and uniform.

    Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Accordingly, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in threshold values caused by variations in interface state density can be suppressed.

    Crystallization of the amorphous semiconductor film may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

In this embodiment, an amorphous semiconductor film is formed over the base film 101b, and the crystalline semiconductor film is formed by crystallizing the amorphous semiconductor film. As the amorphous semiconductor film, amorphous silicon formed using a reactive gas of SiH ₄ and H ₂ is used. In this embodiment mode, the base film 101a, the base film 101b, and the amorphous semiconductor film are formed continuously while switching the reaction gas at the same temperature of 330 ° C. without breaking the vacuum in the same chamber.

    After removing the oxide film formed on the amorphous semiconductor film, the oxide film is reduced to 1 nm by UV light irradiation in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydrogen radicals or hydrogen peroxide, and the like. Form ~ 5 nm. In this embodiment mode, Ni is used as an element for promoting crystallization. An aqueous solution containing 10 ppm of Ni acetate is applied by spin coating.

    In this embodiment mode, heat treatment is performed at 750 ° C. for 3 minutes by an RTA method, and then an oxide film formed over the semiconductor film is removed and laser light is irradiated. The amorphous semiconductor film is crystallized by the above crystallization treatment and formed as a crystalline semiconductor film.

When crystallization using a metal element is performed, a gettering step is performed in order to reduce or remove the metal element. In this embodiment mode, a metal element is captured using an amorphous semiconductor film as a gettering sink. First, an oxide film is formed over the crystalline semiconductor film by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydroxyl radicals or hydrogen peroxide, and the like. The oxide film is preferably thickened by heat treatment. Next, an amorphous semiconductor film is formed to a thickness of 50 nm by a plasma CVD method (conditions 350 W and 35 Pa in this embodiment mode, a deposition gas SiH ₄ (flow rate 5 sccm), Ar (flow rate 1000 sccm)).

Thereafter, heat treatment is performed at 744 ° C. for 3 minutes by the RTA method to reduce or remove the metal element. The heat treatment may be performed in a nitrogen atmosphere. Then, the amorphous semiconductor film serving as the gettering sink and the oxide film formed over the amorphous semiconductor film are removed by hydrofluoric acid or the like, and the crystalline semiconductor film 102 in which the metal element is reduced or removed is removed. Can be obtained (see FIG. 5A). In this embodiment mode, the amorphous semiconductor film serving as a gettering sink is removed by using TMAH (Tetramethyl ammonium hydroxide).

    In order to control the threshold voltage of the thin film transistor, the semiconductor film thus obtained may be doped with a trace amount of impurity element (boron or phosphorus). This doping of the impurity element may be performed on the amorphous semiconductor film before the crystallization step. When the impurity element is doped in the state of the amorphous semiconductor film, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

    Next, the crystalline semiconductor film 102 is processed into a desired shape. In this embodiment, after the oxide film formed over the crystalline semiconductor film 102 is removed, a new oxide film is formed. Then, the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, and the semiconductor layer 106 are formed by etching into a desired shape.

As the etching process, either plasma etching (dry etching) or wet etching may be employed, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based gas such as CF ₄ or NF ₃ or a chlorine-based gas such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, or the like may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. . A droplet discharge (ejection) method (also called an ink-jet method depending on the method) is a method in which a droplet of a composition prepared for a specific purpose is selectively ejected (ejection) to form a predetermined pattern (such as a conductive layer or a conductive layer). An insulating layer or the like can be formed. At this time, a process for controlling wettability and adhesion may be performed on the formation region. In addition, a method by which a pattern can be transferred or drawn, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) can be used.

In this embodiment mode, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used as a mask to be used. Also, a composition comprising an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, translucent polyimide, a compound material obtained by polymerization of a siloxane polymer, a water-soluble homopolymer and a water-soluble copolymer Materials and the like can also be used. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. When using the droplet discharge method, regardless of which material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

    The oxide film over the semiconductor layer is removed, and a gate insulating layer 107 is formed to cover the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, and the semiconductor layer 106. The gate insulating layer is formed of an insulating film containing silicon with a thickness of 10 to 150 nm using a plasma CVD method or a sputtering method. The gate insulating layer may be formed of a known material such as silicon nitride, silicon oxide, silicon oxynitride, or silicon oxide or nitride material typified by silicon nitride oxide, and may be a stacked layer or a single layer. Further, the insulating layer may be a three-layer stack of a silicon nitride film, a silicon oxide film, and a silicon nitride film, or a stack of a single layer and two layers of a silicon oxynitride film. Further, a thin silicon oxide film with a thickness of 1 to 100 nm, preferably 1 to 10 nm, more preferably 2 to 5 nm may be formed between the semiconductor layer and the gate insulating layer. As a method for forming a thin silicon oxide film, a thin silicon oxide film can be formed by oxidizing the surface of the semiconductor region using a GRTA method, an LRTA method, or the like to form a thermal oxide film. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film. In this embodiment, a silicon oxynitride film is formed to a thickness of 110 nm as the gate insulating layer 107.

    Next, a first conductive film 108 with a thickness of 20 to 100 nm and a second conductive film 109 with a thickness of 100 to 400 nm which are used as a gate electrode layer are stacked over the gate insulating layer 107 (see FIG. 5). See B). The first conductive film 108 and the second conductive film 109 can be formed by a known method such as a sputtering method, an evaporation method, or a CVD method. The first conductive film 108 and the second conductive film 109 are tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium. An element selected from (Nd) or an alloy material or compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film 108 and the second conductive film 109. The structure is not limited to a two-layer structure. For example, a tungsten film with a thickness of 50 nm is used as the first conductive film, an aluminum-silicon alloy (Al-Si) film with a thickness of 500 nm is used as the second conductive film, The conductive film may have a three-layer structure in which titanium nitride films with a thickness of 30 nm are sequentially stacked. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. In this embodiment, tantalum nitride (TaN) is formed to a thickness of 30 nm as the first conductive film 108 and tungsten (W) is formed to a thickness of 370 nm as the second conductive film 109.

    On the gate insulating layer 107, the first conductive film 108, and the second conductive film 109, a mask layer 157a, a mask layer 157b, a mask layer 157c, a mask layer 157d, and a mask layer made of resist for processing into a desired shape are formed. 157e is formed (see FIG. 5C). The mask layer 157a, the mask layer 157b, the mask layer 157c, the mask layer 157d, and the mask layer 157e are also similar to the mask layer 306, the mask layer 366a, the mask layer 366b, and the mask layer 366c described in Embodiments 1 and 4. And an exposure mask provided with an auxiliary pattern having a light intensity reducing function made of a diffraction grating pattern or a semi-transmissive film. With such an exposure mask, various exposure controls can be performed more accurately, so that the resist can be processed into a more precise shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in different shapes according to desired performance in the same process. Accordingly, thin film transistors having different characteristics, wirings having different sizes and shapes, and the like can be manufactured without increasing the number of steps.

    Next, the first conductive film 108 and the second conductive film 109 are etched into desired shapes using the mask layer 157a, the mask layer 157b, the mask layer 157c, the mask layer 157d, and the mask layer 157e, and the first conductive film 108 is etched. The gate electrode layer 121, the first gate electrode layer 122, the first gate electrode layer 124, the first gate electrode layer 125, the first gate electrode layer 126, the second gate electrode layer 131, the second A gate electrode layer 132, a second gate electrode layer 134, a second gate electrode layer 135, and a second gate electrode layer 136 are formed (see FIG. 5D). Through the etching process of the first conductive film 108 and the second conductive film 109, the mask layer 157a, the mask layer 157b, the mask layer 157c, the mask layer 157d, and the mask layer 157e are etched, respectively, and the mask layer 110a and the mask layer 110b are etched. , Mask layer 110c, mask layer 110d, and mask layer 110e, and then removed.

As an etching method, a plasma etching method, a reactive ion etching method, or an ICP (Inductively Coupled Plasma) etching method can be used. In this embodiment mode, an ICP etching method is used. Etching conditions (such as the amount of power applied to the coil-type electrode layer, the amount of power applied to the electrode layer on the substrate side, the electrode temperature on the substrate side) may be adjusted as appropriate. The etching process may be performed a plurality of times, or may be performed in a single process as in this embodiment. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , CF ₅ , SF ₆ or NF _3, or O _{2 is used.} Can be used as appropriate. In this embodiment mode, the gate electrode layer is formed by dry etching, but may be wet etching.

    In this embodiment mode, the first gate electrode layer and the second gate electrode layer have a tapered shape. However, the present invention is not limited thereto, and only one gate electrode layer may have a tapered shape, and the other may have a vertical side surface. As in this embodiment, the taper angle may be different between the stacked gate electrode layers, or may be the same. By having a tapered shape, the coverage of a film stacked thereon is improved and defects are reduced, so that reliability is improved. Fine and precise control of the shape of the gate electrode layer such as a tapered shape can be performed by the resist mask formed by the exposure process shown in FIG. 19 as in this embodiment.

    The gate insulating layer 107 may be slightly etched by an etching process when forming the gate electrode layer, and the film thickness may be reduced (so-called film reduction).

Next, a mask layer 153 a that covers the first gate electrode layer 121, the second gate electrode layer 131, and the semiconductor layer 103, a mask layer that covers the first gate electrode layer 126, the second gate electrode layer 136, and the semiconductor layer 106 153b is formed. Next, an impurity element imparting one conductivity type is introduced into the semiconductor layer 104 and the semiconductor layer 105 to form impurity regions. 6A, an n-type impurity element (phosphorus (P) in this embodiment) is used as an impurity element imparting one conductivity type in order to form an n-channel thin film transistor.

    The semiconductor layer 104 provided with the first gate electrode layer 122 and the second gate electrode layer 132, the first gate electrode layer 124, the first gate electrode layer 125, the second gate electrode layer 134, and the first gate electrode layer 134 An impurity element 152 imparting n-type conductivity is added to the semiconductor layer 105 provided with the second gate electrode layer 135, and the first n-type impurity region 145a, the first n-type impurity region 145b, and the first n-type impurity region are added. Impurity region 148a, first n-type impurity region 148b, first n-type impurity region 148c, first n-type impurity region 148d, second n-type impurity region 144a, second n-type impurity region 144b, Two n-type impurity regions 147a, a second n-type impurity region 147b, and a second n-type impurity region 147c are formed (see FIG. 6A). The regions of the semiconductor layer 104 and the semiconductor layer 105 to which the impurity element 152 is not added are a channel formation region 146, a channel formation region 149a, and a channel formation region 149b. Note that the semiconductor layer 103 and the semiconductor layer 106 are masked with the impurity element 152 by the mask layer 153a or the mask layer 153b.

    The impurity element 152 imparting n-type conductivity is formed using the first gate electrode layer 122, the first gate electrode layer 124, the first gate electrode layer 125, the second gate electrode layer 132, the second gate electrode layer 134, And the second n-type impurity region 144a, the second n-type impurity region 144b, and the second n-type impurity region 144a that are formed by adding to the region of the semiconductor layer 104 or the semiconductor layer 105 that is not covered with the second gate electrode layer 135. The type impurity region 147a, the second n-type impurity region 147b, and the second n-type impurity region 147c are high-concentration n-type impurity regions. On the other hand, the impurity element 152 imparting n-type conductivity is added to the second gate electrode layer 132, the second gate electrode layer 134, or the first gate electrode layer 122 that is not covered with the second gate electrode layer 135, The first n-type impurity region 145a and the first n-type impurity region which are formed by adding to the semiconductor layer 104 or the semiconductor layer 105 through the region of the first gate electrode layer 124 or the first gate electrode layer 125 145b, the first n-type impurity region 148a, the first n-type impurity region 148b, the first n-type impurity region 148c, and the first n-type impurity region 148d are low-concentration n-type impurity regions.

    In this embodiment, the gate electrode layer has a stacked structure, and the first gate electrode layer 122, the first gate electrode layer 124, the first gate electrode layer 125, the second gate electrode layer 132, which have different shapes, Using the shapes of the second gate electrode layer 134 and the second gate electrode layer 135, the first n-type impurity region 145a is self-aligned by adding the impurity element 152 imparting n-type once. , First n-type impurity region 145b, first n-type impurity region 148a, first n-type impurity region 148b, first n-type impurity region 148c, first n-type impurity region 148d, and second n A type impurity region 144a, a second n-type impurity region 144b, a second n-type impurity region 147a, a second n-type impurity region 147b, and a second n-type impurity region 147c are formed.

    The addition of the impurity element 152 imparting n-type conductivity may be performed once, or each impurity region may be formed by a plurality of addition steps. By controlling the doping conditions at the time of adding the impurity element, it is possible to select whether the impurity regions having different concentrations are formed in one addition step or the impurity regions are formed by performing a plurality of times. .

    The second n-type impurity region 144a, the second n-type impurity region 144b, the second n-type impurity region 147a, the second n-type impurity region 147b, and the second n-type impurity region 147c are high-concentration n It is a type impurity region and functions as a source region and a drain region. On the other hand, the first n-type impurity region 145a, the first n-type impurity region 145b, the first n-type impurity region 148a, the first n-type impurity region 148b, the first n-type impurity region 148c, The n-type impurity region 148d is a low-concentration n-type impurity region and becomes an LDD region. In this embodiment, the first n-type impurity region 145a and the first n-type impurity region 145b are Lov regions because they are covered with the first gate electrode layer 122 with the gate insulating layer 107 interposed therebetween. It is possible to alleviate the electric field in the vicinity of the drain region and suppress deterioration of on-current due to hot carriers. As a result, a thin film transistor capable of high-speed operation can be formed.

In this embodiment mode, a region where the impurity region overlaps with the gate electrode layer through the gate insulating layer is referred to as a Lov region, and a region where the impurity region does not overlap with the gate electrode layer through the gate insulating layer is referred to as a Loff region. In FIG. 6, hatching and white background are shown in the impurity region, but this does not indicate that the impurity element is not added to the white background part, but the concentration distribution of the impurity element in this region is mask or doping. This is because it is possible to intuitively understand that the conditions are reflected. This also applies to other drawings in this specification.

In this embodiment, PH ₃ (doping gas is PH ₃ diluted with hydrogen (H ₂ ) and the ratio of PH _{3 in} the gas is 5%) is used as a doping gas containing an impurity element, and the gas flow rate is 80 sccm. Doping is performed with a beam current of 540 μA / cm, an acceleration voltage of 70 kV, and a dose of 5.0 × 10 ¹⁵ ions / cm ² to be added. First n-type impurity region 145a, first n-type impurity region 145b, first n-type impurity region 148a, first n-type impurity region 148b, first n-type impurity region 148c, first n-type impurity region An impurity element imparting n-type conductivity is included in the impurity region 148d at a concentration of about 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . The n-type is imparted to the second n-type impurity region 144a, the second n-type impurity region 144b, the second n-type impurity region 147a, the second n-type impurity region 147b, and the second n-type impurity region 147c. Impurity elements are included at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ .

    Next, the mask layer 153a and the mask layer 153b are removed, and the mask layer 155a, the first gate electrode layer 124, the first gate electrode layer 122, the second gate electrode layer 132, and the semiconductor layer 103 are covered. A mask layer 155 b that covers the gate electrode layer 125, the second gate electrode layer 134, the second gate electrode layer 135, and the semiconductor layer 105 is formed. An impurity element imparting p-type conductivity (using boron (B) in this embodiment) is added to the semiconductor layer 103 and the semiconductor layer 106 as an impurity element imparting one conductivity type, so that an impurity region is formed. In this embodiment mode, the semiconductor layer 103 provided with the first gate electrode layer 121 and the second gate electrode layer 131, and the first gate electrode layer 126 and the second gate electrode layer 136 are provided. An impurity element 154 imparting p-type conductivity is added to the semiconductor layer 106, and the first p-type impurity region 161a, the first p-type impurity region 161b, the first p-type impurity region 164a, and the first p-type impurity are added. A region 164b, a second p-type impurity region 160a, a second p-type impurity region 160b, a second p-type impurity region 163a, and a second p-type impurity region 163b are formed (see FIG. 6B). ). Further, the region of the semiconductor layer 103 or the semiconductor layer 106 to which the impurity element 154 is not added becomes a channel formation region 162 or a channel formation region 165. Note that the semiconductor layer 104 and the semiconductor layer 105 are masked with the impurity element 154 by the mask layer 155a or the mask layer 155b.

    The impurity element 154 imparting p-type conductivity is added to the first gate electrode layer 121, the first gate electrode layer 126, the second gate electrode layer 131, the semiconductor layer 103 not covered with the second gate electrode layer 136, and The second p-type impurity region 160a, the second p-type impurity region 160b, the second p-type impurity region 163a, and the second p-type impurity region 163b formed by adding to the region of the semiconductor layer 106 are high A concentration p-type impurity region is formed. On the other hand, the impurity element 154 imparting p-type conductivity is applied to the regions of the first gate electrode layer 121 and the first gate electrode layer 126 which are not covered with the second gate electrode layer 131 and the second gate electrode layer 136. A first p-type impurity region 161a, a first p-type impurity region 161b, a first p-type impurity region 164a, and a first p-type impurity region which are formed to be added to the semiconductor layer 103 and the semiconductor layer 106. 164b becomes a low concentration p-type impurity region.

    The addition of the impurity element 154 imparting p-type to the semiconductor layer 103 and the semiconductor layer 106 may be performed a plurality of times, or each impurity region may be formed by a single addition step. In this embodiment, the first p-type impurity region 161a, the first p-type impurity region 161b, the first p-type impurity region 164a, and the first p-type impurity region 164b are the second p-type impurity regions. Although the impurity region 160a, the second p-type impurity region 160b, the second p-type impurity region 163a, and the second p-type impurity region 163b have a lower concentration of the impurity element imparting p-type, Depending on the impurity addition conditions, the impurity regions under the first gate electrode layer 121 and the first gate electrode layer 126 are covered with the first gate electrode layer 121 and the first gate electrode layer 126. In some cases, the impurity concentration is higher than that of the impurity region without the impurity region. Therefore, the first p-type impurity region 161a, the first p-type impurity region 161b, the first p-type impurity region 164a, and the first p-type impurity region 164b are more preferable than the second p-type impurity region 160a, The concentration of the impurity element imparting p-type may be higher than or comparable to that of the second p-type impurity region 160b, the second p-type impurity region 163a, and the second p-type impurity region 163b.

In this embodiment, since boron (B) is used as the impurity element, diborane (B ₂ H ₆ ) (doping gas is obtained by diluting B ₂ H ₆ with hydrogen (H ₂ ) as a doping gas containing the impurity element. The ratio of B ₂ H ₆ in the gas is 15%), and doping is performed at a gas flow rate of 70 sccm, a beam current of 180 μA / cm, an acceleration voltage of 80 kV, and a dose of 2.0 × 10 ¹⁵ ions / cm ² to be added. Here, the impurity element imparting p-type to the second p-type impurity region 160a, the second p-type impurity region 160b, the second p-type impurity region 163a, and the second p-type impurity region 163b is 1 × 10. ^It is added so as to be contained at a concentration of about ^{20 to} 5 × 10 ²¹ / cm ³ . In addition, the impurity element imparting p-type conductivity to the first p-type impurity region 161b, the first p-type impurity region 164a, and the first p-type impurity region 164b is about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3. To be included at a concentration of In this embodiment, the first p-type impurity region 161 a, the first p-type impurity region 161 b, the first p-type impurity region 164 a, and the first p-type impurity region 164 b are included in the first gate electrode layer 121. Reflecting the shapes of the first gate electrode layer 126, the second gate electrode layer 131, and the second gate electrode layer 136, the second p-type impurity region 160a and the second p-type impurity are self-aligned. The region 160b, the second p-type impurity region 163a, and the second p-type impurity region 163b are formed to have a lower concentration.

    The second p-type impurity region 160a, the second p-type impurity region 160b, the second p-type impurity region 163a, and the second p-type impurity region 163b are high-concentration p-type impurity regions and function as sources and drains. To do. On the other hand, the first p-type impurity region 161a, the first p-type impurity region 161b, the first p-type impurity region 164a, and the first p-type impurity region 164b are low-concentration p-type impurity regions. Become. The first p-type impurity region 161a, the first p-type impurity region 161b, the first p-type impurity region 164a, and the first p-type impurity region 164b are connected to the first gate electrode through the gate insulating layer 107. Since it is covered with the layer 121 and the first gate electrode layer 126, it is a Lov region, and an electric field in the vicinity of the drain can be reduced.

    Mask layer 156a covering the first gate electrode layer 121, the second gate electrode layer 131, the semiconductor layer 103, the first gate electrode layer 122, the second gate electrode layer 132, and the semiconductor layer 104, the first gate A mask layer 156b is formed to cover the electrode layer 126, the second gate electrode layer 136, and the semiconductor layer 106, and the first gate electrode layer is formed using the second gate electrode layer 134 and the second gate electrode layer 135 as a mask. 124 and the first gate electrode layer 125 are etched, so that the first gate electrode layer 120a and the first gate electrode layer 120b are formed (see FIG. 7A). The first gate electrode layer 120a and the first gate electrode layer 120b reflect the shapes of the second gate electrode layer 134 and the second gate electrode layer 135, and the second gate electrode layer 134 and the second gate electrode layer 135b are reflected. The regions of the first gate electrode layer 124 and the first gate electrode layer 125 extending outside the gate electrode layer 135 are removed. Therefore, the side edge of the first gate electrode layer 120a and the side edge of the second gate electrode layer 134, the side edge of the first gate electrode layer 120b and the side edge of the second gate electrode layer 135 are Each is almost identical.

    Since the first gate electrode layer 124 and the first gate electrode layer 125 are processed like the first gate electrode layer 120a and the first gate electrode layer 120b, the first n-type impurity region 148a and the first n-type impurity region 148a are processed. The type impurity region 148b, the first n-type impurity region 148c, and the first n-type impurity region 148d are not covered with the first gate electrode layer 120a or the first gate electrode layer 120b with the gate insulating layer 107 interposed therebetween. It will be formed as a Loff region. The first n-type impurity region 148a, the first n-type impurity region 148b, the first n-type impurity region 148c, or the first n-type impurity region 148d formed in the Loff region on the drain region side is the drain region It has the effect of reducing the off-current as well as preventing the deterioration due to hot carrier injection by relaxing the electric field in the vicinity. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

The mask layer 156a and the mask layer 156b are removed by O ₂ ashing or resist stripping solution.

    In order to activate the impurity element, heat treatment, intense light irradiation, or laser light irradiation may be performed. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

    Next, a first interlayer insulating layer is formed to cover the gate electrode layer and the gate insulating layer. In this embodiment, a stacked structure of the insulating film 167 and the insulating film 168 is employed (see FIG. 7B). A silicon nitride oxide film is formed to a thickness of 200 nm as the insulating film 167 and a silicon oxynitride film is formed to a thickness of 800 nm as the insulating film 168 to have a stacked structure. Further, a three-layer stack including a silicon oxynitride film with a thickness of 50 nm, a silicon nitride oxide film with a thickness of 140 nm, and a silicon oxynitride film with a thickness of 800 nm is formed covering the gate electrode layer and the gate insulating layer. It is good also as a structure. In this embodiment, the insulating film 167 and the insulating film 168 are continuously formed using a plasma CVD method as in the case of the base film. As the insulating film 167 and the insulating film 168, a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, a silicon oxide film, or the like using a sputtering method or plasma CVD can be used, and another insulating film containing silicon can be used. A single layer or a stacked structure of three or more layers may be used.

    Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating film 167 which is an interlayer insulating layer. In this embodiment, heat treatment is performed at 410 degrees (° C.).

    In addition, as the insulating films 167 and 168, aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide (AlNO) or aluminum oxide in which the nitrogen content is higher than the oxygen content, diamond like carbon (DLC) , Nitrogen-containing carbon (CN), polysilazane, and other materials including inorganic insulating materials. A siloxane resin may also be used. Further, an organic insulating material may be used, and as the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, or benzocyclobutene can be used. Moreover, an oxazole resin can also be used, for example, photosensitive polybenzoxazole can be used. Photosensitive polybenzoxazole has a low dielectric constant (dielectric constant 2.9 at room temperature 1 MHz), high heat resistance (differential thermal balance (TGA) temperature increase 5 ° C./min, thermal decomposition temperature 550 ° C.), water absorption rate Low (0.3% at room temperature for 24 hours) material. A coating film formed by a coating method with good flatness may be used.

Next, contact holes (openings) that reach the semiconductor layers are formed in the insulating film 167, the insulating film 168, and the gate insulating layer 107 using a resist mask. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used. The insulating film 168, the insulating film 167, and the gate insulating layer 107 are removed, and a second p-type impurity region 160a, a second p-type impurity region 160b, a second p-type impurity region 163a, which are source regions or drain regions, Openings reaching second p-type impurity region 163b, second n-type impurity region 144a, second n-type impurity region 144b, second n-type impurity region 147a, and second n-type impurity region 147b are formed. . Etching may be wet etching or dry etching, or a combination of both. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, CCl ₄ or the like, a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can. Further, an inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used.

    A conductive film is formed so as to cover the opening, and the conductive film is etched to be electrically connected to part of each source region or drain region, respectively, and a source electrode layer or a drain electrode layer 169 b , Source or drain electrode layer 170a, source or drain electrode layer 170b, source or drain electrode layer 171a, source or drain electrode layer 171b, source or drain electrode layer 172a, source or drain electrode layer 172a A drain electrode layer 172b is formed. The source electrode layer or the drain electrode layer can be formed by forming a conductive film by a PVD method, a CVD method, an evaporation method, or the like and then etching the conductive film into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the source electrode layer or the drain electrode layer is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba Or a metal nitride thereof or a metal nitride thereof. Moreover, it is good also as these laminated structures. In this embodiment mode, titanium (Ti) is formed to a thickness of 100 nm, an alloy of aluminum and silicon (Al—Si) is formed to a thickness of 700 nm, and titanium (Ti) is formed to a thickness of 200 nm and processed into a desired shape. To do.

    Through the above steps, the peripheral driver circuit region 204 includes a thin film transistor 173 which is a p-channel thin film transistor having a p-type impurity region in the Lov region, and a thin film transistor 174 which is an n-channel thin film transistor having an n-channel impurity region in the Lov region. In 206, an active matrix substrate having a thin film transistor 175 which is a multi-channel n-channel thin film transistor having an n-type impurity region in a Loff region and a thin film transistor 176 which is a p-channel thin film transistor having a p-type impurity region in a Lov region is manufactured. (See FIG. 7C).

    The active matrix substrate can be used for a light emitting device having a self light emitting element, a liquid crystal display device having a liquid crystal element, and other display devices. Further, it can be used for various processors typified by a CPU (Central Processing Unit) and a semiconductor device such as a card equipped with an ID chip.

    Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. The thin film transistor in the peripheral driver circuit region may have a single gate structure, a double gate structure, or a triple gate structure.

    Next, an insulating film 181 and an insulating film 182 are formed as a second interlayer insulating layer (see FIG. 8A). FIG. 8 shows a manufacturing process of a display device. A separation region 201 for separation by scribing, an external terminal connection region 202 as an FPC pasting portion, a wiring region 203 as a peripheral wiring region, A driving circuit area 204 and a pixel area 206. The wiring region 203 is provided with wirings 179a and 179b, and the external terminal connection region 202 is provided with a terminal electrode layer 178 that is connected to an external terminal.

    As the insulating film 181 and the insulating film 182, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride (AlN), aluminum oxide containing nitrogen (also referred to as aluminum oxynitride) (AlON), aluminum nitride containing oxygen (Also called aluminum nitride oxide) (AlNO), aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon film (CN), PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina film, other inorganic insulating properties It can be formed of a material selected from substances including a material. A siloxane resin may also be used. Further, an organic insulating material may be used, and the organic material may be either photosensitive or non-photosensitive, and polyimide, acrylic, polyamide, polyimide amide, resist or benzocyclobutene, polysilazane, low dielectric constant (Low− k) Materials can be used. Moreover, an oxazole resin can also be used, for example, photosensitive polybenzoxazole can be used. Photosensitive polybenzoxazole has a low dielectric constant (dielectric constant 2.9 at room temperature 1 MHz), high heat resistance (differential thermal balance (TGA) temperature increase 5 ° C./min, thermal decomposition temperature 550 ° C.), water absorption rate Low (0.3% at room temperature for 24 hours) material.

    An interlayer insulating layer provided for planarization is required to have high heat resistance and high insulation and a high planarization rate. Therefore, a method for forming the insulating film 181 is represented by a spin coating method. It is preferable to use a coating method. In this embodiment, a coating film using a siloxane resin material is formed as the insulating film 181, and a silicon nitride oxide film is formed as the insulating film 182 using a CVD method.

    The insulating film 181 and the insulating film 182 can employ other dipping methods, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, and the like. The insulating film 181 and the insulating film 182 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used.

    Next, as illustrated in FIG. 8B, openings are formed in the insulating films 181 and 182 which are interlayer insulating layers. The insulating film 181 and the insulating film 182 need to be etched over a wide area in the connection region 205 (see FIG. 10A), the peripheral driver circuit region 204, the wiring region 203, the external terminal connection region 202, the separation region 201, and the like. . Note that the connection region 205 is a region illustrated in the top view of FIG. 10A, and is a wiring layer manufactured in the same step as the source electrode layer or the drain electrode layer, and later becomes an upper electrode layer of the light-emitting element. This is a region where the second electrode layer is electrically connected. The connection area 205 is not shown in FIG. Therefore, it is necessary to provide openings in the insulating film 181 and the insulating film 182 also in the connection region 205. However, the opening area of the pixel region 206 is very small and fine compared to the opening area of the peripheral drive circuit region 204 and the like. Therefore, if a photolithography process for forming an opening in the pixel region and a photolithography process for forming an opening in the connection region are provided, a margin for etching conditions can be further increased. As a result, the yield can be improved. Further, since the margin of the etching condition is widened, the contact hole formed in the pixel region can be formed with high accuracy.

    Specifically, wide openings are formed in the insulating film 181 and the insulating film 182 provided in the connection region 205, the peripheral driver circuit region 204, the wiring region 203, the external terminal connection region 202, and the separation region 201. Therefore, a mask is formed so as to cover the insulating film 181 and the insulating film 182 in the non-opening region in the pixel region 206, the connection region 205, the peripheral driver circuit region 204, the wiring region 203, and the external terminal connection region 202. For the etching, a parallel plate RIE apparatus or an ICP etching apparatus can be used. Note that the etching time is preferably set such that the wiring layer and the insulating film 168 are over-etched. When the over-etching is performed as described above, it is possible to reduce the film thickness variation in the substrate and the etching rate variation. In this way, openings are formed in the connection region 205, the peripheral drive circuit region 204, the wiring region 203, the external terminal connection region 202, and the separation region 201, respectively. An opening 183 is formed in the external terminal connection region 202, and the terminal electrode layer 178 is exposed.

    Thereafter, fine openings, that is, contact holes are formed in the insulating film 181 and the insulating film 182 in the pixel region 206. At this time, a mask is formed so as to cover the insulating film 181 and the insulating film 182 in the non-opening region of the pixel region 206 and the connection region 205, the peripheral driver circuit region 204, the wiring region 203, and the external terminal connection region 202. The mask is a mask for forming an opening in the pixel region 206, and a fine opening is provided at a predetermined location. As such a mask, for example, a resist mask can be used.

    Then, the insulating film 181 and the insulating film 182 are etched using a parallel plate RIE apparatus. Note that the etching time is preferably set such that the wiring layer and the insulating film 168 are over-etched. When the over-etching is performed as described above, it is possible to reduce the film thickness variation in the substrate and the etching rate variation.

    An ICP apparatus may be used as the etching apparatus. Through the above steps, an opening 184 reaching the source or drain electrode layer 172b is formed in the pixel region 206 (see FIG. 8B).

    The etching for forming the opening may be performed a plurality of times at the same location. For example, since the opening of the connection region 205 has a large area, the amount of etching is large. Such a wide-area opening may be etched a plurality of times. In addition, when a deep opening is formed as compared with other openings, etching may be performed a plurality of times in the same manner.

Further, although an example in which the openings in the insulating film 181 and the insulating film 182 are formed in a plurality of times is described in this embodiment mode, the openings may be formed by one etching process. In this case, using an ICP apparatus, etching is performed with an ICP power of 7000 W, a bias power of 1000 W, a pressure of 0.8 Pascal (Pa), CF ₄ as an etching gas of 240 sccm, and O ₂ of 160 sccm. The bias power is preferably 1000 to 4000 W. Since the opening can be formed by one etching process, there is an advantage that the process is simplified.

    When all the openings are formed in the insulating film 181 and the insulating film 182 in a single step, as shown in the above embodiment, an auxiliary pattern having a light intensity reducing function made of a diffraction grating pattern or a semi-transmissive film. It is preferable to use a mask layer formed by an exposure mask provided with. With such an exposure mask, a mask layer having regions with different film thicknesses can be formed. Therefore, the thickness of the mask layer can be increased in a region where the depth of the opening is shallow, such as the opening 184, and the thickness of the mask layer can be decreased in a region where the depth of the opening is deep, such as the opening 183. If a mask layer having a gradient in film thickness according to such a desired etching depth is used, etching at different depths can be performed in one etching process. Therefore, since the exposed wiring layer is not exposed to the etching process for a long time in the shallow opening, damage to the wiring layer due to a large amount of over-etching can be prevented.

Next, a first electrode layer 185 (also referred to as a pixel electrode layer) is formed so as to be in contact with the source or drain electrode layer 172b. The first electrode layer functions as an anode or a cathode, and an element selected from Ti, Ni, W, Cr, Pt, Zn, Sn, In, or Mo, or TiN, TiSi _X N _Y , WSi _X , WN A film mainly containing an alloy material or compound material containing _X , WSi _X N _Y , NbN, or the like as a main component or a stacked film thereof may be used in a total film thickness range of 100 nm to 800 nm.

    In this embodiment, a light-emitting element is used as a display element and light from the light-emitting element is extracted from the first electrode layer 185 side; thus, the first electrode layer 185 has a light-transmitting property. A transparent conductive film is formed as the first electrode layer 185 and etched into a desired shape, whereby the first electrode layer 185 is formed (see FIG. 9A). In this embodiment mode, the insulating film 182 also functions as an etching stopper when the first electrode layer 185 is etched by etching a transparent conductive film thereon into a desired shape.

    In the present invention, a transparent conductive film made of a light-transmitting conductive material may be used for the first electrode layer 185 that is a light-transmitting electrode layer, indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can also be used.

    The composition ratio of each light-transmitting conductive material will be described. The composition ratio of indium oxide containing tungsten oxide may be 1.0 wt% tungsten oxide and 99.0 wt% indium oxide. The composition ratio of indium zinc oxide containing tungsten oxide may be 1.0 wt% tungsten oxide, 0.5 wt% zinc oxide, and 98.5 wt% indium oxide. The indium oxide containing titanium oxide may be 1.0 wt% to 5.0 wt% titanium oxide and 99.0 wt% to 95.0 wt% indium oxide. The composition ratio of indium tin oxide (ITO) may be 10.0 wt% tin oxide and 90.0 wt% indium oxide. The composition ratio of indium zinc oxide (IZO) may be 10.7 wt% zinc oxide and 89.3 wt% indium oxide. The composition ratio of indium tin oxide containing titanium oxide may be 5.0 wt% titanium oxide, 10.0 wt% tin oxide, and 85.0 wt% indium oxide. The above composition ratio is an example, and the ratio of the composition ratio may be set as appropriate.

    Further, even when a material such as a metal film that does not have translucency is used, the first film thickness can be reduced by thinning (preferably about 5 nm to 30 nm) so that light can be transmitted. It becomes possible to emit light from the electrode layer 185. As the metal thin film that can be used for the first electrode layer 185, a conductive film made of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, or an alloy thereof is used. Can do.

    The first electrode layer 185 can be formed by an evaporation method, a sputtering method, a CVD method, a printing method, a droplet discharge method, or the like. In this embodiment, the first electrode layer 185 is formed by a sputtering method using indium zinc oxide containing tungsten oxide. The first electrode layer 185 is preferably used with a total thickness of 100 nm to 800 nm, and in this embodiment, has a thickness of 125 nm.

    The first electrode layer 185 may be wiped with a CMP method or a polyvinyl alcohol-based porous material and polished so that the surface thereof is planarized. Further, after polishing using the CMP method, the surface of the first electrode layer 185 may be subjected to ultraviolet irradiation, oxygen plasma treatment, or the like.

    Heat treatment may be performed after the first electrode layer 185 is formed. By this heat treatment, moisture contained in the first electrode layer 185 is released. Therefore, the first electrode layer 185 does not cause degassing. Therefore, even when a light-emitting material that is easily deteriorated by moisture is formed over the first electrode layer, the light-emitting material is not deteriorated and the display device has high reliability. Can be produced.

    Next, an insulating layer 186 (referred to as a partition wall, a barrier, or the like) is formed to cover the end portion of the first electrode layer 185 and the source or drain electrode layer (see FIG. 9B). In the same step, an insulating layer 187a and an insulating layer 187b are formed in the external terminal connection region 202.

    If the material selection ratio between the first electrode layer 185 and the insulating layer 186 is high, etching is performed into a desired shape in order to form the insulating layer 186 that functions as a partition wall that covers part of the first electrode layer 185. At this time, the first electrode layer 185 functions as an etching stopper.

    The insulating layer 186 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and other inorganic insulating materials, acrylic acid, methacrylic acid, and derivatives thereof, polyimide, aromatic, and the like. It can be formed using a heat-resistant polymer such as polyamide, polybenzimidazole, or a siloxane resin. You may form using photosensitive and non-photosensitive materials, such as an acryl and a polyimide. Moreover, an oxazole resin can also be used, for example, photosensitive polybenzoxazole can be used. Photosensitive polybenzoxazole has a low dielectric constant (dielectric constant 2.9 at room temperature 1 MHz), high heat resistance (differential thermal balance (TGA) temperature increase 5 ° C./min, thermal decomposition temperature 550 ° C.), water absorption rate Low (0.3% at room temperature for 24 hours) material. The insulating layer 186 preferably has a shape in which the radius of curvature continuously changes, and the coverage of the electroluminescent layer 188 and the second electrode layer 189 formed thereon is improved.

    In the connection region 205 illustrated in FIG. 10A, the wiring layer formed using the same material and the same process as the second electrode layer is electrically connected to the wiring layer formed using the same material and the same process as the gate electrode layer. To do. For this connection, an opening exposing the wiring layer formed of the same material and the same process as the gate electrode layer is formed. By covering the step around the opening with the insulating layer 186, the step is made gentle. The coverage of the second electrode layer 189 to be stacked can be improved.

    In order to further improve the reliability, it is preferable to perform deaeration by performing vacuum heating before forming the electroluminescent layer 188. For example, before vapor deposition of the organic compound material, it is desirable to perform heat treatment at 200 to 400 ° C., preferably 250 to 350 ° C. in a reduced pressure atmosphere or an inert atmosphere in order to remove gas contained in the substrate. In addition, it is preferable to form the electroluminescent layer 188 by vacuum deposition or a droplet discharge method under reduced pressure without exposing it to the atmosphere. By this heat treatment, moisture contained in and adhering to the conductive film or insulating layer (partition wall) to be the first electrode layer can be released. This heat treatment can be combined with the previous heating step as long as the substrate can be transported in the vacuum chamber without breaking the vacuum, and the previous heating step may be performed once after the formation of the insulating layer (partition wall). . Here, if the interlayer insulating film and the insulating layer (partition wall) are formed using a material having high heat resistance, a heat treatment process for improving reliability can be sufficiently performed.

    An electroluminescent layer 188 is formed over the first electrode layer 185. Although only one pixel is shown in FIG. 10B, in the present embodiment, field electrode layers corresponding to R (red), G (green), and B (blue) colors are separately formed.

    A material that emits red (R), green (G), or blue (B) light (such as a low-molecular or high-molecular material) can also be formed by a droplet discharge method.

Next, a second electrode layer 189 made of a conductive film is provided over the electroluminescent layer 188. As the second electrode layer 189, a material having a low work function (Al, Ag, Li, Ca, Mg, In, or an alloy or compound thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used. . Thus, a light-emitting element 190 including the first electrode layer 185, the electroluminescent layer 188, and the second electrode layer 189 is formed (see FIG. 10B).

    In the display device in this embodiment mode illustrated in FIG. 10, light emitted from the light-emitting element 190 is transmitted through and emitted from the first electrode layer 185 side in the direction of the arrow in FIG.

    In this embodiment, an insulating layer may be provided as a passivation film (a protective film) over the second electrode layer 189. Thus, it is effective to provide a passivation film so as to cover the second electrode layer 189. Examples of the passivation film include silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), and oxynitride in which the nitrogen content is higher than the oxygen content The insulating film includes aluminum (AlNO) or aluminum oxide, diamond-like carbon (DLC), and a nitrogen-containing carbon film (CN), and a single layer or a combination of the insulating films can be used. Alternatively, a siloxane resin may be used.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the electroluminescent layer 188 having low heat resistance. The DLC film is formed by plasma CVD (typically, RF plasma CVD, microwave CVD, electron cyclotron resonance (ECR) CVD, hot filament CVD, etc.), combustion flame, sputtering, ion beam evaporation. It can be formed by laser vapor deposition. The reaction gas used for film formation was hydrogen gas and a hydrocarbon-based gas (for example, CH ₄ , C ₂ H ₂ , C ₆ H _6, etc.), ionized by glow discharge, and negative self-bias was applied. Films are formed by accelerated collision of ions with the cathode. The CN film may be formed using C ₂ H ₄ gas and N ₂ gas as reaction gases. The DLC film has a high blocking effect against oxygen and can suppress oxidation of the electroluminescent layer 188. Therefore, the problem that the electroluminescent layer 188 is oxidized during the subsequent sealing process can be prevented.

    The substrate 100 over which the light-emitting element 190 is formed in this manner and the sealing substrate 195 are fixed with a sealant 192 to seal the light-emitting element (see FIG. 10). In the display device of the present invention, the sealing material 192 and the insulating layer 186 are formed so as not to contact each other. When the sealing material and the insulating layer 186 are separated from each other in this manner, moisture does not easily enter even when an insulating material using a highly hygroscopic organic material is used for the insulating layer 186, and deterioration of the light-emitting element can be prevented. This improves the reliability of the display device. As the sealant 192, it is typically preferable to use a visible light curable resin, an ultraviolet curable resin, or a thermosetting resin. For example, bisphenol A type liquid resin, bisphenol A type solid resin, bromine-containing epoxy resin, bisphenol F type resin, bisphenol AD type resin, phenol type resin, cresol type resin, novolac type resin, cyclic aliphatic epoxy resin, epibis type epoxy Epoxy resins such as resins, glycidyl ester resins, glycidylamine resins, heterocyclic epoxy resins, and modified epoxy resins can be used. Note that a region surrounded by the sealant may be filled with a filler 193, or nitrogen or the like may be sealed by sealing in a nitrogen atmosphere. Since this embodiment mode is a bottom emission type, the filler 193 does not need to have translucency, but in the case of a structure in which light is extracted through the filler 193, the filler 193 needs to have translucency. Typically, a visible light curable, ultraviolet curable, or thermosetting epoxy resin may be used. Through the above steps, a display device having a display function using a light-emitting element in this embodiment is completed. Further, the filler can be dropped in a liquid state and filled in the display device.

    A dropping injection method employing a dispenser method will be described with reference to FIG. In the dropping injection method of FIG. 24, the control device 40, the imaging means 42, the head 43, the filler 33, the marker 35, and the marker 45 include the barrier layer 34, the sealing material 32, the TFT substrate 30, and the counter substrate 20. A closed loop is formed by the sealing material 32, and the filler 33 is dropped from the head 43 once or a plurality of times. When the viscosity of the filler material is high, the filler material is discharged continuously and adheres to the formation region while being connected. On the other hand, when the viscosity of the filler material is low, the filler is intermittently discharged and the filler is dropped as shown in FIG. At that time, a barrier layer 34 may be provided to prevent the sealing material 32 and the filler 33 from reacting. Then, a board | substrate is bonded together in a vacuum, and ultraviolet curing is performed after that and it is set as the state filled with the filler. When a hygroscopic substance such as a desiccant is used as the filler, a further water absorption effect can be obtained and deterioration of the element can be prevented.

    A desiccant is installed in the EL display panel in order to prevent deterioration of the element due to moisture. In this embodiment mode, the desiccant is provided in a recess formed in the sealing substrate so as to surround the pixel region, and the thickness is not hindered. Moreover, since the desiccant is formed also in the area | region corresponding to a gate wiring layer and the water absorption area is taken wide, the water absorption effect is high. Further, when a desiccant is formed on the gate wiring layer that does not emit light directly, it is possible to prevent a decrease in light extraction efficiency.

    Note that in this embodiment mode, a case where a light-emitting element is sealed with a glass substrate is shown; however, the sealing process is a process for protecting the light-emitting element from moisture and is mechanically sealed with a cover material. A method, a method of encapsulating with a thermosetting resin or an ultraviolet light curable resin, a method of encapsulating with a thin film having a high barrier ability such as a metal oxide or a nitride can be used. As the cover material, glass, ceramics, plastic, or metal can be used. However, when light is emitted to the cover material side, it must be translucent. In addition, the cover material and the substrate on which the light emitting element is formed are bonded together using a sealing material such as a thermosetting resin or an ultraviolet light curable resin, and the resin is cured by heat treatment or ultraviolet light irradiation treatment to form a sealed space. Form. It is also effective to provide a hygroscopic material typified by barium oxide in this sealed space. This hygroscopic material may be provided in contact with the sealing material, or may be provided on the partition wall or in the peripheral portion so as not to block light from the light emitting element. Further, the space between the cover material and the substrate on which the light emitting element is formed can be filled with a thermosetting resin or an ultraviolet light curable resin. In this case, it is effective to add a moisture absorbing material typified by barium oxide in the thermosetting resin or the ultraviolet light curable resin.

    In the display device in FIG. 10 which is manufactured in this embodiment mode in FIG. 14, the source or drain electrode layer 172b and the first electrode layer are not in direct contact with each other for electrical connection, but through a wiring layer. An example of connection is shown. In the display device in FIG. 14, the source electrode layer or the drain electrode layer of the thin film transistor that drives the light-emitting element and the first electrode layer 790 are electrically connected to each other through the wiring layer 199. In FIG. 14, the first electrode layer 790 is connected so as to be partially stacked on the wiring layer 199. However, the first electrode layer 790 is formed first, and the first electrode layer 790 is formed. The wiring layer 199 may be formed so as to be in contact with the top.

    In this embodiment mode, the FPC 194 is connected to the terminal electrode layer 178 with the anisotropic conductive layer 196 in the external terminal connection region 202 so as to be electrically connected to the outside. As shown in FIG. 10A, which is a top view of the display device, the display device manufactured in this embodiment includes a peripheral driver circuit region 204 having a signal line driver circuit and a peripheral driver circuit region 209. A peripheral driving circuit region 207 having a scanning line driving circuit and a peripheral driving circuit region 208 are provided.

    In this embodiment mode, the circuit is formed as described above. However, the present invention is not limited to this, and an IC chip may be mounted as a peripheral driver circuit by the above-described COG method or TAB method. Further, the gate line driver circuit and the source line driver circuit may be plural or singular.

    In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

    Furthermore, in a display device in which a video signal is digital, there are a video signal input to a pixel having a constant voltage (CV) and a constant current (CC). A video signal having a constant voltage (CV) includes a constant voltage (CVCV) applied to the light emitting element and a constant current (CVCC) applied to the light emitting element. In addition, a video signal having a constant current (CC) includes a constant voltage (CCCV) applied to the light emitting element and a constant current (CCCC) applied to the light emitting element.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 4.

    By using the present invention, a highly reliable semiconductor device can be manufactured through a simplified process. Therefore, high-definition and high-quality semiconductor devices and display devices can be manufactured with low cost and high yield.

(Embodiment 6)
An embodiment of the present invention will be described with reference to FIGS. This embodiment shows an example in which the second interlayer insulating layer (the insulating film 181 and the insulating film 182) is not formed in the display device manufactured in Embodiment 5. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As shown in Embodiment Mode 5, the thin film transistor 173, the thin film transistor 174, the thin film transistor 175, and the thin film transistor 176 are formed over the substrate 100, and the insulating film 167 and the insulating film 168 are formed. Each thin film transistor is provided with a source electrode layer or a drain electrode layer connected to a source region or a drain region of the semiconductor layer. A first electrode layer 770 is formed in contact with the source or drain electrode layer 172b in the thin film transistor 176 provided in the pixel region 206 (see FIG. 11).

    The first electrode layer 770 functions as a pixel electrode and may be formed using a material and a process similar to those of the first electrode layer 185 in Embodiment 5. In this embodiment mode, a material having a light-transmitting property is used in order to pass light through the first electrode layer 770 as in Embodiment Mode 1. In this embodiment mode, ITSO which is a transparent conductive film is used for the first electrode layer 770 and is etched into a desired shape.

    An insulating layer 186 is formed so as to cover the end portion of the first electrode layer 770 and the thin film transistor. In this embodiment, as the material of the insulating layer 186, a coating film using a siloxane material (inorganic siloxane or organic siloxane) is used.

    The electroluminescent layer 188 is formed over the first electrode layer, and the second electrode layer 189 is stacked, whereby the light emitting element 190 is formed. In the external terminal connection region 202, the terminal electrode layer 178 is bonded to the FPC 194 through the anisotropic conductive layer 196. The substrate 100 is attached to the sealing substrate 195 with a sealant 192, and the display device is filled with a filler 193 (see FIG. 12). In the display device of this embodiment, the sealant 192 and the insulating layer 186 are formed so as not to contact each other. When the sealing material and the insulating layer 186 are separated from each other in this manner, moisture does not easily enter even when an insulating material using a highly hygroscopic organic material is used for the insulating layer 186, and deterioration of the light-emitting element can be prevented. This improves the reliability of the display device.

    In the display device in FIG. 13, the first electrode layer 780 corresponding to the first electrode layer 770 is connected to the thin film transistor 176 with the source or drain electrode layer 781 corresponding to the source or drain electrode layer 172 b. In this example, the insulating film 168 is selectively formed before the formation. In this case, the connection structure between the source or drain electrode layer 781 and the first electrode layer 780 is different from that in this embodiment, and the source or drain electrode layer 781 is stacked over the first electrode layer 780. It becomes a structure. When the first electrode layer 780 is formed before the source or drain electrode layer 781, the first electrode layer 780 can be formed in a flat formation region. Therefore, the first electrode layer 780 can be formed in a flat formation region. There are advantages.

    The display device in FIG. 33 is an example in which after the source or drain electrode layer 172b is formed, the insulating film 771 covering the source or drain electrode layer 172b and the insulating film 168 is formed. The insulating film 771 functions not only as a passivation film but also as a planarization film. The insulating film 771 can also be formed using a material and a method similar to those of the insulating film 168. In FIG. 33, a silicon oxynitride film is formed with a thickness of 50 nm to 500 nm, preferably 100 nm to 300 nm (100 nm in this embodiment) by a plasma CVD method. An opening reaching the source or drain electrode layer 172 b is formed in the insulating film 771, and an opening reaching the terminal electrode layer 178 is formed in the external terminal connection region 202. A first electrode layer 772 is formed so as to cover the opening, and the source or drain electrode layer 172b and the first electrode layer 772 are electrically connected.

    By using the present invention, a highly reliable semiconductor device can be manufactured through a simplified process. Therefore, high-definition and high-quality semiconductor devices and display devices can be manufactured with low cost and high yield.

(Embodiment 7)
Although a display device having a light-emitting element can be formed by applying the present invention, light emitted from the light-emitting element performs any one of bottom emission, top emission, and dual emission. In this embodiment mode, examples of a dual emission type and a top emission type will be described with reference to FIGS.

    16 includes an element substrate 1300, a thin film transistor 1355, a thin film transistor 1365, a thin film transistor 1375, a thin film transistor 1385, a wiring layer 1324a, a wiring layer 1324b, a first electrode layer 1317, an electroluminescent layer 1319, and a second electrode layer 1320. , Filler 1322, sealing material 1325, insulating film 1301a, insulating film 1301b, gate insulating layer 1310, insulating film 1311, insulating film 1312, insulating layer 1314, sealing substrate 1323, wiring layer 1345a, wiring layer 1345b, terminal electrode layer 1381a, a terminal electrode layer 1381b, an anisotropic conductive layer 1382, and an FPC 1383 are included. The display device includes an external terminal connection region 222, a wiring region 223, a peripheral driver circuit region 224, and a pixel region 226. The filler 1322 can be formed into a liquid composition by the dropping method as in the dropping method of FIG. The element substrate 1300 on which the filler is formed and the sealing substrate 1323 are attached to each other by a dropping method to seal the light-emitting display device.

    A thin film transistor 1355, a thin film transistor 1365, a thin film transistor 1375, and a wiring layer (functioning as a source electrode layer or a drain electrode layer) connected to the thin film transistor 1385 have a two-layer structure. Although the wiring layer 1324a and the wiring layer 1324b are also stacked, the wiring layer 1324b extends from the end of the wiring layer 1324a, and the wiring layer 1324b and the first electrode layer 1317 are formed in contact with each other. In the wiring region 223, ends of the gate insulating layer 1310, the insulating film 1311, and the insulating film 1312 are etched into a tapered shape, and the ends are formed so as to be covered with the wiring layer 1345a and the wiring layer 1345b. ing. In this way, when using a mask layer formed by an exposure mask provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, which can form a resist mask layer in a fine shape, Even if it is the etching process in the same process, it can be freely etched into different shapes.

    The display device in FIG. 16 is a dual emission type and has a structure in which light is emitted from both the element substrate 1300 side and the sealing substrate 1323 side in the direction of the arrow. Therefore, a light-transmitting electrode layer is used as the first electrode layer 1317 and the second electrode layer 1320.

    In this embodiment mode, specifically, a transparent conductive film formed using a light-transmitting conductive material may be used for the first electrode layer 1317 and the second electrode layer 1320 which are light-transmitting electrode layers. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can also be used.

    The composition ratio of each light-transmitting conductive material will be described. The composition ratio of indium oxide containing tungsten oxide may be 1.0 wt% tungsten oxide and 99.0 wt% indium oxide. The composition ratio of indium zinc oxide containing tungsten oxide may be 1.0 wt% tungsten oxide, 0.5 wt% zinc oxide, and 98.5 wt% indium oxide. The indium oxide containing titanium oxide may be 1.0 wt% to 5.0 wt% titanium oxide and 99.0 wt% to 95.0 wt% indium oxide. The composition ratio of indium tin oxide (ITO) may be 10.0 wt% tin oxide and 90.0 wt% indium oxide. The composition ratio of indium zinc oxide (IZO) may be 10.7 wt% zinc oxide and 89.3 wt% indium oxide. The composition ratio of indium tin oxide containing titanium oxide may be 5.0 wt% titanium oxide, 10.0 wt% tin oxide, and 85.0 wt% indium oxide. The above composition ratio is an example, and the ratio of the composition ratio may be set as appropriate.

    Further, even when a material such as a metal film that does not have translucency is used, the first film thickness can be reduced by thinning (preferably about 5 nm to 30 nm) so that light can be transmitted. Light can be emitted from the electrode layer 1317 and the second electrode layer 1320. In addition, examples of the metal thin film that can be used for the first electrode layer 1317 and the second electrode layer 1320 include titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, and alloys thereof. A conductive film can be used.

    As described above, the display device in FIG. 16 has a structure in which light emitted from the light-emitting element 1305 passes through both the first electrode layer 1317 and the second electrode layer 1320 and emits light from both sides. .

    In the display device in FIG. 16, a wiring layer 1324a which is a source electrode layer or a drain electrode layer of a thin film transistor 1355 and a first electrode layer 1317 of a light-emitting element which is a pixel electrode layer are directly stacked to perform electrical connection. Instead, the wiring layer 1324a and the first electrode layer 1317 are electrically connected through the wiring layer 1324b formed under the wiring layer 1324a. With such a structure, even when the wiring layer 1324a and the first electrode layer 1317 are in direct contact with each other, it is difficult to make electrical connection between them, and when the materials are in contact with each other, deterioration such as electrical contact may occur. Since the wiring layer 1324b is interposed therebetween, it can be used. Accordingly, the selectivity of materials that can be used for the wiring layer 1324a and the first electrode layer 1317 is increased. Since it is not necessary to consider a problem caused by the lamination of the wiring layer 1324a and the first electrode layer 1317, a material having characteristics required for each of the wiring layer 1324a, the drain electrode layer, and the first electrode layer 1317 is used. You can choose freely. Therefore, a display device with higher function and high reliability can be manufactured with high yield. The connection structure between the saw electrode layer or the drain electrode layer and the first electrode layer is the same as in the display device of FIG.

    The display device of FIG. 15 has a structure in which the top surface is emitted in the direction of the arrow. The display device illustrated in FIG. 15 includes an element substrate 1600, a thin film transistor 1655, a thin film transistor 1665, a thin film transistor 1675, a thin film transistor 1685, a wiring layer 1624a, a wiring layer 1624b, a first electrode layer 1617, an electroluminescent layer 1619, and a second electrode layer 1620. , Protective film 1621, filler 1622, sealing material 1625, insulating film 1601a, insulating film 1601b, gate insulating layer 1610, insulating film 1611, insulating film 1612, insulating layer 1614, sealing substrate 1623, wiring layer 1633a, wiring layer 1633b , A terminal electrode layer 1681a, a terminal electrode layer 1681b, an anisotropic conductive layer 1682, and an FPC 1683.

    In the display device in FIG. 15, the insulating layer stacked over the terminal electrode layer 1681 is removed by etching. As shown in FIGS. 15 and 16, the reliability is further improved when the insulating layer having moisture permeability is not provided around the terminal electrode layer. In addition, the display device includes an external terminal connection region 232, a wiring region 233, a peripheral driver circuit region 234, and a pixel region 236. In the wiring region 233, ends of the gate insulating layer 1610, the insulating film 1611, and the insulating film 1612 are etched into a tapered shape, and the ends are formed so as to be covered with the wiring layer 1633a and the wiring layer 1633b. ing. As described above, an exposure mask provided with an auxiliary pattern having a light intensity reducing function composed of a diffraction grating pattern or a semi-transmissive film, which can form a resist mask layer in a fine shape even by etching in the same process. When the mask layer formed by the above is used, it is possible to freely perform etching into different shapes.

    In the case of the display device in FIG. 15, in the dual emission display device shown in FIG. 16 described above, a wiring layer 1624b which is a reflective metal layer is formed under the first electrode layer 1317. A first electrode layer 1617 which is a transparent conductive film is formed over the wiring layer 1624b. The wiring layer 1624b only needs to have reflectivity, so that a conductive film made of titanium, tungsten, nickel, gold, platinum, silver, copper, tantalum, molybdenum, aluminum, magnesium, calcium, lithium, or an alloy thereof, or the like May be used. Preferably, a substance having high reflectivity in the visible light region is used. In this embodiment, a TiN film is used.

    For the first electrode layer 1617 and the second electrode layer 1620, specifically, a transparent conductive film formed using a light-transmitting conductive material may be used. Indium oxide containing tungsten oxide or indium containing tungsten oxide may be used. Zinc oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can also be used.

    Further, even if the material is a material such as a metal film that does not have translucency, the second film thickness can be reduced (preferably, about 5 nm to 30 nm) so that light can be transmitted. It becomes possible to emit light from the electrode layer 1620. As the metal thin film that can be used for the second electrode layer 1620, a conductive film made of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, or an alloy thereof is used. Can do.

  A structure of the light-emitting element 190 which can be applied in this embodiment mode will be described in detail with reference to FIGS.

  FIG. 18 illustrates an element structure of a light-emitting element. Light emission in which an electroluminescent layer 860 formed by mixing an organic compound and an inorganic compound is sandwiched between a first electrode layer 870 and a second electrode layer 850. It is an element. The electroluminescent layer 860 includes a first layer 804, a second layer 803, and a third layer 802 as shown in the drawing, and particularly has a great feature in the first layer 804 and the third layer 802. .

  First, the first layer 804 is a layer that has a function of transporting holes to the second layer 803, and includes a first organic compound and a first organic electron-accepting property with respect to the first organic compound. It is a structure containing an inorganic compound. What is important is not simply that the first organic compound and the first inorganic compound are mixed, but the first inorganic compound exhibits an electron accepting property with respect to the first organic compound. By adopting such a configuration, many hole carriers are generated in the first organic compound which has essentially no intrinsic carrier, and exhibits extremely excellent hole injection and hole transport properties.

  Therefore, the first layer 804 has not only effects (such as improved heat resistance) that are considered to be obtained by mixing an inorganic compound, but also excellent conductivity (in particular, in the first layer 804, hole injection). And transportability) can also be obtained. This is an effect that cannot be obtained with a conventional hole transport layer in which an organic compound and an inorganic compound that do not have an electronic interaction with each other are simply mixed. Due to this effect, the drive voltage can be made lower than in the prior art. Further, since the first layer 804 can be thickened without causing an increase in driving voltage, a short circuit of an element due to dust or the like can be suppressed.

By the way, as described above, since hole carriers are generated in the first organic compound, the first organic compound is preferably a hole-transporting organic compound. Examples of the hole-transporting organic compound include phthalocyanine (abbreviation: H ₂ Pc), copper phthalocyanine (abbreviation: CuPc), vanadyl phthalocyanine (abbreviation: VOPc), 4,4 ′, 4 ″ -tris (N, N -Diphenylamino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), 1,3 , 5-tris [N, N-di (m-tolyl) amino] benzene (abbreviation: m-MTDAB), N, N′-diphenyl-N, N′-bis (3-methylphenyl) -1,1 ′ -Biphenyl-4,4'-diamine (abbreviation: TPD), 4,4'-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: NPB), 4,4'-bis {N -[4-di m-tolyl) amino] phenyl-N-phenylamino} biphenyl (abbreviation: DNTPD), 4,4 ′, 4 ″ -tris (N-carbazolyl) triphenylamine (abbreviation: TCTA), and the like. It is not limited to. Among the compounds described above, aromatic amine compounds typified by TDATA, MTDATA, m-MTDAB, TPD, NPB, DNTPD, TCTA, etc., are prone to generate hole carriers and are suitable as the first organic compound. A group.

  On the other hand, the first inorganic compound may be anything as long as it can easily receive electrons from the first organic compound, and various metal oxides or metal nitrides can be used. Any transition metal oxide belonging to Group 12 is preferable because it easily exhibits electron acceptability. Specific examples include titanium oxide, zirconium oxide, vanadium oxide, molybdenum oxide, tungsten oxide, rhenium oxide, ruthenium oxide, and zinc oxide. Among the metal oxides described above, any of the transition metal oxides in Groups 4 to 8 of the periodic table has a high electron accepting property and is a preferred group. Vanadium oxide, molybdenum oxide, tungsten oxide, and rhenium oxide are particularly preferable because they can be vacuum-deposited and are easy to handle.

  Note that the first layer 804 may be formed by stacking a plurality of layers to which the above-described combination of an organic compound and an inorganic compound is applied. Moreover, other organic compounds or other inorganic compounds may be further contained.

  Next, the third layer 802 will be described. The third layer 802 is a layer having a function of transporting electrons to the second layer 803, and includes at least a third organic compound and a third inorganic compound that exhibits an electron donating property with respect to the third organic compound. It is the structure containing these. What is important is not that the third organic compound and the third inorganic compound are merely mixed, but that the third inorganic compound exhibits an electron donating property with respect to the third organic compound. By adopting such a structure, many electron carriers are generated in the third organic compound which has essentially no intrinsic carrier, and exhibits extremely excellent electron injection properties and electron transport properties.

  Therefore, the third layer 802 has not only an effect (such as improvement in heat resistance) considered to be obtained by mixing an inorganic compound but also excellent conductivity (especially in the third layer 802, electron injection). And transportability) can also be obtained. This is an effect that cannot be obtained with a conventional electron transport layer in which an organic compound and an inorganic compound that do not have an electronic interaction with each other are simply mixed. Due to this effect, the drive voltage can be made lower than in the prior art. In addition, since the third layer 802 can be thickened without causing an increase in driving voltage, a short circuit of an element due to dust or the like can be suppressed.

By the way, as described above, since an electron carrier is generated in the third organic compound, the third organic compound is preferably an electron-transporting organic compound. Examples of the electron-transporting organic compound include tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) (4-phenylphenolato) aluminum (abbreviation: BAlq), bis [2- (2′-hydroxyphenyl) benzoxa Zolato] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2′-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), 2- (4-biphenylyl) -5- (4-tert-butylphenyl)- , 3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (4-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD) -7), 2,2 ′, 2 ″-(1,3,5-benzenetriyl) -tris (1-phenyl-1H-benzimidazole) (abbreviation: TPBI), 3- (4-biphenylyl)- 4-phenyl-5- (4-tert-butylphenyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-biphenylyl) -4- (4-ethylphenyl) -5- (4- tert-butylphenyl) -1,2,4-triazole (abbreviation: p-EtTAZ) and the like, but are not limited thereto. Among the compounds described above, a chelate metal complex having a chelate ligand containing an aromatic ring typified by Alq ₃ , Almq ₃ , BeBq ₂ , BAlq, Zn (BOX) ₂ , Zn (BTZ) ₂ , Organic compounds having a phenanthroline skeleton typified by BPhen, BCP, etc., and organic compounds having an oxadiazole skeleton typified by PBD, OXD-7, etc. are likely to generate electron carriers and are suitable as a third organic compound. Compound group.

  On the other hand, the third inorganic compound may be anything as long as it easily gives electrons to the third organic compound, and various metal oxides or metal nitrides can be used. Earth metal oxides, rare earth metal oxides, alkali metal nitrides, alkaline earth metal nitrides, and rare earth metal nitrides are preferable because they easily exhibit electron donating properties. Specific examples include lithium oxide, strontium oxide, barium oxide, erbium oxide, lithium nitride, magnesium nitride, calcium nitride, yttrium nitride, and lanthanum nitride. In particular, lithium oxide, barium oxide, lithium nitride, magnesium nitride, and calcium nitride are preferable because they can be vacuum-deposited and are easy to handle.

  Note that the third layer 802 may be formed by stacking a plurality of layers to which the above-described combination of an organic compound and an inorganic compound is applied. Moreover, other organic compounds or other inorganic compounds may be further contained.

  Next, the second layer 803 will be described. The second layer 803 is a layer having a light emitting function and includes a light emitting second organic compound. Moreover, the structure containing a 2nd inorganic compound may be sufficient. The second layer 803 can be formed using various light-emitting organic compounds and inorganic compounds. However, since the second layer 803 is less likely to flow current than the first layer 804 and the third layer 802, the thickness is preferably about 10 nm to 100 nm.

The second organic compound is not particularly limited as long as it is a luminescent organic compound. For example, 9,10-di (2-naphthyl) anthracene (abbreviation: DNA), 9,10-di (2 -Naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), 4,4'-bis (2,2-diphenylvinyl) biphenyl (abbreviation: DPVBi), coumarin 30, coumarin 6, coumarin 545, coumarin 545T Perylene, rubrene, periflanthene, 2,5,8,11-tetra (tert-butyl) perylene (abbreviation: TBP), 9,10-diphenylanthracene (abbreviation: DPA), 5,12-diphenyltetracene, 4- ( Dicyanomethylene) -2-methyl- [p- (dimethylamino) styryl] -4H-pyran (abbreviation: DCM1), 4- (di Cyanomethylene) -2-methyl-6- [2- (julolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCM2), 4- (dicyanomethylene) -2,6-bis [p- (dimethylamino) ) Styryl] -4H-pyran (abbreviation: BisDCM) and the like. In addition, bis [2- (4 ′, 6′-difluorophenyl) pyridinato-N, C ^{2 ′} ] iridium (picolinate) (abbreviation: FIrpic), bis {2- [3 ′, 5′-bis (trifluoromethyl) ) Phenyl] pyridinato-N, C ^{2 ′} } iridium (picolinate) (abbreviation: Ir (CF ₃ ppy) ₂ (pic)), tris (2-phenylpyridinato-N, C ^{2 ′} ) iridium (abbreviation: Ir (Ppy) ₃ ), bis (2-phenylpyridinato-N, C ^{2 ′} ) iridium (acetylacetonate) (abbreviation: Ir (ppy) ₂ (acac)), bis [2- (2′-thienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonate) _{(abbreviation: Ir (thp) 2 (acac} )), bis (2-phenylquinolinato--N, C ^2') iridium (Asechirua Tonato) _{(abbreviation: Ir (pq) 2 (acac} )), bis [2- (2'-benzothienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonate) (abbreviation: Ir _(btp) 2 (acac A compound capable of emitting phosphorescence such as)) can also be used.

As the second layer 803, a triplet excited light-emitting material containing a metal complex or the like may be used in addition to a singlet excited light-emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

Further, in the second layer 803, not only the second organic compound that emits light but also other organic compounds may be added. Examples of the organic compound that can be added include TDATA, MTDATA, m-MTDAB, TPD, NPB, DNTPD, TCTA, Alq ₃ , Almq ₃ , BeBq ₂ , BAlq, Zn (BOX) ₂ , and Zn (BTZ) described above. ₂ , BPhen, BCP, PBD, OXD-7, TPBI, TAZ, p-EtTAZ, DNA, t-BuDNA, DPVBi, etc., 4,4′-bis (N-carbazolyl) biphenyl (abbreviation: CBP), 1 , 3,5-tris [4- (N-carbazolyl) phenyl] benzene (abbreviation: TCPB) can be used, but is not limited thereto. In addition, the organic compound added in addition to the second organic compound in this way has an excitation energy larger than the excitation energy of the second organic compound in order to efficiently emit the second organic compound, and the second organic compound. It is preferable to add more than the organic compound (by this, concentration quenching of the second organic compound can be prevented). Or as another function, you may show light emission with a 2nd organic compound (Thereby, white light emission etc. are also attained).

    The second layer 803 may have a structure in which a light emitting layer having a different emission wavelength band is formed for each pixel to perform color display. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, it is possible to improve color purity and prevent mirror reflection (reflection) of the pixel portion by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel. Can do. By providing the filter, it is possible to omit a circularly polarizing plate that has been conventionally required, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

    The material that can be used for the second layer 803 may be a low molecular weight organic light emitting material or a high molecular weight organic light emitting material. The polymer organic light emitting material has higher physical strength and higher device durability than the low molecular weight material. In addition, since the film can be formed by coating, the device can be manufactured relatively easily.

    Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

    Examples of the polyparaphenylene vinylene include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  The second inorganic compound may be any inorganic compound as long as it is difficult to quench the light emission of the second organic compound, and various metal oxides and metal nitrides can be used. In particular, a metal oxide of Group 13 or Group 14 of the periodic table is preferable because it is difficult to quench the light emission of the second organic compound, and specifically, aluminum oxide, gallium oxide, silicon oxide, and germanium oxide are preferable. . However, it is not limited to these.

  Note that the second layer 803 may be formed by stacking a plurality of layers to which the above-described combination of an organic compound and an inorganic compound is applied. Moreover, other organic compounds or other inorganic compounds may be further contained. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, an electrode layer for this purpose is provided, or a light-emitting material is dispersed. Modifications can be made without departing from the spirit of the present invention.

    A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be delayed, and the reliability of the light-emitting display device can be improved. Further, either digital driving or analog driving can be applied.

    In the case of a top emission display device and a dual emission display device, a color filter (colored layer) may be formed over the sealing substrate. The color filter (colored layer) can be formed by an evaporation method or a droplet discharge method. When the color filter (colored layer) is used, high-definition display can be performed. This is because the color filter (colored layer) can be corrected so that a broad peak becomes a sharp peak in the emission spectrum of each RGB.

    Full color display can be performed by forming a material exhibiting monochromatic light emission and combining a color filter and a color conversion layer. The color filter (colored layer) and the color conversion layer may be formed, for example, on the second substrate (sealing substrate) and attached to the substrate.

    Of course, monochromatic light emission may be displayed. For example, an area color type display device may be formed using monochromatic light emission. As the area color type, a passive matrix type display unit is suitable, and characters and symbols can be mainly displayed.

  The materials of the first electrode layer 870 and the second electrode layer 850 need to be selected in consideration of the work function, and both the first electrode layer 870 and the second electrode layer 850 are anodes depending on the pixel structure. Or a cathode. In the case where the polarity of the driving thin film transistor is a p-channel type, the first electrode layer 870 may be an anode and the second electrode layer 850 may be a cathode as illustrated in FIG. In the case where the polarity of the driving thin film transistor is an n-channel type, it is preferable that the first electrode layer 870 be a cathode and the second electrode layer 850 be an anode as shown in FIG. Materials that can be used for the first electrode layer 870 and the second electrode layer 850 are described. In the case where the first electrode layer 870 and the second electrode layer 850 function as anodes, a material having a high work function (specifically, a material of 4.5 eV or more) is preferable, and the first electrode layer and the second electrode In the case where the layer 850 functions as a cathode, a material having a low work function (specifically, a material having a value of 3.5 eV or less) is preferable. However, since the hole injection and hole transport characteristics of the first layer 804 and the electron injection / transport characteristics of the third layer 802 are excellent, both the first electrode layer 870 and the second electrode layer 850 have almost work. Various materials can be used without being restricted by the function.

18A and 18B has a structure in which light is extracted from the first electrode layer 870, the second electrode layer 850 does not necessarily have a light-transmitting property. As the second electrode layer 850, an element selected from Ti, Ni, W, Cr, Pt, Zn, Sn, In, Ta, Al, Cu, Au, Ag, Mg, Ca, Li, or Mo, or TiN , TiSi _X N _Y , WSi _X , WN _X , WSi _X N _Y , NbN, or other alloy material or compound material containing the above elements as a main component, or a laminated film thereof having a total film thickness of 100 nm to 800 nm It may be used in the range.

    The second electrode layer 850 can be formed by an evaporation method, a sputtering method, a CVD method, a printing method, a droplet discharge method, or the like.

    In addition, when a light-transmitting conductive material such as a material used for the first electrode layer 870 is used for the second electrode layer 850, light is extracted from the second electrode layer 850, so that the light-emitting element can emit light. The emitted light may have a dual emission structure in which both the first electrode layer 870 and the second electrode layer 850 are emitted.

  Note that the light-emitting element of the present invention has various variations by changing types of the first electrode layer 870 and the second electrode layer 850.

  FIG. 18B illustrates a case where the electroluminescent layer 860 includes the third layer 802, the second layer, and the first layer 804 in this order from the first electrode layer 870 side.

  As described above, in the light-emitting element of the present invention, the layer sandwiched between the first electrode layer 870 and the second electrode layer 850 includes a layer in which an organic compound and an inorganic compound are combined. The electroluminescent layer 860 is formed. Then, by mixing the organic compound and the inorganic compound, there are provided layers (that is, the first layer 804 and the third layer 802) that can obtain functions of high carrier injection and carrier transport that cannot be obtained independently. It is a novel organic / inorganic composite light emitting device. In addition, when the first layer 804 and the third layer 802 are provided on the first electrode layer 870 side, the first layer 804 and the third layer 802 need to be a layer in which an organic compound and an inorganic compound are combined. When provided on the 850 side, only an organic compound or an inorganic compound may be used.

  Note that although the electroluminescent layer 860 is a layer in which an organic compound and an inorganic compound are mixed, various known methods can be used as a formation method thereof. For example, there is a technique in which both an organic compound and an inorganic compound are evaporated by resistance heating and co-evaporated. In addition, while the organic compound is evaporated by resistance heating, the inorganic compound may be evaporated by electron beam (EB) and co-evaporated. Further, there is a method of evaporating the organic compound by resistance heating and simultaneously sputtering the inorganic compound and depositing both at the same time. In addition, the film may be formed by a wet method.

  Similarly, for the first electrode layer 870 and the second electrode layer 850, a vapor deposition method using resistance heating, an EB vapor deposition method, a sputtering method, a wet method, or the like can be used.

    FIG. 18C illustrates a structure in which an electrode layer having reflectivity is used for the first electrode layer 870 and a light-transmitting electrode layer is used for the second electrode layer 850 in FIG. Light emitted from the light emitting layer is reflected by the first electrode layer 870 and transmitted through the second electrode layer 850 to be emitted. Similarly, in FIG. 18D, a reflective electrode layer is used for the first electrode layer 870 and a light-transmitting electrode layer is used for the second electrode layer 850 in FIG. 18B. The light emitted from the electroluminescent layer is reflected by the first electrode layer 870 and transmitted through the second electrode layer 850 to be emitted.

    This embodiment mode can be freely combined with the above Embodiment Modes 1 to 6.

    By using the present invention, a highly reliable display device can be manufactured through a simplified process. Therefore, a high-definition and high-quality display device can be manufactured at a low cost and with a high yield.

(Embodiment 8)
An embodiment of the present invention will be described with reference to FIG. This embodiment shows an example of a liquid crystal display device including a liquid crystal display element using a liquid crystal material as a display element in the display device manufactured in Embodiment 5. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    17A is a top view of the liquid crystal display device, and FIG. 17B is a cross-sectional view taken along line CD in FIG. 17A.

    A display device illustrated in FIG. 17 includes an element substrate 600, a thin film transistor 620, a thin film transistor 621, a thin film transistor 622, a capacitor 623, a pixel electrode layer 630, an alignment film 631, a liquid crystal layer 632, an alignment film 633, a counter electrode layer 634, a color filter 635, Counter substrate 695, polarizing plate 636 a, polarizing plate 636 b, sealing material 692, insulating film 604 a, insulating film 604 b, gate insulating layer 611, insulating film 612, insulating film 615, insulating film 616, terminal electrode layer 678, anisotropic conductivity A layer 696, an FPC 694, and a spacer 637 are included. The display device includes a separation region 601, an external terminal connection region 602, a sealing region 603, a driver circuit region 608a, a driver circuit region 608b, and a pixel region 606.

    The pixel electrode layer 630 and the counter electrode layer 634 can be formed using a material similar to that of the first electrode layer 185 of the light-emitting element in Embodiment 5 and can be formed in a similar process. In the case of a transmissive liquid crystal display device, the pixel electrode layer 630 and the counter electrode layer 634 may be formed using a light-transmitting material. In the case of a reflective liquid crystal display device that extracts light from the counter electrode layer 634 side, the pixel electrode layer 630 may be formed using a reflective material.

An alignment film 631 is formed by a printing method or a spin coating method so as to cover the pixel electrode layer 630 and the thin film transistor. Note that the alignment film 631 can be selectively formed by using a screen printing method or an offset printing method. Then, rubbing is performed. Subsequently, a sealant 692 is formed in a peripheral region where pixels are formed by a droplet discharge method.

    After that, a counter substrate 695 provided with an alignment film 633, a counter electrode layer 634, a color filter 635, and a polarizing plate 636b and an element substrate 600 having a TFT are bonded to each other with a spacer 637, and a liquid crystal layer 632 is provided in the gap. Thus, a liquid crystal display device can be manufactured. Further, since the liquid crystal display device of this embodiment mode is a transmissive type, a polarizing plate 636a is also formed on the side of the element substrate 600 that does not have a TFT. A filler may be mixed in the sealing material, and a shielding film (black matrix) or the like may be formed on the counter substrate 695. Note that as a method for forming the liquid crystal layer, a dispenser type (dropping type) or a dip type (pumping type) in which liquid crystal is injected using a capillary phenomenon after the counter substrate 695 is attached can be used.

    The liquid crystal dropping injection method employing the dispenser method may be performed in the same manner as the filling material injection method shown in FIG. Subsequently, the substrates are bonded together in a vacuum, and thereafter UV curing is performed to fill the liquid crystal. Further, a sealing material may be formed on the TFT substrate side, and the liquid crystal may be dropped.

    The spacer may be formed by dispersing particles of several μm, but in this embodiment, a method is used in which a resin film is formed on the entire surface of the substrate and then etched into a desired shape. After applying such a spacer material with a spinner, it is formed into a predetermined pattern by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this way can have different shapes depending on the conditions of exposure and development processing, but preferably, the spacers are columnar and the top is flat, so that the opposite substrate is When combined, the mechanical strength of the liquid crystal display device can be ensured. The shape can be a conical shape, a pyramid shape or the like, and there is no particular limitation.

A connection portion is formed to connect the inside of the display device formed by the above steps and an external wiring board. The insulator layer in the connection portion is removed by ashing using oxygen gas at or near atmospheric pressure. This treatment is performed using oxygen gas and one or more selected from hydrogen, CF ₄ , NF ₃ , H ₂ O, and CHF ₃ . In this step, in order to prevent damage and destruction due to static electricity, ashing is performed after sealing using the counter substrate. However, if there is little influence from static electricity, it may be performed at any timing. .

    Subsequently, the terminal electrode layer 678 which is electrically connected to the pixel portion is provided with an FPC 694 which is a wiring board for connection through an anisotropic conductive layer 696. The FPC 694 plays a role of transmitting an external signal or potential. Through the above steps, a liquid crystal display device having a display function can be manufactured.

    As shown in FIG. 17A, the pixel region 606, the driver circuit region 608a functioning as a scan line driver circuit, and the driver circuit region 608b are sealed between the element substrate 600 and the counter substrate 695 with a sealant 692. In addition, a driving circuit region 607 functioning as a signal line driving circuit formed by an IC driver is provided over the element substrate 600. A driving circuit including a thin film transistor 620 and a thin film transistor 621 is provided in the driving region.

    In the peripheral driver circuit in this embodiment, since the thin film transistor 620 is a p-channel thin film transistor and the thin film transistor 621 is an n-channel thin film transistor, a CMOS circuit including the thin film transistor 620 and the thin film transistor 621 is provided.

    The capacitor 395 and the capacitor 623 described in Embodiment 4 can be manufactured in a similar manner. Since the capacitor 623 can form the first conductive layer 652a in a shape wider than that of the second conductive layer 652b, the n-type impurity region 651 can have a wide region. Since the capacitance formed between the impurity region and the gate electrode is larger than the capacitance formed between the region to which no impurity element is added and the gate electrode, the n-type impurity region 651 under the first conductive layer 652a is made wider. When formed, a large capacity can be obtained.

The thin film transistor 622 is a double-gate n-channel thin film transistor having an LDD in the Loff region. The n-type impurity region formed in the Loff region has an effect of relaxing the electric field in the vicinity of the drain region to prevent deterioration due to hot carrier injection and reducing off-current. As a result, a display device with high reliability and low power consumption can be manufactured.
(Embodiment 9)
One mode in which protective diodes are provided in the scanning line side input terminal portion and the signal line side input terminal portion will be described with reference to FIG. In FIG. 23, a pixel 2702 is provided with a TFT 501, a TFT 502, a capacitor 504, and a pixel electrode layer 503.

    A protection diode 561 and a protection diode 562 are provided in the signal line side input terminal portion. This protection diode is manufactured in the same process as the TFT 501 or the TFT 502, and is operated as a diode by connecting the gate and one of the drain or the source. An equivalent circuit diagram of the top view shown in FIG. 23 is shown in FIG.

    The protection diode 561 includes a gate electrode layer, a semiconductor layer, and a wiring layer. The protective diode 562 has a similar structure. The common potential line 554 and the common potential line 555 connected to the protection diode are formed in the same layer as the gate electrode layer. Therefore, in order to be electrically connected to the wiring layer, it is necessary to form a contact hole in the insulating layer.

    The contact hole to the insulating layer may be etched by forming a mask layer. In this case, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    The signal wiring layer is formed of the same layer as the source and drain wiring layer 505 in the TFT 501, and has a structure in which the signal wiring layer connected thereto and the source or drain side are connected.

    The input terminal portion on the scanning signal line side has the same configuration. The protective diode 563 includes a gate electrode layer, a semiconductor layer, and a wiring layer. The protective diode 564 has a similar structure. The common potential line 556 and the common potential line 557 connected to the protection diode are formed of the same layer as the source electrode layer and the drain electrode layer. A protection diode provided in the input stage can be formed at the same time. Note that the position at which the protective diode is inserted is not limited to this embodiment mode, and can be provided between the driver circuit and the pixel.

    Further, as shown in the top view of FIG. 23, the wiring layer is each corner portion bent in an L shape, and one side of a right triangle is 10 μm or less, or 1 / of the line width of the wiring. The corners are deleted to a size of 2/5 or less and 1/5 or more of the line width, and the corners are rounded. That is, the outer periphery of the wiring layer at the corner portion viewed from the upper surface forms a curve. The corner is ½ or less of the line width, and the corner is rounded to 1/5 or more. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other sandwiching the corner portion, and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the wiring layer corresponding to the right isosceles triangular portion formed by is removed. If removed, two obtuse angled parts are newly formed in the wiring layer. However, by appropriately setting the mask design and etching conditions, each obtuse angled part has a curve in contact with both the first straight line and the second straight line. It is preferable to etch the wiring layer so that it is formed. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion.

    In such a wiring layer, the bend and the corner of the part where the wiring width changes are smoothed and rounded to suppress the generation of fine powder due to abnormal discharge during dry etching by plasma. At this time, even if it is a fine powder, the yield is expected to be greatly improved as a result of washing away that it is easy to gather at the corner. That is, the problem of dust and fine powder in the manufacturing process can be solved. Moreover, it can be expected that the wiring corners are electrically conducted by rounding the corners of the wiring. In addition, a large number of parallel wires are very convenient for washing away dust.

(Embodiment 10)
A television device can be completed with the display device formed according to the present invention. FIG. 26 is a block diagram illustrating a main configuration of a television device (an EL television device in this embodiment). In the display panel, only a pixel portion is formed as shown in FIG. 20A, and a scanning line side driver circuit and a signal line side driver circuit are mounted by a TAB method as shown in FIG. And a case where the TFT is formed by SAS as shown in FIG. 20B, and the pixel portion and the scanning line side driver circuit are integrated on the substrate. When the formed signal line side driver circuit is separately mounted as a driver IC, the pixel portion, the signal line side driver circuit, and the scanning line side driver circuit may be integrally formed on the substrate as shown in FIG. However, any form is acceptable.

    As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 704, the video signal amplification circuit 705 that amplifies the video signal, and the signals output from the video signal amplification circuit 705 are red, green, and blue colors. And a control circuit 707 for converting the video signal into the input specifications of the driver IC. The control circuit 707 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 708 may be provided on the signal line side and an input digital signal may be divided into m pieces and supplied.

    Of the signals received by the tuner 704, the audio signal is sent to the audio signal amplification circuit 709, and the output is supplied to the speaker 713 via the audio signal processing circuit 710. The control circuit 711 receives the receiving station (reception frequency) and volume control information from the input unit 712, and sends a signal to the tuner 704 and the audio signal processing circuit 710.

    As shown in FIGS. 27A and 27B, the display module can be incorporated into a housing to complete the television device. A display panel attached to the FPC is generally referred to as an EL display module. Therefore, when an EL display module is used, an EL television device can be completed. A main screen 2003 is formed by the display module, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. Thus, a television device can be completed according to the present invention.

    Moreover, you may make it cut off the reflected light of the light which injects from the outside using a phase difference plate or a polarizing plate. In the case of a top emission display device, an insulating layer serving as a partition may be colored and used as a black matrix. This partition wall can also be formed by a droplet discharge method or the like. Carbon black or the like may be mixed with a pigment-based black resin or a resin material such as polyimide, or may be laminated. A different material may be discharged to the same region a plurality of times by a droplet discharge method to form a partition wall. As the retardation plate and retardation plate, a λ / 4 plate or a λ / 2 plate may be used and designed so that light can be controlled. As a configuration, a TFT element substrate, a light emitting element, a sealing substrate (sealing material), a phase difference plate, a phase difference plate (λ / 4 plate, λ / 2 plate), and a polarizing plate are sequentially emitted from the light emitting element. The light passes through these and is emitted to the outside from the polarizing plate side. The retardation plate and the polarizing plate may be installed on the side from which light is emitted, and may be installed on both sides as long as the display is a double-sided emission type that emits light on both sides. Further, an antireflection film may be provided outside the polarizing plate. This makes it possible to display a higher-definition and precise image.

    As shown in FIG. 27A, a display panel 2002 using a display element is incorporated in a housing 2001, and a general television broadcast is received by a receiver 2005 and wired or wirelessly via a modem 2004. By connecting to a communication network, information communication in one direction (from the sender to the receiver) or in both directions (between the sender and the receiver or between the receivers) can be performed. The television device can be operated by a switch incorporated in the housing or a separate remote controller 2006, and this remote controller is also provided with a display unit 2007 for displaying information to be output. Also good.

    In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display channels, volume, and the like. In this configuration, the main screen 2003 may be formed using an EL display panel with an excellent viewing angle, and the sub screen may be formed using a liquid crystal display panel that can display with low power consumption. In order to prioritize the reduction in power consumption, the main screen 2003 may be formed using a liquid crystal display panel, the sub screen may be formed using an EL display panel, and the sub screen may blink. When the present invention is used, a highly reliable display device can be obtained even when such a large substrate is used and a large number of TFTs and electronic components are used.

    FIG. 27B illustrates a television device having a large display portion of 20 to 80 inches, for example, which includes a housing 2010, a keyboard portion 2012 that is an operation portion, a display portion 2011, a speaker portion 2013, and the like. The present invention is applied to manufacture of the display portion 2011. Since the display portion in FIG. 27B uses a bendable substance, the television set has a curved display portion. Since the shape of the display portion can be freely designed as described above, a television device having a desired shape can be manufactured.

    According to the present invention, since a display device can be formed through a simple process, cost reduction can also be achieved. Therefore, a television device using the present invention can be formed at low cost even if it has a large screen display portion. Therefore, a high-performance and highly reliable television device can be manufactured with high yield.

    Of course, the present invention is not limited to a television device, but can be applied to various applications such as personal computer monitors, information display boards at railway stations and airports, and advertisement display boards on streets. can do.

(Embodiment 11)
This embodiment will be described with reference to FIG. In this embodiment, an example of a module using a panel including the display device manufactured in Embodiments 1 to 9 will be described.

    28A includes a controller 901, a central processing unit (CPU) 902, a memory 911, a power supply circuit 903, an audio processing circuit 929, a transmission / reception circuit 904, and other resistors. Elements such as a buffer and a capacitive element are mounted. The panel 900 is connected to a printed wiring board 986 via a flexible wiring board (FPC) 908.

  The panel 900 includes a pixel portion 905 in which a light-emitting element is provided in each pixel, a first scanning line driver circuit 906 a that selects a pixel included in the pixel portion 905, and a second scanning line driver circuit 906 b. A signal line driver circuit 907 for supplying a video signal to the pixels is provided.

  Various control signals are input / output via an interface (I / F) unit 909 provided on the printed wiring board 986. An antenna port 910 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 986.

  Note that although a printed wiring board 986 is connected to the panel 900 through the FPC 908 in this embodiment mode, the present invention is not necessarily limited to this structure. The controller 901, the audio processing circuit 929, the memory 911, the CPU 902, or the power supply circuit 903 may be directly mounted on the panel 900 by using a COG (Chip on Glass) method. The printed wiring board 986 is provided with various elements such as a capacitor element and a buffer to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

  FIG. 28B is a block diagram of the module shown in FIG. The module 999 includes a VRAM 932, a DRAM 925, a flash memory 926, and the like as the memory 911. The VRAM 932 stores image data to be displayed on the panel, the DRAM 925 stores image data or audio data, and the flash memory stores various programs.

  In the power supply circuit 903, a power supply voltage to be supplied to the panel 900, the controller 901, the CPU 902, the sound processing circuit 929, the memory 911, and the transmission / reception circuit 931 is generated. Depending on the specifications of the panel, the power supply circuit 903 may be provided with a current source.

  The CPU 902 includes a control signal generation circuit 920, a decoder 921, a register 922, an arithmetic circuit 923, a RAM 924, an interface 935 for the CPU, and the like. Various signals input to the CPU 902 via the interface 935 are once held in the register 922 and then input to the arithmetic circuit 923, the decoder 921, and the like. The arithmetic circuit 923 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 921 is decoded and input to the control signal generation circuit 920. The control signal generation circuit 920 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 923, specifically, a memory 911, a transmission / reception circuit 931, an audio processing circuit 929, a controller 901, and the like. Send to.

  The memory 911, the transmission / reception circuit 931, the sound processing circuit 929, and the controller 901 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 930 is sent to the CPU 902 mounted on the printed wiring board 986 via the interface 909. The control signal generation circuit 920 converts the image data stored in the VRAM 932 into a predetermined format according to a signal sent from the input unit 930 such as a pointing device or a keyboard, and sends the image data to the controller 901.

  The controller 901 performs data processing on a signal including image data sent from the CPU 902 in accordance with the panel specifications, and supplies the processed signal to the panel 900. Further, the controller 901 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply circuit 903 and various signals input from the CPU 902. Generated and supplied to the panel 900.

  In the transmission / reception circuit 904, signals transmitted / received as radio waves in the antenna 933 are processed. Specifically, high-frequency signals such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun are used. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 904 is sent to the audio processing circuit 929 in accordance with a command from the CPU 902.

  A signal including audio information sent in accordance with a command from the CPU 902 is demodulated into an audio signal by the audio processing circuit 929 and sent to the speaker 928. The audio signal sent from the microphone 927 is modulated by the audio processing circuit 929 and sent to the transmission / reception circuit 904 in accordance with a command from the CPU 902.

  The controller 901, the CPU 902, the power supply circuit 903, the sound processing circuit 929, and the memory 911 can be mounted as a package of this embodiment mode. This embodiment can be applied to any circuit other than a high-frequency circuit such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

(Embodiment 12)
The configuration of the semiconductor device of this embodiment will be described with reference to FIG. As shown in FIG. 29, the semiconductor device 28 of the present invention has a function of communicating data without contact, and controls the power supply circuit 11, the clock generation circuit 12, the data demodulation / modulation circuit 13, and other circuits. A circuit 14, an interface circuit 15, a memory circuit 16, a data bus 17, an antenna (antenna coil) 18, a sensor 26, and a sensor circuit 27 are included.

The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 28 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 28 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting / receiving electromagnetic waves or radio waves. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

The memory circuit 16 includes a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers. Note that the memory circuit 16 may include only a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 26 is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 27 detects a change in impedance, reactance, inductance, voltage or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 14.

(Embodiment 13)
This embodiment will be described with reference to FIG. FIG. 25 shows one mode of a portable small telephone (mobile phone) using radio including the module manufactured in the eleventh embodiment. An example in which a semiconductor device using the present invention is also mounted on a small telephone is shown. The panel 900 is detachably incorporated in the housing 981 so that it can be easily combined with the module 999. The shape and size of the housing 981 can be changed as appropriate in accordance with an electronic device to be incorporated.

  A housing 981 to which the panel 900 is fixed is fitted to a printed wiring board 986 and assembled as a module. A plurality of packaged semiconductor devices are mounted on the printed wiring board 986, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 986 have any of functions of a controller, a central processing unit (CPU), a memory, a power supply circuit, a resistor, a buffer, a capacitor, and the like. Further, a signal processing circuit 993 such as an audio processing circuit including a microphone 994 and a speaker 995 and a transmission / reception circuit is provided. Panel 900 is connected to printed wiring board 986 via FPC 908.

  Such a module 999, a housing 981, a printed wiring board 986, input means 998, and a battery 997 are housed in a housing 996. The pixel portion of the panel 900 is arranged so as to be visible from an opening window formed in the housing 996. Since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided. In addition, a highly reliable electronic device can be manufactured with high productivity.

  A housing 996 illustrated in FIG. 25 illustrates the appearance of a telephone as an example. However, the electronic device according to this embodiment can be transformed into various modes depending on the function and application. In the following embodiment, an example of the aspect will be described.

(Embodiment 14)
Various display devices can be manufactured by applying the present invention. That is, the present invention can be applied to various electronic devices in which these display devices are incorporated in a display portion.

    Such electronic devices include cameras such as video cameras and digital cameras, projectors, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, game machines, personal digital assistants (mobile computers, mobile phones or And an image reproducing apparatus (specifically, an apparatus having a display capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image). Examples thereof are shown in FIG.

    FIG. 32A illustrates a computer, which includes a main body 2101, a housing 2102, a display portion 2103, a keyboard 2104, an external connection port 2105, a pointing mouse 2106, and the like. In this computer, the display unit 2103 includes the configuration of the above embodiment. Thereby, the aperture ratio in the display unit 2103 of the computer can be improved. In addition, a computer that displays a high-quality image with high reliability can be provided.

    FIG. 32B shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2201, a housing 2202, a display portion A 2203, a display portion B 2204, and a recording medium (DVD etc.) reading portion 2205. , An operation key 2206, a speaker portion 2207, and the like. The display portion A2203 mainly displays image information, and the display portion B2204 mainly displays character information. In the image reproducing apparatus provided with this recording medium, the display portion A 2203 and the display portion B 2204 include the configuration of the above embodiment. Thereby, the aperture ratio in the display portion A2203 and the display portion B2204 of the image reproducing device provided with the recording medium can be improved. In addition, it is possible to provide an image reproduction device including a recording medium that displays a high-quality image with high reliability.

    FIG. 32C illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display portion 2304, operation switches 2305, an antenna 2306, and the like. In this cellular phone, the display unit 2304 includes the configuration of the above embodiment. Accordingly, the aperture ratio in the display portion 2304 of the mobile phone can be improved. In addition, a mobile phone that displays images with high reliability and high image quality can be provided.

    FIG. 32D illustrates a video camera, which includes a main body 2401, a display portion 2402, a housing 2403, an external connection port 2404, a remote control reception portion 2405, an image receiving portion 2406, a battery 2407, an audio input portion 2408, an eyepiece portion 2409, and an operation. Key 2410 and the like. In this video camera, the display unit 2402 includes the configuration of the above embodiment. Thereby, the aperture ratio in the display portion 2402 of the video camera can be improved. Further, it is possible to provide a video camera that displays a high-quality image with high reliability. This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 15)
According to the present invention, a semiconductor device that functions as a processor chip (also referred to as a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses, such as banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a processor chip 90 (see FIG. 30A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a processor chip 91 (see FIG. 30B). Personal belongings refer to bags, glasses, and the like, and can be provided with a processor chip 97 (see FIG. 30C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a processor chip 93 (see FIG. 30D). Books refer to books, books, and the like, and can be provided with a processor chip 94 (see FIG. 30E). A recording medium refers to DVD software, a video tape, or the like, and can be provided with a processor chip 95 (see FIG. 30F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a processor chip 96 (see FIG. 30G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  The semiconductor device of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

An example that can be applied to an object management or distribution system will be described with reference to FIG. Here, an example in which a processor chip is mounted on a product will be described. As shown in FIG. 31A, a processor chip 3402 is mounted on a beer bottle 3400 using a label 3401.

The processor chip 3402 records basic items such as the date of manufacture, the place of manufacture, and the materials used. Such basic matters do not need to be rewritten, and therefore may be recorded using a non-rewritable memory element (memory) such as a mask ROM or the memory element of the present invention. The basic items such as the date of manufacture, the place of manufacture, and the materials used are information that consumers want to obtain accurately when purchasing a product. By recording such information in a non-rewritable storage element, it is possible to prevent tampering of information and the like, so that reliable and accurate information can be transmitted to consumers. In addition, the processor chip 3402 records individual items such as the delivery destination and delivery date and time of each beer bottle. For example, as shown in FIG. 31B, when the beer bottle 3400 flows through the belt conveyor 3412 and passes through the writer device 3413, each delivery destination and delivery date and time can be recorded. Such individual items may be recorded using a rewritable and erasable memory such as EEROM.

When product information purchased from a delivery destination is transmitted to the distribution management center through the network, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date based on this product information, and the processor A system that records on a chip should be constructed.

Since delivery is performed for each case, a processor chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

By installing a processor chip in such a product that can record a plurality of delivery destinations, it is possible to reduce the time required for manual input and to reduce input errors caused by the time. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by implementing the processor, logistics management can be performed at low cost with few mistakes.

Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced. Such application items may be recorded using a rewritable and erasable memory such as EEROM. By mounting the processor chip in this manner, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

(Embodiment 16)
In this embodiment mode, other structures that can be applied to the light-emitting element of the present invention will be described with reference to FIGS.

A light-emitting element utilizing electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The former has an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, and the latter has an electroluminescent layer made of a thin film of luminescent material, but is accelerated by a high electric field. This is common in that it requires more electrons. Note that the obtained light emission mechanism includes donor-acceptor recombination light emission using a donor level and an acceptor level, and localized light emission using inner-shell electron transition of a metal ion. In general, the dispersion-type inorganic EL often has donor-acceptor recombination light emission, and the thin-film inorganic EL element often has localized light emission.

A light-emitting material that can be used in the present invention includes a base material and an impurity element serving as a light emission center. By changing the impurity element to be contained, light emission of various colors can be obtained. As a method for manufacturing the light-emitting material, various methods such as a solid phase method and a liquid phase method (coprecipitation method) can be used. Also, spray pyrolysis method, metathesis method, precursor thermal decomposition method, reverse micelle method, method combining these methods with high temperature firing, liquid phase method such as freeze-drying method, etc. can be used.

The solid phase method is a method in which a base material and an impurity element or a compound containing the impurity element are weighed, mixed in a mortar, heated and fired in an electric furnace, reacted, and the base material contains the impurity element. The firing temperature is preferably 700 to 1500 ° C. This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state. Although firing at a relatively high temperature is required, it is a simple method, so it has high productivity and is suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing the base material and an impurity element or a compound containing the impurity element are reacted in a solution, dried, and then fired. The particles of the luminescent material are uniformly distributed, and the reaction can proceed even at a low firing temperature with a small particle size.

As a base material used for the light-emitting material, sulfide, oxide, or nitride can be used. Examples of the sulfide include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), sulfide. Barium (BaS) or the like can be used. As the oxide, for example, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. As the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), and the like can also be used. Calcium sulfide-gallium sulfide (CaGa ₂ S ₄ ), strontium sulfide-gallium sulfide (SrGa ₂ S ₄ ), barium sulfide-gallium (BaGa). _It may be a ternary mixed crystal such as ₂ S ₄ ).

As emission centers of localized emission, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium (Pr) or the like can be used. Note that a halogen element such as fluorine (F) or chlorine (Cl) may be added as charge compensation.

On the other hand, a light-emitting material containing a first impurity element that forms a donor level and a second impurity element that forms an acceptor level can be used as the emission center of donor-acceptor recombination light emission. As the first impurity element, for example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used. For example, copper (Cu), silver (Ag), or the like can be used as the second impurity element.

In the case where a light-emitting material for donor-acceptor recombination light emission is synthesized using a solid-phase method, a base material, a first impurity element or a compound containing the first impurity element, a second impurity element, or a second impurity element Each compound containing an impurity element is weighed and mixed in a mortar, and then heated and fired in an electric furnace. As the base material, the above-described base material can be used, and examples of the first impurity element or the compound containing the first impurity element include fluorine (F), chlorine (Cl), and aluminum sulfide (Al ₂ S). ₃ ) or the like, and examples of the second impurity element or the compound containing the second impurity element include copper (Cu), silver (Ag), copper sulfide (Cu ₂ S), and silver sulfide (Ag). ₂ S) or the like can be used. The firing temperature is preferably 700 to 1500 ° C. This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state.

In addition, as an impurity element in the case of using a solid phase reaction, a compound including a first impurity element and a second impurity element may be used in combination. In this case, since the impurity element is easily diffused and the solid-phase reaction easily proceeds, a uniform light emitting material can be obtained. Further, since no extra impurity element is contained, a light-emitting material with high purity can be obtained. As the compound including the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), or the like can be used.

Note that the concentration of these impurity elements may be 0.01 to 10 atom% with respect to the base material, and is preferably in the range of 0.05 to 5 atom%.

In the case of a thin-film inorganic EL, the electroluminescent layer is a layer containing the above-described luminescent material, and is a physical vapor deposition method such as a resistance heating vapor deposition method, a vacuum vapor deposition method such as an electron beam vapor deposition (EB vapor deposition) method, or a sputtering method ( PVD), metal organic chemical vapor deposition (CVD), chemical vapor deposition (CVD) such as hydride transport low pressure CVD, atomic epitaxy (ALE), or the like.

34A to 34C illustrate an example of a thin-film inorganic EL element that can be used as a light-emitting element. 34A to 34C, the light-emitting element includes a first electrode layer 50, an electroluminescent layer 51, and a second electrode layer 53.

A light-emitting element illustrated in FIGS. 34B and 34C has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. The light-emitting element illustrated in FIG. 34B includes an insulating layer 54 between the first electrode layer 50 and the electroluminescent layer 52, and the light-emitting element illustrated in FIG. 34C includes the first electrode layer 50. And an electroluminescent layer 52, and an insulating layer 54 b is provided between the second electrode layer 53 and the electroluminescent layer 52. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Further, the insulating layer may be a single layer or a stacked layer including a plurality of layers.

In FIG. 34B, the insulating layer 54 is provided so as to be in contact with the first electrode layer 50, but the order of the insulating layer and the electroluminescent layer is reversed so as to be in contact with the second electrode layer 53. An insulating layer 54 may be provided.

In the case of a dispersion-type inorganic EL element, a particulate light emitting material is dispersed in a binder to form a film-like electroluminescent layer. When particles having a desired size cannot be obtained sufficiently by the method for manufacturing a light emitting material, the particles may be processed into particles by pulverization or the like in a mortar or the like. A binder is a substance for fixing a granular light emitting material in a dispersed state and maintaining the shape as an electroluminescent layer. The light emitting material is uniformly dispersed and fixed in the electroluminescent layer by the binder.

In the case of a dispersion-type inorganic EL element, the electroluminescent layer can be formed by a droplet discharge method capable of selectively forming an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as a spin coating method, A dipping method, a dispenser method, or the like can also be used. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm. In the electroluminescent layer including the light emitting material and the binder, the ratio of the light emitting material may be 50 wt% or more and 80 wt% or less.

FIGS. 35A to 35C illustrate an example of a dispersion-type inorganic EL element that can be used as a light-emitting element. The light-emitting element in FIG. 35A has a stacked structure of a first electrode layer 60, an electroluminescent layer 62, and a second electrode layer 63, and a light-emitting material 61 held in the electroluminescent layer 62 by a binder. Including.

As a binder that can be used in this embodiment mode, an insulating material can be used, an organic material or an inorganic material can be used, and a mixed material of an organic material and an inorganic material can be used. As the organic insulating material, a polymer having a relatively high dielectric constant such as a cyanoethyl cellulose resin, or a resin such as polyethylene, polypropylene, polystyrene resin, silicone resin, epoxy resin, or vinylidene fluoride can be used. Alternatively, a heat-resistant polymer such as aromatic polyamide, polybenzimidazole, or siloxane resin may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, phenol resins, novolac resins, acrylic resins, melamine resins, urethane resins, and oxazole resins (polybenzoxazole) may be used. The dielectric constant can be adjusted by appropriately mixing fine particles of high dielectric constant such as barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ) with these resins.

Examples of the inorganic insulating material contained in the binder include silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, or aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), BaTiO ₃ , SrTiO ₃ , lead titanate (PbTiO ₃ ), potassium niobate (KNbO ₃ ), lead niobate (PbNbO ₃ ), tantalum oxide (Ta ₂ O ₅ ), tantalum It is made of a material selected from substances including barium oxide (BaTa ₂ O ₆ ), lithium tantalate (LiTaO ₃ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and other inorganic insulating materials. be able to. By including an organic material with an inorganic material having a high dielectric constant (by addition or the like), the dielectric constant of the electroluminescent layer made of the light emitting material and the binder can be further controlled, and the dielectric constant can be further increased. . When a mixed layer of an inorganic material and an organic material is used for the binder and the dielectric constant is high, a larger charge can be induced in the light emitting material.

In the manufacturing process, the light-emitting material is dispersed in a solution containing a binder, but as a solvent for the solution containing the binder that can be used in this embodiment, a method of forming an electroluminescent layer by dissolving the binder material (various types) The wet process) and a solvent capable of producing a solution having a viscosity suitable for a desired film thickness may be selected as appropriate. For example, when a siloxane resin is used as a binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also referred to as PGMEA), 3-methoxy-3-methyl-1-butanol (also referred to as MMB). Etc. can be used.

35B and 35C each have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 35A. The light-emitting element illustrated in FIG. 35B includes an insulating layer 64 between the first electrode layer 60 and the electroluminescent layer 62, and the light-emitting element illustrated in FIG. 35C includes the first electrode layer 60. And an electroluminescent layer 62, and an insulating layer 64 b between the second electrode layer 63 and the electroluminescent layer 62. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Further, the insulating layer may be a single layer or a stacked layer including a plurality of layers.

35B, the insulating layer 64 is provided so as to be in contact with the first electrode layer 60. However, the order of the insulating layer and the electroluminescent layer is reversed so as to be in contact with the second electrode layer 63. An insulating layer 64 may be provided on the substrate.

The insulating layers such as the insulating layer 54 in FIG. 34 and the insulating layer 64 in FIG. 35 are not particularly limited, but preferably have high insulation resistance, a dense film quality, and a high dielectric constant. It is preferable. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), etc., a mixed film thereof, or two or more kinds thereof A laminated film can be used. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. The insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm.

The light-emitting element described in this embodiment mode can emit light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, but can operate in either DC driving or AC driving.

By using the present invention, a thin film transistor for driving the light-emitting element described in this embodiment can be manufactured with a simple method and high reliability. Therefore, a highly reliable display device can be manufactured through a simplified process. Therefore, a high-definition and high-quality display device can be manufactured at a low cost and with a high yield.

8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 3A and 3B each illustrate a structure of a light-emitting element that can be applied to the present invention. 8A and 8B illustrate a manufacturing process of a semiconductor device of the present invention. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. FIG. 24 is an equivalent circuit diagram of the display device described in FIG. 6A and 6B illustrate a display device of the present invention. The figure explaining the dripping injection method which can be applied to this invention. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 14 illustrates an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. FIG. 11 illustrates an electronic device to which the present invention is applied. 6A and 6B illustrate a display device of the present invention. 3A and 3B each illustrate a structure of a light-emitting element that can be applied to the present invention. 3A and 3B each illustrate a structure of a light-emitting element that can be applied to the present invention.

Claims (13)

Forming a first semiconductor layer and a second semiconductor layer;
Forming a gate insulating layer on the first semiconductor layer and the second semiconductor layer;
Forming a first conductive film on the gate insulating layer;
Forming a second conductive film on the first conductive film;
A first mask layer on the first semiconductor layer and the second semiconductor on the first conductive film and the second conductive film using an exposure mask that transmits light with a plurality of intensities Forming a second mask layer on the layer;
The first conductive layer and the second conductive layer are etched using the first mask layer and the second mask layer, and the first gate electrode layer and the second second conductive layer are etched by the first mask layer. Forming a third gate electrode layer and a fourth gate electrode layer from the gate electrode layer and the second mask layer;
The first semiconductor layer using the first gate electrode layer and the second gate electrode layer as a mask, and the second semiconductor layer using the third gate electrode layer and the fourth gate electrode layer as a mask. In addition, an impurity element imparting one conductivity type is added, a first low-concentration impurity region overlapping the first high-concentration impurity region and the first gate electrode layer in the first semiconductor layer, and a second Forming a second high-concentration impurity region and a second low-concentration impurity region overlapping with the third gate electrode layer in the semiconductor layer;
Forming a third mask layer on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer;
Using the third mask layer and the second gate electrode layer as a mask, a region overlapping with the first low-concentration impurity region in the first gate electrode layer is removed. Method. Forming a first semiconductor layer and a second semiconductor layer;
Forming a gate insulating layer on the first semiconductor layer and the second semiconductor layer;
Forming a first conductive film on the gate insulating layer;
Forming a second conductive film on the first conductive film;
A first mask layer on the first semiconductor layer and the second semiconductor layer on the first conductive film and the second conductive film using an exposure mask having a light intensity reduction function And forming a second mask layer on
The first conductive layer and the second conductive layer are etched using the first mask layer and the second mask layer, and the first gate electrode layer and the second second conductive layer are etched by the first mask layer. Forming a third gate electrode layer and a fourth gate electrode layer from the gate electrode layer and the second mask layer;
The first semiconductor layer using the first gate electrode layer and the second gate electrode layer as a mask, and the second semiconductor layer using the third gate electrode layer and the fourth gate electrode layer as a mask. In addition, an impurity element imparting one conductivity type is added, a first low-concentration impurity region overlapping the first high-concentration impurity region and the first gate electrode layer in the first semiconductor layer, and a second Forming a second high-concentration impurity region and a second low-concentration impurity region overlapping with the third gate electrode layer in the semiconductor layer;
Forming a third mask layer on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer;
Using the third mask layer and the second gate electrode layer as a mask, a region overlapping with the first low-concentration impurity region in the first gate electrode layer is removed. Method.     3. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity element imparting one conductivity type is an impurity element imparting n-type conductivity.     3. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity element imparting one conductivity type is an impurity element imparting p-type conductivity. Forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer;
Forming a gate insulating layer on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;
Forming a first conductive film on the gate insulating layer;
Forming a second conductive film on the first conductive film;
A first mask layer on the first semiconductor layer and the second semiconductor on the first conductive film and the second conductive film using an exposure mask that transmits light with a plurality of intensities. Forming a second mask layer on the layer, forming a third mask layer on the third semiconductor layer,
The first conductive layer and the second conductive layer are etched using the first mask layer, the second mask layer, and the third mask layer, and the first mask layer is used to etch the first conductive layer. A gate electrode layer and a second gate electrode layer; a third gate electrode layer and a fourth gate electrode layer by the second mask layer; and a fifth gate electrode layer and a sixth gate electrode by the third mask layer. Forming a gate electrode layer of
Forming a fourth mask layer on the third semiconductor layer, the fifth gate electrode layer, and the sixth gate electrode layer;
The third gate electrode layer and the fourth gate electrode layer are formed on the first semiconductor layer by using the fourth mask layer, the first gate electrode layer, and the second gate electrode layer as a mask. Is used as a mask, an impurity element imparting n-type conductivity is added to the second semiconductor layer, and the first n-type high concentration impurity region and the first gate electrode layer are overlapped with the first semiconductor layer. Forming a first n-type low concentration impurity region and a second n-type low concentration impurity region overlapping the second n-type high concentration impurity region and the third gate electrode layer in the second semiconductor layer; And
A fifth layer is formed on the first semiconductor layer, the second semiconductor layer, the first gate electrode layer, the second gate electrode layer, the third gate electrode layer, and the fourth gate electrode layer. Forming a mask layer,
An impurity element imparting p-type conductivity is added to the third semiconductor layer using the fifth mask layer, the fifth gate electrode layer, and the sixth gate electrode layer as a mask, and the third semiconductor layer Forming a p-type impurity region in
Forming a sixth mask layer on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer;
Using the sixth mask layer and the second gate electrode layer as a mask, a region overlapping with the first low-concentration impurity region in the first gate electrode layer is removed. Method.     6. The method for manufacturing a semiconductor device according to claim 5, wherein the third mask layer is formed using an exposure mask which transmits light with a plurality of intensities. Forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer;
Forming a gate insulating layer on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;
Forming a first conductive film on the gate insulating layer;
Forming a second conductive film on the first conductive film;
On the first conductive film and the second conductive film, using the exposure mask having a light intensity reducing function, the first mask layer on the first semiconductor layer and the second semiconductor layer And forming a second mask layer on the third semiconductor layer, and forming a third mask layer on the third semiconductor layer,
The first conductive layer and the second conductive layer are etched using the first mask layer, the second mask layer, and the third mask layer, and the first mask layer is used to etch the first conductive layer. A gate electrode layer and a second gate electrode layer; a third gate electrode layer and a fourth gate electrode layer by the second mask layer; and a fifth gate electrode layer and a sixth gate electrode by the third mask layer. Forming a gate electrode layer of
Forming a fourth mask layer on the third semiconductor layer, the fifth gate electrode layer, and the sixth gate electrode layer;
The third gate electrode layer and the fourth gate electrode layer are formed on the first semiconductor layer by using the fourth mask layer, the first gate electrode layer, and the second gate electrode layer as a mask. Is used as a mask, an impurity element imparting n-type conductivity is added to the second semiconductor layer, and the first n-type high concentration impurity region and the first gate electrode layer are overlapped with the first semiconductor layer. Forming a first n-type low concentration impurity region and a second n-type low concentration impurity region overlapping the second n-type high concentration impurity region and the third gate electrode layer in the second semiconductor layer; And
A fifth layer is formed on the first semiconductor layer, the second semiconductor layer, the first gate electrode layer, the second gate electrode layer, the third gate electrode layer, and the fourth gate electrode layer. Forming a mask layer,
An impurity element imparting p-type conductivity is added to the third semiconductor layer using the fifth mask layer, the fifth gate electrode layer, and the sixth gate electrode layer as a mask, and the third semiconductor layer Forming a p-type impurity region in
Forming a sixth mask layer on the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer;
Using the sixth mask layer and the second gate electrode layer as a mask, a region overlapping with the first low-concentration impurity region in the first gate electrode layer is removed. Method.     8. The method for manufacturing a semiconductor device according to claim 7, wherein the third mask layer is formed using an exposure mask having a light intensity reduction function.     9. The method for manufacturing a semiconductor device according to claim 5, wherein a high-concentration p-type impurity region and a low-concentration p-type impurity region are formed as the p-type impurity region.     10. The method for manufacturing a semiconductor device according to claim 5, wherein an upper end portion of the fifth gate electrode layer and a lower end portion of the sixth gate electrode layer coincide with each other.     10. The method for manufacturing a semiconductor device according to claim 9, wherein the low-concentration p-type impurity region is formed in the third semiconductor layer so as to overlap with the fifth gate electrode layer.     12. The method for manufacturing a semiconductor device according to claim 1, wherein the exposure mask uses a semi-transmissive film that reduces the intensity of light passing therethrough.     12. The method for manufacturing a semiconductor device according to claim 1, wherein the exposure mask uses a diffraction grating pattern having an opening and a non-opening portion having a width equal to or less than a resolution of an exposure apparatus.

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