JP2007059681A - Printed circuit board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed circuit board which can suppress the generation of an intermetallic compound in a solder-joined part and can suppress the melting out of Cu from a wiring circuit of the printed circuit board, and also to provide a method for manufacturing the circuit board. <P>SOLUTION: The printed circuit board comprises a wiring circuit which mainly constitutes of a substrate 100, a metal foil layer 101 formed on the substrate 100, a first plated layer 102 formed on the metal foil layer 101, a second plated layer 103 formed on the first plated layer 102, and an intermetallic compound layer 104 formed on the second plated layer 103 and containing Co and/or Ni by a predetermined amount. With such an arrangement, mechanical strength or thermal fatigue resistance at a solder-jointed part can be improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a printed circuit board provided with a wiring circuit, and more particularly to a printed circuit board capable of maintaining excellent mechanical strength and thermal strength at a solder joint in the wiring circuit and a method for manufacturing the same.

  An electronic circuit used for an electronic device is manufactured by soldering an electronic component to a wiring circuit on a printed board. Moreover, the wiring circuit in this conventional printed circuit board is mainly formed of Cu. The soldering of the electronic component to the printed board is performed by, for example, a wave soldering device.

  Conventionally, an alloy containing Sn and Pb has been used for solder. However, in recent years, Pb-free solder not containing Pb has been used for environmental considerations. Similarly, Pb-free plating has been used for plating. Against this background, mechanical properties and physical properties equivalent to those obtained when using an alloy containing Sn as a main component and containing Pb as opposed to Pb-free solder and plating containing Sn as the main component are used. Nature is required.

For example, in a Sn-Ag-Cu alloy, an alloy such as Sn-3.0 wt% Ag-0.5 wt% Cu is used in order to ensure mechanical properties such as solder strength and thermal fatigue strength. . In such a Sn—Ag—Cu alloy, Cu is concentrated in the front of solidification of (βSn) dendrite whose Cu solid solution amount is about 0.006 wt%, and (βSn) and η (Cu ₆ Sn ₅ : Sn 43.5-45.5 atomic%) eutectic structure, primary crystal η, or (βSn) and η eutectic structure. These intermetallic compounds, which are eutectic structures, have low mechanical strength and sometimes crack when cooled. Therefore, a solder whose thermal fatigue resistance is improved by suppressing the formation of these intermetallic compounds is disclosed (for example, see Patent Document 1).
JP 2002-307187 A

  However, when using a conventional solder as described above, for example, a solder made of an Sn—Ag—Cu alloy and mounting a surface mounting component or an insertion mounting component on a printed board, Cu is used for wiring on the printed board. Therefore, as described above, an intermetallic compound of Sn and Cu is generated at the interface of the joint, the mechanical strength at the joint is reduced, and there is a problem that a crack occurs when cooled.

  In addition, when soldering surface-mounted components and insertion-mounted components to a printed circuit board using a wave soldering device, etc., with the use of solder that suppresses the formation of these intermetallic compounds, Cu constituting the printed circuit board's wiring circuit is eluted. In some cases, it may be mixed in the molten solder bath of the wave soldering apparatus. As a result, the Cu concentration in the molten solder bath changes, and there is a problem that a uniform solder composition cannot be maintained.

  Therefore, the present invention has been made to solve the above-described problems, and can suppress the generation of intermetallic compounds at the solder joints and suppress the elution of Cu from the printed circuit board wiring circuit. An object of the present invention is to provide a printed circuit board that can be manufactured and a method for manufacturing the same.

  In order to achieve the above object, the printed circuit board of the present invention is a printed circuit board having a wiring circuit pattern, and the wiring circuit pattern is formed on the metal foil layer formed on the substrate and the metal foil layer. And an intermetallic compound layer formed on the plating layer.

According to this printed board, the formation of the intermetallic compound (for example, Cu ₆ Sn ₅ ) generated at the interface of the solder joint can be suppressed by forming the surface layer of the wiring circuit pattern with the intermetallic compound layer. it can. As a result, the mechanical strength and heat fatigue resistance of the solder joint formed between the intermetallic compound layer and the solder can be improved.

  The printed circuit board manufacturing method of the present invention includes a conductor pattern forming step of forming a predetermined conductor pattern by etching a metal foil layer formed on the substrate, and plating on the metal foil layer of the formed conductor pattern. A plating layer forming step of forming a layer; and an intermetallic compound layer forming step of forming an intermetallic compound layer on the plating layer.

According to this printed circuit board manufacturing method, the intermetallic compound layer can be formed on the plating layer in the intermetallic compound layer forming step. Thus, the intermetallic compound generated at the interface of the solder joint formed between the intermetallic compound layer and the solder (e.g., Cu 6 _{Sn 5)} can be suppressed generation of.

  In this invention, while being able to suppress the production | generation of the intermetallic compound in a solder joint part, the printed circuit board which can suppress elution of Cu from the wiring circuit of a printed circuit board, and its manufacturing method can be provided.

  Hereinafter, a printed circuit board 10 according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a printed circuit board 10 having a wiring circuit formed on one side. FIG. 2 is a cross-sectional view of the printed board 20 having through-holes and wiring circuits formed on both sides.

  As shown in FIG. 1 and FIG. 2, the printed circuit board 10, 20 has a wiring circuit section including a substrate 100, a metal foil layer 101 formed on the substrate 100, and a first layer formed on the metal foil layer 101. 1 plating layer 102, a second plating layer 103 formed on the first plating layer 102, and an intermetallic compound layer 104 formed on the second plating layer 103. ing. Further, in the printed circuit board 20 having the through hole 110, a third plating layer 111 is formed on the inner peripheral surface of the through hole 110 formed through the substrate 100, and on the third plating layer, A first plating layer 102 is formed.

  The substrate 100 is a base material having electrical insulation, and includes, for example, PET (polyethylene terephthalate), phenol resin, urea resin, melamine resin, polytetrafluoroethylene, polyethylene, polypropylene, polystyrene, polyethersulfone, polyphenylene sulfide. , PBT (polybutylene terephthalate), polyarylate, silicon resin, diallyl phthalate, polyimide and the like.

  The metal foil layer 101 is made of Cu (copper) foil or the like. The first plating layer 102 and the second plating layer 103 are formed by electrolytic Cu plating, and the thickness of the first plating layer 102 is formed to about 10 to 24 μm. When the plating layer is formed to be thicker, the second plating layer 103 is further formed on the first plating layer 102 by electrolytic Cu plating. In this case, the thickness of the plating layer, that is, the total thickness of the first plating layer 102 and the second plating layer 103 is about 20 to 40 μm. A plating layer having a thickness of about 70 to 80 μm can be formed by adjusting the time for performing electrolytic Cu plating. Accordingly, FIGS. 1 and 2 show an example of the printed circuit boards 10 and 20 having the second plating layer 103, but a configuration without the second plating layer 103 may be used. The third plating layer 111 is formed to a thickness of about 0.3 μm by electroless Cu plating.

  The intermetallic compound layer 104 is made of, for example, Sn—Cu—Co or Sn—Cu—Ni ternary intermetallic compound. The intermetallic compound layer 104 is formed on the second plating layer 103 by, for example, wet plating such as electroless plating or electrolytic plating, or dry plating such as vacuum deposition or sputtering. When the ternary intermetallic compound of Sn—Cu—Co is used, the atomic ratio of the intermetallic compound layer 104 is a substantially constant value of Sn: Cu: Co = 40.5: 57: 2.5. On the other hand, when composed of a ternary intermetallic compound of Sn—Cu—Ni, the atomic ratio of the intermetallic compound layer 104 is a substantially constant value of Sn: Cu: Ni = 40.5: 57: 2.5.

The content of Co (cobalt) or Ni (nickel) in the intermetallic compound layer 104 is 0.05 to 1.0% by weight. The content ratio of Co or Ni is set within this range when the content of Co or Ni is less than 0.05% by weight, the growth of the intermetallic compound (Cu ₆ Sn ₅ ) at the interface between the wiring circuit and the solder is suppressed. This is because the effect cannot be expected and the occurrence of cracks and peeling may be promoted. On the other hand, when the content exceeds 1.0% by weight, the wettability when forming the intermetallic compound layer 104 on the second plating layer 103 is deteriorated, and the thickness of the intermetallic compound layer 104 is not uniform. This is because it may lead to exposure of the image. In addition, you may contain both Co and Ni in the range of the above-mentioned content rate. A more preferable range of the content of Co and / or Ni is 0.3 to 0.7% by weight.

  Furthermore, the thickness of the intermetallic compound layer 104 is formed in the range of 0.5 to 2.0 μm. Here, the thickness of the intermetallic compound layer 104 is set within this range. It is difficult to manufacture the intermetallic compound layer 104 to be thinner than 0.5 μm, and when the thickness exceeds 2.0 μm, This is because the mechanical strength and heat fatigue resistance at the solder joints are reduced. A more preferable range of the thickness of the intermetallic compound layer 104 is 1 to 2 μm.

  Further, the intermetallic compound layer 104 may be formed with a concentration gradient composition so that the Co and / or Ni content increases toward the surface of the intermetallic compound layer 104. For example, assuming that the Co content is 0.5 at the center of the intermetallic compound layer 104 in the thickness direction, the surface of the intermetallic compound layer 104 has a concentration gradient composition so that the Co content becomes 1. Thus, the intermetallic compound layer 104 is formed. Note that the rate of change in the content ratio of Co and / or Ni toward the surface side of the intermetallic compound layer 104 is not limited to this, and Co and / or toward the surface side of the intermetallic compound layer 104 is not limited thereto. What is necessary is just to be comprised so that the content rate of Ni may become high gradually. Thus, when forming the intermetallic compound layer 104 having a concentration gradient composition, it is preferable to form the intermetallic compound layer 104 by vacuum deposition, sputtering, or the like.

  Next, a method for manufacturing a printed circuit board will be described with reference to FIGS. 3A to 3I. In addition, since the basic process is the same as the manufacturing method of the printed circuit board 10 and the printed circuit board 20, here, the manufacturing method of the printed circuit board 20 is mainly demonstrated.

  3A to 3I are diagrams schematically showing a cross section of the printed circuit board in each manufacturing process.

  First, the through hole 140 is formed at a predetermined position of the substrate 100 having the metal foil layer 101 formed on both sides (FIG. 3A).

  Subsequently, a resist 150 is printed on the metal foil layer 101 corresponding to the conductor pattern to be formed (FIG. 3B).

  Subsequently, an etching process is performed to form a conductor pattern (FIG. 3C), and the resist is washed and removed (FIG. 3D).

  Subsequently, electroless Cu plating is applied to the inner peripheral surface of the through hole 140 formed in the substrate 100 to form a third plating layer 111 (FIG. 3E).

  Subsequently, the electrically insulating film 151 is transferred to the gap between the metal foil layers 101 forming the conductor pattern, and the exposed surface of the substrate 100 is covered (FIG. 3F).

  Subsequently, electrolytic plating is performed to form the first plating layer 102 on the metal foil layer 101 and the third plating layer 111 that form the conductor pattern (FIG. 3G). When the plating layer is formed to be thicker, electrolytic plating is further performed to form the second plating layer 103 on the first plating layer 102 (FIG. 3G).

  Subsequently, an intermetallic compound layer 104 is formed on the second plating layer 103 by vacuum deposition (FIG. 3H). Note that, here, an example in which the intermetallic compound layer 104 is formed by vacuum deposition is shown, but the intermetallic compound layer 104 may be formed by sputtering or the like.

  Subsequently, the film 151 is removed to obtain the printed circuit board 20 including the wiring circuit having the intermetallic compound layer 104 formed on the surface (FIG. 3I).

  Here, in the vacuum deposition apparatus for forming the intermetallic compound layer 104, when the intermetallic compound layer 104 of Cu, Sn, and Co is formed, the vacuum deposition apparatus includes the evaporation source Cu, the evaporation source Sn, and the evaporation. A source Co is provided. Moreover, when forming the intermetallic compound layer 104 of Cu, Sn, and Ni, the vacuum evaporation apparatus includes an evaporation source Cu, an evaporation source Sn, and an evaporation source Ni. Furthermore, when forming the intermetallic compound layer 104 of Cu, Sn, Co, and Ni, the vacuum evaporation apparatus includes an evaporation source Cu, an evaporation source Sn, an evaporation source Co, and an evaporation source Ni. And the content rate of each component which comprises the intermetallic compound layer 104 can be adjusted by adjusting the evaporation amount from each evaporation source in a vacuum evaporation system. For example, when the Co content is increased toward the surface of the intermetallic compound layer 104, the amount of evaporation from each evaporation source is increased so that the Co concentration gradually increases in the intermetallic compound layer 104 formation step. Is adjusted.

  Furthermore, as described above, when the intermetallic compound layer 104 is formed with a concentration gradient composition so that the Co and / or Ni content increases toward the surface side of the intermetallic compound layer 104. In addition, the intermetallic compound layer 104 having a concentration gradient composition can be formed by adjusting the amount of evaporation from each evaporation source in the vacuum deposition apparatus.

  When the printed circuit board 10 having the wiring circuit formed on one side is manufactured, the through hole 140 in FIG. 3A in the method for manufacturing the printed circuit board 20 having the above-described through hole and the wiring circuit formed on both surfaces is formed. Except for the step of forming and the step of forming the plating layer 111 on the inner peripheral surface of the through hole 140 in FIG. 3E, the other manufacturing steps are the same as the steps for manufacturing the printed circuit board 20. Moreover, the process of manufacturing the printed circuit boards 10 and 20 described above is an example, and is not limited to this process.

According to the printed circuit boards 10 and 20 of one embodiment described above, the surface layer of the wiring circuit pattern is formed of an intermetallic compound layer of Cu, Sn, and Co, an intermetallic compound layer of Cu, Sn, and Ni, or Cu And an intermetallic compound (for example, Cu ₆ Sn ₅₎ formed at the interface of the solder joint formed between the intermetallic compound layer 104 and the solder. ) Can be suppressed. Thereby, the mechanical strength and heat fatigue resistance in the solder joint can be improved, and high reliability can be obtained in the solder joint.

  In addition, since the surface layer of the wiring circuit pattern is formed of the above-described intermetallic compound layer 104, elution of Cu from the wiring circuit pattern can be suppressed, for example, when soldering with a wave soldering apparatus. Therefore, the Cu concentration in the molten solder furnace of the wave soldering apparatus can be kept constant.

Further, the intermetallic compound layer 104 and the second metal layer 104 are formed so as to have a concentration gradient composition so that the Co and / or Ni content continuously increases toward the surface side of the intermetallic compound layer 104. In the surface side on which the mounted parts are soldered, the growth of intermetallic compounds such as Cu ₆ Sn _{5 at} the interface of the solder joints is improved by improving the adhesion with the plated layer 103 of 2 Can be suppressed.

(Example)
Next, specific examples of the present invention will be described.

(Peel strength test)
Here, by setting the content of Co and / or Ni in the intermetallic compound layer of the printed circuit board to the predetermined range (0.05 to 1% by weight) of the present invention, the intermetallic compound layer on the surface of the wiring circuit is obtained. It will be described based on the peel strength test results that the mechanical strength at the solder joint between 104 and the conductive member joined to the intermetallic compound layer 104 is improved. Furthermore, by setting the thickness of the intermetallic compound layer to a predetermined range (0.5 to 2 μm) of the present invention, the intermetallic compound layer 104 on the surface of the wiring circuit is bonded to the intermetallic compound layer 104. The fact that the mechanical strength at the solder joint with the conductive member is improved will be described based on the peel strength test result.

  First, the relationship between the Co content of the intermetallic compound layer and the peel strength will be described.

FIG. 4 is a diagram for explaining the outline of the peel strength test method. Here, external input / output leads 202 disposed on four sides of a QFP (Quad Flat Package) 201 are soldered to a wiring circuit 200 having an intermetallic compound layer formed on the surface. Here, the intermetallic compound layer was formed of an intermetallic compound made of (Cu ₆ Sn ₅ ) Co, and the thickness thereof was 1 μm. Moreover, the solder of the component which consists of Sn-3.0Ag-0.5Cu was used for the solder, and the thickness of the solder in a solder joint part was 20 micrometers. The lead 202 is a member having 240 pins made of an alloy of iron and Ni.

  Then, as shown in FIG. 4, the substrate 203 is inclined 45 degrees, the hook 204 is inserted between the lead 202 and the substrate 203, the hook 204 is hooked on the lead 202, and the hook 204 is moved upward at a speed of 10 mm / min. And peel strength test was conducted. The peel strength test was performed based on the provisions of JIS Z 3198 for QFP.

  FIG. 5 shows the relationship between the Co content (% by weight) and the peel strength (N) as a test result. FIG. 5 also shows a range of data variation when the same test is performed a plurality of times.

  As shown in FIG. 5, it was found that the peel strength showed a high value when the Co content was in the range of 0.05 to 1% by weight. Furthermore, even within this range, it was found that the Co content was particularly high in the range of 0.3 to 0.7% by weight.

  From the above peel strength test results, it was revealed that high peel strength can be obtained in the range of Co content (0.05 to 1% by weight) of the present invention.

  Although the relationship between the Co content and the peel strength is shown here, the relationship between the Ni content and the peel strength is the same. Further, when both Co and Ni were contained, high peel strength was obtained in the content range of the present invention (0.05 to 1% by weight).

  Next, the relationship between the thickness of the intermetallic compound layer and the peel strength will be described.

Here, the intermetallic compound layer was formed of an intermetallic compound made of (Cu ₆ Sn ₅ ) Co, and the peel strength was measured by changing the thickness of the intermetallic compound. In addition, the structure of the other measurement object and the test method of the peel strength test are the same as those described in relation to the Co content of the intermetallic compound layer and the peel strength.

  FIG. 6 shows the relationship between the thickness (μm) of the intermetallic compound layer and the peel strength (N) as a test result. FIG. 6 also shows the range of data variation when the same test is performed a plurality of times.

  As shown in FIG. 6, it was found that the peel strength showed a high value when the thickness of the intermetallic compound layer was in the range of 0.5 to 2 μm. Furthermore, even within this range, it was found that the intermetallic compound layer showed a particularly high value in the range of 1 to 2 μm.

  From the peel strength test results regarding the thickness of the intermetallic compound layer described above, it was revealed that high peel strength can be obtained in the thickness range (0.5 to 2 μm) of the intermetallic compound layer of the present invention.

  Here, the relationship between the thickness of the intermetallic compound layer containing Co and the peel strength is shown, but the relationship between the thickness of the intermetallic compound layer containing Ni and the peel strength is the same. Further, when both Co and Ni were contained, high peel strength was obtained in the thickness range (0.5 to 2 μm) of the intermetallic compound layer of the present invention.

(Measurement of growth rate of intermetallic compounds)
Here, the surface of the wiring circuit in a printed circuit board, (Cu 6 _{Sn 5)} intermetallic compound layer made of, or (Cu 6 _Sn 5) form an intermetallic compound layer made of _Co, respectively intermetallic compound layer The solder which consists of Sn-3.0Ag-0.5Cu was joined. And the growth rate of the intermetallic compound layer when the printed circuit board with which solder was joined was exposed to each temperature condition was measured.

  The thickness of the intermetallic compound layer before the start of measurement was 1 μm for both. Moreover, the thickness of the solder in a solder joint part was 100 micrometers in both. The temperature conditions were 70, 100, 135, and 170 ° C.

FIG. 7 shows the relationship between the measurement result time (days) and the intermetallic compound layer thickness (μm). Also shows in (Cu 6 Sn ₅₎ intermetallic compound layer made of _Co, only the measurement results at a temperature of 170 ° C. intermetallic compound layer is most growing conditions in FIG.

As shown in FIG. 7, in the case of an intermetallic compound layer made of (Cu ₆ Sn ₅ ), it is found that the thickness of the intermetallic compound layer increases with time, and the increase rate becomes more remarkable as the temperature increases. It was. On the other hand, in the case of an intermetallic compound layer such as (Cu ₆ Sn ₅ ) Co, it was found that there was almost no increase in the size of the intermetallic compound layer with time.

  Here, the intermetallic compound has, for example, a hardness that is about twice that of Sn. And generally, when hardness increases, it tends to become brittle, and further, the tendency becomes remarkable as the thickness of the intermetallic compound increases. However, as is apparent from the above results, by containing Co at a predetermined content rate, growth of the intermetallic compound layer can be suppressed, and mechanical characteristics and the like at the solder joint can be improved. It became clear that it was possible.

  Here, the relationship between the time and the thickness of the intermetallic compound layer in the intermetallic compound layer containing Co is shown. However, the time and the thickness of the intermetallic compound layer in the intermetallic compound layer containing Ni are shown. The relationship was similar. Further, in the intermetallic compound layer containing both Co and Ni, the relationship between the time and the thickness of the intermetallic compound layer was the same.

(Measurement of Cu elution amount from wiring circuit)
When a surface mounting component or an insertion mounting component is soldered to a printed circuit board with a wave soldering device or the like, Cu constituting the wiring circuit of the printed circuit board may be eluted and mixed into the molten solder tank of the wave soldering device.

Here, a printed circuit board in which the wiring circuit is made of Cu, and a printed circuit board in which an intermetallic compound layer made of (Cu ₆ Sn ₅ ) Co is formed on the surface of the wiring circuit are used. The temporal change of the Cu content in the molten solder bath when a predetermined surface-mounted component or the like was soldered was measured. In addition, the alloy which consists of Sn-3.0Ag-0.5Cu was used for the solder, and the content rate of Cu in the initial state in a molten solder tank was 0.5 weight%. The temperature of the solder in the molten solder bath was 250 ° C.

FIG. 8 shows the relationship between the measurement result time (month) and the Cu content (wt%). As shown in FIG. 8, when using the wiring circuit which consists of Cu, it turned out that the content rate of Cu increases with time. On the other hand, when using a wiring circuit having an intermetallic compound layer made of (Cu ₆ Sn ₅ ) Co on the surface, the Cu content slightly increases for one month after use, but the increase in Cu content thereafter I found almost no. Furthermore, the increase in the Cu content in one month from the use in the case of using a wiring circuit having an intermetallic compound layer made of (Cu ₆ Sn ₅ ) Co on the surface is about 20%, whereas from Cu From the use in the case of using a wiring circuit, the increase in the Cu content in one month was about 70%, and it was found that the increase was large.

  From the measurement results described above, it was found that by containing Co at a predetermined content, elution of Cu from the wiring circuit of the printed circuit board can be suppressed. Accordingly, even when a wave soldering device is used as a soldering device, for example, the Cu concentration in the molten solder bath of the wave soldering device can be maintained almost constant, so that a uniform solder composition can be maintained. I knew it was possible.

  In addition, although it showed here that it was effective in suppressing the elution of Cu from the wiring circuit of a printed circuit board about the wiring circuit which has the intermetallic compound layer containing Co on the surface, the intermetallic compound containing Ni Similar results were obtained for a wiring circuit having a surface or an intermetallic compound layer containing both Co and Ni on the surface.

Sectional drawing of the printed circuit board in which the wiring circuit was formed in the single side | surface of one embodiment of this invention. Sectional drawing of the printed circuit board which has the through hole of one embodiment of this invention, and the wiring circuit was formed in both surfaces. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The cross section of the printed circuit board for demonstrating the manufacturing process of a printed circuit board. The figure for demonstrating the outline | summary of the peel strength test method. The figure which shows the relationship between the content rate of Co, and peel strength. The figure which shows the relationship between the thickness of an intermetallic compound layer, and peel strength. The figure which shows the relationship between time and the thickness of an intermetallic compound layer. The figure which shows the relationship between time and the content rate of Cu.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Printed circuit board, 100 ... Board | substrate, 101 ... Metal foil layer, 102 ... 1st plating layer, 103 ... 2nd plating layer, 104 ... Intermetallic compound layer.

Claims (9)

A printed circuit board provided with a wiring circuit pattern,
The wiring circuit pattern is
A metal foil layer formed on the substrate;
A plating layer formed on the metal foil layer;
A printed circuit board comprising: an intermetallic compound layer formed on the plating layer.   The printed circuit board according to claim 1, wherein the intermetallic compound layer includes Cu and a component that forms an intermetallic compound with Cu.   The intermetallic compound layer is formed of an intermetallic compound of Cu, Sn, and Co, an intermetallic compound of Cu, Sn, and Ni, or an intermetallic compound of Cu, Sn, Co, and Ni. The printed circuit board according to claim 1 or 2.   The printed circuit board according to claim 3, wherein the content of Co and / or Ni in the intermetallic compound is 0.05 wt% to 1 wt%.   The printed circuit board according to claim 1, wherein the intermetallic compound layer has a thickness of 0.5 μm to 2 μm.   The printed circuit board according to claim 1, wherein the intermetallic compound layer is formed by wet plating or dry plating.   The said intermetallic compound layer is formed by the density | concentration gradient composition which raised the content rate of Co and / or Ni toward the surface side of the said intermetallic compound layer, The Claim 3 or 4 characterized by the above-mentioned. Printed board. A conductor pattern forming step of forming a predetermined conductor pattern by etching the metal foil layer formed on the substrate;
A plating layer forming step of forming a plating layer on the metal foil layer of the formed conductor pattern;
And a step of forming an intermetallic compound layer on the plating layer. In the intermetallic compound layer forming step,
The intermetallic compound layer is formed with a concentration gradient composition in which the content of Co and / or Ni contained in the intermetallic compound layer is increased toward the surface side of the intermetallic compound layer. Item 9. A printed circuit board manufacturing method according to Item 8.

Images