JP2007055203A - Image formation apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform buffer control so that efficiency in the use of a memory of an image formation apparatus is improved. <P>SOLUTION: Image processing is divided into RIP processing, UCR processing, and compression processing. The processing is shared and performed by processors 13 and 14. In that course, each processing is conducted while processing data is passed via a data buffer 24. The processing states of the processors 13 and 14 are stored in a control information table 23. A control unit 20 controls allocation of the processing to the processors in accordance with the processing states of the processors 13 and 14. Furthermore, in the data buffer 24, a plurality of buffers having optimal sizes corresponding to the divided processing are prepared. A memory control unit 21 references the control information table 23 and allocates the buffers corresponding to the processing performed by the processors 13 and 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus that prints a color image, such as a color printer or a multi-function peripheral, and more particularly to an image forming apparatus configured to perform printing processing of image data in a shared manner by a plurality of processors. It is.

  In recent years, most documents are processed by an information processing apparatus such as a personal computer and output using a printer. In order to print a large amount of documents at high speed, it is required to improve the printing speed of the printer.

  On the other hand, color images are easily processed in personal computers, and the number of documents including color images is increasing. Moreover, the resolution of the image is greatly improved, and the amount of image data transmitted for printing from a personal computer is enormous.

  Therefore, in order to improve the printing speed of the printer, it is essential to improve the processing speed of image data in the printer. Therefore, for example, as disclosed in the following Patent Document 1 (Japanese Patent Laid-Open No. 2000-198240), there is a technique for greatly improving the processing speed by performing printing processing of image data in a shared manner by a plurality of processors. Has been developed.

  That is, in the printer shown in Patent Document 1, two CPUs are provided as image processing processors, and the first processor includes processing for receiving print data and processing for converting print data into an intermediate code and outputting it. And the second processor controls the process of generating drawing data from the intermediate code, the process of color conversion, and the process of binarization, thereby speeding up the process.

  However, if the image processing is divided into two stages, pre-processing and post-processing, and each of them is shared by the first and second processors, the processing load on both processors is not necessarily equal depending on the contents of the image data. However, there is a problem in that the standby state of one processor continues for a long time, resulting in waste and a decrease in overall efficiency. For example, even if the processing of the second processor is finished, if the processing of the first processor is continuing, the second processor has to wait until the processing of the first processor is finished, and the time Is wasted.

  A technique for solving such inconvenience is disclosed in the following Patent Document 2 (Japanese Patent Application Laid-Open No. 2004-326307). That is, in the printer shown in Patent Document 2, a control information table for storing the processing status of each processor is provided, and the processing allocation of each processor is controlled with reference to the control information table, so that each processor is efficiently It can be used. In this image forming apparatus, image processing is divided into a plurality of step processes such as bit map processing and bit map data compression processing for each color of cyan, magenta, yellow, and black. Processing is assigned to each processor.

  In this way, for example, if the processing of the second processor is ongoing when the processing of the first processor is finished, the first processor continues the processing of the next stage of the data that has been processed. Do it. Further, if the processing of the first processor is continued when the processing of the second processor is finished, the second processor does not wait for the end of the processing of the first processor, and does not wait for the completion of the processing of the first processor. As in the first stage processing, the processing share of each processor can be dynamically changed, and efficient operation can be achieved. As a result, the processing speed of image data can be further improved.

  When executing such processing, each processor stores the processed data in the data buffer when one step of processing is completed, and the processor that takes over the processing reads the data from the data buffer and performs the next step. Execute the process. At this time, buffer allocation is performed as follows.

  That is, FIG. 4 is an explanatory diagram of a conventional data buffer. A plurality of buffers having a fixed size are prepared in the RAM of the image forming apparatus. When buffers are needed during the processing of the first and second processors, the buffers are sequentially allocated. Then, the buffer that has been used after the data transfer is completed is reassigned for subsequent processing, and used sequentially.

JP 2000-198240 A JP 2004-326307 A

  However, the buffer management in the conventional image forming apparatus has a problem that the use efficiency of the memory is deteriorated because the buffer area is secured more than necessary in the memory.

  That is, the buffer size required for processing performed by the processor of the image forming apparatus varies greatly depending on the content of the processing. For example, in the bitmap processing, the processed data becomes large and a buffer for storing the data needs to have a large size, but in the compression processing, the processed data becomes small and the buffer size for storing the data is small. I'm sorry.

  However, as shown in FIG. 4, the buffers prepared in the RAM are all of a fixed size, and since the vacant ones are allocated in order, each buffer is also used for bitmap processing. It is also necessary to support compression processing, and eventually the buffer size is set in accordance with processing that requires the maximum size. For this reason, even a process that does not require a large size buffer, such as a compression process, is wasted because a large size buffer is used, and the use efficiency of the memory is deteriorated.

  The present invention has been made in view of such problems, and an object of the present invention is to realize buffer management that improves the use efficiency of the memory of the image forming apparatus.

In order to solve the above-mentioned problem, the invention according to claim 1 of the present application is
In an image forming apparatus configured to share and execute image processing from reception of image data to printing by a plurality of processors,
The image processing from reception of image data to printing is divided into a plurality of step processes, each of which is assigned to one of the step processes, and processed while delivering the processing data via a buffer. A processor;
A control unit for controlling the allocation of the buffer,
As the buffer, a plurality of buffers each having an optimal size are provided corresponding to the step processing, and the control unit assigns a buffer corresponding to the step processing executed by each processor to each processor. It is characterized by that.

According to a second aspect of the present invention, in the image forming apparatus according to the first aspect,
A control information table for storing the processing status of each processor is provided, and the control unit refers to the control information table, controls processing allocation to each processor according to the processing status of each processor, and It is characterized by controlling buffer allocation.

The image forming apparatus of the present invention has the following effects.
That is, in the invention according to claim 1, a plurality of buffers having an optimum size are provided for each stage process, and the control unit assigns a buffer corresponding to the stage process executed by the processor to each processor. Therefore, the use efficiency of the memory can be improved by minimizing the buffer size to be used.

  According to a second aspect of the present invention, in the image forming apparatus according to the first aspect, a control information table for storing the processing status of each processor is provided, and the control unit refers to the control information table, The processing allocation to each processor is controlled according to the processing status of each processor, and the buffer allocation is controlled. As a result, the processing status of each processor can be monitored to dynamically change the processing share of each processor, and a buffer corresponding to the stage processing executed by each processor can be created using the control information table. It becomes possible to assign.

  Hereinafter, specific examples of the present invention will be described in detail with reference to examples and drawings. FIG. 1 is a block diagram showing a schematic configuration of an image forming apparatus according to the present invention. FIG. 2 shows the contents of the control information table. FIG. 3 is an explanatory diagram of the data buffer.

  FIG. 1 is a block diagram showing a schematic configuration of an image forming apparatus according to the present invention. The image forming apparatus 10 is converted by a reception buffer 11 that receives image data from a client PC, a display list conversion unit 12 that converts image data received by the reception buffer 11 into a display list, and a display list conversion unit 12. The display list data is provided with a first processor (CPU 1) 13 and a second processor (CPU 2) 14 that perform processing to be described later and generate final print data, and a printing mechanism unit 30. . The first processor 13 and the second processor 14 have cache memories 15 and 16, respectively, and data generated after processing is temporarily held in the cache memories 15 and 16.

  When the image data is color image data, the processing by the first processor 13 and the second processor 14 is a RIP (Raster Image) that expands display list data into bitmap data for each color of cyan, magenta, yellow, and black. Processor) and UCR (Under Color Removal) processing that replaces the point where three colors overlap with black in cyan, magenta, and yellow bitmap data developed by RIP processing and RIP processing, and RIP The process is divided into a plurality of stage processes, such as a compression process for compressing bitmap data for each color obtained by the process and the UCR process. The compressed image data created by the series of processes is decompressed and sent to the printing mechanism unit 30 for printing.

  Each of the first processor 13 and the second processor 14 has a function of executing the RIP processing, UCR processing, and compression processing, and the processors 13 and 14 share the processing and perform parallel processing. Has been made.

  The image data is divided into an appropriate size after being received by the reception buffer 11 or after being converted into a display list by the display list conversion unit 12. For example, a first processor is provided for each divided data unit. The RIP process is performed at 13, and the UCR process and the compression process are performed by the second processor 14. That is, the first processor 13 and the second processor 14 advance parallel processing in a pipeline manner in units of divided data. When one page of image data processed by the two processors 13 and 14 is prepared in this way, it is sent to the printing mechanism unit 30 and printing is performed. As a division unit, for example, image data for one page may be divided into a plurality of data, or image data for a plurality of pages may be divided into data for one page.

  In order to control the processing of the first processor 13 and the second processor 14, the image forming apparatus 10 is provided with a control unit 20 and a memory 22 shared by the two processors 13 and 14. The memory 22 is constituted by SDRAM or the like, and a control information table 23, a data buffer 24, and a page buffer 25 are provided therein, and these are managed by the memory control unit 21 in the control unit 20. The control information table 23 is used by the control unit 20 to monitor the processing status of the processors 13 and 14, and the image data processed by the processors 13 and 14, and the processors 13 and 14 perform RIP processing and UCR processing. It is stored which stage of the compression process is executed and whether the process is completed.

  Then, the control unit 20 refers to the control information table 23 to check the processing status of the two processors 13 and 14 and assigns processing to each of the processors 13 and 14.

  The data buffer 24 buffers data obtained as a result of processing by one processor. When a series of stage processing is not completed, this data can be transferred to the other processor. The page buffer 25 buffers data that has undergone a series of step processing by any processor. When a series of step processing is completed for each of the divided image data, the page buffer 25 is buffered in the page buffer 25 and 1 When the image data for the page is ready, it is sent to the printing mechanism unit 30 and printing processing is performed.

  FIG. 2 is a diagram showing the contents of the control information table 23, and the control unit 20 controls the processing in the two processors 13 and 14 while rewriting the flag of the control information table 23. As shown in FIG. 2, the control information table 23 stores the data ID of each divided image data obtained by dividing the image data to be processed in the vertical direction, and the first processor 13 and the second processor in the horizontal direction. 14, fields for storing the processing status of each RIP processing, UCR processing, and compression processing are provided.

In the case of FIG. 2, first, RIP processing of the cyan image data D _1C of the first divided image is executed by the first processor 13 (processing field is “on”), and the processing is completed (completion field is “1”). ") and, RIP processing is executed processing of the image data D _1M for magenta of the first divided image in the second processor 14 has been completed. Subsequently, the RIP processing of the yellow image data _D1Y of the first divided image is executed by the first processor 13, the processing is completed, and the black image data D of the first divided image is processed by the second processor 14. _{The 1K} RIP process is executed and the process is completed.

When the cyan, magenta, and yellow RIP processes are completed, the UCR process becomes possible. Therefore, the UCR process is executed by the first processor 13 and the process is completed. Thereafter, compression processing of the image data D _1C , D _1M , D _1Y , and D _1K for cyan, magenta, yellow, and black is sequentially performed by the second processor 14 and the first processor 13, and currently the data D _1K This indicates that the compression process is being executed.

  As described above, the processing unit 20 assigns processing to the two processors 13 and 14 while referring to the control information table 23, but the control unit 20 refers to the control information table 23 as well. However, the data buffer 24 that temporarily holds the data generated by the processing by the processors 13 and 14 is also assigned. Next, allocation of the data buffer 24 will be described.

  FIG. 3 is an explanatory diagram of the data buffer 24. The data buffer 24 prepares a plurality of buffers having optimum sizes for each stage of RIP processing, UCR processing, and compression processing, as RIP buffers, UCR buffers, and compression buffers, respectively. The RIP buffers B1 to B4 store the maximum data generated by RIP processing the divided data if the image forming apparatus processes the image data for one page into a plurality of data, for example. Similarly, the UCR buffer B5 has a size capable of storing the maximum data generated by the UCR process, and the compression buffers B6 to B9 have a size capable of storing the maximum data generated by the compression process. To do. Further, an MCB (Memory Control Block) is provided at the head of each buffer, and a flag indicating whether or not the buffer is in use is provided therein.

Then, the memory control unit 21 of the control unit 20 refers to the control information table 23 and allocates a buffer corresponding to the stage process executed by each of the processors 13 and 14. For example, in the case of FIG. 2, first, the control unit 20 assigns RIP processing of the data D _1C and D _1M to the first and second processors 13 and 14, and the memory control unit 21 performs the processing for the processing. , RIP buffers B1 and B2 are allocated in order from the RIP buffers B1 to B4. Thereafter, when the RIP process of each processor 13 and 14 is completed, the RIP process of the data D _1Y and D _1K is subsequently assigned to the first and second processors 13 and 14, and the memory control unit 21 RIP buffers B3 and B4 are allocated for this purpose.

After that, when the RIP processing of the data D _1Y by the processor 13 is completed, bitmap data of cyan, magenta, and yellow is generated and the UCR processing can be executed. Therefore, the control unit 20 subsequently performs UCR processing on the processor 13. The allocation and memory control unit 21 allocates the UCR buffer B5 for the processing. On the other hand, the compression processing of cyan, magenta, yellow, and black bitmap data generated by the RIP processing is sequentially assigned to the second processor 14 and the first processor 13, and the compression buffers B6 to B6 are used for the processing. B9 is assigned sequentially.

  As described above, in the image forming apparatus of the present invention, a plurality of buffers each having an optimum size for each process are prepared as the data buffer 24, and the memory control unit 21 refers to the control information table 23 to each processor. A buffer corresponding to the processing executed by 13 and 14 is assigned. As a result, a large buffer is allocated to a process that requires a large buffer, such as RIP processing, and a small buffer is allocated to a process that does not require a large buffer, such as compression processing. This eliminates waste and improves the memory usage efficiency.

1 is a block diagram showing a schematic configuration of an image forming apparatus according to the present invention. It is a figure which shows the content of the control information table. It is explanatory drawing of a data buffer. It is explanatory drawing of the data buffer of a conventional system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Image forming apparatus 11 ... Reception buffer 12 ... Display list conversion part 13 ... 1st processor 14 ... 2nd processor 4
15, 16... Cache memory 20... Control unit 21... Memory control unit 22... Memory 23... Control information table 24. .... Page buffer 30 ... Printing mechanism

Claims (2)

In an image forming apparatus configured to share and execute image processing from reception of image data to printing by a plurality of processors,
The image processing from reception of image data to printing is divided into a plurality of step processes, each of which is assigned to one of the step processes, and processed while delivering the processing data via a buffer. A processor;
A control unit for controlling the allocation of the buffer,
As the buffer, a plurality of buffers each having an optimal size are provided corresponding to the step processing, and the control unit assigns a buffer corresponding to the step processing executed by each processor to each processor. An image forming apparatus.   A control information table for storing the processing status of each processor is provided, and the control unit refers to the control information table, controls processing allocation to each processor according to the processing status of each processor, and 2. The image forming apparatus according to claim 1, wherein buffer allocation is controlled.

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