JP2007054404A - Pachinko game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pachinko game machine in a new structure capable of suitably coping even with sudden CPU reset and performing restoration securing reliability of internal information. <P>SOLUTION: The pachinko game machine comprises: updating means (S57, S60, S77, S102, S112 and S122) for storing the internal information in a plurality of storage areas 126 and 128 when the content of the internal information is changed; propriety decision means (S45, S46 and S47) for deciding whether or not the internal information of correct content is stored by using the majority decision of the content stored in the plurality of storage areas 126 and 128; and restoration means (S49) for adopting the internal information of the correct content and restarting game control when it is decided that the internal information of the correct content is stored by the propriety decision means (S45, S46 and S47). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a pachinko machine that performs operation control of game operations and game effects according to internal information stored in a main body.

  Conventionally, pachinko machines have been provided with electronic control circuits for controlling the payout of prize balls, counting the number of rounds when a big win is made, opening / closing of a big prize opening, and the like. Furthermore, the pachinko machine is usually adapted to perform various effects such as sound and light according to the game situation. For example, various effect displays are performed on the symbol display device, and the symbol display device. In addition to the display content, voice, music, and sound effects are emitted from the speaker, and a lamp provided on the housing of the pachinko machine is lit or flashing. In order to perform such control, the pachinko machine is provided with many electronic control circuits.

  Such an electronic control circuit stops operating when power supply to the pachinko machine is interrupted due to a short circuit in the hall or a power failure. Even if the power supply is resumed, the internal information stored in each electronic control circuit returns to the initial state, so that the internal information related to the gaming state up to that point is discarded. In particular, if a power failure or the like occurs during a jackpot game and information regarding the jackpot game is discarded, there is a possibility that a big disadvantage may be given to the player.

  In order to deal with such a problem, for example, in Patent Document 1 and Patent Document 2, a power supply is stopped by providing a standby power source in an electronic control circuit that controls main operations such as paying out a prize ball and jackpot game. In this case, the checksum of the internal information is created and stored using the power of the standby power supply, and when the power supply is resumed, the checksum value is compared with the internal information, and the internal information is stored correctly. When it is determined that the game state has been determined, a pachinko machine is disclosed that uses the internal information to continue the gaming state before the power failure.

  However, such a method is effective for an electronic control circuit that controls a game effect such as a symbol display device or a sound, even if it can be suitably used for an electronic control circuit that controls the basic part of the game operation. It was not possible to get a good effect.

  In other words, it is not common to provide a spare power source or the like as described above in an electronic control circuit that controls game effects that are not directly related to the player's profit. Therefore, most of these electronic control circuits stop operating at the same time as the power supply is cut off. Therefore, it is impossible to create a checksum after the power supply is cut off.

  Also, even if a spare power supply is provided to generate a checksum, the data size of internal information used for game effects, particularly symbol display effects, is larger than the internal information used to control the basic part of the game operation. It is much bigger. Generating such a checksum of large-capacity data has a high possibility of causing an error, and is not preferable from the viewpoint of the time required for generating the checksum and the time required for checking at the time of recovery.

  In addition, with the recent advancement of the contents of effects, the clock frequency of arithmetic devices used in electronic control circuits that control game effects is increasing, and malfunctions due to noise are likely to occur. And since many devices such as ball transport devices are installed on the back side of the island facilities where pachinko machines are installed, unexpected CPU resets occur due to static electricity and noise such as radio waves generated from those devices. There is a high risk of doing so.

  Such an unexpected CPU reset can occur regardless of the presence or absence of a standby power supply. For example, even if the checksum of the storage area at the time of noise reset is generated, it is doubtful whether an arithmetic unit that must be reset due to noise can generate a checksum correctly. It is difficult to think that a good effect can be obtained.

  When such an unexpected CPU reset occurs, the internal information up to that point is discarded as in the case of a power failure or the like, and recovery is performed with incorrect internal information stored. Thereby, there exists a possibility that operation | movement of a game effect may not be performed normally. For example, when a CPU reset occurs only in the electronic control circuit related to the effect display with the other circuits operating normally, nothing is displayed on the screen even though the game continues. There is also a possibility that problems such as no longer appearing or the timing of effect display differ.

Japanese Patent No. 3380498 JP 2003-190425 A

  Here, the present invention has been made in the background as described above, and the problem to be solved is a recovery that ensures the reliability of the internal information by suitably dealing with an unexpected CPU reset. It is to provide a pachinko machine having a novel structure that can be performed.

  Hereinafter, embodiments of the present invention made to solve the above-described problems will be described. In addition, the component employ | adopted in each aspect as described below is employable by arbitrary combinations as much as possible. In addition, aspects or technical features of the present invention are not limited to those described below, but are based on the entire specification and drawings, or based on the inventive concept that can be grasped by those skilled in the art from these descriptions. It should be understood that

(Aspect 1 of the present invention)
That is, according to aspect 1 of the present invention, in a pachinko machine that performs game control according to internal information, (a) storage means including a plurality of storage areas corresponding to the same internal information, and (b) content of the internal information Updating means for storing the changed internal information in the plurality of storage areas when the game control changes, and (c) storing the correct internal information when the game control is resumed after the game control is interrupted. Correctness determination means for determining whether or not the content is stored using a majority vote of the contents stored in the plurality of storage areas, and (d) when the correctness determination means determines that the internal information having the correct contents is stored. Is provided with a recovery means that employs the correct internal information and resumes game control.

  In the pachinko machine structured according to this aspect, a plurality of storage areas for storing one piece of internal information are provided and stored in the storage area at the timing when the content of the internal information changes. As a result, internal information is not saved under an abnormal condition in which a power failure or noise reset occurs, but is saved under normal operating conditions. Even information can be stored in a storage area with high reliability while suppressing occurrence of errors. Further, since the internal information is stored in advance before the CPU reset occurs at the timing when the content of the internal information changes, it is possible to effectively cope with an unexpected CPU reset.

  In this aspect, in particular, by providing correct / incorrect determination means for determining the correctness of the contents of the internal information by using a majority vote at the time of recovery, and a recovery means for restoring information according to the determination result of the correct / incorrect determination means. The internal information is adopted only when the information stored in the storage area is likely to be correct information. As a result, it is possible to effectively avoid recovery using incorrect information after the CPU reset, and to perform recovery with high reliability.

  The internal information stored in the storage area and used for game control includes not only information directly related to the game state, such as the number of times of opening / closing the big winning opening in the jackpot game, the number of payout of the winning ball, but also a symbol display It also includes information related to effects such as moving image data and audio information displayed on the apparatus, and the present invention can be more effectively employed for information with a large data size related to such effects.

  And as internal information used as the object of correct / incorrect determination, for example, the state before the CPU reset such as the identification number of the currently performed effect mode or the identification number of the moving image data displayed on the symbol display device is restored. The information necessary for this is selected as appropriate, and is further selected in consideration of the degree of restoration after the CPU reset. Specifically, for example, in order to continuously display the display content of the symbol display device after the CPU reset from the time point when it was displayed until then, in addition to the identification number of the video data being displayed, the current display Even the progress information such as the frame number and playback time in the middle will be subject to the correctness judgment, but for the first purpose of avoiding that nothing is displayed on the display screen, the display contents will be slightly returned. In the case of allowance, only the identification number of the moving image data may be set as the correctness determination target, and the moving image data may be displayed again from the beginning when the CPU is reset. It is appropriately selected according to the degree of restoration and the like. As the storage means for storing internal information, a single storage device may be provided with a plurality of storage areas, or may be configured using a plurality of storage devices. Furthermore, the updating means for storing the internal information in the storage area only needs to store information having substantially the same content as the target internal information. For example, information unnecessary for control is removed from the internal information. You may memorize it.

(Aspect 2 of the present invention)
Aspect 2 of the present invention stores, in the pachinko machine according to aspect 1, a plurality of non-inverted information storage areas that store the same contents as the internal information as the storage areas and inverted information obtained by inverting the contents of the internal information. A plurality of inversion information storage areas, and the correctness determination means determines whether the contents of the internal information stored in the storage area are correct or not by majority of the contents stored in the non-inversion information storage area and the inversion information storage area. It is characterized by determining using the majority vote of the content memorize | stored in this.

  In the pachinko machine structured according to this aspect, in addition to the non-inverted information storage area that stores the same contents as the internal information, the correctness of the stored contents of the inverted information storage area that stores the inverted information obtained by inverting the contents of the internal information Can be backed up with higher reliability. In this aspect, the same content as the internal information stored in the non-inverted information storage area may be stored as long as the same content is stored in a range necessary for recovery, and exactly the same content is stored. There is no need to be.

(Aspect 3 of the present invention)
According to aspect 3 of the present invention, in the pachinko machine according to aspect 2, the correctness determination unit determines whether the content of the internal information stored in the storage area is correct or not and the content stored in the non-inverted information storage area. The determination is made using an addition value with the content stored in the inversion information storage area.

  In the pachinko machine structured according to this aspect, a more reliable backup can be performed by matching the storage contents of the non-inversion information storage area and the storage contents of the inversion information storage area.

  In addition, as the determination using the added value of the content stored in the non-inverted information storage area and the content stored in the inverted information storage area, all combinations of a plurality of non-inverted information storage areas and a plurality of inverted information storage areas It may be determined by taking the addition value for the above and by determining the majority of those addition values, or by previously obtaining the majority result of the non-inverted information storage area and the majority result of the inverted information storage area, You may determine the addition value of a majority decision result.

(Aspect 4 of the present invention)
According to aspect 4 of the present invention, in the pachinko machine according to any one of aspects 1 to 3, a game control operation is controlled based on a main control board that controls a game operation and a signal received from the main control board. A sub-control board, and the sub-control board includes the storage unit, the update unit, the correctness determination unit, and the recovery unit.

  In the pachinko machine structured according to this aspect, the load on the main board can be reduced by performing control related to the game effect on the sub-control board. Then, by providing storage means, update means, correctness determination means, and recovery means for the sub-control board that requires a large storage capacity in order to perform control related to the game effect, a sudden CPU reset occurs on the sub-control board. Even if it occurs, it can be avoided that the production stops.

  Such a sub-control board widely includes an electronic control circuit that performs control relating to game effects, and includes, for example, a board for controlling the symbol display device, a board for controlling sound and lamps, and the like. Also, as a board for integrating these symbol display devices, boards for controlling sounds and lamps, an integrated board for receiving signals from the main board and controlling the operation of each control board based on such signals may be provided. good. Further, for example, an appropriate combination mode can be adopted, for example, the symbol display device and the substrate for controlling the sound are constituted by one substrate.

  As is clear from the above description, in the pachinko machine structured according to the present invention, large-capacity stored information related to game effects and the like is effectively backed up, and an unexpected CPU reset due to noise factors such as static electricity and radio waves. Even if it occurs, it is possible to perform highly reliable recovery.

  Hereinafter, in order to clarify the present invention more specifically, embodiments of the present invention will be described in detail with reference to the drawings.

  First, FIG. 1 shows a pachinko machine 10 as an embodiment of the present invention. In the pachinko machine 10, a vertical rectangular inner frame 14 for setting various game components is assembled on the front side of the opening of the outer frame 12 that forms the outer shell of the machine body so as to be opened and closed and detachable. On the front side of the middle frame 14, a glass frame 18 that holds a glass plate for see-through protection of the game board 16 that is detachably attached to the middle frame 14, and a dish plate 22 that includes an upper dish 20. Are assembled in a state that can be opened and closed, and the casing of the pachinko machine 10 is configured including the outer frame 12, the inner frame 14, the glass frame 18, and the dish plate 22. And LED21, 21 as a lamp for electrical decoration is provided in the appropriate several places of the glass frame 18. As shown in FIG. In addition, the upper plate 20 has, for example, an operation button 23 as an operation device that receives an operation from the player in order to change an aspect of the effect display based on the operation of the player, and a plurality of effects for performing an effect by sound. Speakers 25 are provided. Further, a lower plate 24 is provided below the upper plate 20, and a firing handle 26 is provided to the right of the lower plate 24. Then, when the player rotates the launch lever 28 that is attached to the launch handle 26 so as to be able to rotate, the game ball stored in the upper plate 20 passes through a ball feed mechanism (not shown). After being sent to a launching device (not shown), it is fired toward a game area 30 formed on the game board 16.

  The game board 16 includes a game board having a synthetic resin sheet attached to the surface thereof, and is substantially at the center of a substantially circular game area 30 surrounded by a guide rail 32 fixed to the surface side of the game board. Is attached with a liquid crystal display 34 as a symbol display device. The left special symbol 36a, the middle special symbol 36b, and the right special symbol 36c as the changing symbols are displayed on the liquid crystal display 34 so as to change and stop.

  In the present embodiment, these three special symbols 36a, 36b, and 36c are all configured by numerical symbols from “0” to “9”, and “0” is displayed from the upper side to the lower side of the liquid crystal display 34. "→" 9 "" 0 "... Are scrolled and displayed in a loop. In the present embodiment, the three special symbols 36a, 36b and 36c are started to display all at once, while the left special symbol 36a, the right special symbol 36c and the middle special symbol 36b are in this order. Is stopped and displayed. Note that the variable display in the present embodiment refers to a display state in which a special symbol is recognized as if it is not fixed, for example, a state in which the special symbol is scroll-displayed. A state in which the symbols of the left special symbol 36a, the middle special symbol 36b, and the right special symbol 36c are determined and recognized is set as a stop symbol. In addition, the stop display in the present embodiment refers to a display state that is recognized as if the stop symbol of the special symbol is confirmed, for example, a state in which the scroll display of the special symbol ends and the stop symbol is stopped at the stop symbol. Say.

  Further, a starting port 38 is provided below the liquid crystal display 34, and the starting port 38 is configured by a proximity switch on a ball path for discharging a game ball that has entered the ball to the back side of the game board 16. A starting port switch 40 (see FIG. 3) is provided as a starting ball entering detecting means. When a game ball enters the start port 38, the start port switch 40 detects the passage of the game ball and outputs an electric signal (detection signal) as a start signal. Based on the start signal, After the determination, the variable display of the plurality of special symbols 36a, 36b, 36c according to the contents determined based on the determination result is started.

  On the other hand, a plurality of holding LEDs 42 (four in the present embodiment) are provided above the liquid crystal display 34. While the special symbols 36a, 36b, and 36c are variably displayed, one hold LED 42 is turned on every time a game ball enters the start port 38, and the special symbols 36a, 36b, and 36c are displayed. The player is notified that the variable display is held for a predetermined number of times (maximum of four in this embodiment).

  Furthermore, a large winning port 44 as a variable winning port is provided below the start port 38. A door 46 that opens and closes when the special symbols 36a, 36b, and 36c are all stopped and displayed on the liquid crystal display 34, that is, when a big hit occurs, is provided at the entrance of the big winning opening 44. Yes. The door 46 is maintained in a closed state in a normal gaming state and is in a disadvantageous state for the player. On the other hand, when a big hit occurs, the door 46 is opened and closed so as to be in a big hit state advantageous to the player. It has become.

  In FIG. 2, the back surface of the pachinko machine 10 is shown. On the back side of the pachinko machine 10, there is a main control board storage case 48 for storing a main control circuit 56 (see FIG. 3) for controlling game operations, and a display control circuit 60 for controlling the operation of the liquid crystal display 34 (see FIG. 3). From the display control board storage case 50 for storing the sound, the sound control circuit 62 (see FIG. 3) for controlling the operation of the speaker 25, the light control circuit 64 (see FIG. 3) for controlling the operation of the LED 21, and the main control circuit 56. An effect control board storage case 52 for storing an effect control circuit 58 (see FIG. 3) that comprehensively controls the effect operation of the pachinko machine 10 based on the signal, obtains power from the outside, and supplies power to each control board and drive device A power supply unit 54 and the like are distributed and supplied.

  In such a pachinko machine 10, when a player inserts a game ball into the upper plate 20 and rotates the launch lever 28, the game ball is launched into the game area 30 and hit against the game area 30. It falls so as to hit the obstacle nail (not shown).

  Here, when the game ball enters the start port 38, the liquid crystal display 34 starts the variable display of the three special symbols 36a, 36b, 36c. When a predetermined time elapses from the start of the variable display, the left special symbol 36a and the right special symbol 36c are temporarily stopped in this order, and the presence or absence of the reach state is determined depending on the symbol combination of the left special symbol 36a and the right special symbol 36c. Informed. The reach state means a state in which the left special symbol 36a and the right special symbol 36c are stopped at the same symbol. Further, in such a temporary stop, the left special symbol 36a and the right special symbol 36c are displayed so as to be shaken in the liquid crystal display 34, and it is visually expressed that there is a possibility that the display is changed again.

  When a predetermined time further elapses, the middle special symbol 36b is temporarily stopped following the left special symbol 36a and the right special symbol 36c. Then, the left special symbol 36a, the right special symbol 36c, and the middle special symbol 36b are set as stationary symbols that are stationary along one horizontal line. The player is notified of the big hit state or the missed state by the combination of the stopped symbols of these three special symbols 36a, 36b, 36c.

  In the present embodiment, the specific symbol combination that becomes the jackpot symbol is a combination in which all of the three special symbols 36a, 36b, and 36c are arranged in the same symbol. On the other hand, the other symbol combinations are out-of-band symbols. Further, as for the off symbol, the symbol combination in which the left special symbol 36a and the right special symbol 36c are the same, and the middle special symbol 36b is different is the reach off symbol, and the left special symbol 36a and the right special symbol 36c are different. Is considered to be a completely off-line design. The determination result of the start signal triggered by the ball entering the start port 38 is referred to as a jackpot symbol, and the determination result that is a completely missed symbol is completely defeated, and the reach is a miss symbol. The determination result is referred to as “reach”.

  Then, when the three special symbols 36a, 36b, and 36c are stopped at the jackpot symbol, the jackpot game is started. The jackpot game is to allow a game ball to be awarded to the big prize opening 44 by opening the door 46 of the big prize opening 44, and the player does not have a normal gaming state, that is, a big hit. More prize balls can be obtained than prize balls that can be obtained in the game state. The door 46 is held in an open state until a number condition for winning a predetermined number (for example, 10) of game balls or a time condition for elapse of a predetermined time (for example, 27 seconds) is satisfied.

  Such a single opening operation of the door 46 is referred to as a jackpot round. When the above condition is satisfied, the door 46 is closed and a predetermined interval between rounds (in this embodiment, The next jackpot round is started after 2 seconds). Note that the number of jackpot rounds performed in one jackpot game is determined in advance, and in this embodiment, 15 jackpot rounds are performed in one jackpot game.

  Next, FIG. 3 shows a circuit configuration of the pachinko machine 10. The main control circuit 56 constituting the main control board is a circuit that controls main operations of the game, such as determining the winning of the game ball won to the start opening 38 and controlling the big hit game. The main control circuit 56 is connected to an effect control circuit 58 that comprehensively controls the effect operation of the pachinko machine 10, and the display that controls the operation of the liquid crystal display 34 with respect to the effect control circuit 58. A control circuit 60, a sound control circuit 62 that controls the operation of the speaker 25, and a light control circuit 64 that controls the operation of the LED 21 are connected. The display control circuit 60, the sound control circuit 62, the light control circuit 64, and the effect control circuit 58 that controls them constitute a sub-control board, and the effect operation of the pachinko machine 10 is controlled by these sub-control boards. As a result, the load on the main control circuit 56 is reduced.

  FIG. 4 shows the configuration of the main control circuit 56. The main control circuit 56 includes a main control CPU 66 that controls the entire main control circuit 56, a main control ROM 68 that stores control programs and data necessary for various control processes, and storage means that stores various process data and the like. Are provided with a main control RAM 70, an input circuit 72, and an output circuit 74, which are connected to each other by a bus. The input circuit 72 is a circuit that converts an analog signal or the like input from the outside into a digital signal and outputs the digital signal. The output circuit 74 is a circuit that converts various data generated by the main control CPU 66 into serial data and outputs the data. The main control CPU 66 is connected to a clock circuit 76 that outputs a clock signal. The main control CPU 66 has noise countermeasures such as a shield to prevent the CPU reset from being unexpectedly caused by noise such as static electricity.

  The input circuit 72 of the main control circuit 56 is provided at the start port 38 and is provided at the start port switch 40 for detecting a ball entering the start port 38 and the big prize port 44, and enters the big prize port 44. A count switch 78 for detecting the number of balls and a RAM erase switch 79 provided on the back surface of the pachinko machine 10 are connected. The output circuit 74 of the main control circuit 56 controls the light emission of the solenoid drive circuit 82 for driving the door opening / closing solenoid 80 for opening and closing the door 46 closing the entrance of the big prize opening 44 and the holding LED 42. An effect control circuit 58 that controls the effect operation based on signals from the hold LED control circuit 84 and the main control circuit 56 is connected.

  The main control RAM 70 is provided with the following flags and storage areas as internal information. In the following description, the flag is a value that stores either “0” or “1”, and “set the flag to ON” means that “1” is stored in the flag. “Turn flag off” indicates that “0” is stored in the flag. Further, even if each flag is set to ON after being already set to ON, or is set to OFF after being already set to OFF, the value of the flag does not reverse.

The backup flag 86 is a flag indicating whether or not the backup process at the time of power-off is completed. When the backup flag 86 is “ON”, the backup process at the time of power-off is completed and “OFF” is displayed. Indicates that the backup processing at the time of power-off was not completed.
The checksum storage area 88 is an area for storing a checksum of the contents stored in the main control RAM 70.

  As shown in FIG. 5, the main control circuit 56 has a backup power supply circuit 90 that supplies a spare power for generating a checksum of the main control RAM 70 when the power is cut off due to a power failure or the like. It is configured.

  The backup power supply circuit 90 includes a power supply monitoring IC 92 that monitors a voltage for operating the main control CPU 66, the main control RAM 70, and the like, and a large-capacitance capacitor 96 as a backup power supply that is detachably connected via the connector 100. A backup power supply board 98 is included.

  The power monitoring IC 92 monitors the operating voltage applied between the terminal GND and the terminal Vcc of the main control RAM 70, and when the operating voltage becomes a predetermined voltage value (for example, 5V) or less, A voltage drop signal indicating that the voltage has dropped from the monitoring output terminal K to the main control CPU 66 is transmitted.

  The large-capacitance capacitor 96 is in a charged state when an operating voltage is supplied through the diode 102 in a normal state. When the operating voltage applied between the terminal Vcc and the terminal GND of the main control RAM 70 decreases, the charge stored in the large-capacitance capacitor 96 causes the terminal Vcc and the terminal GND of the main control RAM 70 to be connected. In the meantime, backup power is supplied.

  Next, FIG. 6 shows the configuration of the effect control circuit 58. The effect control circuit 58 stores an effect control CPU 104 that controls the entire effect control circuit 58, the control program related to the effect operation, data necessary for various control processes, and the like in substantially the same manner as the main control circuit 56 described above. An effect control ROM 106, an effect control RAM 108 constituting a storage means for storing various processing data, an input circuit 110, and an output circuit 112 are connected to each other by a bus. A clock circuit 114 is connected to the effect control CPU 104.

  An operation switch 116 for detecting that the main control circuit 56 and the operation button 23 are pressed is connected to the input circuit 110 of the effect control circuit 58. On the other hand, a display control circuit 60, a sound control circuit 62, and a light control circuit 64 are connected to the output circuit 112. As a result, the effect control circuit 58 transmits a control signal corresponding to the signal received from the main control circuit 56 to each of the display control circuit 60, the sound control circuit 62, and the light control circuit 64, thereby producing the effect of the pachinko machine 10. The operation can be controlled centrally.

The effect control RAM 108 is provided with the following flags and storage areas as internal information.
The button input flag 120 is a flag indicating whether or not the operation button 23 has been pressed. When the button input flag 120 is “ON”, it indicates that the operation button 23 has been pressed. It indicates that the button 23 is not pressed.
The command storage area 122 stores a command transmitted from the main control circuit 56.
In the effect pattern storage area 123, an effect pattern selected based on a command transmitted from the main control circuit 56 is stored.

  Further, the effect control RAM 108 is provided with a backup data storage area 124 as a storage area. The backup data storage area 124 is for storing information necessary for restoring the previous state when a CPU reset occurs in the effect control circuit 58. FIG. 7 shows an outline of the backup data storage area 124. The backup data storage area 124 includes three non-inverted information storage areas of a copy data storage area “A” 126a, a copy data storage area “B” 126b, and a copy data storage area “C” 126c as non-inverted information storage areas. Inverted data storage areas “a” 128a, inverted data storage areas “b” 128b, and inverted data storage areas “c” 128c are provided as inverted information storage areas. Note that an odd number of copy data storage areas 126 and inverted data storage areas 128 are prepared for each piece of internal information, and in this embodiment, three are provided. The copy data storage areas 126a, 126b, and 126c store the same contents as the contents stored in the storage target storage area 130 in which internal information to be stored in the effect control RAM 108 is stored. On the other hand, in the inverted data storage areas 128a, 128b, and 128c, inverted data obtained by inverting the bit string of the information stored in the copy data storage areas 126a, 126b, and 126c is stored. The storage target storage area 130 constitutes a storage area used for game control, and the storage target storage area 130, the copy data storage area 126 as a non-inverted information storage area, and the inverted data as an inverted information storage area A plurality of storage areas for storing internal information are configured including the storage area 128.

  In the effect control circuit 58 according to the present embodiment, the button input flag 120, the command storage area 122, and the effect pattern storage area 123 are set as the storage target storage area 130, and the backup data storage area 124 has a button input. Selected based on the value of the flag 120, the command transmitted from the main control circuit 56 stored in the command storage area 122, and the command transmitted from the main control circuit 56 stored in the effect pattern storage area 123 The production pattern is stored as the storage target information.

  Next, FIG. 8 shows a configuration of the display control circuit 60. The display control circuit 60 is substantially the same as the effect control circuit 58 described above, a display control CPU 132 that controls the entire display control circuit 60, a control program for controlling the operation of the display control CPU 132, and an effect control circuit 58. Display control ROM 134 storing control data such as a selection table for selecting image data corresponding to the command received from the display, display control RAM 136 constituting storage means for storing various processing data, VDP 138, input The circuit 140 and the output circuit 142 are connected to each other via a bus, and a clock circuit 144 is connected to the display control CPU 132. Further, a VROM 146 and a VRAM 148 are connected to the VDP 138. Image data is stored in the VROM 146, and the VDP 138 reads out image data stored in the VROM 146 based on a control signal from the display control CPU 132 and generates a display signal using the VRAM 148 as a work area. .

  An effect control circuit 58 is connected to the input circuit 140 of the display control circuit 60. On the other hand, the output circuit 142 is connected to a liquid crystal display circuit 150 that displays an image corresponding to the received display signal on the liquid crystal display 34. The display signal generated by the VDP 138 is output to the liquid crystal display circuit 150 via the output circuit 142, and the liquid crystal display circuit 150 that has received the display signal displays an image corresponding to the display signal on the liquid crystal display. 34 is displayed.

The display control RAM 136 is provided with the following flags and storage areas as internal information.
The button input flag 154 is a flag indicating whether or not the operation button 23 has been pressed. When the button input flag 154 is “ON”, it indicates that the operation button 23 has been pressed. It indicates that the button 23 is not pressed. Note that the content of the button input flag 154 in the display control circuit 60 is set based on information related to button input included in the command transmitted from the effect control circuit 58.
The command storage area 156 stores a command transmitted based on the effect pattern selected by the effect control circuit 58.
The backup data storage area 158 has substantially the same structure as the backup data storage area 124 provided in the effect control circuit 58 described above, and constitutes a storage area in the display control circuit 60. In the display control circuit 60 according to the present embodiment, a command transmitted based on the value of the button input flag 154 and the effect pattern selected by the effect control circuit 58 stored in the command storage area 156 is backed up as save target information. It is stored in the data storage area 158.

  Next, FIG. 9 shows a configuration of the sound control circuit 62. The sound control circuit 62 is substantially the same as the effect control circuit 58 described above, a sound control CPU 160 for controlling the entire sound control circuit 62, a control program for controlling the operation of the sound control CPU 160, and an effect control circuit 58. A sound control ROM 162 storing control data such as a selection table for selecting sound data corresponding to the command received from the sound, a sound control RAM 164 constituting a storage means for storing various processing data, and the input circuit 166. The output circuit 168 is connected to each other by a bus, and a clock circuit 170 is connected to the sound control CPU 160.

  An effect control circuit 58 is connected to the input circuit 166 of the sound control circuit 62. On the other hand, a speaker circuit 172 is connected to the output circuit 168. The speaker circuit 172 outputs sound from the speakers 25 and 25 provided in various places of the pachinko machine 10 based on the sound signal from the sound control CPU 160.

The sound control RAM 164 is provided with the following flags and storage areas as internal information.
The command storage area 178 stores a command transmitted based on the effect pattern selected by the effect control circuit 58.
The backup data storage area 180 has substantially the same structure as the backup data storage area 124 provided in the effect control circuit 58 described above, and constitutes a storage area in the sound control circuit 62. In the sound control circuit 62 in the present embodiment, a command selected based on the effect pattern selected by the effect control circuit 58 and stored in the command storage area 178 is stored in the backup data storage area 180 as storage target information. It is like that.

  Next, FIG. 10 shows a configuration of the light control circuit 64. The light control circuit 64 is substantially similar to the effect control circuit 58 described above, a light control CPU 182 that controls the entire light control circuit 64, a control program for controlling the operation of the light control CPU 182, and the effect control circuit 58. A light control ROM 184 storing control data such as a selection table for selecting a lighting pattern corresponding to the command received from the light, a light control RAM 186 constituting storage means for storing various processing data and the like, and an input circuit 188. The output circuit 190 is connected to each other by a bus, and a clock circuit 192 is connected to the light control CPU 182.

  An effect control circuit 58 is connected to the input circuit 188 of the light control circuit 64. On the other hand, the LED circuit 194 is connected to the output circuit 190. The LED circuit 194 controls the blinking operation of the LEDs 21 and 21 as lamps provided in various places of the pachinko machine 10 based on the light signal from the light control CPU 182.

The light control RAM 186 is provided with the following flags and storage areas as internal information.
The command storage area 198 stores a command transmitted based on the effect pattern selected by the effect control circuit 58.
The backup data storage area 200 has substantially the same structure as the backup data storage area 124 provided in the effect control circuit 58 described above, and constitutes a storage area in the light control circuit 64. In the light control circuit 64 in the present embodiment, the command transmitted based on the effect pattern selected by the effect control circuit 58 and stored in the command storage area 198 is stored in the backup data storage area 200 as storage target information. It is like that.

  Next, FIG. 11 shows processing when the main control CPU 66 in the main control circuit 56 is turned on. First, when power is turned on to the pachinko machine 10 and the main control CPU 66 is activated, interrupt processing is prohibited in step (hereinafter referred to as S) 1. In S2, the main control RAM 70 is made accessible.

  Subsequently, in S3, the main control CPU 66 determines whether or not the RAM erase switch 79 is turned on. If the RAM erase switch 79 is turned on (S3: YES), the processing after S11 is performed. The main control RAM 70 is initialized. On the other hand, if the RAM erase switch 79 is not ON (S3: NO), the main control CPU 66 determines whether or not the backup flag 86 is ON in S4, and if the backup flag 86 is not ON (S4: NO). In step S11 and subsequent steps, the main control RAM 70 is initialized because the backup at the time of the previous power shutdown is not normally performed.

  If the backup flag 86 is ON (S4: YES), the main control CPU 66 generates a checksum of the data stored in the main control RAM 70 in S5, and the value stored in the checksum storage area 88. Collate. If the collation result is invalid (S5: NO), the processing after S11 is performed and the main control RAM 70 is initialized. On the other hand, if the result of collation between the checksum stored in the checksum storage area 88 and the stored contents of the main control RAM 70 is correct (S5: YES), the main control CPU 66 is saved in the main control RAM 70 in S6. Each control information that has been stored is returned to the register. In step S7, the main control CPU 66 transmits a power recovery command indicating that the content is backed up when the power is turned off to the effect control circuit 58. In step S8, the main control CPU 66 returns the backup flag 86 to OFF.

  Subsequently, in S9 and S10, the main control CPU 66 performs processing from the address when the power is turned off after setting the interrupt permission when the interrupt is permitted when the power is turned off last time. As described above, the state before the power interruption is restored.

  On the other hand, when the RAM erase switch 79 is not ON (S3: NO), the backup flag 86 is not ON (S4: NO), or the checksum verification result is incorrect (S5: NO), the main control CPU 66 In S11, the contents of the main control RAM 70 are cleared and the main control RAM 70 is initialized. As a result, the backup flag 86 is also turned OFF. Subsequently, the main control CPU 66 transmits a power-on command indicating that power is turned on and initialization is performed to the effect control circuit 58 in S12, and then sets an interrupt permission in S13. Then, the power-on process is terminated.

  Next, FIG. 12 shows processing when the main control CPU 66 in the main control circuit 56 is powered off. First, when the supply of power to the pachinko machine 10 is interrupted by a power failure or a power switch operation, the main control CPU 66 receives a voltage drop signal from the power monitoring IC 92 (see FIG. 5) (S15).

  When detecting a voltage drop (S15: YES), the main control CPU 66 saves the register value in S16 and saves the current interrupt processing state in S17. Subsequently, the main control CPU 66 generates a checksum from the contents stored in the main control RAM 70 in S18 and stores it in the checksum storage area 88, and then turns on the backup flag 86 in S19. In step S20, the main control CPU 66 prohibits access to the main control RAM 70, thereby waiting for the power supply to stop while maintaining the contents of the main control RAM 70.

  In this way, when the voltage supplied to the pachinko machine 10 drops due to a power failure or the like, the main control circuit 56 uses the charge of the large-capacitance capacitor 96 as a reserve power supply to check the contents stored in the main control RAM 70. You can create a thumb. At the time of recovery, the checksum is compared with the contents stored in the main control RAM 70, so that the previous state when the power is turned off can be restored.

  Next, FIG. 13 shows an outline of processing performed by the effect control CPU 104 of the effect control circuit 58. First, when the power is turned on or a CPU reset caused by noise or the like occurs, the effect control CPU 104 executes a reset process (S30) as an initialization process. After the reset process (S30) is completed, the command reception process (S31) and the button input process (S32) are repeated by an interrupt process every predetermined period (for example, 4 ms) generated by the clock circuit 114. . Since the production control circuit 58 does not have a reserve power supply unlike the main control circuit 56, no special processing is performed when the power supply is cut off, and the supply of voltage is cut off. At the same time, the operation is stopped.

  FIG. 14 shows the contents of the reset process (S30). The effect control CPU 104 first checks whether or not a command has been received from the main control circuit 56 in S35 when the power is turned on or reset due to noise or the like.

  When the command is received from the main control circuit 56 (S35: YES), the reset control is not the effect control circuit 58 alone but the pachinko machine 10 as a whole. In S36, it is determined whether or not the received command is a power-on command indicating that initialization is performed when the pachinko machine 10 is powered on.

  When the received command is not a power-on command (S36: NO), the received command is a power-recovery command indicating that the backed-up contents are restored when the power is turned off. The control information is restored based on the information included in the received power recovery command, and the power recovery command is transmitted to the display control circuit 60, the sound control circuit 62, and the light control circuit 64 in S38. The power recovery command transmitted from the effect control circuit 58 may be transmitted as it is from the main control circuit 56, or based on the power recovery command received from the main control circuit 56, A power recovery command newly generated by the effect control circuit 58 may be transmitted.

  On the other hand, when the received command is a power-on command (S36: YES), the effect control CPU 104 clears the effect control RAM 108 in S39, and in S40, the display control circuit 60, the sound control circuit 62, A power-on command is transmitted to the light control circuit 64. As the power-on command transmitted from the effect control circuit 58, the power-on command received from the main control circuit 56 may be transmitted as it is, or the power-on command received from the main control circuit 56. The power-on command newly generated by the effect control circuit 58 may be transmitted based on the above.

  On the other hand, if the command is not received from the main control circuit 56 (S35: NO), the effect control circuit 104 is backed up in the effect control RAM 108 in S41 because the effect control circuit 58 is a single CPU reset. Correct / incorrect determination processing is performed to determine whether the content is correct.

  The contents of the correctness determination process are shown in FIG. First, the effect control CPU 104 compares the contents stored in the copy data storage area “A” 126a, the copy data storage area “B” 126b, and the copy data storage area “C” 126c of the backup data storage area 124 in S45. Then, it is determined whether the contents of two or more, that is, the majority of the copy data storage areas 126a to 126c match. If the contents of the majority of the copy data storage areas 126a to 126c do not match (S45: NO), it is determined that the correct contents are not backed up, and the contents of the effect control RAM 108 are cleared in S50. .

  On the other hand, if the contents of the majority of the copy data storage areas 126a to 126c match (S45: YES), the effect control CPU 104, in S46, the reverse data storage area “a” 128a, the reverse data storage area “b”. "128b" and the contents stored in the inverted data storage area "c" 128c are compared to determine whether two or more, that is, the majority of the contents of the inverted data storage areas 128a to 128c match. If the contents of the majority of the inverted data storage areas 128a to 128c do not match (S46: NO), it is determined that the correct contents are not backed up, and the contents of the effect control RAM 108 are cleared in S50. .

  On the other hand, if the majority of the contents of the inverted data storage area 128 match (S46: YES), the effect control CPU 104 determines that all of the copy data storage areas 126a to 126c and the inverted data storage areas 128a to 128c are all in S47. For each combination, a logical sum of the stored contents is created, and whether or not all the bit strings of the logical sum are “1”, that is, one of the selected copy data storage areas 126a to 126c. It is determined whether one value and one of the selected inverted data storage areas 128a to 128c have the same contents. If five or more of these combinations (9 in this embodiment), that is, the majority of the combinations do not satisfy the condition (S47: NO), it is determined that the correct content is not backed up. In step S50, the contents of the effect control RAM 108 are cleared. Note that “FF” in the figure means that all of the created bit sequence of logical sum is 1, and means that the data size of management information to be saved is limited to 1 byte. Not what you want.

  If all of the above majority determinations (S45, S46, S47) are satisfied (S45: YES and S46: YES and S47: YES), the effect control CPU 104 performs the majority determination in S45 in S48. For the copy data storage area 126 and the inverted data storage area 128 in which the majority data is not stored, the majority data (the inverted data of the majority data for the inverted data storage area 128) is stored. The stored contents of the copy data storage areas 126a to 126c and the inverted data storage areas 128a to 128c are made the same. Subsequently, the effect control CPU 104 returns the majority data to the storage target storage area 130 in S49. As a result, the backup data stored in the backup data storage area 124 is restored to the storage area in the effect control RAM 108 as control information.

  Note that backup data used for restoration in the effect control circuit 58 of the present embodiment includes a command transmitted from the main control circuit 56, an effect pattern selected based on the command, and whether or not the operation button 23 is input. In the command reception process (S31), which will be described later, the received command and the effect pattern are stored in the backup data storage area 124, and in the button input process (S32) performed at the time of button input. The presence / absence of button input is stored in the backup data storage area 124.

  FIG. 16 shows command reception processing (S31) for performing processing related to commands received from main control circuit 56. First, the effect control CPU 104 determines whether or not a command is received from the main control circuit 56 in S55, and if no command is received from the main control circuit 56 (S55: NO), the command receiving process is performed. (S31) ends.

  When a command is received from the main control circuit 56 (S55: YES), the effect control CPU 104 stores the received command in the command storage area 122 in S56 and then stores it in the command storage area 122 in S57. A backup process for storing the received contents (data of the received command) in the backup data storage area 124 is performed.

  The contents of such backup processing are shown in FIG. First, the effect control CPU 104 stores the received commands stored in the command storage area 122 that is the storage target storage area 130 in the copy data storage areas 126a to 126c of the backup data storage area 124 in S70, respectively. Note that the data stored in the copy data storage area 126 is not necessarily the same copy as the target control information (the received command in this description). For example, information unnecessary for restoration is deleted. Thus, it may be stored after processing only necessary information.

  Subsequently, in S71, the effect control CPU 104 stores inversion data obtained by inverting the bit string of the information stored in the copy data storage areas 126a to 126c in the inversion data storage areas 128a to 128c. In the present embodiment, the same number of the inverted data storage areas 128 are provided so as to be paired with the copy data storage areas 126a to 126c, and the information stored in each of the copy data storage areas 126a to 126c is stored. After being inverted, the information is stored in the corresponding inverted data storage areas 128a to 128c. However, the information stored in the storage target storage area 130 is inverted and directly stored in the inverted data storage areas 128a to 128c. Each may be stored. Specifically, in the present embodiment, the contents stored in the storage target storage area 130 are temporarily stored in the copy data storage areas 126a to 126c, and the information stored in the copy data storage areas 126a to 126c is inverted. Then, the data is stored in the corresponding inverted data storage areas 128a to 128c (see FIG. 7) but stored in the storage target storage area 130 without using the information stored in the copy data storage area 126. The information may be inverted and stored directly in each of the inverted data storage areas 128a to 128c. Further, the data stored in the inverted data storage area 128 is stored in the inverted data storage area 128 because its identity is confirmed by a logical sum with the data stored in the copy data storage area 126. The data is stored as data that has been faithfully inverted without processing the data stored in the copy data storage area 126.

  As described above, the effect control CPU 104 that stores the received command in the backup data storage area 124 determines whether or not the received command is a command for selecting an effect pattern in S58. When the received command is a command for selecting an effect pattern (S58: YES), effect control CPU 104 provides an effect corresponding to the command received from the plurality of effect patterns stored in effect control ROM 106 in S59. A pattern is selected and stored in the effect pattern storage area 123. In the present embodiment, the effect pattern selected by the effect control circuit 58 is also subject to backup, and the effect control CPU 104 stores the contents stored in the effect pattern storage area 123 in S60. Store in the backup data storage area 124. The backup process (S60) is the same as the backup process (S57) described above (see FIGS. 17 and 7), and the storage target storage area 130 is used as the effect pattern storage area 123. .

  On the other hand, when the received command is a command that does not select an effect pattern, for example, a command indicating the start of each round in the jackpot game (S58: NO), the effect control CPU 104 received in S61. Various processes corresponding to the command are executed. In the command processing (S61), when there is control information that requires backup, the above-described backup processing can be performed on appropriate control information.

  Then, after performing processing based on the command received from the main control circuit 56, the effect control CPU 104 sends a command corresponding to the received command to the display control circuit 60, the sound control circuit 62, and the light control circuit 64 in S62. Each is transmitted, and the command reception process (S31) is terminated.

  The effect control CPU 104 that has finished the command receiving process (S31) executes the button input process in S32. Such button input processing is shown in FIG.

  First, the effect control CPU 104 determines whether or not the operation button 23 has been operated based on the input from the operation switch 116 in S75, and if the operation button 23 has not been operated (S75: NO), the button The input process (S32) ends.

  On the other hand, when the operation button 23 is operated (S75: YES), the effect control CPU 104 sets the button input flag 120 to ON in S76, and stores the contents of the button input flag 120 in S77 as backup data. Store in area 124. The backup process (S77) is the same as the above-described backup process (S57) (see FIGS. 17 and 7), and the storage target storage area 130 is used as the button input flag 120.

  Subsequently, the effect control CPU 104 executes a process corresponding to the button input in S78. Although not shown, when the state of the button input flag 120 is changed during the button input process (S78) or other processes, the backup process is similarly executed at that time. Become.

  Then, after performing the process corresponding to the button input, the effect control CPU 104 transmits a command corresponding to the button input to the display control circuit 60, the sound control circuit 62, and the light control circuit 64 in S79, respectively. The process (S32) ends.

  Next, FIG. 19 shows an outline of processing performed by the display control CPU 132 of the display control circuit 60. First, the display control CPU 132 executes a reset process (S85) as an initialization process when the power is turned on or a reset due to noise or the like occurs. After the reset process (S85) is completed, the command reception process (S86) is repeated by an interrupt process for every predetermined period (for example, 4 ms) generated by the clock circuit 144. Thereby, the display control of the liquid crystal display 34 is performed based on the command transmitted from the effect control circuit 58. The display control circuit 60 does not perform any special processing when the power is shut off, and the supply of voltage is shut off and the operation is stopped.

  FIG. 20 shows the contents of the reset process (S85). The display control CPU 132 first checks whether or not a command has been received from the effect control circuit 58 in S90 when the power is turned on or reset due to noise or the like.

  When a command is received from the effect control circuit 58 (S90: YES), the reset control is not the display control circuit 60 alone but the pachinko machine 10 as a whole. In S91, it is determined whether or not the received command is a power-on command indicating that initialization is performed when the pachinko machine 10 is powered on.

  If the received command is not a power-on command (S91: NO), the received command is a power recovery command indicating that the backed up content is restored when the power is turned off. Then, the control information is restored based on the information included in the received power recovery command.

  On the other hand, when the received command is a power-on command (S91: YES), the display control CPU 132 clears the display control RAM 136 in S93.

  On the other hand, if the command is not received from the effect control circuit 58, the display control circuit 60 determines whether the contents backed up in the display control RAM 136 are correct or not in S94 because the display control circuit 60 is a CPU reset. The correctness / incorrectness determination process is performed.

  Since this correct / incorrect determination process (S94) is the same as the correct / incorrect determination process (S41) (see FIG. 15) performed in the above-described effect control circuit 58, description of the processing content is omitted. In the correctness determination process (S94) performed in the display control circuit 60, the commands stored in the command storage area 156 and the contents stored in the button input flag 120 are the targets of the correctness determination process. If the correct / incorrect determination result is correct, the command information and button input information stored in the backup data storage area 158 are restored to the command storage area 156 and the button input flag 154, respectively. On the other hand, if the determination result of the correctness / incorrectness is incorrect, the stored contents of the display control RAM 136 are cleared, and the reset process (S85) ends.

  The display control CPU 132 that has completed the reset process (S85) executes the command reception process (S86) at every predetermined interval (4 ms in the present embodiment) generated by the clock circuit 144.

  FIG. 21 shows the contents of the command reception process (S86). First, in S100, the display control CPU 132 determines whether or not a command is received from the effect control circuit 58. If no command is received from the effect control circuit 58 (S100: NO), a command reception is performed. The process (S86) ends.

  When a command is received from the effect control circuit 58 (S100: YES), the display control CPU 132 stores the received command in the command storage area 156 in S101, and then stores it in the command storage area 156 in S102. A backup process for storing the received contents (data of the received command) in the backup data storage area 158 is performed.

  The backup process (S102) is the same as the above-described backup process (S57) (see FIGS. 17 and 7), and the storage target storage area 130 is the command storage area 156.

  In step S103, the display control CPU 132 selects image data corresponding to the received command based on the image data selection table stored in the display control ROM 134, and in step S104, designates the image data to the VDP 138. . Receiving the designation of the image data, the VDP 138 reads the corresponding image data stored in the VROM 146, edits the VRAM 148 as a work area, and transmits the image data stored in the VRAM 148 to the liquid crystal display circuit 150 as a display signal. To do. The liquid crystal display circuit 150 displays an image on the liquid crystal display 34 based on the received display signal. Here, when there is control information that needs to be backed up, and such control information is changed during processing accompanying command reception, the above-described backup processing can be performed on the control information. . Particularly in the present embodiment, although not shown, the command transmitted from the effect control circuit 58 includes the operation state of the operation button 23, and the operation state of the operation button 23 is stored in the button input flag 154. In addition, the contents of the button input flag 154 are also stored in the backup data storage area 158.

  Next, processing performed by the sound control CPU 160 of the sound control circuit 62 will be described. The outline of the process performed by the sound control CPU 160 of the sound control circuit 62 is substantially the same as the process (see FIG. 19) performed by the display control CPU 132 of the display control circuit 60 described above. In addition, the contents of the reset process (S85 in FIG. 19) that is initially performed at the time of power-on or CPU reset due to noise or the like is substantially similar to the process (see FIG. 20) performed by the display control CPU 132 described above. Therefore, the outline of the process performed by the sound control CPU 160 and the content of the reset process will be omitted by referring to FIGS. 19 and 20. In the sound control circuit 62, the command information from the effect control circuit 58 to be stored in the command storage area 178 is stored in the backup data storage area 180, and the correctness / incorrectness determination process in the reset process (in FIG. 20). , S94).

  FIG. 22 shows the contents of command reception processing performed by the sound control CPU 160. First, the sound control CPU 160 determines whether or not a command from the effect control circuit 58 has been received in S110. If no command has been received from the effect control circuit 58 (S110: NO), the sound control CPU 160 receives a command. The process ends.

  If a command is received from the effect control circuit 58 (S110: YES), the sound control CPU 160 stores the received command in the command storage area 178 in S111, and then stores it in the command storage area 178 in S112. A backup process for storing the received contents (data of the received command) in the backup data storage area 180 is performed.

  The backup process (S112) is the same as the above-described backup process (see FIGS. 17 and 7), and the storage target storage area 130 is the command storage area 178.

  Then, in S113, the sound control CPU 160 selects and acquires the sound data corresponding to the received command from the sound data stored in the sound control ROM 162. Then, the sound control CPU 160 outputs the selected audio data to the speaker circuit 172 in S114. Thereby, the speaker circuit 172 outputs sound based on the received sound data from the speakers 25 and 25. Here, when there is control information that needs to be backed up, and such control information is changed during processing accompanying command reception, the above-described backup processing can be performed on the control information. .

  Next, processing performed by the light control CPU 182 of the light control circuit 64 will be described. Note that the outline of the process performed by the light control CPU 182 and the reset process are also substantially the same as the process performed by the display control CPU 132 of the display control circuit 60 (see FIGS. 19 and 29). Therefore, the outline of the process performed by the light control CPU 182 and the content of the reset process will not be described in detail by referring to FIGS. In the light control circuit 64, command information from the effect control circuit 64 to be stored in the command storage area 198 is stored in the backup data storage area 200, and correctness determination processing in the reset processing (in FIG. 20). , S94).

  FIG. 23 shows the contents of command reception processing performed by the light control CPU 182. First, in S120, the light control CPU 182 determines whether or not a command is received from the effect control circuit 58. If no command is received from the effect control circuit 58 (S120: NO), a command reception is performed. The process ends.

  If a command is received from the effect control circuit 58 (S120: YES), the light control CPU 182 stores the received command in the command storage area 198 in S121, and then stores it in the command storage area 198 in S122. A backup process for storing the received contents (data of the received command) in the backup data storage area 200 is performed.

  The backup process (S122) is the same as the above-described backup process (see FIGS. 17 and 7), and the storage target storage area 130 is used as the command storage area 198.

  In S123, the light control CPU 182 selects and acquires lighting data corresponding to the received command from the lighting data stored in the light control ROM 184. Then, the light control CPU 182 outputs the selected lighting data to the LED circuit 194 in S124. Thereby, the LED circuit 194 controls lighting of the LEDs 21 and 21 provided in a plurality of locations of the pachinko machine 10 based on the received lighting data. Here, when there is control information that needs to be backed up, and such control information is changed during processing accompanying command reception, the above-described backup processing can be performed on the control information. .

  As described above, in this embodiment, the updating unit is configured to include S57, S60, S77, S102, S112, and S122 that back up commands received from other circuits. Further, the correctness determination means for determining the correctness of the contents of the backed up internal information includes S45, S46, and S47, and when the determination result of the correctness determination means is correct, the internal information is adopted. The recovery means for resuming the game control is configured including S49. These storage means, update means, correctness determination means, and recovery means are provided in each of the effect control circuit 58, the display control circuit 60, the sound control circuit 62, and the light control circuit 64 that constitute the sub-control board.

  In the pachinko machine 10 having such a structure, the CPU reset by the circuit alone due to noise or the like is performed for each of the effect control circuit 58, the display control circuit 60, the sound control circuit 62, and the light control circuit 64. In such a case, the contents backed up in the RAMs 108, 136, 164, and 186 are restored. As a result, even when a CPU reset occurs on these substrates that are susceptible to noise, it is possible to restore the state before the reset as much as possible and prevent the production from being interrupted.

  In particular, in the present embodiment, since backup is performed when information necessary for recovery is changed, it is generally related to effect control that does not have a standby power supply or the like and can suddenly stop operating. The present invention can be effectively applied to a circuit that performs this. As a result, it is possible to realize backup means that can cope with an unexpected CPU reset only by changing the software configuration without changing the hardware configuration such as providing a standby power supply. Also, since the control information is backed up in the power supply state, care about the data size of the internal information as in the method of generating the checksum before the power supply from the standby power supply is cut off. In addition, control information having a large data size can be effectively backed up.

  In particular, in this embodiment, the backup is performed during normal operation when the CPU is operating normally, thereby improving the reliability of the backup data. In addition, the backup is performed when the CPU is reset. By providing correct / incorrect determination means for determining whether the data is correct or not by using a majority vote, it is possible to perform recovery using backup data with higher reliability.

  As mentioned above, although one Embodiment of this invention was explained in full detail, this is an illustration to the last, Comprising: This invention is not limited at all by the specific description in this Embodiment.

  For example, the specific determination method of the correctness determination means is not limited to the method as described above. FIG. 24 shows still another aspect of the above-described correctness determination process (S41 in FIG. 14; see FIG. 15). Note that the correctness determination process shown in FIG. 24 has substantially the same processing content as the correctness determination process (S41) in the above-described embodiment, and therefore the same number is assigned to the same process as in the above-described embodiment. A detailed description will be omitted by attaching.

  In S140, the correctness determination process in this aspect is performed by calculating the logical value of the majority value of the copy data storage areas 126a to 126c obtained in S45 and the majority value of the inverted data storage areas 128a to 128c obtained in S46. When the sum is obtained and all the bit strings of the logical sum become 1, it is determined that the backup data is correct. According to such an aspect, it is possible to more easily determine whether backup data is correct or not, and it is possible to shorten the time required for recovery.

  Further, in order to further shorten the time required for the correctness determination processing, the values of the copy data storage areas 126a to 126c and the inverted data storage areas 128a to 128c in which erroneous information is stored, which are performed in S48, are correct. The process of storing the value again may be performed after the initialization is completed.

  Further, as in the above-described embodiment, the storage area is not clearly distinguished into the storage target storage area 130 and the backup data storage area 124, and a plurality of equivalent storage areas are provided, One may be used for control processing. FIG. 25 illustrates an effect control circuit 202 having such a configuration. In addition, since the effect control circuit 202 shown in FIG. 25 is different only in the configuration of the effect control RAM 108 in the effect control circuit 58 described above, the other structure is the same as the effect control circuit 58 described above. Detailed description is omitted by assigning numbers.

  In the effect control RAM 204 in the effect control circuit 202, first to third button input flags 206a to 206c as non-inverted information storage areas and inverted information storage areas as storage areas for storing button input flags as internal information. 6 storage areas of first to third reverse button input flags 208a to 208c are provided. Here, the first to third button input flags 206a to 206c correspond to the copy data storage areas 126a to 126c (see FIG. 7) in the effect control circuit 58 described above, and the value of the button input flag is inverted. This is a storage area that is stored without being processed. On the other hand, the first to third reverse button input flags 208a to 208c correspond to the reverse data storage areas 128a to 128c in the effect control circuit 58 described above, and the values of the button input flags are inverted and stored. It is a storage area. The first button input flag 206a is a storage area used for game control.

  Similarly to the button input flag, the command storage area includes first to third command storage areas 210a to 210c as non-inversion information storage areas and first to third inversion command storage areas as inversion information storage areas. Six storage areas 212a to 212c are provided. Further, as the effect pattern storage areas, the first to third effect pattern storage areas 214a to 214c as the non-inverted information storage areas and the first to third reverse effect pattern storage areas 216a to 216c as the inversion information storage areas. Six storage areas are provided. The first command storage area 210a and the first effect pattern storage area 214a are storage areas used for game control.

  The effect control CPU 104 of the effect control circuit 202 having such a structure stores the value in the first to third button input flags 206a to 206c when the contents of the button input flag change, for example. Values obtained by inverting these values are stored in the first to third inversion button input flags 208a to 208c. Further, when necessary for the control process, the value stored in the first button input flag 206a is referred to.

  And when noise reset etc. generate | occur | produce in production control CPU104 and the value of a button input flag is restored, these 1st thru | or 3rd button input flags 206a-206c and 1st thru | or 3rd reverse button input Based on the majority of the values of the flags 208a to 208c, whether the contents of the button input flag are correct or not is determined.

  Of course, such a configuration can be applied to the display control circuit 60, the sound control circuit 62, and the light control circuit 64 described above.

  Further, the number of non-inverted information storage areas for storing internal information without being inverted and the number of inverted information storage areas for storing inverted information of internal information need not be the same, and may be different from each other. Further, the number of storage areas for storing the internal information may be varied for each internal information in consideration of the nature such as the importance of the internal information.

  Furthermore, the specific example of the internal information that is subject to correctness determination in the above-described embodiment is merely an example, and the control information that is subject to correctness determination includes the degree of required recovery, backup processing, and recovery processing. It is appropriately selected in consideration of the time required for this. For example, in the display control circuit 60 in the above-described embodiment, since the command received from the effect control circuit 58 is stored as the object of correctness determination (see S102 in FIG. 21), the CPU reset of the display control circuit 60 alone is performed. If this occurs, the display returns to the time when the command is received from the effect control circuit 58, and the display performed on the liquid crystal display 34 is returned to the content at the time when the command is received. Therefore, in order to avoid such inconvenience, for example, the current frame number of the image data being displayed is also stored as the right / no-go judgment target information, so that the state immediately before the occurrence of the reset can be restored. . This also applies to the sound control circuit 62 and the light control circuit 64. For example, a reset is generated by storing the elapsed time from the start of music playback, the number of steps of the LED lighting procedure, and the like. It is also possible to restore the state immediately before the operation and continue the operation from the state immediately before the occurrence of the reset.

  Further, in the above-described embodiment, the display control circuit 60, the sound control circuit 62, the light control circuit 64, and the effect control circuit 58 that controls them are configured separately from each other. It is. Therefore, for example, the display control circuit 60 and the sound control circuit 62 can be integrally configured.

  Further, for example, the backup power supply circuit 90 provided in the main control circuit 56 is provided in the effect control circuit 58, the display control circuit 60, the sound control circuit 62, and the light control circuit 64 for controlling the game effects. Regarding the circuit, internal information may be held by a backup power source at the time of a power failure, and correct / incorrect determination may be made based on a majority decision at the time of return.

  In addition, although not enumerated one by one, the present invention can be carried out in a mode to which various changes, modifications, improvements, and the like are added based on the knowledge of those skilled in the art. It goes without saying that all are included in the scope of the present invention without departing from the spirit of the present invention.

It is a front view showing a pachinko machine as one embodiment of the present invention. It is a rear view of the pachinko machine shown in FIG. It is a block diagram which shows the structure of the electronic control circuit of the pachinko machine shown in FIG. FIG. 4 is a block diagram showing a configuration of a main control circuit shown in FIG. 3. FIG. 5 is an explanatory diagram for explaining a backup power supply circuit of the main control circuit shown in FIG. 4. FIG. 4 is a block diagram showing a configuration of an effect control circuit shown in FIG. 3. It is explanatory drawing for demonstrating the structure of the backup data storage area shown in FIG. FIG. 4 is a block diagram illustrating a configuration of a display control circuit illustrated in FIG. 3. It is a block diagram which shows the structure of the sound control circuit shown in FIG. FIG. 4 is a block diagram illustrating a configuration of a light control circuit illustrated in FIG. 3. It is a flowchart which shows the power-on process which main control CPU performs. It is a flowchart which shows the power-off process which main control CPU performs. It is a flowchart which shows the presentation control process which presentation control CPU performs. It is a flowchart which shows the reset process which presentation control CPU performs. It is a flowchart which shows the right / wrong determination process which presentation control CPU performs. It is a flowchart which shows the command reception process which presentation control CPU performs. It is a flowchart which shows the backup process which presentation control CPU performs. It is a flowchart which shows the button input process which presentation control CPU performs. It is a flowchart which shows the display control process which display control CPU performs. It is a flowchart which shows the reset process which display control CPU performs. It is a flowchart which shows the command reception process which a display control CPU performs. It is a flowchart which shows the command reception process which sound control CPU performs. It is a flowchart which shows the command reception process which light control CPU performs. It is a flowchart which shows the different aspect of a right / wrong determination process. It is a block diagram which shows a different structure of an effect control circuit.

Explanation of symbols

10 Pachinko machine 21 LED
23 Operation button 25 Speaker 26 Launch handle 34 Liquid crystal display 48 Main control board storage case 50 Display control board storage case 52 Production control board storage case 54 Power supply unit 56 Main control circuit 58 Production control circuit 60 Display control circuit 62 Sound control circuit 64 Optical control circuit 79 RAM erase switch 100 Connector 102 Diode

Claims (4)

In pachinko machines that perform game control according to internal information,
Storage means comprising a plurality of storage areas corresponding to the same internal information;
Updating means for storing the changed internal information in each of the plurality of storage areas when the content of the internal information changes;
Correctness determination means for determining whether or not the internal information having the correct content is stored when the game control is resumed after the game control is interrupted, using a majority vote of the content stored in the plurality of storage areas; ,
And a recovery means for resuming game control by adopting the correct internal information when the correct / incorrect determination means determines that the correct internal information is stored. Machine.   As the storage area, a plurality of non-inversion information storage areas for storing the same contents as the internal information and a plurality of inversion information storage areas for storing inversion information obtained by inverting the contents of the internal information are provided. The determination as to whether the content of the internal information stored in the storage area is correct or not is made by using the majority of the contents stored in the non-inverted information storage area and the majority of the contents stored in the inverted information storage area. The pachinko machine described.   The correct / incorrect determination means uses the addition value of the content stored in the non-inverted information storage area and the content stored in the inverted information storage area to determine the correctness of the content of the internal information stored in the storage area. The pachinko machine according to claim 2 which is judged by. A main control board for controlling a game operation; and a sub control board for controlling a game effect operation based on a signal received from the main control board; and the storage means, the update means, and the correct / incorrect on the sub control board. The pachinko machine according to any one of claims 1 to 3, further comprising a determination unit and the recovery unit.

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