JP2007049598A - Image processing controller, electronic apparatus and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing controller, electronic apparatus and image processing method in which image data for displaying a high-quality image can be generated at low cost. <P>SOLUTION: An image processing controller 10 includes a selector 100 for selecting and outputting any one of first and second image data input asynchronously with each other, a switching control section 110 for performing switching control of the selector 100 for each frame of image data in accordance with a given switching order, and a frame memory 130 for storing first and second image data for one frame output from the selector in accordance with the switching order, or storing synthetic image data for one frame combining the first and second image data output from the selector in accordance with the switching order. Either synthetic image data combining the first and second image data stored in the frame memory 130 or the synthetic image data stored in the frame memory 130 are supplied to a display driver 30. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image processing controller, an electronic device, and an image processing method.

  In recent years, liquid crystal display (LCD) panels (display panels in a broad sense; electro-optical devices in a broad sense) mounted on portable electronic devices such as mobile phones have been improved in quality, and various contents have been developed. Images and images taken with a camera or the like can be displayed. And in order to satisfy a user's request | requirement by making it more elaborate, it is also possible to display a three-dimensional image on an LCD panel.

Image data for performing such a stereoscopic image display is generated by the technique described in Patent Document 1, for example. In Patent Document 1, images taken by two cameras provided for the right eye and for the left eye are stored directly in a frame memory provided for each camera, and the left and right are switched by a selection circuit. Disclosed is a technique for performing interleaving of the image data and performing a synthesis process.
JP-A-8-7125

  However, providing a frame memory for each of the two cameras increases the cost and is not suitable for mounting on a portable electronic device. In addition, when each of the two cameras inputs image data asynchronously, a stereoscopic image may become uncomfortable due to a temporal shift in the images of the two image data, and the image quality may deteriorate. This is not limited to a stereoscopic image, and the same applies when a plurality of images are connected to generate a single image.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide an image processing controller, an electronic device capable of generating image data for displaying a high-quality image at low cost. To provide an apparatus and an image processing method.

In order to solve the above problems, the present invention
An image processing controller for supplying composite image data obtained by combining first and second image data to a drive device that drives an electro-optical device,
A selector that selects and outputs one of the first and second image data input asynchronously with each other;
A switching control unit that performs switching control of the selector for each frame of image data according to a given switching order;
One frame of the first and second image data for one frame output from the selector in accordance with the switching order, or one frame in which the first and second image data output from the selector in accordance with the switching order are combined A frame memory for storing the composite image data for
The present invention relates to an image processing controller that supplies composite image data obtained by combining the first and second image data stored in the frame memory or combined image data stored in the frame memory to the driving device.

  According to the present invention, when the composite image data generated using the first and second image data is supplied to the driving device, the frame memory can be shared with the first and second image data. Become. Thereby, cost reduction of the image processing controller can be realized.

In the image processing controller according to the present invention,
The switching control unit is
The period from the end timing of one image data of one of the first and second image data to the start timing of the next one frame of the other image data of the first and second image data is the shortest. Thus, the switching order can be determined, and the selector switching control can be performed according to the switching order.

  According to the present invention, switching is performed so that the period from the end timing of one frame of one of the first and second image data to the start timing of the next frame of the other image data is the shortest. Since the order is determined, the time difference between the first and second image data switched by the selector can be shortened. Therefore, by sharing the frame memory, it is possible to greatly reduce the uncomfortable feeling of the image displayed by the composite image data due to the time difference between the first and second image data and to improve the image quality of the composite image. .

The present invention also provides
An image processing controller for supplying composite image data obtained by combining first and second image data to a drive device that drives an electro-optical device,
A switching control unit that performs switching control for each image data of one frame in accordance with a given switching order for any of the first and second image data input asynchronously with each other;
One frame of the first and second image data selected according to the switching order, or one frame of combined image data obtained by combining the first and second image data selected according to the switching order. Frame memory to be stored,
The switching control unit is
The period from the end timing of one image data of one of the first and second image data to the start timing of the next one frame of the other image data of the first and second image data is the shortest. The switching order is determined so that the switching order is controlled according to the switching order,
The present invention relates to an image processing controller that supplies composite image data obtained by combining the first and second image data stored in the frame memory or combined image data stored in the frame memory to the driving device.

  According to the present invention, when the composite image data generated using the first and second image data is supplied to the driving device, the frame memory can be shared with the first and second image data. Become. Thereby, cost reduction of the image processing controller can be realized. In addition, the switching order is determined so that the period from the end timing of one frame of one of the first and second image data to the start timing of the next frame of the other image data is the shortest. Since it did in this way, the time difference of the 1st and 2nd image data selected can be shortened. Therefore, by sharing the frame memory, it is possible to greatly reduce the uncomfortable feeling of the image displayed by the composite image data due to the time difference between the first and second image data and to improve the image quality of the composite image. .

In the image processing controller according to the present invention,
The switching control unit is
The switching order can be determined based on the vertical and horizontal synchronization signals of the first image data and the vertical and horizontal synchronization signals of the second image data.

  According to the present invention, it is possible to generate high-quality composite image data at low cost using the first and second image data with a simple configuration.

In the image processing controller according to the present invention,
An acquisition start line setting register for designating an acquisition start line within one vertical scanning period;
An acquisition end line setting register for designating an acquisition end line within one vertical scanning period,
The end timing is a timing at which a period corresponding to a setting value of the capture end line setting register has elapsed with reference to a change timing of a vertical synchronization signal defining one vertical scanning period;
The start timing is a timing at which a period corresponding to a set value of the capture start line setting register has elapsed with reference to a change timing of the vertical synchronization signal in a vertical scanning period subsequent to a vertical scanning period including the end timing. May be.

  According to the present invention, synthesized image data can be generated from captured images in a specifiable range.

In the image processing controller according to the present invention,
An image correction unit that performs a shading process of at least one of the first and second image data, or an interpolation process of defective pixels interpolated by surrounding pixel data;
The image correction unit is
Performing the shading process or the interpolation process on the first or second image data output from the selector;
In the frame memory, the first and second image data after the shading process or the interpolation process, or the synthesized image in which the first and second image data after the shading process or the interpolation process are combined. Data may be stored.

  According to the present invention, the image correction unit can be made common to the first and second image data, and the cost of the image processing controller can be reduced. Furthermore, it is possible to generate composite image data after shading correction processing or interpolation processing while maintaining high image quality.

In the image processing controller according to the present invention,
An image reduction unit that performs an image reduction process for reducing the image size of the first and second image data or the composite image data;
The frame memory may store the first and second image data after the image reduction process, or the composite image data after the image reduction process.

  According to the present invention, the image reduction unit can be made common to the first and second image data, and the cost of the image processing controller can be reduced. Furthermore, the capacity of the frame memory can be reduced.

In the image processing controller according to the present invention,
The first image data is one of right-eye image data and left-eye image data;
The second image data is the other of the right-eye image data and the left-eye image data;
The composite image data may be stereoscopic display image data.

  According to the present invention, it is possible to provide an image processing controller that can generate image data for displaying a high-quality stereoscopic display image at low cost.

The present invention also provides
A display panel;
Any one of the image processing controllers described above;
The present invention relates to an electronic device including a display driver that drives the display panel based on image data supplied by the image processing controller.

  According to the present invention, it is possible to provide an electronic apparatus including an image processing controller that can generate image data for displaying a high-quality stereoscopic display image at low cost.

The present invention also provides
An image processing method for supplying composite image data obtained by combining first and second image data to a drive device that drives an electro-optical device,
Either one of the first and second image data input asynchronously with each other is switched and output for each frame of image data according to a given switching order,
One frame of the first and second image data output according to the switching order, or one frame of combined image data obtained by combining the first and second image data output according to the switching order. Stored in frame memory,
The present invention relates to an image processing method in which the composite image data obtained by combining the first and second image data stored in the frame memory or the composite image data stored in the frame memory is supplied to the driving device.

In the image processing method according to the present invention,
The period from the end timing of one image data of one of the first and second image data to the start timing of the next one frame of the other image data of the first and second image data is the shortest. The switching order can be determined as follows.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Image Processing Controller FIG. 1 is a diagram showing a configuration example of a system to which the image processing controller of this embodiment is applied. The image processing controller 10 of the present embodiment supplies image data to a display driver (driving device) 30 that drives a display panel (electro-optical device) 20. The display panel 20 includes a plurality of data lines and a plurality of scanning lines, each pixel having a plurality of pixels specified by each data line and each scanning line, and can display a stereoscopic image. The display driver 30 has a function of a data driver that drives a plurality of data lines of the display panel 20 based on image data, and a function of a scan driver that scans a plurality of scanning lines of the display panel 20.

  The first camera data is input to the image processing controller 10 from the first camera module 40 as, for example, right-eye image data. In addition, the second camera data is input to the image processing controller 10 from the second camera module 50 that is image data for the left eye, for example. The first and second camera data are input to the image processing controller 10 at asynchronous timings. The image processing controller 10 generates combined image data obtained by combining the first and second image data, and supplies the combined image data to the display driver 30 as stereoscopic display image data. Therefore, the first and second camera modules 40 and 50 are provided in consideration of the parallax between the eyes of the observer who views the screen of the display panel 20.

  The image processing controller 10 is controlled by the host 60. The host 60 includes a CPU (Central Processing Unit) and a memory, and the image processing controller 10 is controlled by the CPU executing a process according to a program stored in the memory. The image processing controller 10 has a control register (not shown), and a control signal is generated based on setting data of the control register set by the host 60, and operates based on the control signal.

  FIG. 2 shows a block diagram of a configuration example of the first camera module 40. In the present embodiment, the configuration and operation of the first camera module 40 are the same as the configuration and operation of the second camera module 50, but are not limited thereto.

  The first camera module 40 includes a lens 42 and generates image data of an image captured through the lens 42. More specifically, the first camera module 40 further includes an image sensor 44, an analog to digital (A / D) converter 46, and a timing generation circuit 48. The image pickup device 44 generates and accumulates electric charges corresponding to the amount of light incident through the lens 42, and an analog signal corresponding to the electric charge amount is synchronized with the timing signal from the timing generation circuit 48 in an A / D converter. Output to 46. The A / D converter 46 converts the analog signal into a digital signal, and outputs it to the image processing controller 10 as image data GD1. The first camera module 40 sequentially synchronizes the image data from the A / D converter 46 with the timing signals (dot clock DCK1, horizontal synchronization signal HSYNC1, vertical synchronization signal VSYNC1) generated by the timing generation circuit 48. Output. That is, image data of an image captured through the lens 42 is sequentially output as digital data corresponding to the amount of light detected by the image sensor 44. Such a function of the first camera module 40 can be realized by a CCD (Charge Coupled Device) sensor module or a CMOS (Complementary Metal Oxide Semiconductor) sensor module.

  FIG. 3 shows the relationship between the timing signal generated by the timing generation circuit 48 of FIG. 2 and the pixel data.

  The timing generation circuit 18 generates a vertical synchronization signal VSYNC1, a horizontal synchronization signal HSYNC1, and a dot clock (pixel clock) DCK1 as timing signals. The vertical synchronization signal VSYNC1 is a signal that defines one vertical scanning period, and has a pulse indicating the head of the image captured by the image sensor 44. The horizontal synchronization signal HSYNC1 is a signal that defines one horizontal scanning period, and has a pulse indicating the head of one line in the horizontal scanning direction of the image captured by the image sensor 44. The A / D converter 46 outputs the image data GD1 of each pixel in synchronization with the dot clock DCK1.

  Thus, the first camera module 40 outputs image data asynchronously with the operation of the image processing controller 10. Therefore, the first camera module 40 supplies the image data to the image processing controller 10 asynchronously with the second camera module 50 that similarly outputs the image data asynchronously.

  Here, an example of the principle of stereoscopic vision using a stereoscopic image generated based on the composite image data in the present embodiment will be described. In the present embodiment, description is made assuming that a parallax barrier method is adopted. However, the present invention is not limited to this, and for example, stereoscopic viewing may be realized by a lenticular method.

  FIG. 4 is an explanatory diagram of the principle of the parallax barrier method.

  In the parallax barrier method, for example, when the left eye and the right eye of the observer are aligned in the direction DIR1 that is the horizontal direction, the display panel 20 displays images such that the right-eye image R and the left-eye image L are alternately arranged in a strip shape. Is displayed. Each of the right-eye image R and the left-eye image L extends, for example, in a direction DIR2 that is a vertical direction orthogonal to the horizontal direction with a width of one pixel in the horizontal direction.

  A parallax barrier having a vertical grid-like gap (gap in the vertical direction) is provided between the display image on the display panel 20 and the observer. The display panel 20 can include a parallax barrier. The display panel 20 may include means for providing a parallax barrier or not providing a parallax barrier, for example, electrically or mechanically.

  The right-eye image R is an image that only the viewer's right eye should see, and the left-eye image L is an image that only the viewer's left eye should see. Therefore, the right eye looks at the right eye image R and the left eye looks at the left eye image L, and the depth is felt due to the parallax between both images, and is recognized as a stereoscopic image.

  The image processing controller 10 according to the present embodiment generates composite image data for generating an image in which the right-eye image R and the left-eye image L are alternately arranged in a strip shape as shown in FIG. Is supplied to the display driver 30.

  FIG. 5 shows a block diagram of a configuration example of the image processing controller 10 of FIG. In FIG. 5, the same parts as those in FIG.

  The image processing controller 10 includes a selector 100, a switching control unit 110 that performs switching control of the selector 100, and a frame memory 130. Right-eye image data (first camera data) is input from the first camera module 40 to the selector 100, and the left-eye image is output from the second camera module 50 at a timing asynchronous with the right-eye image data. Data (second camera data) is input. The selector 100 selects and outputs either the right-eye image data or the left-eye image data. The switching control unit 110 performs switching control of the selector 100 for each image data of one frame (for one vertical scan and for one screen) according to a given switching order.

  The frame memory 130 stores, for example, at least one frame of right-eye image data and at least one frame of left-eye image data output from the selector 100 according to a given switching order. For example, as shown in FIG. 6A, the right-eye image data storage area RA and the left-eye image data storage area LA are individually assigned to the storage areas of the frame memory 130, respectively. The right-eye image data input from the first camera module 40 is stored in the right-eye image data storage area RA of the frame memory 130. The left-eye image data input from the second camera module 50 is stored in the left-eye image data storage area LA of the frame memory 130. Then, the image processing controller 10 outputs composite image data obtained by combining the right-eye image data and the left-eye image data stored in the frame memory 130 to the display driver.

  Therefore, the image processing controller 10 can further include a composition processing unit 140 and a driver interface (InterFace: I / F) (image data output interface in a broad sense) 150. The composition processing unit 140 generates composite image data from the right-eye image data and the left-eye image data. More specifically, the composition processing unit 140 reads the right-eye image data from the right-eye image data storage area RA of the frame memory 130, reads the left-eye image data from the left-eye image data storage area LA of the frame memory 130, Composite image data is generated by combining the image data for the right eye and the image data for the left eye.

  The driver I / F 150 performs processing for outputting the composite image data generated based on the right-eye image data and the left-eye image data read from the frame memory 130 to the display driver 30. The driver I / F 150 performs image data interface processing (transmission processing with the display driver and signal buffering), and outputs the image data after the interface processing to the display driver. The driver I / F 150 can perform read control of image data stored in the frame memory 130 at a given read cycle.

  The image processing controller 10 further includes a first camera I / F (first image data input interface in a broad sense) 160 and a second camera I / F (second image data input interface in a broad sense) 170. Can be included. The first camera I / F 160 receives image data in the effective pixel area of the image sensor captured through the lens of the first camera module 40. The first camera I / F 160 performs interface processing of the image data (reception processing with the camera module and signal buffering), and outputs the image data after the interface processing to the selector 100 as image data for the right eye. To do. The second camera I / F 170 receives image data in the effective pixel area of the image sensor captured through the lens of the second camera module 50. The second camera I / F 170 performs interface processing of the image data (reception processing with the camera module and signal buffering), and outputs the image data after the interface processing to the selector 100 as left-eye image data. To do.

  As shown in FIG. 5, the image processing controller 10 can include an image reduction unit 190. The image reduction unit 190 is provided between the selector 100 and the frame memory 130, for example, and can perform image reduction processing for reducing the image size of the right-eye image data and the left-eye image data output from the selector 100. The frame memory 130 stores right-eye image data and left-eye image data after image reduction processing. By providing the image reduction unit 190 in this way, the data sizes of the right-eye image data and the left-eye image data stored in the frame memory 130 can be reduced, and thus the capacity of the frame memory 130 can be reduced.

  Further, the image processing controller 10 includes a control register 180 accessed by the host 60 and is controlled based on a control signal generated according to a set value of the control register 180.

  In such an image processing controller 10, the composition processing unit 140 generates composite image data from the right-eye image data and the left-eye image data input to the frame memory 130 and writes the composite image data to the frame memory 130. It may be. In this case, the driver I / F 150 supplies the composite image data read from the frame memory 130 to the display driver 30.

  7A and 7B are explanatory diagrams of the composite image data in the present embodiment.

  FIG. 7A schematically shows an image displayed on the display panel 20 based on the composite image data for one frame. In FIG. 7A, the pixel of the right eye image (coordinate (1, 0)) and the pixel of the left eye image (coordinate (2, 0)) in the horizontal direction of the image with reference to the image coordinate (0, 0). , Pixels (coordinates (3, 0)) of the right-eye image are arranged. Each pixel includes an R component, a G component, and a B component. Similarly for the next scanning line, the pixel of the right eye image (coordinate (1, 1)) and the pixel of the left eye image (coordinate (2, 1)) in the horizontal direction with reference to the image coordinate (0, 1). ), Right eye image pixels (coordinates (3, 1)),.

  As shown in FIG. 7A, the composition processing unit 140 sequentially reads out the right-eye image data and the left-eye image data, and as shown in FIG. Composite image data for displaying a composite image in which a work image is arranged is generated.

  As described above, the frame memory 130 may store composite image data for at least one frame obtained by combining the right-eye image data and the left-eye image data output from the selector 100 in accordance with a given switching order. Good. In this case, for example, as shown in FIG. 6B, the composite image data storage area CA is allocated to the storage area of the frame memory 130. Then, the right-eye image data input from the first camera module 40 and the left-eye image data input from the second camera module 50 are combined by the combining processing unit 140 as shown in FIG. 7A. The synthesized image data is stored in the synthesized image data storage area CA of the frame memory 130. Then, the image processing controller 10 outputs the composite image data stored in the frame memory 130 to the display driver.

  If the image reduction unit 190 is included, the image reduction unit 190 performs an image reduction process for reducing the image size of the combined image data combined by the combining processing unit 140. The frame memory 130 stores composite image data after image reduction processing. By providing the image reduction unit 190 in this manner, the data size of the composite image data stored in the frame memory 130 can be reduced, so that the capacity of the frame memory 130 can be reduced.

  Since the format of the composite image data is determined according to the method of realizing the stereoscopic view of the display panel 20, there may be a case where the stereoscopic view cannot be realized when the composite image data is transmitted to another electronic device. Therefore, in the case of FIG. 6A, if either the right-eye image data or the left-eye image data is transmitted to another electronic device, the image data can be transmitted for general use. On the other hand, in the case of FIG. 6B, since it is sufficient to simply read the composite image data from the frame memory 130, the effect of reducing the capacity of the frame memory 130 and the display panel 20 that is periodically read-out controlled. An effect of simplifying the display control can be obtained.

2. Detailed Configuration Example of Image Processing Controller Next, a configuration example of a main part of the image processing controller 10 in FIG. 5 will be described.

2.1 Switching Control Unit FIG. 8 is a block diagram showing a configuration example of the selector 100 and the switching control unit 110 in FIG. The selector 100 includes a dot clock selector 102, an image data selector 104, a vertical synchronization signal selector 106, and a horizontal synchronization signal selector 108. The dot clock selector 102 selects either the dot clock DCK1 from the first camera module 40 or the dot clock DCK2 from the second camera module 50 based on the selection signal Selc from the switching control unit 110 to dot. Output as clock DCK. The image data selector 104 selects either the right-eye image data GD1 from the first camera module 40 or the left-eye image data GD2 from the second camera module 50 based on the selection signal Selc from the switching control unit 110. Select and output as image data GD. The vertical synchronization signal selector 106 selects either the vertical synchronization signal VSYNC1 from the first camera module 40 or the vertical synchronization signal VSYNC2 from the second camera module 50 based on the selection signal Selc from the switching control unit 110. And output as a vertical synchronization signal VSYNC. The horizontal synchronization signal selector 108 selects either the horizontal synchronization signal HSYNC1 from the first camera module 40 or the horizontal synchronization signal HSYNC2 from the second camera module 50 based on the selection signal Selc from the switching control unit 110. And output as a horizontal synchronization signal HSYNC.

  The switching control unit 110 includes a switching order determination unit 112 and a switching unit 114. The switching order determination unit 112 (switching control unit 110 in a broad sense) includes the vertical synchronization signal VSYNC1 and horizontal synchronization signal HSYNC1 of the right-eye image data (first image data) and the left-eye image data (second image data). Based on the vertical synchronization signal VSYNC2 and the horizontal synchronization signal HSYNC2, the switching order of the right-eye image data and the left-eye image data input to the selector 100 is determined, and an order determination signal DesOrd corresponding to the switching order is generated. More specifically, the switching order determination unit 112 (switching control unit 110 in a broad sense) determines the right-eye image data and the left-eye from the end timing of one frame of one of the right-eye image data and the left-eye image data. The switching order is determined so that the period until the start timing of the next one frame of the other image data of the image data for use is minimized. The switching unit 114 (switching control unit 110 in a broad sense) generates a selection signal Selc for performing switching control of the selector 100 in accordance with the switching order determined by the switching order determination unit 112. That is, the switching unit 114 generates the selection signal Selc based on the order determination signal DesOrd.

  FIG. 9 shows a block diagram of a configuration example of the switching order determination unit 112 in FIG.

  The switching order determination unit 112 includes first and second horizontal counters HCNT1 and HCNT2, first to fifth comparators CMP1 to CMP5, and first and second measurement counters MCNT1 and MCNT2.

  The first horizontal counter HCNT1 counts the number of pulses of the horizontal synchronization signal HSYNC1 during the active period of the vertical synchronization signal VSYNC1. The active period of the vertical synchronization signal VSYNC1 starts at the rising timing from the L level to the H level and ends at the falling timing from the H level to the L level. The count value of the first horizontal counter HCNT1 is initialized during the inactive period of the vertical synchronization signal VSYNC1. The second horizontal counter HCNT2 counts the number of pulses of the horizontal synchronization signal HSYNC2 during the active period of the vertical synchronization signal VSYNC2. The active period of the vertical synchronization signal VSYNC2 starts at the rising timing from the L level to the H level and ends at the falling timing from the H level to the L level. The count value of the second horizontal counter HCNT2 is initialized during the inactive period of the vertical synchronization signal VSYNC2.

  The switching order determination unit 112 receives the capture start line information from the capture start line setting register 182 and the capture end line information from the capture end line setting register 184. The capture start line is specified by the capture start line information. The capture end line is specified by the capture end line information. The control register 180 of FIG. 5 includes a capture start line setting register 182 and a capture end line setting register 184.

  FIG. 10 is an explanatory diagram of the capture start line and the capture end line.

  One vertical scanning period defined by the vertical synchronization signal VSYNC (VSYNC1, VSYNC2) includes a plurality of horizontal scanning periods. Each horizontal scanning period is defined by a horizontal synchronization signal HSYNC (HSYNC1, HSYNC2), and the data lines of the display panel 20 are driven based on image data for one scanning line.

  The capturing start line is a scanning line corresponding to a horizontal scanning period in which capturing of image data from the camera module (first and second camera modules) is started after one vertical scanning period is started. On the other hand, the capturing end line is a scanning line corresponding to a horizontal scanning period in which capturing of image data from the camera module (first and second camera modules) ends after one vertical scanning period is started. The right-eye image and the left-eye image are generated based on image data from the capture start line to the capture end line.

  In FIG. 9, the first comparator CMP1 compares the count value of the first horizontal counter HCNT1 with the capture start line information set in the capture start line setting register 182. The first comparator CMP1 outputs a coincidence detection pulse when they coincide. The second comparator CMP2 compares the count value of the first horizontal counter HCNT1 with the capture end line information set in the capture end line setting register 184. Then, the second comparator CMP2 outputs a coincidence detection pulse when they coincide. The third comparator CMP3 compares the count value of the second horizontal counter HCNT2 with the capture start line information set in the capture start line setting register 182. Then, the third comparator CMP3 outputs a coincidence detection pulse when they coincide. The fourth comparator CMP4 compares the count value of the second horizontal counter HCNT2 with the capture end line information set in the capture end line setting register 184. Then, the fourth comparator CMP4 outputs a coincidence detection pulse when both coincide.

  The coincidence detection pulse from the first comparator CMP1 is input to the stop terminal of the first measurement counter MCNT1. The coincidence detection pulse from the fourth comparator CMP4 is input to the start terminal of the first measurement counter MCNT1. The first measurement counter MCNT1 starts counting the number of dot clocks DCK using the coincidence detection pulse input to the start terminal as a start trigger. The first measurement counter MCNT1 stops counting the number of dot clocks DCK using the coincidence detection pulse input to the stop terminal as a start trigger. As a result, the first measurement counter MCNT1 takes the scan start line setting register 182 from the scan timing of the scan line specified by the capture end line information set in the capture end line setting register 184 with respect to the right-eye image data. It is possible to count the period Pd1 corresponding to the number of dot clocks DCK until the scanning timing of the scanning line based on the left-eye image data specified by the capture start line information of the next vertical scanning period.

  The coincidence detection pulse from the second comparator CMP2 is input to the start terminal of the second measurement counter MCNT2. The coincidence detection pulse from the third comparator CMP3 is input to the stop terminal of the second measurement counter MCNT2. The second measurement counter MCNT2 starts counting the number of dot clocks DCK using the coincidence detection pulse input to the start terminal as a start trigger. The second measurement counter MCNT2 stops counting the number of dot clocks DCK using the coincidence detection pulse input to the stop terminal as a start trigger. As a result, the second measurement counter MCNT2 takes the scan start line setting register 182 from the scan timing of the scan line specified by the capture end line information set in the capture end line setting register 184 for the left eye image data. The period Pd2 corresponding to the number of dot clocks DCK until the scanning timing of the scanning line based on the right-eye image data specified by the acquisition start line information in the next vertical scanning period can be counted.

  The fifth comparator CMP5 compares the period Pd1 counted by the first measurement counter MCNT1 with the period Pd2 counted by the second measurement counter MCNT2. The fifth comparator CMP5 outputs the order determination signal DesOrd at the H level when Pd1> Pd2, and outputs the order determination signal DesOrd at the L level when Pd1 <Pd2. When Pd = Pd2, the order determination signal DesOrd may be set to H level or L level.

  FIG. 11 shows a timing chart of an operation example of the switching order determination unit 112 in FIG.

  First, when the vertical synchronization signal VSYNC1 becomes H level at the rising edge (change timing) TM1 of the vertical synchronization signal VSYNC1 from the first camera module 40, the first horizontal counter HCNT1 receives the horizontal signal from the first camera module 40. The number of pulses of the synchronization signal HSYNC1 is counted. When the first comparator CMP1 detects that the count value of the first horizontal counter HCNT1 matches the capture start line information of the capture start line setting register 182 (timing TM2), one frame of image data A coincidence detection pulse indicating that the start timing is detected is output. Further, when the second comparator CMP2 detects that the count value of the first horizontal counter HCNT1 matches the capture end line information of the capture end line setting register 184 (timing TM3), one frame of image data A coincidence detection pulse indicating that the end timing is detected is output. After the rising edge TM1 of the vertical synchronization signal VSYNC1, an image input from the first camera module 40 during a period from when the number of pulses of the horizontal synchronization signal HSYNC1 coincides with the capture start line information until it coincides with the capture end line information. The data becomes right-eye image data.

  Similarly, when the vertical synchronization signal VSYNC2 becomes H level at the rising edge (change timing) TM10 of the vertical synchronization signal VSYNC2 from the second camera module 50, the second horizontal counter HCNT2 is output from the second camera module 50. The number of pulses of the horizontal synchronization signal HSYNC2 is counted. When it is detected by the fourth comparator CMP4 that the count value of the second horizontal counter HCNT2 matches the capture start line information of the capture start line setting register 182 (timing TM11), one frame of image data A coincidence detection pulse indicating that the start timing is detected is output. Further, when the third comparator CMP3 detects that the count value of the second horizontal counter HCNT2 matches the capture end line information of the capture end line setting register 184 (timing TM12), one frame of image data A coincidence detection pulse indicating that the end timing is detected is output. After the rising edge TM10 of the vertical synchronization signal VSYNC2, an image input from the second camera module 50 during a period from when the number of pulses of the horizontal synchronization signal HSYNC2 coincides with the capture start line information until it coincides with the capture end line information. The data is left-eye image data.

  The first measurement counter MCNT1 is from timing TM12 at which the coincidence detection pulse of the fourth comparator CMP4 is output to timing TM2 at the next vertical scanning period at which the coincidence detection pulse of the first comparator CMP1 is output. The period Pd1 is measured. The second measurement counter MCNT2 is from the timing TM3 at which the coincidence detection pulse of the second comparator CMP2 is output to the timing TM11 at the next vertical scanning period at which the coincidence detection pulse of the third comparator CMP3 is output. The period Pd2 is measured.

  The fifth comparator CMP5 compares the periods Pd1 and Pd2, and since Pd1 <Pd2 in FIG. 11, the order determination signal DesOrd changes to the L level.

  As described above, the switching order determination unit 112 determines the next image data of the right-eye image data and the left-eye image data from the end timing of one frame of the right-eye image data and the left-eye image data. The switching order is determined so that the period until the start timing of one frame is the shortest. At this time, the end timing is a timing at which a period corresponding to the set value of the capture end line setting register 184 has elapsed with reference to the change timing of the vertical synchronization signal defining one vertical scanning period. The start timing is a timing at which a period corresponding to the set value of the capture start line setting register 182 has elapsed with reference to the change timing of the vertical synchronization signal in the vertical scanning period following the vertical scanning period including the end timing.

  12 and 13 are flowcharts showing an operation example of the switching control unit 110 shown in FIG. The function of the switching control unit 110 is realized by hardware such as a combinational circuit that operates in the following flow, or a processing unit (processor or the like) that executes firmware stored in a ROM (not shown).

  First, for example, in the system of FIG. 1, when the mode is changed to a shooting mode by mode setting from an operation input unit (not shown), the first and second camera modules 40 and 50 are activated. The image processing controller 10 can detect activation of the first and second camera modules 40 and 50 (step S10). For example, the image processing controller 10 directly detects the mode setting from the operation input unit described above, or the image data, the vertical synchronization signal, the horizontal synchronization signal, and the image data input from the first and second camera modules 40 and 50 after activation. The activation of the first and second camera modules 40 and 50 can be detected by detecting one of the dot clocks.

  Thereafter, the switching order determination unit 112 of the switching control unit 110 measures the periods Pd1 and Pd2 as described above (step S11), and determines the switching order (step S12).

  Thereafter, the switching control unit 110 waits for an acquisition start instruction from the operation input unit (step S20: N). This capturing start instruction is an image capturing instruction. Then, when there is an instruction to start capturing (step S20: Y), it is determined whether the order determination signal DesOrd determined in step S12 of FIG. 12 is H level or L level (step S21).

  When the order determination signal DesOrd is at the H level (step S21: Y), the switching unit 114 of the switching control unit 110 performs switching control of the selector 100 in FIG. 8 so as to select the first camera module 40 (step S22). ). When the switching unit 114 detects the start timing and the end timing of the vertical synchronization signal VSYNC1 from the first camera module 40 (step S23), the switching unit 114 selects the second camera module 50 so that the second camera module 50 is selected. Switching control is performed (step S24). The right-eye image data is captured from when the start timing of the vertical synchronization signal VSYNC1 is detected until the end timing is detected. Thereafter, when the switching unit 114 detects the start timing and end timing of the vertical synchronization signal VSYNC2 from the second camera module 50 (step S25), the series of processing ends (end). Note that the image data for the left eye is captured from when the start timing of the vertical synchronization signal VSYNC2 is detected until the end timing is detected.

  In step S21, when the order determination signal DesOrd is at the L level (step S21: N), the switching unit 114 of the switching control unit 110 performs the switching control of the selector 100 in FIG. 8 so as to select the second camera module 50. It performs (step S26). Then, when the switching unit 114 detects the start timing and the end timing of the vertical synchronization signal VSYNC2 from the second camera module 50 (step S27), the switching unit 114 selects the first camera module 40 so as to select the first camera module 40. Switching control is performed (step S28). The left-eye image data is captured from the time when the start timing of the vertical synchronization signal VSYNC2 is detected until the end timing is detected. Thereafter, when the switching unit 114 detects the start timing and end timing of the vertical synchronization signal VSYNC1 from the first camera module 40 (step S29), the series of processing ends (end). The right-eye image data is taken in from the detection of the start timing of the vertical synchronization signal VSYNC1 to the detection of the end timing.

  As described above, the switching control unit 110 determines the next one of the other image data of the right-eye image data and the left-eye image data from the end timing of one image data of the right-eye image data and the left-eye image data. The switching order is determined so that the period until the frame start timing is the shortest. Therefore, when the right-eye image data and the left-eye image data are combined, the time difference between the right-eye image data and the left-eye image data is reduced, and image data for displaying a high-quality stereoscopic image can be generated.

  Furthermore, since the image reduction unit 190 and the frame memory 130 can be shared, the cost of the image processing controller 10 can be reduced.

2.2 Image Reduction Unit Next, a configuration example of the image reduction unit 190 in FIG. 5 will be described.

  FIG. 14 shows a configuration example of the image reducing unit 190 in FIG. The image reduction unit 190 receives the dot clock DCK, the image data GD, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC selected by the selector 100 in FIG.

  Further, the image reduction unit 190 has the horizontal reduction rate set in the horizontal reduction rate setting register included in the control register 180 of FIG. 5 and the vertical reduction rate set in the vertical reduction rate setting register included in the control register 180. Entered. The horizontal reduction ratio is a reduction ratio in the horizontal direction of the image, and is a decimal value greater than 0 and less than or equal to 1. The vertical reduction ratio is a reduction ratio in the vertical direction of the image, and is a decimal value greater than 0 and less than or equal to 1.

  The image reduction unit 190 generates image data of an image whose size is reduced in the horizontal direction by thinning out pixels arranged in the horizontal direction according to the horizontal reduction rate. The image reduction unit 190 generates image data of an image whose size is reduced in the vertical direction by thinning out pixels arranged in the vertical direction according to the vertical reduction rate. The image reducing unit 190 includes a horizontal direction thinning circuit 362, a vertical direction thinning circuit 364, a timing adjustment circuit 368, and an output thinning circuit 370. In one horizontal scanning period, the image data GD of each pixel is sequentially input to the image reduction unit 190 in synchronization with the dot clock DCK.

  In FIG. 14, the horizontal direction thinning circuit 362 generates a horizontal direction write request WRqh that becomes H level only during a period corresponding to the horizontal reduction ratio within one horizontal scanning period defined by the horizontal synchronization signal. Further, the vertical direction thinning circuit 364 generates a vertical direction write request WRqv that becomes H level only during a period corresponding to the vertical reduction ratio within one vertical scanning period defined by the vertical synchronization signal. A thinning control signal to the output thinning circuit 370 is generated by a logical product operation of the horizontal direction write request WRqh and the vertical direction write request WRqv.

  The timing adjustment circuit 368 includes a data latch. The timing adjustment circuit 368 latches image data in synchronization with the dot clock DCK, and outputs the timing-adjusted data to the output thinning circuit 370.

  FIG. 15 is a block diagram showing a configuration example of the horizontal direction thinning circuit 362.

  Each part of the horizontal direction thinning circuit 362 operates in synchronization with the dot clock DCK.

  The subtracter SUB outputs an output Z1 obtained by subtracting the horizontal reduction ratio Nh from the input Y and obtained as a decimal value. The subtractor SUB initializes the output Z1 to 0 in synchronization with the rising detection signal of the horizontal synchronization signal HSYNC.

  The latch LAT1 latches the output Z1 of the subtracter SUB. The output Z2 of the latch LAT1 is output to the selector SEL and the adder ADD.

  The adder ADD adds 1 to the output Z2 of the latch LAT1 and outputs the output X obtained as a decimal value. The output X of the adder ADD is output to the selector SEL.

  The comparator CMPH compares the output Z1 of the subtracter SUB with the horizontal reduction ratio Nh. More specifically, the comparator CMPH sets the horizontal write request WRqh to the H level when the horizontal reduction ratio Nh is smaller than the output Z1 of the subtractor SUB and the output Z1 of the subtractor SUB is 0 or more. At this time, the horizontal direction write request WRqh is set to the L level.

  The output of the comparator CMPH is also supplied to the latch LAT2. The output of the latch LAT2 serves as a switching control signal for the selector SEL. When the output of the latch LAT2 is 1 (H level), the selector SEL outputs the output X of the adder ADD, and when the output of the latch LAT2 is 0 (L level), the selector SEL outputs the output Z2 of the latch LAT1.

  FIG. 16 is an explanatory diagram of the horizontal reduction ratio Nh.

  When the accuracy of the horizontal direction thinning circuit 362 is 8 bits, the horizontal reduction ratio Nh can be expressed as MSB as integer data and the rest as data after the decimal point. For example, when the horizontal reduction ratio Nh is 1, “10000000” is obtained.

  Hereinafter, an example of the operation of the horizontal direction thinning circuit 362 shown in FIG. 15 will be described assuming that the horizontal reduction ratio Nh is 0.781. When the horizontal reduction ratio Nh is 0.781, it can be approximated as 0.781 = 1/2 + 1/4 + 1/32, and can be expressed as 8-bit data “01100100”.

  FIG. 17 shows a timing chart of an operation example of the horizontal direction thinning circuit 362 in FIG.

  When the horizontal synchronization signal HSYNC changes from the L level to the H level at time t1, the output Z1 of the subtractor SUB is initialized to 0. At this time, since the horizontal reduction ratio Nh (= 0.781) is larger than the output Z1 (= 0) of the subtractor SUB, the output WRqh of the comparator CMPH becomes 1 (H level).

  At the next falling time t2 of the dot clock DCK, the output of the latch LAT2 becomes 1 (H level). At this time, the latch LAT1 takes in the output Z1 of the subtracter SUB and outputs it as an output Z2. The output X of the adder ADD is 1. Since the output of the latch LAT2 is 1, the output Y of the selector SEL is the output X (= 1) of the adder ADD. Therefore, the output Z1 of the subtracter SUB is 0.219 (= 1−0.781). At this time, since the horizontal reduction ratio Nh (= 0.781) is larger than the output Z1, the output WRqh of the comparator CMPH remains 1 (H level).

  Similarly, when the next falling time t3 of the dot clock DCK elapses, the output X of the adder ADD becomes 1.219, and the output Z1 of the subtractor SUB becomes 0.438 (= 1.219-0). .781). At this time, since the horizontal reduction ratio Nh (= 0.781) is larger than the output Z1, the output WRqh of the comparator CMPH remains 1 (H level).

  Also, when the falling time t4 of the next dot clock DCK elapses, the output Z1 of the subtracter SUB is 0.657 (= 1.438−0.781). At this time, since the horizontal reduction ratio Nh (= 0.781) is larger than the output Z1, the output WRqh of the comparator CMPH remains 1 (H level).

  When the next falling time t5 of the dot clock DCK elapses, the output Z1 of the subtracter SUB becomes 0.876 (= 1.657−0.781). At this time, since the horizontal reduction ratio Nh (= 0.781) is smaller than the output Z1, the output WRqh of the comparator CMPH changes to 0 (L level).

  When the next falling time t6 of the dot clock DCK elapses, the output of the latch LAT2 becomes 0 (L level). At this time, the latch LAT1 takes in the output Z1 of the subtracter SUB and outputs it as an output Z2. The output X of the adder ADD is 1.876. Since the output of the latch LAT2 is 0, the output Y of the selector SEL is the output Z2 (= 0.7676) of the latch LAT1. Therefore, the output Z1 of the subtracter SUB is 0.095 (= 0.786−0.781). At this time, since the horizontal reduction ratio Nh (= 0.781) is larger than the output Z1, the output WRqh of the comparator CMPH changes to 1 (H level) again.

  Similarly, output WRqh of comparator CMPH changes to 0 (L level) at time t7, and output WRqh of comparator CMPH changes to 1 (H level) at time t8.

  In this manner, the output WRqh of the comparator CMPH can be set to the H level for a period corresponding to the horizontal reduction ratio Nh (= 0.781).

  The configuration and operation of the horizontal direction thinning circuit 362 shown in FIG. 14 have been described so far, but the same applies to the vertical direction thinning circuit 364 shown in FIG. Each part of the vertical direction thinning circuit 364 operates on the basis of the horizontal synchronization signal HSYNC, the subtractor is initialized at the rising edge of the vertical synchronization signal VSYNC, and the vertical reduction rate Nv is input, except that the vertical direction thinning is performed. Since the circuit 364 can be similarly realized, the description thereof is omitted.

  When the image data of each pixel is sequentially supplied to the image reduction unit 190 in the order of the vertical direction of the image along the horizontal direction of the image data, the output thinning circuit 370 of FIG. 14 is generated as described above. Only the image data of the pixels for which the horizontal write request WRqh and the vertical write request WRqv are at the H level are output.

  Here, the image reduction unit 190 has been described as performing image reduction processing on the image data GD from the selector 100 (that is, image data for the right eye and image data for the left eye). An image reduction process may be performed on the combined image data obtained by combining the image data.

  As described above, by storing the right-eye image data and the left-eye image data after the image reduction processing, or the composite image data after the image reduction processing in the frame memory 130, the capacity of the frame memory 130 can be reduced. become.

3. Image Processing Controller in Modification Example The image processing controller 10 of the present embodiment is not limited to the configuration shown in FIG. The image processing controller in the modification of the present embodiment can further include an image correction unit.

  FIG. 18 shows a block diagram of a configuration example of the image processing controller in the present modification. In FIG. 18, the same parts as those in FIG.

  The image processing controller 400 in the present modification is different from the image processing controller 10 of the present embodiment in that an image correction unit 410 is provided between the selector 100 and the image reduction unit 190. The image correction unit 410 performs shading processing of at least one of right-eye image data and left-eye image data or interpolation processing of defective pixels interpolated by surrounding pixel data. That is, the image correction unit 410 performs a shading process or an interpolation process on the right-eye image data or the left-eye image data output from the selector 100.

  The shading process is a process for correcting a change in the amount of light in the image because the amount of light at the center of the lens of each camera module is different from the amount of light at the periphery of the lens. Interpolation processing is processing for interpolating defective pixels with image data of surrounding pixels.

  As a result, the frame memory 130 stores the right-eye image data and the left-eye image data after the shading process or the interpolation process. The frame memory 130 may store composite image data obtained by combining the right-eye image data and the left-eye image data after the shading process or the interpolation process.

4). Electronic Device FIG. 19 shows a block diagram of a configuration example of an electronic device to which the image processing controller according to the present embodiment or the modification is applied as a display controller. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device.

  The mobile phone 600 includes first and second camera modules 610 and 612. The first and second camera modules 610 and 612 correspond to the first and second camera modules 40 and 50 in FIG. 1, and supply captured image data to the display controller 620.

  The mobile phone 600 includes a display panel 630 corresponding to the display panel 20 of FIG. An LCD panel can be used as the display panel 630. In this case, the display panel 630 is driven by a display driver 640 corresponding to the display driver 30 of FIG. The display panel 630 includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels. The display driver 640 has a function of a scanning driver that selects a scanning line in units of one or a plurality of scanning lines, and also has a function of a data driver that supplies a voltage corresponding to image data to the plurality of data lines.

  The display controller 620 is connected to the display driver 640 and supplies image data to the display driver 640.

  The host 650 is connected to the display controller 620. The host 650 corresponds to the host 60 in FIG. 1, and the host 650 controls the display controller 620. Further, the host 650 can supply image data received via the antenna 660 to the display controller 620 after demodulating by the modem 670. Based on the image data, the display controller 620 causes the display driver 640 to display an image on the display panel 630.

  The host 650 modulates the image data generated by the first and second camera modules 610 and 612 or the compressed data obtained by compressing the image data by the modulation / demodulation unit 670, and then transmits it to another communication device via the antenna 660. Can be sent.

  The host 650 performs image data transmission / reception processing, imaging of the first and second camera modules 610 and 612, and display panel display processing based on operation information from the operation input unit 680.

  Accordingly, the mobile phone 600 (electronic device in a broad sense) shown in FIG. 19 drives the display panel 630 based on the display panel 630, the display controller 620 in the present embodiment, and the image data supplied by the display controller 620. A display driver 640. Furthermore, the mobile phone 600 can include a host 650 that inputs and outputs image data to and from the display controller 620.

  According to the cellular phone 600, it is possible to generate image data suitable for a stereoscopic image with low cost and high image quality using image data captured from the first and second camera modules 610 and 612.

  In FIG. 19, the LCD panel is described as an example of the display panel 630, but the present invention is not limited to this. The display panel 630 may be an electroluminescence or plasma display device, and can be applied to a display controller that supplies image data to a display driver that drives them.

  In the present embodiment or the modification, the image data captured by the first and second camera modules is used as the right-eye image data and the left-eye image data to generate the image data of the stereoscopic image. However, the present invention is not limited to this. For example, the image data captured by the first and second camera modules may be directly connected in the horizontal direction to generate panoramic image data.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. In addition, in each of FIGS. 1, 2, 5, 8, 8, 9, 14, 15, 18, and 19, it is not necessary to include all the blocks, and some of the blocks are omitted. It may be.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a diagram illustrating a configuration example of a system to which an image processing controller according to an embodiment is applied. The block diagram of the structural example of the 1st camera module of FIG. The figure which shows the relationship between the timing signal produced | generated by the timing generation circuit of FIG. 2, and pixel data. Explanatory drawing of the principle of a parallax barrier system. FIG. 2 is a block diagram of a configuration example of an image processing controller in FIG. 1. 6A and 6B are explanatory diagrams of a frame memory. FIG. 7A and FIG. 7B are explanatory diagrams of composite image data in the present embodiment. FIG. 6 is a block diagram of a configuration example of a selector and a switching control unit in FIG. 5. The block diagram of the structural example of the switching order determination part of FIG. Explanatory drawing of the acquisition start line and acquisition end line of this embodiment. The timing diagram of the operation example of the switching order determination part of FIG. The flowchart of the operation example of the switching control part of FIG. The flowchart of the operation example of the switching control part of FIG. The figure which shows the structural example of the image reduction part of FIG. The block diagram of the structural example of a horizontal direction thinning circuit. Explanatory drawing of a horizontal reduction rate. FIG. 16 is a timing diagram of an operation example of the horizontal direction thinning circuit in FIG. 15. The block diagram of the structural example of the image processing controller in this modification. The block diagram of the structural example of the electronic device to which the image processing controller in this embodiment or this modification is applied as a display controller.

Explanation of symbols

10 image processing controller, 30 display driver,
40 first camera module, 50 second camera module,
100 selector, 102 dot clock selector,
104 image data selector, 106 vertical sync signal selector,
108 horizontal synchronization signal selector, 110 switching control unit, 112 switching order determining unit,
114 switching unit, 130 frame memory, 140 synthesis processing unit,
150 driver I / F, 160 first camera I / F,
170 Second camera I / F, 180 control register, 190 image reduction unit

Claims (11)

An image processing controller for supplying composite image data obtained by combining first and second image data to a drive device that drives an electro-optical device,
A selector that selects and outputs one of the first and second image data input asynchronously with each other;
A switching control unit that performs switching control of the selector for each frame of image data according to a given switching order;
One frame of the first and second image data for one frame output from the selector in accordance with the switching order, or one frame in which the first and second image data output from the selector in accordance with the switching order are combined A frame memory for storing the composite image data for
An image processing controller for supplying the driving device with synthesized image data obtained by synthesizing the first and second image data stored in the frame memory, or synthesized image data stored in the frame memory. . In claim 1,
The switching control unit is
The period from the end timing of one image data of one of the first and second image data to the start timing of the next one frame of the other image data of the first and second image data is the shortest. An image processing controller, wherein the switching order is determined so that the selector is switched according to the switching order. An image processing controller for supplying composite image data obtained by combining first and second image data to a drive device that drives an electro-optical device,
A switching control unit that performs switching control for each image data of one frame in accordance with a given switching order for any of the first and second image data input asynchronously with each other;
One frame of the first and second image data selected according to the switching order, or one frame of combined image data obtained by combining the first and second image data selected according to the switching order. Frame memory to be stored,
The switching control unit is
The period from the end timing of one image data of one of the first and second image data to the start timing of the next one frame of the other image data of the first and second image data is the shortest. The switching order is determined so that the switching order is controlled according to the switching order,
An image processing controller for supplying the driving device with synthesized image data obtained by synthesizing the first and second image data stored in the frame memory, or synthesized image data stored in the frame memory. . In any one of Claims 1 thru | or 3,
The switching control unit is
An image processing controller, wherein the switching order is determined based on a vertical synchronization signal and a horizontal synchronization signal of the first image data and a vertical synchronization signal and a horizontal synchronization signal of the second image data. In claim 4,
An acquisition start line setting register for designating an acquisition start line within one vertical scanning period;
An acquisition end line setting register for designating an acquisition end line within one vertical scanning period,
The end timing is a timing at which a period corresponding to a setting value of the capture end line setting register has elapsed with reference to a change timing of a vertical synchronization signal defining one vertical scanning period;
The start timing is a timing at which a period corresponding to a set value of the capture start line setting register has elapsed with reference to a change timing of the vertical synchronization signal in a vertical scanning period subsequent to a vertical scanning period including the end timing. An image processing controller characterized by that. In any one of Claims 1 thru | or 5,
An image correction unit that performs a shading process of at least one of the first and second image data, or an interpolation process of defective pixels interpolated by surrounding pixel data;
The image correction unit is
Performing the shading process or the interpolation process on the selected first or second image data;
In the frame memory, the first and second image data after the shading process or the interpolation process, or the synthesized image in which the first and second image data after the shading process or the interpolation process are combined. An image processing controller in which data is stored. In any one of Claims 1 thru | or 6.
An image reduction unit that performs an image reduction process for reducing the image size of the first and second image data or the composite image data;
The image processing controller according to claim 1, wherein the frame memory stores the first and second image data after the image reduction processing or the composite image data after the image reduction processing. In any one of Claims 1 thru | or 7,
The first image data is one of right-eye image data and left-eye image data;
The second image data is the other of the right-eye image data and the left-eye image data;
An image processing controller, wherein the composite image data is stereoscopic display image data. A display panel;
An image processing controller according to any one of claims 1 to 8,
An electronic apparatus comprising: a display driver that drives the display panel based on image data supplied by the image processing controller. An image processing method for supplying composite image data obtained by combining first and second image data to a drive device that drives an electro-optical device,
Either one of the first and second image data input asynchronously with each other is switched and output for each frame of image data according to a given switching order,
One frame of the first and second image data output according to the switching order, or one frame of combined image data obtained by combining the first and second image data output according to the switching order. Stored in frame memory,
An image processing method comprising: supplying to the driving device composite image data obtained by combining the first and second image data stored in the frame memory, or composite image data stored in the frame memory. . In claim 10,
The period from the end timing of one image data of one of the first and second image data to the start timing of the next one frame of the other image data of the first and second image data is the shortest. An image processing method characterized in that the switching order is determined as follows.

Images