JP2007049273A - Host controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a host controller including a cut detection circuit for detecting cut between a host and a device with high precision and low power consumption. <P>SOLUTION: The host controller 400 includes a cut detection circuit 52-3 for detecting cut state between a host and a device by detecting the reflected wave of a frame packet occurring when a state where the host and the device are connected through a connection cable changes to a state where the device is cut from the connection cable. The cut detection circuit 52-3 compares the voltage level at a given timing after the frame packet of a first differential signal DP out of a pair of first and second differential signals DP and DM with a reflected wave comparison voltage RCV. If the voltage level at a given timing of at least one of the first and second differential signals DP and DM is higher than the reflected wave comparison voltage RCV, cut state between the host and the device is detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a host controller.

  In recent years, USB (Universal Serial Bus) has attracted attention as an interface standard for connecting a personal computer and peripheral devices (electronic devices in a broad sense). This USB has the advantage that peripheral devices such as mice, keyboards, and printers that were conventionally connected with connectors of different standards can be connected with connectors of the same standard, and so-called plug and play and hot plug can be realized. .

  On the other hand, this USB has a problem that the transfer speed is lower than that of IEEE 1394, which is also in the spotlight as a serial bus interface standard.

  Therefore, the USB 2.0 standard has been established that can realize a data transfer speed of 480 Mbps (HS (High Speed) mode) that is much faster than USB 1.1 while having backward compatibility with the conventional USB 1.1 standard. , Attracting attention. In addition, UTMI (USB 2.0 Transceiver Macrocell Interface) that defines interface specifications for USB 2.0 physical layer circuits and logic layer circuits has been established.

  In USB 2.0, in addition to the FS (Full Speed) mode defined in the conventional USB 1.1, a transfer mode called the HS mode described above is prepared. Since data transfer is performed at 480 Mbps in the HS mode, data transfer can be performed at a much higher speed than the FS mode in which data transfer is performed at 12 Mbps. Therefore, according to USB 2.0, an optimum interface can be provided for a storage device such as a hard disk drive or an optical disk drive that requires a high transfer speed.

  However, in USB 2.0, a signal having a small amplitude is transferred faster than USB 1.1. A small amplitude signal having a high frequency is greatly affected by the quality of the transmission line and the termination resistance of the host and the device. Therefore, in USB 2.0, the host controller needs a disconnection detection circuit capable of detecting the disconnection between the host and the device with high accuracy even for such a small amplitude signal that is easily affected.

Patent Document 1 discloses a window voltage comparator for determining whether a difference between two voltages of a differential signal line is larger or smaller than a set value. Patent Document 2 discloses that a squelch circuit that detects the presence / absence of a reception signal of a differential pair is provided, and detection of disconnection of the differential pair is detected using one voltage level.
JP 2002-232273 A JP 2002-344540 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a host controller including a disconnection detection circuit that can detect disconnection between a host and a device with low power consumption and high accuracy. Is to provide.

  The present invention provides a host controller that performs data transfer by a differential signal pair via a bus and transmits frame packets defined by a given standard to a device side at intervals defined by the given standard. The host-device disconnection state is detected by detecting the reflected wave of the frame packet that is generated when the host and device are connected via the connection cable to the device being disconnected from the connection cable. A disconnection detection circuit configured to perform a given signal after the frame packet of the first differential signal among the first and second differential signals constituting the differential signal pair. The voltage level at the timing and the reflected wave comparison voltage are compared, and the voltage level and the reflected wave comparison voltage at a given timing after the frame packet of the second differential signal are compared. On the other hand, if the voltage level at the given timing of at least one of the first and second differential signals is higher than the reflected wave comparison voltage, the host that detects the disconnection state between the host and the device Concerning the controller.

  Thus, even when the frame packet is affected by the reflected wave and the disconnection state cannot be detected even if the voltage level of the differential signal in the frame packet is monitored, the disconnection state between the host and the device is detected. Can do. Further, by doing this, it is possible to perform disconnection detection when the voltage level of at least one reflected wave of the first and second differential signals is higher than the reflected wave comparison voltage. As compared with the case where only one of the two differential signals is monitored, the disconnection detection can be performed with higher accuracy.

  Also, in the present invention, the disconnection detection circuit receives the first differential signal, the voltage level of the first differential signal at a given timing after the frame packet and the reflected wave comparison voltage When the voltage level of the first differential signal at a given timing in the previous period is higher than the reflected wave comparison voltage, the first reflected wave comparison for detecting the disconnection state between the host and the device And receiving the second differential signal, comparing the reflected wave comparison voltage with a voltage level at a given timing after the frame packet of the second differential signal, And a second reflected wave comparator for detecting a disconnection state between the host and the device when the voltage level of the second differential signal at the terminal is higher than the reflected wave comparison voltage. The circuit compares the first and second reflected waves. At least one of host - when detecting a disconnection between the device host - may be detected disconnection between devices.

  By doing in this way, the cutting | disconnection detection circuit can detect a cutting | disconnection state reliably also when the voltage level of the reflected wave of either the 1st or 2nd differential signal is higher than a reflected wave comparison voltage. Further, by connecting the first and second reflected wave comparators to the side where the first and second differential signals are supplied, the balance of the parasitic capacitance that affects the first and second differential signals is balanced. The signal quality of the differential signal can be improved compared to the case where the reflected wave comparator is provided on either one of the first and second differential signals.

  In the present invention, the first differential signal is received, the voltage level of the first differential signal is compared with the reflected wave comparison voltage, and the voltage level of the first differential signal in the previous period is the reflected wave. When the voltage is higher than the comparison voltage, the first reflected wave comparator for detecting the disconnection state between the host and the device, the second differential signal, the voltage level of the second differential signal, and the second differential signal are received. A second reflected wave comparator for comparing a reflected wave comparison voltage and detecting a disconnection state between the host and the device when the voltage level of the second differential signal in the previous period is higher than the reflected wave comparison voltage; A latch circuit that latches the logical sum of the output signals of the first and second reflected wave comparators based on the reflected wave detection signal, wherein the frame packet is transmitted as the reflected wave detection signal Set to active at a given time after The latch circuit latches the logical sum result based on the reflected wave detection signal set in the previous period, and the disconnection detection circuit is configured such that at least one of the first and second reflected wave comparators is a host-device. When disconnection between the host and the device is detected, disconnection between the host and the device may be detected.

  Also, in the present invention, the disconnection detection circuit receives the first differential signal, a voltage level corresponding to the given range in the frame packet of the first differential signal, and the comparison voltage A first comparator for detecting a disconnection state between the host and the device when the voltage level of the first differential signal corresponding to the given range is higher than the comparison voltage; The second differential signal is received, the voltage level corresponding to the given range in the frame packet of the second differential signal is compared with the comparison voltage, and the second differential signal corresponds to the given range. A second comparator for detecting a disconnection state between a host and a device when the voltage level of the second differential signal is higher than the comparison voltage, and the disconnection detection circuit includes the first differential signal. And at least one of the second comparators is a host-device When detecting the disconnection between the host - it may be detected disconnection between devices.

  In this way, the disconnection detection circuit can reliably detect the disconnection state even when the voltage level of either the first or second differential signal is higher than the comparison voltage. In addition, by connecting the first and second comparators to the side where the first and second differential signals are supplied, the parasitic capacitance affecting the first and second differential signals is balanced. Thus, the signal quality of the differential signal can be made better than when a comparator is provided on either one of the first and second differential signals.

  Also, in the present invention, the disconnection detection circuit receives an enable signal for performing enable control of the disconnection detection circuit, and the enable signal is set to turn on a constant current source of a transmission circuit on the host controller side, and When the frame packet is transmitted from the host to the device, it is set to active, and when the frame packet is not transmitted, it is set to inactive, and the disconnection detection circuit sets the enable signal to active. In such a case, the disconnection state between the host and the device may be monitored, and when the enable signal is set to non-active, the operation may be set to the off state.

  By doing in this way, operation | movement of a cutting | disconnection detection circuit can be controlled efficiently. For example, when it is not necessary to monitor the disconnection state, it is not necessary to send a wasteful current to the disconnection detection circuit, so that power consumption can be reduced. Further, since the voltage level of the differential signal corresponding to a given range in the frame packet is compared with the comparison voltage, the operation of the disconnection detection circuit can be turned off when the frame packet is not transmitted. Therefore, it is possible to suppress a wasteful current from flowing through the disconnection detection circuit, and it is possible to reduce power consumption.

  In the present invention, the first and second comparators include an output fixing switch for fixing the output to a ground level, and the output fixing switch is set to be off when the enable signal is active. If the enable signal is inactive, it may be set to ON.

  Thereby, even when the operation state of the first and second comparators is off, the output level of each comparator can be set to the ground level. It is possible to prevent the output level from becoming unstable. Therefore, erroneous detection of the disconnection detection circuit can be prevented.

  The present invention further includes a bias signal generation circuit that generates a bias signal for adjusting a current source of the first and second comparators, and the bias signal generation circuit includes the bias signal when the enable signal is active. A signal may be generated, and the bias signal may not be generated when the enable signal is inactive.

  Thus, the current sources of the first and second comparators can be controlled based on the enable signal, and current consumption can be reduced.

In the present invention, the first and second comparators include first and second differential amplifiers,
The first differential amplifier includes first and second input transistors provided in parallel between a first power source and a second power source, and the comparison voltage is applied to a gate of the first input transistor. , And one of the first and second differential signals is input to the gate of the second input transistor, and the second differential amplifier includes a first power source and the first A third and fourth input transistor provided in parallel between a second power supply having a power supply voltage higher than that of the power supply, wherein the gate of the third input transistor is connected to the first input transistor and the second input transistor; The fourth output transistor is connected to a first output node between the second power supply and the second output node between the second input transistor and the second power supply. Good.

  Thereby, even when the difference between the comparison voltage and the voltage level of one of the first and second differential signals is small, the comparison voltage and the voltage level of the differential signal can be compared.

  In the present invention, the first, second, third and fourth input transistors may be P-type transistors.

  In the present invention, the detection results of the first and second comparators are output based on a voltage level of a third output node between the fourth input transistor and the second power supply. Also good.

  Thereby, the comparison result between the comparison voltage and the voltage level of the first or second differential signal can be output as the detection result of the first or second comparator.

  In the present invention, the first and second input transistors may be P-type transistors, and the third and fourth input transistors may be N-type transistors.

  As a result, the third and fourth input transistors of the second differential amplifier can cope with the case where the voltage levels of the first and second output nodes swing at a high frequency. Therefore, the disconnection detection circuit can detect disconnection at high speed.

  In the present invention, the first and second comparators may generate a second differential amplifier bias signal for adjusting a current source of the second differential amplifier. The second differential amplifier bias signal generating circuit generates the second differential amplifier bias signal when the enable signal is active, and the enable signal is non-active. In this case, the second differential amplifier bias signal may not be generated.

  Thereby, the current source of the second differential amplifier can be controlled efficiently, and the power consumption of the disconnection detection circuit can be reduced.

  In the present invention, the detection results of the first and second comparators are output based on the voltage level of the third output node between the fourth input transistor and the first power supply. A host controller characterized by that.

  Thereby, the comparison result between the comparison voltage and the voltage level of the first or second differential signal can be output as the detection result of the first or second comparator.

  In the present invention, the given standard may be a USB 2.0 standard.

  Thereby, the disconnection detection circuit can be applied to a product compliant with the USB 2.0 standard.

  In the present invention, the frame packet may be an SOF (Start Of Frame) packet defined by the USB 2.0 standard.

  As a result, the disconnection detection circuit can accurately detect disconnection in the USB 2.0 standard.

  In the present invention, the given range may correspond to EOP (End Of Point) defined by the USB 2.0 standard.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention. In the following drawings, the same reference numerals have the same meaning.

1. USB2.0
According to USB 2.0 (a given standard in a broad sense), a plurality of peripheral devices (devices) compatible with USB 1.1 or USB 2.0 can be connected to a host via a hub device, for example.

  Such a host is equipped with a host controller compatible with USB 2.0. The host controller determines whether the connected device is compatible with USB 1.1 or UBS 2.0, and controls data transfer via the bus.

  The hub device is mounted with a hub controller compatible with USB 2.0, for example. The hub controller determines whether the peripheral device to be connected is compatible with USB 1.1 or USB 2.0, and controls the bus transfer method.

  A peripheral device (device) is also equipped with a device controller that supports USB 1.1 or USB 2.0. For example, when the device controller is compatible with USB 2.0, the device controller is a logic that performs data transfer control according to the physical layer circuit corresponding to the USB 1.1 and USB 2.0 interface standards and the mounted peripheral device. Layer circuit.

  The host controller in the present embodiment can perform data transfer defined by, for example, USB 2.0 via the bus.

2. Host Controller FIG. 1 shows an example of the configuration of the host controller 400 in this embodiment.

  The host controller 400 includes a logical layer circuit and a physical layer circuit, but is not limited thereto.

  The logic layer circuit includes a data handler circuit 10, an HS (High Speed) circuit 20, and an FS (Full Speed) circuit 30. The physical layer circuit includes an analog front end circuit 40. The host controller 400 does not have to include all of the circuit blocks, and a part of them may be omitted.

  The data handler circuit 10 performs various transmission processes and reception processes for data transfer conforming to USB 2.0. More specifically, at the time of transmission, the data handler circuit performs processing for adding SYNC (SYNChronization), SOP (Start Of Packet), EOP (End Of Packet) to transmission data, bit stuffing processing, and the like. On the other hand, at the time of reception, the data handler circuit 10 detects and deletes SYNC, SOP, and EOP of received data and performs processing such as bit unstuffing processing. Further, the data handler circuit 10 also performs processing for generating various timing signals for controlling data transmission / reception. Such a data handler circuit 10 is connected to an SIE (Serial Interface Engine).

  The SIE includes an SIE control logic for identifying a USB packet ID and an address, and an endpoint logic for performing endpoint processing such as identification of an endpoint number and FIFO control.

  The HS circuit 20 is a logic circuit for transmitting and receiving data at HS (High Speed) at which the data transfer rate is 480 Mbps.

  The FS circuit 30 is a logic circuit for transmitting and receiving data at FS (Full Speed) at which the data transfer rate is 12 Mbps.

  The analog front end circuit 40 is an analog circuit including a driver and a receiver for performing transmission / reception by FS and HS. In USB, data is transmitted and received by a differential pair of signals using DP (Data +, first differential signal in a broad sense) and DM (Data-, second differential signal in a broad sense).

  In addition, the host controller 400 in this embodiment includes various control signals for the 480 MHz clock used in the HS circuit 20, a clock circuit (not shown) that generates a 60 MHz clock inside the apparatus and used in the SIE, and the analog front end circuit 40. Further includes a control circuit (not shown) for generating.

  The HS circuit 20 includes a DLL (Delay Line PLL) circuit 22 and an elasticity buffer 24.

  The DLL circuit 22 generates a data sampling clock based on a clock generated by a clock circuit (not shown) and a received signal.

  The elasticity buffer 24 is a circuit for absorbing a clock frequency difference (clock drift) between the inside of the device and an external device (an external device connected to the bus).

  In USB 2.0, HS mode and FS mode are defined as transfer modes. The HS mode is a transfer mode newly defined by USB 2.0. The FS mode is a transfer mode already defined in the conventional USB 1.1.

  In the HS mode, data transmission / reception is performed between the data handler circuit 10 and the analog front end circuit 40 via the HS circuit 20.

  In the FS mode, data is transmitted and received between the data handler circuit 10 and the analog front end circuit 40 via the FS circuit 30.

  Therefore, in the analog front end circuit 40, an HS mode driver and receiver for transmitting and receiving DP and DM, which are differential pair transmission / reception signals, in the HS mode, an FS mode driver for transmitting and receiving in the FS mode, and A receiver is provided separately.

  More specifically, the analog front end circuit 40 includes an FS driver 42, an FS differential data receiver 44, an SE (Single Ended) _DP receiver 46, an SE_DM receiver 48, an HS current driver 50, a disconnection detection circuit 52, and an HS_SQ circuit 54. HS differential data receiver 56.

  In the FS mode, the FS driver 42 outputs a differential pair transmission signal composed of FS_DPout and FS_DMout from the FS circuit 30 as a differential pair transmission signal composed of DP and DM. The output of the FS driver 42 is controlled by FS_OutDis from the FS circuit 30.

  In the FS mode, the FS differential receiver 44 amplifies the reception signals of the DP and DM differential pairs and outputs the amplified signals to the FS circuit 30 as FS_DataIn. The amplification of the FS differential receiver 44 is controlled by FS_CompEnb.

  In the FS mode, the SE_DP receiver 46 amplifies DP, which is a single-ended reception signal, and outputs the amplified DP as SE_DPin to the FS circuit 30.

  The SE_DM receiver 48 amplifies DM, which is a single-ended received signal, in the FS mode, and outputs the amplified signal to the FS circuit 30 as SE_DMin.

  In the HS mode, the HS current driver 50 amplifies the differential pair transmission signal composed of HS_DPout and HS_DMout from the HS circuit 20 and outputs the amplified differential pair transmission signal composed of DP and DM. The output of the HS current driver 50 is controlled by HS_OutDis from the HS circuit 20, and the drive current is controlled by HS_CurrentSourceEnb.

  The disconnection detection circuit 52 monitors the connection state between the host and the device in the HS mode, and outputs HS_Disco as a disconnection detection result when the connection between the host and the device is disconnected. Details of the disconnection detection circuit 52 will be described later.

  In the HS mode, the HS_SQ circuit 54 detects the presence / absence of the received signal of the DP and DM differential pairs, and outputs HS_SQ to the HS circuit 20 as a signal detection result. The HS_SQ circuit 54 may be controlled in operation by HS_SQ_Enb from the HS circuit 20 and may be controlled in power saving by HS_SQ_Pwr.

  In the HS mode, the HS differential data receiver 56 amplifies the reception signals of the DP and DM differential pairs, and outputs HS_DataIn and HS_DataIn_L. The amplification of the HS differential receiver 56 is controlled by HS_RxEnb.

  Of the transmission / reception signals DP and DM of the differential pair, DP is connected (electrically) to the power supply voltage 3.3V via SW1 and the pull-up resistor Rpu. Also, DM of the differential pair transmission / reception signals is connected to SW2. SW1 and SW2 are controlled by RpuEnb. Considering the load balance, DM may be pulled up via SW2 via a resistor equivalent to the pullup resistor Rpu. RpuEnb connects DP to the pull-up resistor Rpu by at least SW1 in the FS mode.

  As described above, the data transfer control device is configured to include a driver and a receiver corresponding to transfer rates in the HS mode and the FS mode.

3. Disconnection detection 3.1. SOF
In the USB 2.0 standard, a SOF (Start Of Frame) packet is transmitted from the host controller to the device at given intervals. This given interval is defined by the USB 2.0 standard.

  The SOF packet transmitted from the host is composed of SYNC, PID (Packet Identifier), frame number, CRC5, and EOP (End Of Point), and has a total length of 96 bits. SYNC is defined by a 32-bit length. PID indicates a packet to be transmitted. In the case of SOF, PID is defined in A5h. The frame number indicates the frame number of the SOF packet. In the USB 2.0 standard HS mode, the frame number is incremented by 1 every 8 microframes. CRC5 is 5-bit data added to detect a bit error called Cyclic Redundancy Check. This is used to protect the frame number data. Thereby, the bit error can be detected with higher efficiency than the parity check.

  EOP is set to 40 bits in the HS mode. The EOP data is set to K or J state data continuously for 40 bits. In the USB 2.0 standard, the K state indicates a state where DM is at a high level and DP is at a low level. Conversely, the J state indicates a state in which DP is at a high level and DM is at a low level. The EOP data is set to either the K or J state depending on the frame number and CRC5 data. This is because in the USB 2.0 standard, data other than EOP is prohibited from being set to the same state (K or J state) continuously for 8 bits or more.

  FIG. 2 is a diagram for explaining an SOF packet defined by the USB 2.0 standard. FIG. 2 is not an actually measured signal waveform, but for simplicity of explanation, DM waveform amplitude is schematically illustrated, and data (PID, frame number, CRC5) is omitted. FIG. 2 shows the waveform amplitude of DM when the host-device is disconnected.

  In the USB 2.0 standard, when the host-device is in a connected state, an amplitude of 400 mV is ideally observed in the DP and DM of the host controller 400. As shown in FIG. 3A, an EOP can confirm an amplitude of 400 mV. When the host-device is disconnected, ideally, an amplitude of 800 mV is observed in the DP and DM of the host controller 400. As shown in FIG. 3B, an EOP amplitude of 800 mV can be confirmed. This is because the termination resistor on the device side is disconnected from the host in the disconnected state.

  That is, as shown in FIG. 2, for example, the cut voltage can be detected by setting the comparison voltage to 700 mV and comparing the waveform amplitude level of the SOF packet with the comparison voltage.

  Note that the USB 2.0 standard stipulates that the disconnection detection between the host and the device is performed when the amplitude level at the EOP of the SOF packet exceeds 525 mV to 625 mV, but a specific detection method is specified. Not.

3.2. Cut Detection Circuit of Comparative Example FIG. 4 shows a cut detection circuit 500 of a comparative example. The disconnection detection circuit 500 of FIG. 4 compares the amplitude level of either DM or DP (for example, DM) with the comparison voltage, and outputs the detection result. By doing so, when the waveform shown in FIG. 3A or FIG. 3B is transmitted as an SOF packet, either the connection state or the disconnection state between the host and the device can be detected.

  However, since the EOP amplitude of the SOF packet is such that DP and DM are differential signals, DM is low when DP is high. Conversely, when DM is at a high level, DP is at a low level. That is, in the disconnection detection circuit 500 of the comparative example that only sees the amplitude on the DM side, when the DM amplitude level is low in the EOP of the SOF packet, the disconnection state between the host and the device cannot be detected correctly. . In this case, correct disconnection detection cannot be performed until an SOF packet having a high DM amplitude level in EOP is transmitted.

  In the disconnection detection circuit 500 of the comparative example, the disconnection detection circuit 500 is connected only to the host-side DM, and the disconnection detection circuit 500 is not connected to the host-side DP. Since the HS mode of the USB 2.0 standard is a mode for performing high-speed data transfer, the accuracy required for DP and DM from which a differential signal is output is severe. For example, in order to correctly read data from a differential signal, it is important that the capacitance and resistance added to DP and DM are the same for both DP and DM.

  In this regard, in the comparative example, as described above, the disconnection detection circuit 500 is connected to the DM side of the host. For example, the gate capacitance of the input transistor of the disconnection detection circuit 500 is an additional capacitance with respect to DM. On the other hand, in the comparative example, the disconnection detection circuit 500 is not connected to the DP side of the host, and as a result, the DP and DM capacities (for example, wiring capacities, etc.) are greatly different on the host side. If the DP and DM capacities are different, the eye pattern of the differential signal is disturbed and the signal quality is degraded. Also, if the DP and DM capacities on the host side are different, not only will the quality of the differential signal transmitted from the host to the device deteriorate, but also when the host side receives the differential signal transmitted from the device side. Reducing the quality of the received signal. As described above, the disconnection detection circuit 500 according to the comparative example causes the signal quality of the differential signal transferred between the host and the device to deteriorate.

  The waveforms in FIGS. 3A and 3B are close to the ideal state, and the termination resistances on the host side and the device side, and the connection portion (for example, connection cable) connecting the host and the device are USB 2.0. It is a waveform of the SOF packet when it conforms to the standard.

  There are cases where products that do not satisfy the USB 2.0 standard are on the market. For example, if at least one of the DP-side termination resistor and the DM-side termination resistor of the device does not satisfy the USB 2.0 standard, the waveform of the SOF packet is disturbed. For example, if the termination resistance on the DP side of the device meets the standard and the termination resistance on the DM side of the device does not meet the standard, signal reflection occurs on the DM side of the device, and waveform disturbance occurs in the SOF packet on the DM side. . As a result, the EOP amplitude of the SOF packet on the DM side is far from the ideal state, and the disconnection detection circuit 500 of the comparative example that only sees the DM may not be able to detect the disconnection state correctly.

3.3. Cut Detection Circuit A part of the cut detection circuit 52 of the present invention is shown in FIG. The disconnection detection circuit 52 includes first and second comparators CMP1 and CMP2. The first comparator CMP1 compares the signal level of DP with the comparison voltage CV, and outputs a detection signal COMP_OUT_DP as the comparison result. The second comparator CMP2 compares the signal level of DM with the comparison voltage CV, and outputs a detection signal COMP_OUT_DM as the comparison result.

  The detection signals COMP_OUT_DP and COMP_OUT_DM are input to the NOR circuit, and an output signal from the NOR circuit is output as a disconnection detection signal HS_Disco through an inverter. Note that the NOR circuit and the inverter of the disconnection detection circuit 52 are examples, and the disconnection detection circuit 52 may be configured by replacing the NOR circuit and the inverter with an OR circuit, for example.

  As described above, the disconnection detection circuit 52 according to the present invention compares the signal levels of both DP and DM with the comparison voltage CV using the individual comparators, and at least one of the comparators CMP1 and CMP2. When the disconnection state is detected, for example, the disconnection detection signal HS_Disco set to active is output.

  By doing so, it becomes possible to monitor the signal waveforms of DP and DM, and it is possible to accurately detect the disconnection between the host and the device regardless of whether the EOP is in the K or J state.

  The first and second comparators CMP1 and CMP2 can be configured with similar circuits. This makes it possible to make the parasitic capacitances such as the DP and DM wiring capacitances equal, and to reduce signal quality degradation compared to the comparative example of FIG.

3.3.1. Specific Example of Cut Detection Circuit FIG. 6 shows a specific configuration example of a part of the cut detection circuit 52. The disconnection detection circuit 52-1 includes the first and second comparators CMP1 and CMP2, the control circuit 100, and the bias circuit 110 (bias signal generation circuit in a broad sense), but is not limited thereto. For example, the disconnection detection circuit 52-1 may be configured not to include the control circuit 100.

  The control circuit 100 receives an enable signal EN from an upper layer circuit (for example, the data handler circuit 10 in FIG. 1), and receives the control signal XENH based on the enable signal EN as a first comparator, a second comparator CMP1, CMP2, and a bias circuit. 110. When receiving the enable signal EN set to active, the control circuit 100 sets the control signal XENH to active. On the contrary, when receiving the enable signal EN set to non-active, the control circuit 100 sets the control signal XENH to non-active.

  The bias circuit 110 generates a bias signal BP based on the control signal XENH from the control circuit 100 and outputs it to the first and second comparators CMP1 and CMP2. Specifically, when the control signal XENH is set to active, the bias circuit 110 sets the bias signal BP from the high level to the low level. Conversely, when the control signal XENH is set to non-active, the bias circuit 110 sets the bias signal BP at a high level.

  The current sources of the first and second comparators CMP1 and CMP2 are adjusted based on the signal level of the bias signal BP. Specifically, when the bias signal BP is set to a low level, the current sources of the comparators CMP1 and CMP2 are set to on, and when the bias signal BP is set to a high level, each comparator CMP1. , CMP2 current source is set to OFF.

  Further, the first and second comparators CMP1 and CMP2 detect the comparison result between DP (or DM) and the comparison voltage CV when the control signal XENH from the control circuit 100 is set to active, as a detection signal COMP_OUT_DP. (Or COMP_OUT_DM). On the other hand, when the control signal XENH is set to non-active, the first and second comparators CMP1 and CMP2 set the signal levels of the detection signals COMP_OUT_DP and COMP_OUT_DM to a low level.

  That is, the detection signals COMP_OUT_DP and COMP_OUT_DM of the comparators CMP1 and CMP2 are set to either a comparison result of DP (or DM) and the comparison voltage CV or a low level signal based on the enable signal EN. For example, the enable signal EN is set to non-active when the operation of the disconnection detection circuit 52-1 is set to an off state.

  The disconnection detection circuit 52-1 can operate with low power consumption, and the output levels of the comparators CMP1 and CMP2 become unstable even when the disconnection detection circuit 52-1 is set to the off state. There is a fear. On the other hand, in the present embodiment, when the enable signal EN is set to non-active, the outputs of the comparators CMP1 and CMP2 are set to low level signals. It is possible to prevent the comparators CMP1 and CMP2 from performing erroneous detection in the off state.

  The enable signal EN is set to active when a packet is transmitted from the host to the device and when the transmitted packet is an SOF packet. In this way, when no SOF packet is transmitted from the host or when no packet is transmitted from the host, the power consumed by the disconnection detection circuit 52-1 can be suppressed to the limit. For example, when the enable signal EN is set to non-active, the bias signal BP output from the bias circuit 110 is set to a high level. For this reason, the current sources of the first and second comparators CMP1 and CMP2 are set to OFF, and wasteful current consumption can be cut when the operation of the disconnection detection circuit 52-1 is unnecessary.

(Comparator)
FIG. 7 shows a configuration example of the first comparator CMP1. The second comparator CMP2 has a circuit configuration similar to that of the first comparator CMP1. The comparator CMP1 includes p-type MOS transistors PTR1 to PTR3 (current source in a broad sense), an n-type MOS transistor FNT (output fixed switch in a broad sense), and NTR1. The comparator CMP1 includes a first differential amplifier 200 and a second differential amplifier 210. A bias signal BP supplied from the bias circuit 110 in FIG. 6 is input to the gates of the transistors PTR1 to PTR3. Based on the voltage level of the bias signal BP, the current supplied to the differential amplifiers 200 and 210 and the current supplied to the node ND5 are adjusted.

  A control signal XENH supplied from the control circuit 100 of FIG. 6 is input to the gate of the n-type MOS transistor FNT. When receiving the active enable signal EN as described above, the control circuit 100 sets the control signal XENH to active. At this time, the control signal XENH is set to a low level, for example. As a result, the bias signal BP set to, for example, a low level from the bias circuit 110 is supplied to the comparators CMP1 and CMP2. Further, in response to the control signal XENH set to the low level, the n-type transistor FNT in FIG. 7 is turned off, and the comparison result between the voltage levels of the comparison voltage CV and the differential signal DM (or DP) is the detection signal COMP_OUT_DM (COMP_OUT_DP). Is output as

  The first differential amplifier 200 includes a first input transistor IPT1 and a second input transistor IPT2. The first and second input transistors IPT1 and IPT2 are p-type MOS transistors, and the comparison voltage CV is input to the gate of the first input transistor IPT1. The differential signal DM (or DP) is input to the gate of the second bathing transistor IPT2.

  The second differential amplifier 210 includes a third input transistor IPT3 and a fourth input transistor IPT4. The third and fourth input transistors IPT3 and IPT4 are p-type MOS transistors, and the gate of the third input transistor IPT3 is connected to the node ND2 (second output node in a broad sense) of the first differential amplifier 200. Connected. The gate of the fourth input transistor IPT4 is connected to the node ND1 (first output node in a broad sense) of the first differential amplifier 200.

  The gate of the n-type transistor NTR1 is connected to the node ND4 of the second differential amplifier 210.

  As described above, when the enable signal EN supplied to the control circuit 100 in FIG. 6 is set to active, the bias signal BP of the bias circuit 110 is activated. As a result, the p-type transistors PTR1 to PTR3 of the comparators CMP1 and CMP2 are turned on, the differential amplifiers 200 and 210 of the comparators CMP1 and CMP2 are activated, and the comparison voltage CV and the differential signal DM (or DP). The potential of the node ND4 (third output node in a broad sense) of the second differential amplifier 210 changes according to the signal level difference between the first and second differential amplifiers 210. The n-type transistor NTR1 is controlled according to the potential of the node ND4, and the comparison result between the comparison voltage CV and the differential signal DM (or DP) is output as the detection signal COMP_OUT_DM (COMP_OUT_DP).

  Next, the operations of the comparators CMP1 and CMP2 will be described with reference to the waveform diagrams of FIGS. 8A to 8D and FIGS. 9A to 9D. 8A to 8D are waveform diagrams when the host and the device are in a connected state, and FIGS. 9A to 9D are disconnected between the host and the device. It is a wave form diagram in a state. Further, in FIGS. 8A to 8D and FIGS. 9A to 9D, the comparison voltage CV is set to, for example, 600 mV as shown in FIG. 8A.

  In FIG. 8A, A1 indicates EOP of the differential signal DP, for example, and A2 indicates EOP of the differential signal DM, for example. 8A indicates, for example, EOP of the differential signal DM, and A4 indicates, for example, EOP of the differential signal DP.

  First, the operation of the disconnection detection circuit 52-1 when the host-device is not disconnected will be described. When the host-device is connected, as shown in A1 and A3 in FIG. 8A, the voltage levels of the EOPs of the differential signals DP and DM when the SOF packet is transmitted are equal to the comparison voltage CV. Below the voltage level. In this case, the disconnection detection circuit 52 must output a signal indicating that the host-device is connected.

  At this time, the voltage levels of the nodes ND1 of the comparators CMP1 and CMP2 in FIG. 7 are low as shown by A6 and A8 in FIG. 8B, and the voltage level of the node ND2 is shown by A5 and A7. Become high level. This is because the voltage level input to the gate of the input transistor IPT1 is higher than the voltage level input to the gate of the input transistor IPT2. 8B is a waveform diagram showing the voltage levels of the nodes ND1 and ND2 in FIG. 7, and A5 to A8 are the voltage levels of the nodes ND1 and ND2 in the period corresponding to the EOP of the differential signals DP and DM. It is.

  Accordingly, a high level voltage is input to the gate of the input transistor IPT3 of the differential amplifier 210 of FIG. 7, and a low level voltage is input to the gate of the input transistor IPT4. Accordingly, the voltage level of the node ND4 at this time becomes a high level as indicated by A9 and A11 in FIG. 8C. Note that the voltage level of the node ND3 is low as indicated by A10 and A12 in FIG.

  Since the voltage level of the node ND4 is set to the high level, the n-type transistor NTR1 is turned on, and the voltage level of the node ND5 changes to the ground level side. Therefore, as indicated by A13 in FIG. 8D, the voltage levels of the detection signals COMP_OUT_DM and COMP_OUT_DP of the comparators CMP1 and CMP2 are set to a low level. That is, the disconnection detection circuit 52-1 of FIG. 6 can output a detection signal indicating that disconnection has not occurred without erroneously detecting disconnection when the host-device is connected.

  A14 indicates the voltage level of the enable signal EN in FIG. When the disconnection is detected, the enable signal EN is set to the high level (active), and accordingly, the bias signal BP is set from the high level to the low level as indicated by A15 in FIG. 8D. Thereby, a current flows between the source and drain of each of the transistors PTR1 to PTR3 in FIG.

  Next, the operation of the disconnection detection circuit 52-1 when the host-device is disconnected will be described. When the host-device is disconnected, as shown in B1 and B3 in FIG. 9A, the voltage levels of the differential signal DP and DM EOP when the SOF packet is transmitted are compared. It is higher than the voltage level of the voltage CV. In this case, the disconnection detection circuit 52 must output a signal indicating that the host-device is disconnected.

  For example, in the EOP of the SOF packet, when the differential signals DP and DM are as indicated by B1 and B2 in FIG. 9A, the comparison voltage CV is input to the gate of the input transistor IPT1 of the comparator CMP1 in FIG. A differential signal DP having a voltage level higher than the comparison voltage CV is input to the gate of the input transistor IPT2 of the comparator CMP1 as shown in FIG.

  As a result, the voltage level of the node ND1 of the comparator CMP1 in FIG. 7 becomes a high level as indicated by B5 in FIG. 9B, and the voltage level of the node ND2 of the comparator CMP1 becomes a low level as indicated by B6. . Accordingly, a low level voltage is input to the gate of the input transistor IPT3 of the differential amplifier 210 of the comparator CMP1, and a high level voltage is input to the gate of the input transistor IPT4. That is, the voltage level of the node ND3 of the differential amplifier 210 is higher than the voltage level of the node ND4 of B8 as indicated by B7 in FIG. 9C, and the voltage level of the node ND4 is B8 of FIG. 9C. As shown, it goes low.

  Accordingly, since a low level voltage is input to the gate of the n-type transistor NTR1 of the comparator CMP1 in FIG. 7, the voltage level of the node ND5 in FIG. 7 becomes a level adjusted by the p-type transistor PTR3. The detection signal COMP_OUT_DP of CMP1 becomes high level.

  On the other hand, on the side of the comparator CMP2 to which the differential signal DM is input, the comparison voltage CV is input to the gate of the input transistor IPT1 of the comparator CMP2 of FIG. 7, and the gate of the input transistor IPT2 of the comparator CMP2 is A differential signal DM having a voltage level lower than the comparison voltage CV is input as indicated by B2 in 9 (A).

  As a result, the voltage level of the node ND1 of the comparator CMP2 in FIG. 7 becomes a low level as indicated by B9 in FIG. 9B, and the voltage level of the node ND2 of the comparator CMP2 becomes a high level as indicated by B10. . Therefore, a high level voltage is input to the gate of the input transistor IPT3 of the differential amplifier 210 of the comparator CMP2, and a low level voltage is input to the gate of the input transistor IPT4. That is, the voltage level of the node ND3 of the differential amplifier 210 is lower than the voltage level of the node ND4 of B12, as indicated by B11 in FIG. 9C, and the voltage level of the node ND4 is B12 of FIG. 9C. High level as shown.

  Accordingly, since a high level voltage is input to the gate of the n-type transistor NTR1 of the comparator CMP2 in FIG. 7, the voltage level of the node ND5 in FIG. It changes to the ground level side as well.

  As described above, the detection signal COMP_OUT_DP of the comparator CMP1 is set to a high level, and the detection signal COMP_OUT_DM of the comparator CMP2 is set to a low level. That is, the disconnection detection circuit 52-1 outputs a high level signal as indicated by B13 in FIG. 9D, and detects the disconnection state between the host and the device. This is disconnection detection when the voltage level of the differential signal DP exceeds the voltage level of the comparison voltage CV as indicated by B1 in FIG. 9A, and disconnection detection is indicated as indicated by B13 in FIG. 9D. The circuit 52-1 can detect disconnection immediately by comparing the differential signal DP of B1 of FIG. 9A with the comparison voltage CV.

  Note that B14 in FIG. 9D indicates the voltage level of the enable signal EN in FIG. 6 as in FIG. 8D, and B15 indicates the bias signal BP.

  Further, as shown by B3 and B4 in FIG. 9A, in the EOP of the SOF packet, the voltage level of the differential signal DM is higher than the voltage level of the comparison voltage CV, and the voltage level of the differential signal DP is higher than the comparison voltage CV. 7 is input to the gate of the input transistor IPT1 of the comparator CMP1 in FIG. 7, and the gate of the input transistor IPT2 of the comparator CMP1 is input to the gate of the input transistor IPT2 as shown in FIG. A differential signal DM having a voltage level higher than that of the comparison voltage CV is input.

  The operation of the disconnection detection circuit 52-1 in this case is almost the same as the case where the voltage level of the differential signal DP is higher than the voltage level of the comparison voltage CV, and the waveform indicating the voltage level of each of the nodes ND1 to ND4. Only the comparators CMP1 and CMP2 are switched.

  For example, B16 in FIG. 9B indicates the voltage level of the node ND1 of the comparator CMP2, and B17 indicates the voltage level of the node ND2 of the comparator CMP2. B18 indicates the voltage level of the node ND1 of the comparator CMP1, and B19 indicates the voltage level of the node ND2 of the comparator CMP1.

  Similarly, B20 in FIG. 9C indicates the voltage level of the node ND3 of the comparator CMP2, and B21 indicates the voltage level of the node ND4 of the comparator CMP2. B22 indicates the voltage level of the node ND3 of the comparator CMP1, and B23 indicates the voltage level of the node ND4 of the comparator CMP1.

  As a result, since a high level voltage is input to the gate of the n-type transistor NTR1 of the comparator CMP1 in FIG. 7, the detection signal COMP_OUT_DP of the comparator CMP1 becomes a low level. Further, since a low level voltage is input to the gate of the n-type transistor NTR1 of the comparator CMP2, the detection signal COMP_OUT_DM of the comparator CMP2 becomes high level. That is, the disconnection detection circuit 52-1 outputs a high level signal to detect disconnection as indicated by B24 in FIG.

  As described above, the disconnection detection circuit 52-1 can immediately detect disconnection even when the voltage level of the differential signal DM exceeds the voltage level of the comparison voltage CV.

  As described above, the disconnection detection circuit 52-1 can immediately detect disconnection between the host and the device when the voltage level of one of the differential signals DP and DM exceeds the comparison voltage CV.

3.3.2. Modification of Cut Detection Circuit FIG. 10 shows a modification of a specific configuration example of a part of the cut detection circuit 52. 10 includes a first and second comparators CMP1, CMP2, a control circuit 100, and a bias circuit 112 (a bias signal generating circuit in a broad sense, a second differential amplifier bias signal generating circuit). ), But is not limited to this. For example, the disconnection detection circuit 52-2 may not include the control circuit 100.

  The control circuit 100 may have the same configuration as the disconnection detection circuit 52-1, and supplies the control signal XENH to the first and second comparators CMP1 and CMP2 and the bias circuit 112 based on the enable signal EN.

  The bias circuit 112 generates bias signals BP and BN (second differential amplifier bias signal in a broad sense) based on the control signal XENH from the control circuit 100, and the first and second comparators CMP1, CMP2 Output to. Specifically, when the control signal XENH is set to active, the bias circuit 110 sets the bias signal BP from a high level to a low level and sets the bias signal BN from a low level to a high level. On the other hand, when the control signal XENH is set to non-active, the bias circuit 110 sets the bias signal BP at a high level and keeps the bias signal BN at a low level.

  The current sources of the first and second comparators CMP1 and CMP2 are adjusted based on the signal levels of the bias signals BP and BN. Specifically, as shown in FIG. 11, when the bias signal BP is set to a low level, the current source of the first differential amplifier 200 of each of the comparators CMP1 and CMP2 is set to ON. When the bias signal BP is set to the high level, the current source of the first differential amplifier 200 of each of the comparators CMP1 and CMP2 is set to OFF. Similarly, when the bias signal BN is set to the high level, the current source of the second differential amplifier 210 of each of the comparators CMP1 and CMP2 is set to on, and the bias signal BN is set to the low level. In this case, the current source of the second differential amplifier 210 of each of the comparators CMP1 and CMP2 is set off.

  The difference between the disconnection detection circuit 52-2 and the disconnection detection circuit 52-1 is the configuration of the bias circuit 112 and the comparators CMP1 and CMP2. In other respects, the disconnection detection circuit 52-2 is the same as the disconnection detection circuit 52-1.

(Comparator)
FIG. 11 shows a configuration example of the first comparator CMP1 of the disconnection detection circuit 52-2 according to the modification. The second comparator CMP2 has a circuit configuration similar to that of the first comparator CMP1. The comparator CMP1 of FIG. 11 includes a first differential amplifier 200 and a second differential amplifier 220. The difference between the comparator CMP1 of the disconnection detection circuit 52-1 and the comparator CMP1 of the modification is the second differential amplifiers 210 and 220. Other configurations are the same as the disconnection detection circuits 52-1 and 52-2.

  The second differential amplifier 220 includes a third input transistor INT1 and a fourth input transistor INT2. The third and fourth input transistors INT1 and INT2 are n-type MOS transistors, and the gate of the third input transistor INT1 is connected to the node ND2 of the first differential amplifier 200. The gate of the fourth input transistor INT2 is connected to the node ND1 of the first differential amplifier 200.

  The second differential amplifier 220 includes an n-type transistor NTR2, and the bias signal BN from the bias circuit 112 in FIG. 10 is input to the gate of the n-type transistor NTR2. The current supplied to the differential amplifier 220 is adjusted based on the voltage level of the bias signal BN.

  The gate of the n-type transistor NTR1 is connected to the node ND14 of the second differential amplifier 220.

  When receiving the active enable signal EN as described above, the control circuit 100 sets the control signal XENH to active. At this time, the control signal XENH is set to a low level, for example. Thereby, the bias signal BP set from the high level to the low level, for example, and the bias signal BN set from the low level to the high level, for example, are supplied from the bias circuit 112 to the comparators CMP1 and CMP2. As a result, the transistors PTR1 and NTR2 which are current sources of the differential amplifiers 200 and 220 are turned on.

  As described above, when the enable signal EN supplied to the control circuit 100 of FIG. 10 is set to active, the bias signals BP and BN of the bias circuit 112 are made active. As a result, the current sources of the comparators CMP1 and CMP2 are turned on, the differential amplifiers 200 and 220 of the comparators CMP1 and CMP2 are activated, and the signal level between the comparison voltage CV and the differential signal DM (or DP). The potential of the node ND14 of the second differential amplifier 220 changes according to the difference. The n-type transistor NTR1 is controlled according to the potential of the node ND14, and the comparison result between the comparison voltage CV and the differential signal DM (or DP) is output as the detection signal COMP_OUT_DM (COMP_OUT_DP).

  Next, operations of the comparators CMP1 and CMP2 in the modification will be described with reference to waveform diagrams of FIGS. 12A to 12D and 13A to 13D. 12A to 12D are waveform diagrams when the host and the device are in a connected state, and FIGS. 13A to 13D are disconnected between the host and the device. It is a wave form diagram in a state. Further, in FIGS. 12A to 12D and FIGS. 13A to 13D, the comparison voltage CV is set to, for example, 600 mV as shown in FIG. 8A.

  In FIG. 12A, A1 indicates, for example, EOP of the differential signal DP, and A2 indicates, for example, EOP of the differential signal DM. Further, A3 in FIG. 12A indicates EOP of the differential signal DM, for example, and A4 indicates EOP of the differential signal DP, for example. The waveforms in FIGS. 12A and 12B are the same as those in FIGS. 8A and 8B. In the disconnection detection circuits 52-1, 52-2, the first differential amplifier 200 operates in the same manner. Therefore, if the input differential signals DP, DM are the same, the waveforms of the nodes ND1, ND2 are substantially the same. Become.

  First, the operation of the disconnection detection circuit 52-2 when the host-device is not disconnected will be described. When the host-device is connected, as shown in A1 and A3 of FIG. 12A, the voltage levels of the differential signals DP and DM EOP when the SOF packet is transmitted are equal to the comparison voltage CV. Below the voltage level. In this case, the disconnection detection circuit 52-2 must output a signal indicating that the host-device is connected.

  At this time, the voltage levels of the nodes ND1 of the comparators CMP1 and CMP2 in FIG. 11 are low levels as indicated by A6 and A8 in FIG. 12B, and the voltage levels of the nodes ND2 are indicated by A5 and A7. Become high level. FIG. 12B is a waveform diagram showing voltage levels of the nodes ND1 and ND2 in FIG.

  Accordingly, a high level voltage is input to the gate of the input transistor INT1 of the differential amplifier 220 in FIG. 11, and a low level voltage is input to the gate of the input transistor INT2. Accordingly, the voltage level of the node ND4 at this time becomes a high level as indicated by C1 and C3 in FIG. Note that the voltage level of the node ND3 is low as indicated by C2 and C4 in FIG.

  Since the voltage level of the node ND4 is set to the high level, the n-type transistor NTR1 is turned on, and the voltage level of the node ND5 changes to the ground level side. Accordingly, as indicated by C5 in FIG. 12D, the voltage levels of the detection signals COMP_OUT_DM and COMP_OUT_DP of the comparators CMP1 and CMP2 are set to a low level. That is, the disconnection detection circuit 52-2 in FIG. 10 can output a detection signal indicating that disconnection has not occurred without erroneously detecting disconnection when the host-device is connected.

  Note that C7 in FIG. 12D indicates the voltage level of the enable signal EN in FIG. When the disconnection is detected, the enable signal EN is set to a high level (active), and accordingly, the bias signal BP is set from a high level to a low level as indicated by C8 in FIG. Further, the bias signal BN is set from the low level to the high level as indicated by C6. As a result, a current flows between the source and drain of each of the transistors PTR1, PTR3, and NTR2 in FIG.

  Next, the operation of the disconnection detection circuit 52-2 when the host-device is disconnected will be described. When the host-device is disconnected, the voltage levels of the differential signal DP and DM EOP when the SOF packet is transmitted are compared as indicated by D1 and D3 in FIG. It is higher than the voltage level of the voltage CV. In this case, the disconnection detection circuit 52-2 must output a signal indicating that the host-device is disconnected.

  For example, in the EOP of the SOF packet, when the differential signals DP and DM are as indicated by D1 and D2 in FIG. 13A, the comparison voltage CV is input to the gate of the input transistor IPT1 of the comparator CMP1 in FIG. A differential signal DP having a voltage level higher than the comparison voltage CV is input to the gate of the input transistor IPT2 of the comparator CMP1 as shown in FIG.

  As a result, the voltage level of the node ND1 of the comparator CMP1 in FIG. 11 becomes a high level as indicated by D5 in FIG. 13B, and the voltage level of the node ND2 of the comparator CMP1 becomes a low level as indicated by D6. . Accordingly, a low level voltage is input to the gate of the input transistor INT1 of the differential amplifier 220 of the comparator CMP1, and a high level voltage is input to the gate of the input transistor INT2. That is, the voltage level of the node ND3 of the differential amplifier 220 is higher than the voltage level of the node ND4 of D8 as indicated by D7 in FIG. 13C, and the voltage level of the node ND4 is D8 of FIG. 13C. As shown, it goes low.

  Accordingly, since a low level voltage is input to the gate of the n-type transistor NTR1 of the comparator CMP1 in FIG. 11, the voltage level of the node ND5 in FIG. 11 becomes a level adjusted by the p-type transistor PTR3. The detection signal COMP_OUT_DP of CMP1 becomes high level.

  On the other hand, on the side of the comparator CMP2 to which the differential signal DM is input, the comparison voltage CV is input to the gate of the input transistor IPT1 of the comparator CMP2 in FIG. 11, and the gate of the input transistor IPT2 of the comparator CMP2 is A differential signal DM having a voltage level lower than the comparison voltage CV is input as indicated by D2 in 13 (A).

  As a result, the voltage level of the node ND1 of the comparator CMP2 in FIG. 11 becomes a low level as indicated by D9 in FIG. 13B, and the voltage level of the node ND2 of the comparator CMP2 becomes a high level as indicated by D10. . Accordingly, a high level voltage is input to the gate of the input transistor INT1 of the differential amplifier 220 of the comparator CMP2, and a low level voltage is input to the gate of the input transistor INT2. That is, the voltage level of the node ND3 of the differential amplifier 220 is lower than the voltage level of the node ND4 of D12, as indicated by D11 of FIG. 13C, and the voltage level of the node ND4 is D12 of FIG. 13C. High level as shown.

  Accordingly, since a high level voltage is input to the gate of the n-type transistor NTR1 of the comparator CMP2 in FIG. 11, the voltage level of the node ND5 in FIG. It changes to the ground level side as well.

  As described above, the detection signal COMP_OUT_DP of the comparator CMP1 is set to a high level, and the detection signal COMP_OUT_DM of the comparator CMP2 is set to a low level. That is, the disconnection detection circuit 52-2 outputs a high level signal as indicated by D13 in FIG. 13D, and detects the disconnection state between the host and the device. This is disconnection detection when the voltage level of the differential signal DP exceeds the voltage level of the comparison voltage CV as indicated by D1 in FIG. 13A, and disconnection detection is indicated as indicated by D13 in FIG. The circuit 52-2 can immediately detect disconnection by comparing the differential signal DP of D1 in FIG. 13A and the comparison voltage CV.

  Note that C7 in FIG. 13D indicates the voltage level of the enable signal EN in FIG. 10 as in FIG. 12D, C6 indicates the bias signal BN, and C8 indicates the bias signal BP.

  Further, as indicated by B3 and B4 in FIG. 13A, in the EOP of the SOF packet, the voltage level of the differential signal DM is higher than the voltage level of the comparison voltage CV, and the voltage level of the differential signal DP is higher than the comparison voltage CV. 11 is input to the gate of the input transistor IPT1 of the comparator CMP1 in FIG. 11, and the gate of the input transistor IPT2 of the comparator CMP1 is as shown in FIG. 11A. A differential signal DM having a voltage level higher than that of the comparison voltage CV is input.

  The operation of the disconnection detection circuit 52-2 in this case is almost the same as that when the voltage level of the differential signal DP is higher than the voltage level of the comparison voltage CV, and the waveform indicating the voltage level of each of the nodes ND1 to ND4. Only the comparators CMP1 and CMP2 are switched. Accordingly, the disconnection detection circuit 52-2 outputs a high level signal as indicated by D14 in FIG. 13D, and detects the disconnection state between the host and the device. Also in this case, as shown by D14 in FIG. 13D, the disconnection detection circuit 52-2 can detect the disconnection immediately by comparing the differential signal DP of D1 in FIG. 13A and the comparison voltage CV. Is possible.

Here, when the disconnection detection circuit 52-1 and the disconnection detection circuit 52-2 are compared, the period during which the detection signal is at a high level when disconnection detection is performed differs. In the case of the disconnection detection circuit 52-1, for example, a signal indicating disconnection detection is set to a high level during a period corresponding to EOP of the differential signals DP and DM, as indicated by B25 in FIG. 9D. In the disconnection detection circuit 52-2 of the modified example, disconnection is performed in a period corresponding to EOP of the differential signals DP and DM as shown in D15 of FIG. 13D and in a period other than EOP as shown in D16. A signal indicating detection is set to a high level. That is, the comparators CMP1 and CMP2 of the disconnection detection circuit 52-2 can compare the voltage levels of the differential signals DP and DM in the period before EOP with the comparison voltage CV. In a period prior to EOP, the differential signals DP and DM have an amplitude at a high frequency as shown in FIGS. 9A and 13A. For this reason, the comparators CMP1 and CMP2 of the disconnection detection circuit 52-1 cannot follow the differential signals DP and DM that are amplified at a high frequency.

  On the other hand, the comparators CMP1 and CMP2 used in the disconnection detection circuit 52-2 of the modified example include the third and fourth input transistors INT1 and INT2 of the second differential amplifier 220 as shown in FIG. Is composed of n-type transistors. Since the n-type transistor can be switched at higher speed than the p-type transistor, the comparators CMP1 and CMP2 in FIG. 11 can operate faster than the comparators CMP1 and CMP2 in FIG. The voltage level of the comparison voltage CV can also be compared with the differential signals DP and DM having amplitude.

  Further, the comparators CMP1 and CMP2 in FIG. 11 can be regarded as the differential amplifier 210 of the comparators CMP1 and CMP2 in FIG. The power consumption of the differential amplifiers 210 and 220 can be made substantially the same. Therefore, in the modified example, high-speed operation can be realized while maintaining low power consumption.

  As described above, the disconnection detection circuit 52-2 according to the modification can detect disconnection even before the EOP, and disconnects faster than the disconnection detection circuit 52-1 when the host-device is disconnected. Detection can be performed.

4). Reflected wave comparison detection The host and the device may be connected via a cable having a predetermined length, for example. At this time, the receptacle on the host side is the A receptacle, and the receptacle on the device side is the B receptacle. When the cable is disconnected from the device at the B receptacle, the host-device is disconnected. In this case, the SOF packet is reflected at the B receptacle side at both ends of the cable, and the reflected wave is observed at the A receptacle side. The When the cable is cut from the host on the A receptacle side, this reflected wave is hardly seen.

  The effect of this reflected wave increases as the cable length increases, and FIGS. 14A and 14B each perform cutting on the B receptacle side when, for example, 5 m and 10 m cables are used. Shows a waveform diagram of the SOF packet observed on the A receptacle side in the case of

  As indicated by E1 in FIG. 14A and E2 in FIG. 14B, the differential signals DP and DM are affected by the reflected wave, and the waveform of the EOP portion is disturbed. As a result, there is a situation in which the host side erroneously recognizes the connection state even though the host-device is disconnected.

  For example, in FIG. 14A, due to the influence of reflection, the period during which the differential signals DP and DM remain at a higher voltage level than the comparison voltage in the EOP portion is considerably shortened as indicated by E1. In such a case, the disconnection detection circuits 52-1 and 52-2 may not be able to accurately detect disconnection.

  In FIG. 14B, the differential signals DP and DM in the EOP period are very disturbed due to the influence of the reflected wave, and the disconnection detection circuits 52-1 and 52-2 cannot detect the disconnection.

  FIG. 15 shows a configuration example of the disconnection detection circuit 52-3 according to the present invention. The disconnection detection circuit 52-3 includes first and second reflected wave comparators RCMP1 and RCMP2 and a latch circuit 120 in addition to the configuration of the disconnection detection circuit 52-1 or 52-2. The specific configurations of the first and second reflected wave comparators RCMP1 and RCMP2 are the same as the configurations of the comparators CMP1 and CMP2 shown in FIG. 7 or FIG. 11, and E3 in FIG. The voltage level of the reflected wave indicated by E4 in (B) is compared with the reflected wave comparison voltage RCV.

  The comparison result between the reflected wave voltage level and the reflected wave comparison voltage RCV is supplied to the latch circuit 120. The latch circuit 120 latches the comparison result based on the reflected wave detection signal STB. Specifically, when the reflected wave detection signal STB is set to active, for example, the latch circuit 120 latches the comparison result.

  The reflected wave detection signal STB is set by, for example, an upper layer circuit block, and is set to be active at a predetermined timing after the SOF packet is transmitted, for example. Thereby, when the reflected wave is generated, the comparison result between the reflected wave voltage level and the reflected wave comparison voltage RCV can be latched by the latch circuit 120. Since it is possible to instruct the upper layer circuit block to send the SOF packet, the host controller side can grasp the timing of sending the SOF packet. The number of bits of the SOF packet is defined by the USB 2.0 standard. Therefore, the reflected wave detection signal STB can be set to active at a predetermined timing after EOP of the SOF packet.

  Next, the operation of the disconnection detection circuit 52-3 will be described with reference to FIGS. 16 (A) to 16 (C) and FIGS. 17 (A) to 17 (C).

  16A to 16C are waveform diagrams when the host and the device are in a connected state, and FIGS. 17A to 17C are disconnected between the host and the device. It is a wave form diagram in a state. Further, in FIGS. 16A to 16C and FIGS. 17A to 17C, the comparison voltage CV is set to, for example, 600 mV as shown in FIG. 16A, and the reflected wave comparison voltage is set. RCV is set to 200 mV, for example.

  In FIG. 16A, F1 and F6 indicate EOP of the differential signal DP, for example, and F2 and F5 indicate EOP of the differential signal DM, for example. Further, F3 and F8 in FIG. 16A indicate, for example, reflected waves of the differential signal DP, and F4 and F7 indicate, for example, reflected waves of the differential signal DM.

  First, the operation of the disconnection detection circuit 52-3 when the host-device is not disconnected will be described. When the host-device is connected, as shown in F1 and F2 of FIG. 16A, the voltage levels of the EOPs of the differential signals DP and DM when the SOF packet is transmitted are equal to the comparison voltage CV. Below the voltage level. In this case, the disconnection detection circuit 52 must output a signal indicating that the host-device is connected.

  At this time, as indicated by F1 in FIG. 16A, the voltage level of the differential signal DP is higher than the reflected wave comparison voltage RCV. Accordingly, the detection signal OUTDP2 of the first reflected wave comparator RCMP1 in FIG. 15 becomes high level as indicated by F9 in FIG.

  However, as indicated by F16 in FIG. 16C, the reflected wave detection signal STB is set active at a predetermined timing after the EOP of the SOF packet. For this reason, since the reflected wave detection signal STB is set to non-active (for example, low level) at the timing indicated by F10 in FIG. 16C, the high level detection signal OUTDP2 indicated by F9 in FIG. Are not latched by the latch circuit 120.

  Since the voltage level of the differential signal DM is lower than the reflected wave comparison voltage RCV as indicated by F2 in FIG. 16A, the detection signal OUTDM2 of the second reflected wave comparator RCMP2 in FIG. ) At a low level as indicated by F11.

  Also, as indicated by F1 and F2 in FIG. 16A, the voltage levels of the differential signals DP and DM are lower than the comparison voltage CV, so that the detection signals OUTDP1 and OUTDM1 of the comparators CMP1 and CMP2 in FIG. It becomes a low level as indicated by F11 of 16 (B).

  As described above, the disconnection detection circuit 52-3 outputs a low-level detection signal as indicated by F15 in FIG. 16C, and detects that the host-device is connected.

  Note that F14 in FIG. 16C represents an enable signal EN. Further, when the voltage level at the EOP of the differential signal DM is higher than the reflected wave comparison voltage RCV as indicated by F5 in FIG. 16A, as indicated by F12 in FIG. The detection signal OUTDM2 of the second reflected wave comparator RCMP2 becomes high level. This is also the same as described above, and the reflected wave detection signal STB is set to non-active (for example, low level) at the timing indicated by F13 in FIG. 16C, so that the detection signal OUTDM2 is sent to the latch circuit 120. Not latched. Accordingly, even in this case, the detection signal of the disconnection detection circuit 52-3 is set to a low level as indicated by F17 in FIG. 16C, so that the connection state between the host and the device can be accurately detected.

  Next, the operation of the disconnection detection circuit 52-3 when the host-device is disconnected is described. When the host-device is disconnected, the disconnection detection circuit 52 must output a signal indicating that the host-device is disconnected. At this time, if the voltage levels of the differential signals DP and DM do not exceed the comparison voltage CV due to the influence of reflected waves as indicated by G1 and G5 in FIG. As shown in G6, the voltage level of the reflected wave can be compared with the reflected wave comparison voltage RCV.

  Since the voltage level of the differential signal DP is higher than the reflected wave comparison voltage RCV as indicated by G1 in FIG. 17A, the detection signal OUTODP2 of the reflected wave comparator RCMP1 is high as indicated by G9 in FIG. Become a level. However, as described above, since the latch circuit 120 performs a latch operation based on the reflected wave detection signal STB, the high-level detection signal OUTDP2 indicated by G9 is not latched by the latch circuit 120.

  Further, as indicated by G1 and G2 in FIG. 17A, since the voltage levels of the differential signals DP and DM are lower than the comparison voltage CV, the detection signals OUTDP1 and OUTDM1 of the comparators CMP1 and CMP2 in FIG. It is set to a low level as indicated by G10 of 17 (B).

  Since the voltage level of the differential signal DP becomes higher than the reflected wave comparison voltage RCV as indicated by G3 in FIG. 17A, the detection signal of the reflected wave comparator RCMP1 is indicated as indicated by G11 in FIG. OUTDP2 is set to a high level. At this time, since the reflected wave detection signal STB is set active as indicated by F16 in FIG. 17C, the high level detection signal OUTDP2 indicated by G11 in FIG. The Accordingly, as indicated by G12 in FIG. 17C, the disconnection detection circuit 52-3 outputs a high-level detection signal, and even if the SOF packet is affected by the reflected wave, the disconnection state between the host and the device Can be detected.

  Even when the voltage level of the differential signal DM exceeds the reflected wave comparison voltage RCV as indicated by G6 in FIG. 17A, the detection signal OUTDM2 of the second reflected wave comparator RCMP2 is obtained by the same operation as described above. Is set to a high level as indicated by G13 in FIG. Thereby, the disconnection detection circuit 52-3 can accurately detect the disconnection state between the host and the device.

  As described above, the disconnection detection circuit 52-3 sets the reflected wave voltage level to the reflected wave comparison voltage RCV even when the voltage level at the EOP of the differential signals DP and DM is affected by the reflected wave. Therefore, accurate cutting detection can be performed.

  As described above, the embodiments of the present invention have been described in detail. However, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. . Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term anywhere in the specification or the drawings.

It is a figure which shows the structural example of the host controller which concerns on this invention. It is a figure for demonstrating a SOF packet. 3A is a waveform diagram of the SOF packet in the connected state, and FIG. 3B is a waveform diagram of the SOF packet in the disconnected state. It is a figure which shows the structural example of the detection circuit of the comparative example which concerns on this invention. It is a figure which shows the structural example of the cutting | disconnection detection circuit based on this invention. It is a figure which shows the structural example of a part of cutting | disconnection detection circuit based on this invention. It is a figure which shows the circuit structure of the comparator which concerns on this invention. FIGS. 8A to 8D are waveform diagrams for explaining the operation of the disconnection detection circuit according to the present invention in the connected state. FIGS. 9A to 9D are waveform diagrams for explaining the operation of the disconnection detection circuit according to the present invention in the disconnected state. It is a figure which shows the structural example of the cutting | disconnection detection circuit which concerns on a modification. It is a figure which shows the circuit structure of the comparator which concerns on a modification. 12 (A) to 12 (D) are waveform diagrams for explaining the operation of the disconnection detection circuit of the modification according to the present invention in the connected state. FIGS. 13A to 13D are waveform diagrams for explaining the operation of the cutting detection circuit according to the modification of the present invention in the cutting state. FIGS. 14A and 14B are waveform diagrams showing the influence of reflected waves received by the SOF packet. It is a figure which shows the modification based on this invention. 16A to 16C are other waveform diagrams for explaining the operation of the disconnection detection circuit according to the present invention in the connected state. 17A to 17C are other waveform diagrams for explaining the operation of the disconnection detection circuit according to the present invention in the disconnected state.

Explanation of symbols

52, 52-1, 52-2, 52-3 disconnection detection circuit, 100 control circuit,
110 bias circuit, 112 bias circuit, 120 latch circuit,
200 first differential amplifier, 210 second differential amplifier, 220 second differential amplifier,
BN bias signal, BP bias signal, CMP1 first comparator,
CMP2 second comparator, CV comparison voltage, DM second differential signal,
DP first differential signal, EN enable signal, FNT n-type transistor,
IPT1 first input transistor, IPT2 second input transistor,
IPT3 third input transistor, IPT4 fourth input transistor,
INT1 third input transistor, INT2 fourth input transistor,
ND1 first output node, ND2 second output node, ND3 third output node,
RCMP1 first reflected wave comparator, RCMP2 second reflected wave comparator,
RCV reflected wave comparison voltage, XENH control signal

Claims (16)

A host controller that performs data transfer by a differential signal pair via a bus and transmits frame packets defined by a given standard to the device side at intervals defined by the given standard,
The host-device disconnection state is detected by detecting the reflected wave of the frame packet generated when the host and the device are connected via the connection cable to the state where the device is disconnected from the connection cable. Including a disconnect detection circuit,
The disconnection detection circuit includes:
Of the first and second differential signals constituting the differential signal pair, a voltage level at a given timing after the frame packet of the first differential signal is compared with a reflected wave comparison voltage. ,
Comparing the reflected wave comparison voltage with a voltage level at a given timing after the frame packet of the second differential signal;
When the voltage level at the given timing of at least one of the first and second differential signals is higher than the reflected wave comparison voltage, a disconnection state between the host and the device is detected. Host controller to be used. In claim 1,
The disconnection detection circuit includes:
The first differential signal is received, the voltage level at a given timing after the frame packet of the first differential signal is compared with the reflected wave comparison voltage, and the reflected wave comparison voltage is compared at the given timing in the previous period. If the voltage level of the first differential signal is higher than the reflected wave comparison voltage, a first reflected wave comparator for detecting a disconnection state between the host and the device;
The second differential signal is received, the voltage level of the second differential signal at a given timing after the frame packet is compared with the reflected wave comparison voltage, and the reflected wave comparison voltage is compared with the given timing in the previous period. A second reflected wave comparator for detecting a disconnection state between the host and the device when the voltage level of the second differential signal is higher than the reflected wave comparison voltage;
Including
The disconnection detection circuit detects disconnection between a host and a device when at least one of the first and second reflected wave comparators detects disconnection between the host and the device. In claim 1,
When the first differential signal is received, the voltage level of the first differential signal is compared with the reflected wave comparison voltage, and the voltage level of the first differential signal in the previous period is higher than the reflected wave comparison voltage Includes a first reflected wave comparator for detecting a disconnection state between the host and the device;
When the second differential signal is received, the voltage level of the second differential signal is compared with the reflected wave comparison voltage, and the voltage level of the second differential signal in the previous period is higher than the reflected wave comparison voltage Includes a second reflected wave comparator for detecting a disconnection state between the host and the device;
A latch circuit for latching a logical sum result of output signals of the first and second reflected wave comparators based on a reflected wave detection signal;
Including
The reflected wave detection signal is set to active at a given timing after the frame packet is transmitted, and the latch circuit calculates the logical sum result based on the previous reflected wave detection signal set to active. Latch and
The disconnection detection circuit detects disconnection between a host and a device when at least one of the first and second reflected wave comparators detects disconnection between the host and the device. In claim 2 or 3,
The disconnection detection circuit includes:
The first differential signal is received, the voltage level corresponding to the given range in the frame packet of the first differential signal is compared with the comparison voltage, and corresponding to the given range in the previous period A first comparator for detecting a disconnection state between the host and the device when the voltage level of the first differential signal is higher than the comparison voltage;
The second differential signal is received, the voltage level corresponding to the given range in the frame packet of the second differential signal is compared with the comparison voltage, and corresponding to the given range in the previous period A second comparator for detecting a disconnection state between the host and the device when the voltage level of the second differential signal is higher than the comparison voltage;
Including
The disconnection detection circuit detects disconnection between a host and a device when at least one of the first and second comparators detects disconnection between a host and a device. In claim 4,
The disconnection detection circuit receives an enable signal for enabling control of the disconnection detection circuit,
The enable signal is
When the constant current source of the transmission circuit on the host controller side is set to ON and the frame packet is transmitted from the host to the device, it is set to active,
When the frame packet is not transmitted, it is set to inactive,
The disconnection detection circuit includes:
When the enable signal is set to active, the disconnection state between the host and the device is monitored,
When the enable signal is set to non-active, the operation is set to an off state. In claim 4 or 5,
The first and second comparators include output fixing switches that fix their outputs to ground level;
The host controller is characterized in that the output fixing switch is set off when the enable signal is active and is turned on when the enable signal is inactive. In any one of Claims 4 thru | or 6.
A bias signal generating circuit for generating a bias signal for adjusting a current source of the first and second comparators;
The host controller, wherein the bias signal generation circuit generates the bias signal when the enable signal is active and does not generate the bias signal when the enable signal is inactive. In any of claims 4 to 7,
The first and second comparators include first and second differential amplifiers,
The first differential amplifier includes first and second input transistors provided in parallel between a first power source and a second power source,
The comparison voltage is input to the gate of the first input transistor,
One of the first and second differential signals is input to the gate of the second input transistor,
The second differential amplifier includes third and fourth input transistors provided in parallel between a first power supply and a second power supply having a power supply voltage higher than that of the first power supply,
A gate of the third input transistor is connected to a first output node between the first input transistor and the second power supply;
The gate controller of the fourth input transistor is connected to a second output node between the second input transistor and the second power supply. In claim 8,
The host controller, wherein the first, second, third and fourth input transistors are P-type transistors. In claim 8 or 9,
A detection result of the first and second comparators is output based on a voltage level of a third output node between the fourth input transistor and the second power supply. controller. In claim 8,
The host controller, wherein the first and second input transistors are N-type transistors, and the third and fourth input transistors are N-type transistors. In claim 11,
The first and second comparators include a second differential amplifier bias signal generation circuit for generating a second differential amplifier bias signal for adjusting a current source of the second differential amplifier. Including
The second differential amplifier bias signal generation circuit generates the second differential amplifier bias signal when the enable signal is active, and the second differential amplifier bias signal generation circuit when the enable signal is inactive. A host controller characterized by not generating a differential amplifier bias signal. In claim 8, 11 or 12,
The detection result of the first and second comparators is output based on a voltage level of a third output node between the fourth input transistor and the first power supply. controller. In any one of Claims 1 thru | or 13.
The given controller is a USB 2.0 standard. In claim 14,
The frame controller is a SOF (Start Of Frame) packet defined by the USB 2.0 standard. In claim 15,
The given range corresponds to EOP (End Of Point) defined by the USB 2.0 standard.

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