JP2007049143A - Dual gate structure and its manufacturing method, and semiconductor device with dual gate structure and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dual gate structure and its manufacturing method, and to provide a semiconductor device with dual gate structure and its manufacturing method. <P>SOLUTION: The semiconductor device has at least two stacked gate structures formed on the substrate. The two stacked gate structures each has a semiconductor layer and a metal layer formed on the semiconductor layer. The two stacked gate structures formed on the board have intermediate layers which are different from each other. One of the two stacked gate structures has an ohmic layer while the other structure does not. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to the manufacture of semiconductor devices, and more particularly to a semiconductor device having a dual gate structure.

  As the size of the semiconductor device gradually decreases and the speed of the semiconductor device increases, the signal delay due to the lack of dopant and high resistance in the conventional polysilicon gate electrode increases. Therefore, signal delay reduction has become an important issue in the semiconductor industry.

  With this trend, polymetal gates or metal gates are pursued to reduce signal delay and further reduce resistance in semiconductor devices. However, in the case of a metal gate, the gate dielectric can be contaminated if the metal layer is formed immediately on top of the gate dielectric. Thus, the metal layer is generally formed on a doped polysilicon layer. It is generally known that the RC signal delay time is significantly reduced if a metal such as tungsten with low sheet resistance is used as the gate material.

However, it is still necessary to overcome the problems of the prior art, such as reducing the high resistance of the gate electrode and poly depletion.
US Pat. No. 6,103,610

  The technical problem to be solved by the present invention is to provide a dual gate structure and a manufacturing method thereof, a semiconductor device having a dual gate structure, and a manufacturing method thereof.

  The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

  A semiconductor device according to an embodiment of the present invention for achieving the technical problem includes a semiconductor substrate and at least two stack gate structures formed on the substrate, and the two stack gate structures include: Each including a gate insulating film formed on the substrate, a semiconductor layer formed on the gate insulating film, a reaction barrier layer formed on the semiconductor layer, and a metal layer formed on the barrier layer, One of the two stacked gate structures further includes an ohmic layer provided between the semiconductor layer and the reaction barrier layer, and the other one of the two stacked gate structures is interposed therebetween. Does not include ohmic layer.

  According to another embodiment of the present invention, there is provided a semiconductor device having at least two stack gate structures formed on a substrate, wherein each of the two stack gate structures includes a semiconductor layer and a semiconductor. A metal layer formed on the layer, wherein one structure of the two stack gate structures includes an ohmic layer, and one other structure of the two stack gate structures does not include an ohmic layer, The two stacked gate structures on the substrate are characterized by having different intermediate layers.

  According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate insulating film on a semiconductor substrate; forming a polysilicon layer on the gate insulating film; A first impurity type polysilicon layer and a second impurity type polysilicon layer are formed, an ohmic layer is selectively formed on the first impurity type polysilicon layer, and the ohmic layer and the second impurity type are formed. A reaction barrier layer is formed on the polysilicon layer, a metal layer is formed on the barrier layer, and a structure including the first and second impurity type polysilicon layers is continuously patterned to form a first type gate stack A second type gate stack is formed.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein at least two stacked gate structures are formed on a substrate, and the gate structures are formed on a gate insulating film on the substrate. The semiconductor device includes a semiconductor layer on the gate insulating film, a barrier film on the semiconductor layer, and a metal layer on the barrier layer, and one structure of the two stacked gate structures selectively includes an ohmic layer.

  Specific details of other embodiments are included in the detailed description and drawings.

  The present invention has one or more of the following effects.

  First, in the semiconductor element of the present invention, an ohmic layer is selectively formed only in the N-type transistor, and no ohmic layer is formed in the P-type transistor. Accordingly, the performances of the N-type transistor and the P-type transistor are both optimized, and a more stable semiconductor device can be realized, and the characteristics of the semiconductor device can be improved.

  Second, since the process of forming the ohmic layer only in the N-type transistor region is performed without a mask process, the cost can be reduced and the process can be simplified.

  Third, the process of forming an ohmic layer only in the N-type transistor region and the process of forming dual polysilicon are performed in a single mask process, which simplifies the process, reduces the time, and increases productivity. Can be improved.

  Advantages and features of the present invention and methods of achieving the same will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various forms that deviate from the embodiments, and the embodiments described herein complete the disclosure of the present invention. It is provided so that the scope of the invention may be fully disclosed to those skilled in the art to which the invention pertains, and the invention is only defined by the claims and the detailed description of the invention. On the other hand, the same reference numerals denote the same components throughout the specification.

  As described above, the polymetal gate structure is the current mainstream structure selected to further reduce resistance in semiconductor devices and thereby reduce signal delay. However, metals such as tungsten can react with polysilicon at high temperatures to form undesired compounds. As a result, the interfacial resistance therebetween increases, and the operation speed of the semiconductor element can be reduced. Thereby, the reaction barrier layer that can be formed between the metal and the polysilicon suppresses the interdiffusion between the metal and the silicon and reduces the reaction between them, for example, the formation of a silicide material such as tungsten silicide, It can be prevented.

  Unfortunately, the interfacial resistance of the reaction barrier layer is very high, and this problem becomes more pronounced as the size of the transistor gets progressively smaller. Applicants have found that high interface resistance causes device failure, especially in the case of N-type transistors (unlike P-type transistors). Accordingly, an ohmic layer is formed between the polysilicon layer of the N-type transistor and the reaction barrier layer in order to reduce the resistance of the contact or interface between the polysilicon layer and the reaction barrier layer.

  On the other hand, in the case of a P-type transistor, if an ohmic layer, for example, a metal silicide is formed on the PMOS gate stack, the so-called “poly depletion” problem is exacerbated and can be used as a diffusion path for the dopant. In particular, a dopant such as boron (B) leads to unsuitable (unacceptable) CV characteristics spreading from the polysilicon layer to the outside during heat treatment from the polysilicon layer by a process such as RTP. . This results in degradation of the characteristics of the P-type transistor and the overall characteristics of the semiconductor element.

  Furthermore, poly-depletion is less problematic with N-type transistors than P-type transistors, while the element characteristics of P-type transistors are less affected by interface resistance, unlike N-type transistors. In other words, the overall characteristics of the semiconductor device are such that poly depletion is more important than interface resistance in the case of P-type transistors, and interface resistance is more important than poly depletion in the case of N-type transistors. It is.

  In view of the above, the embodiments of the present invention improve the device characteristics by separately treating the above problems, that is, the high interface resistance problem of the N-type transistor and the poly-depletion problem causing the unsuitable CV characteristic of the P-type transistor. Let

  FIG. 1 is a cross-sectional view illustrating a semiconductor device having stacked gates, for example, transistor structures 100 and 101 according to an embodiment of the present invention. Specifically, the P-type transistor 101 and the N-type transistor 100 are formed on a semiconductor substrate 105 having an NMOS region and a PMOS region. The N-type transistor 100 is formed in the NMOS region, and the P-type transistor 101 is formed in the PMOS region.

  The N-type transistor 100 includes a gate insulating film 110 and a gate stack 130N continuously formed on an impurity region of the NMOS region, for example, a channel region between the source / drain regions 160. The gate stack 130N includes a reaction of an N-type polysilicon layer 120N doped with an N-type impurity such as phosphorus (P), arsenic (As), and antimony (Sb), an ohmic layer 132 such as a metal silicide layer, and a metal nitride film. Further including a barrier layer 134, a metal layer 136, and the like, the above-described ones are continuously laminated.

  On the other hand, the P-type transistor 101 includes a gate insulating film 110 and a gate stack 130P formed in a channel region between impurity regions of the PMOS region. The gate stack 130P further includes a P-type polysilicon layer 120P doped with a P-type impurity such as boron, a reaction barrier layer 134, a metal layer 136, and the like.

  The metal layer 136 is formed of a metal having a low surface resistance, such as W, Ta, Re, Os, Mo, Nb, V, Hf, Zr, and Ti. A general hard mask layer 140 formed of a material such as a silicon nitride film is formed on the gate stacks 100 and 101, and an insulating spacer 150 is formed along the side surfaces of the gate stacks 130N and 130P. .

  According to some embodiments of the present invention, the reaction barrier layer 134 may be a metal nitride film such as WN, TiN, or TaN. As described above, the reaction barrier layer 134 is formed between the metal layer 136 and the doped silicon layer 120N or 120P, and suppresses mutual internal diffusion between the metal and silicon, thereby causing a reaction therebetween, for example, Reaction formation of silicide materials such as tungsten silicide can be reduced or prevented. The silicide material generally has a higher resistance value than the metal, so that the resistance increases at the gate electrode.

  An important difference between the gate stack 130P and the gate stack 130N is that the gate stack 130P includes an ohmic layer such as an ohmic layer 132 provided between the silicon layer 120P doped in the gate stack 130N and the reaction barrier layer 134. That is not. Thereby, in the gate stack 130P, the reaction barrier layer 134 is in contact with the directly doped polysilicon layer 120P without the ohmic layer 132 provided therebetween.

  The ohmic layer 132 of the gate stack 130N reduces the contact resistance or interface resistance between the doped polysilicon layer 120N and the reaction barrier layer 134. Since the interface resistance between the doped polysilicon layer 120N and the reaction barrier layer 134 such as WN or TiN is high, the ohmic layer 132 is selectively formed in the gate stack 130N to reduce the interface resistance therebetween. . The ohmic layer 132 may be a heat resistant metal silicide such as WSix, TiSix, CoSix. Desirably, the refractory metal silicide includes tungsten (W) and silicon (Si). The thickness of the ohmic layer 132 is about 30-200 mm, and may be about 80 mm.

  However, as described above, if the metal silicide ohmic layer 132 is formed in the gate stack 130P of the P-type transistor 101, the ohmic layer 132 can be used as a diffusion path for a dopant such as boron (B). Specifically, the dopant from the doped polysilicon layer 120P is rapidly diffused or absorbed into the metal silicide, for example, through the metal silicide grain boundary. This reduces the density of the dopant inside the doped polysilicon layer 120P and changes the threshold voltage of a transistor, eg, a CMOS transistor (“poly-depletion”). As a result, the inversion capacitance (inversion capacitance) of the semiconductor element is further reduced, and undesirable CV characteristics appear.

  In view of the above, according to one aspect of the present invention, the semiconductor device of the present invention is selectively and intentionally formed between the reaction barrier layer 134 of the gate stack 130P and the doped polysilicon layer 120P. Not included. Thereby, the diffusion of the dopant is substantially reduced. That is, according to the present invention, it is a feature of two different stacked gate structures having different intermediate layers. These important differences are briefly summarized below.

  In general, the main structural difference between P-type and N-type stacked gate structures is the supplied P-type or N-type dopant.

  In accordance with the present invention, the additional structural differences comprise different intermediate layers with the addition or exclusion of ohmic contact layers between the semiconductor layers, such as the silicon layer and the reaction barrier layer, in the stacked gate structure. This difference in the intermediate layer structure emphasizes that the interface resistance is more important than the poly-depletion problem in the N-type stack gate structure, and that the poly-depletion is more important than the interface resistance in the P-type stack gate structure. Emphasize that there is.

  As a result, in the semiconductor device according to the embodiment of the present invention, the N-type gate electrode 130N of the N-type transistor selectively includes the ohmic layer 132 between the N-type polysilicon layer 120N and the reaction barrier layer 134. As a result, the interface resistance characteristic of the N-type transistor 100 is improved, while the ohmic layer 132 is not formed on the P-type gate electrode 130P of the P-type transistor (101 in FIG. 11). Can be increased.

  2 to 6 illustrate a continuous process of manufacturing a semiconductor device having a dual gate structure of a P-type gate stack and an N-type gate stack having different intermediate layers according to an embodiment of the present invention. 1 having the same or similar functions are denoted by the same or similar reference numerals, and detailed description thereof is omitted.

  Referring to FIG. 2, an isolation layer (not shown) is formed on the semiconductor substrate 105 to define an active region. The semiconductor substrate 105 generally has an NMOS region for the cell region and a PMOS region for the peripheral / core region. The substrate 105 can be formed of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, InP, or a combination thereof. Further, the substrate 105 may be an SOI substrate.

A gate insulating film 110 is formed on the semiconductor substrate 105. The gate insulating layer 110 may be formed of a suitable gate insulating material including a high-k insulating material such as HfO ₂ . Next, an N-type polysilicon layer 120N doped with an N-type impurity such as phosphorus or arsenic is formed on the gate insulating film 110. As is known, the N-type polysilicon layer 120N is formed by in-situ N-type doping during the formation of the polysilicon layer or by implanting N-type impurities after forming the polysilicon layer. Optionally, a plasma doping process can be used. N-type polysilicon layer 120N may contain N-type impurities. Optionally, the N-type polysilicon layer has a higher concentration of N-type impurities than P-type impurities.

Referring to FIG. 3, a photoresist pattern 310 is formed on the substrate 105. The photoresist pattern 310 is formed to cover the NMOS region using a general photo etching technique. Next, a P counter implantation process indicated by an arrow 122 is performed, that is, using the photoresist pattern 310 as a mask, a P type impurity is ion-implanted in the N type polysilicon layer 120N to form a P type polysilicon in the PMOS region. A silicon layer 120P is formed. The P counter implantation step 122 is performed at a concentration of about 1.0 × 10 ¹⁵ to 10 ¹⁷ / cm ² with energy greater than 3 KeV, such as boron (B), boron fluoride (BF ₂ , BF ₃ ), indium (In), etc. P-type impurities are used. Therefore, as a whole, the concentration of the P-type impurity is higher than the concentration of the N-type impurity, the conductivity type of the ion implantation layer is P-type, and the P-type polysilicon layer 120P is formed in the PMOS region. Alternatively, the P-type polysilicon layer 120P may include only P-type impurities.

  As a result, an N-type silicon layer and a P-type silicon layer, i.e., a dual polysilicon layer, are formed on the substrate 105 as shown. Then, in order to activate the N-type or P-type impurity, heat treatment such as RTP or a general annealing process is performed. The temperature can be, for example, about 600 ° C. or higher.

  Alternatively, the dual polysilicon layer can be formed by continuously implanting N-type impurities into the N-type transistor region after forming the P-type polysilicon layer 120P, and vice versa. Further, in order to form a dual polysilicon layer, N-type impurities and P-type impurities can be implanted by using two masks exposing the N-type transistor region and the P-type transistor region, respectively. However, as described above, forming using only one mask can simplify the process and reduce the manufacturing cost. In each case, the mask is removed by an appropriate method including a general method after ion implantation. Also, as known to those skilled in the art, rapid nitridation and cleaning processes can be performed to complete the ion implantation process steps.

Referring to FIG. 4, an ohmic layer 132 is formed on the N-type polysilicon layer 120N. Ohmic layer 132 is selected for example, instead of SiH _4, by the method of hexafluoro tungsten (WF ₆₎ and dichlorosilane CVD using _{(SiH 2 C l2) (Chemical} Vapor Deposition) on the N-type polysilicon layer 120N Can be formed. Desirably, the gas flow ratio of WF ₆ and _SiH 2 _{C l2} is about 1: may be 25 to 160. Ar can be used as a carrier gas having a partial pressure of 200 mtorr or more in a selective CVD process. As the process proceeds, the wafer may be heated above about 450 ° C. In such a case, the ohmic layer 132 is not formed or negligibly formed on the P-type polysilicon layer 120P. The ohmic layer 132 includes metal silicide such as titanium silicide (TiSix), tantalum silicide (TaSix), cobalt silicide (CoSix), tungsten silicide (WSix), and molybdenum silicide (MoSix). The thickness of the ohmic layer 132 may be about 30 to 200 mm.

  Alternatively, the ohmic layer 132 is formed by forming the ohmic layer 132 on the N-type and P-type polysilicon layer 120P and then removing the ohmic layer 132 on the P-type polysilicon layer 120P by, for example, an etching process. Yes. In this case, the ohmic layer 132 can be formed by a general CVD process or PVD method in which heat treatment is continuously performed.

  However, in the selective deposition process described above, the ohmic layer 132 is selectively formed in the NMOS region without an etching process. Thereby, the manufacturing cost can be reduced and the manufacturing process can be simplified.

  Referring to FIG. 5, a reaction barrier layer 134 having a thickness of about 50 to 100 mm is formed on the ohmic layer 132 in the NMOS region and on the reaction barrier layer 134 in the PMOS region by a general method such as CVD, PVD or ALD. Form using technology. Subsequently, a metal layer 136 made of a metal such as a refractory metal is formed on the reaction barrier layer. The metal layer is formed to a thickness of about 300 to 600 mm. The reaction barrier layer 134 may include at least one of tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The metal layer 136 may include at least one of W, Re, Ta, Os, Mo, Nb, V, Hf, Zr, and Ti.

  Next, a hard mask pattern 140 for defining the gate electrode is formed on the refractory metal layer 136. The hard mask pattern 140 may be formed of PE-SiN (Plasma Enhanced-SiN) or LP-SiN (Low Pressure-SiN).

  Referring to FIG. 6, using the hard mask pattern 140, the metal layer 136, the reaction barrier layer 134, the ohmic layer 132, the N-type and P-type polysilicon layers 120P, and the gate insulating film 110 are sequentially patterned to form an NMOS region. A gate structure is formed in each of the PMOS regions. Next, an ion implantation process is performed on the impurity regions (160 in FIG. 1) of the NMOS region and the PMOS region, for example, the LDD region. Next, as shown in FIG. 1, in order to form a high concentration impurity region (not shown) such as a source / drain region, a sidewall of a gate structure formed on each NMOS region and PMOS region is formed. Sidewall spacers are formed.

  As a result, a stack gate, that is, an N-type gate electrode 130N and a P-type gate electrode 130P are formed on the substrate 105. The N-type gate electrode 130N and the P-type gate electrode 130P have similar layups but are different. N-type gate electrode 130N includes ohmic layer 132, but does not include P-type gate electrode 130P. As described above, in terms of the overall characteristics of the semiconductor element, the interface resistance is a case of a P-type transistor, and poly depletion is not a significant problem in the case of an N-type transistor. As a result, the present invention forms a pair of gate electrodes of a CMOS transistor and has optimum conditions in both regions (an N-type gate electrode having a lower resistance and a poly-depletion reduced or a further improved P-type gate electrode. ).

  Further, the potential negative effect caused by the differentiated intermediate stack gate structure, for example, the poly-depletion of the N-type transistor and the interface resistance of the P-type transistor are determined according to the element characteristics as described later.

  Briefly summarized, one of the two stacked gate structures includes an ohmic layer formed between semiconductor layers such as a polysilicon layer and a reaction barrier layer, the other is not. That is, only one of the two stacked gate structures includes an ohmic layer formed between a polysilicon layer and a semiconductor layer such as a reaction barrier layer. As shown in FIG. 11, which will be described later, the improvement in device characteristics of the segmented stacked gate structure pair is remarkable as compared with the conventional technique.

  A semiconductor device is completed by further performing process steps such as a step of forming wiring that enables continuous input / output and a step of packaging a substrate. However, since these are well known to those skilled in the art, a detailed description thereof is omitted here.

  7-10 illustrate a semiconductor device having a dual gate structure of a P-type gate stack and an N-type gate stack having other intermediate layers, similar to an embodiment of the present invention, but using other process steps. It shows the continuous process steps to do. Components having the same functions are denoted by the same or similar reference numerals as those in FIGS. 2 to 6, and detailed description thereof is omitted.

  Those skilled in the art will understand that the process shown in FIGS. 2 to 6 can be performed by selectively forming the ohmic layer 132 only on the silicon layer of the substrate region where the N-type stacked gate structure is formed. It can be seen that this involves a process (evaporation).

  Those skilled in the art of the present invention can form the ohmic layer 132 entirely on the silicon layer by the steps shown in FIGS. 7 to 10 and selectively remove the substrate region where the P-type stack gate structure is formed. It can be seen that this is a general vapor deposition process.

  Understand that selective deposition of ohmic layers, or overall deposition and selective removal, as well as detailed description, drawings and claims, results in the same structure and improved device characteristics. It will be possible. This is because the ohmic layer is selectively removed in the P-type stack gate structure and the ohmic layer is left in the N-type stack gate structure.

  Referring to FIG. 7, an isolation layer (not shown) is formed on a semiconductor substrate having an NMOS region for a cell region and a PMOS region for a peripheral / core region, as in the above-described embodiment.

  Next, a gate insulating film 110 is formed over the semiconductor substrate 105. Next, an N-type polysilicon 120N is formed by doping an N-type impurity such as phosphorus or arsenic on the gate insulating film 110 by the method described in the embodiment of the present invention.

  Referring to FIG. 8, an ohmic layer 132 is formed on the entire surface of the N-type polysilicon 120N. Here, the ohmic layer 132 may be formed by a thermal process after being stacked by a CVD or PVD (Physical Vapor Deposition) method.

  Referring to FIG. 9, a photoresist pattern 330 is formed to cover the NMOS region. The ohmic layer 132 in the PMOS region is removed by dry etching or wet etching using the photoresist pattern 330 as an etching mask. As a result, the N-type silicon layer is exposed in the PMOS region.

  Referring to FIG. 10, using the photoresist pattern 330 as a mask, a P counter ion implantation process is performed on the exposed N-type polysilicon layer 120N, and a P-type impurity doped with a P-type impurity in the P-type transistor region. A silicon layer 120P is formed. The overall conductivity of the ion implanted polysilicon layer is preferably P-type. That is, the concentration of P-type impurities is higher than the concentration of N-type impurities. As a result, a dual polysilicon layer having an N-type polysilicon layer 120N in the NMOS region and a P-type polysilicon layer 120P in the PMOS region is formed. Continuously, a rapid nitridation process and a cleaning process (including removal of the photoresist pattern 330) can be performed on the structure.

  The process steps described above are cost effective because the use of a single ion implantation mask eliminates the need to use two different masks that respectively expose the NMOS and PMOS regions to form a dual polysilicon layer. It can go down and simplify the manufacturing process.

  The remaining manufacturing steps for forming the N-type transistor 100 and the P-type transistor 101 are the same as those described in the embodiment of the present invention.

  FIG. 11 is a graph showing a capacitance-voltage (CV) curve of a PMOS tungsten polymetal gate depending on whether an ohmic layer is provided.

Referring to FIG. 11, curve D (no ohmic layer) showing experimental test results of the present invention is contrasted with curve C (including ohmic layers) showing experimental test results of prior art structures. All experimental stacked gate electrodes use W poly-metal as the gate electrode and WSix as the selectively included ohmic layer. Those skilled in the art will understand that the vertical axis represents the measured capacitance across the gate electrode junction as F, and the horizontal axis represents the value represented by the gate electrode voltage across the gate electrode as V. . As illustrated in FIG. 11, for example, at a voltage of −1.5 V, the capacitance of the curve D is 2.0 × 10 ⁻¹⁰ F, and the capacitance of the curve C is 10 ⁵ × 10 ⁻¹⁰ F. is there. Thus, using a gate electrode structure without an ohmic layer, gate depletion is reduced (improved) to approximately 33% at -1.5V, resulting in an increase in overall inversion capacitance value.

The table below shows experimental calculated data for three different cases.
(1) When the ohmic layer is formed non-selectively (entirely).
(2) When an ohmic layer is selectively formed only on the NMOS stack gate structure.
(3) The ohmic layer is not formed selectively or entirely.

  Here, the yield represents the percentage of semiconductor dies that function normally relative to the total number of dies tested on the wafer.

Also, experimental results in three different cases were obtained using multiple wafers to provide a statistically meaningful sample number.

  Thus, devices that consume even faster speeds and lower power are obtained with a single semiconductor stack gate layer structure according to the various embodiments disclosed and illustrated herein. The only selective inclusion of the ohmic semiconductor stack gate layer structure and the selective inclusion of the ohmic layer only in the N-type stacked gate layer region of the structure significantly reduces the interface resistance of the N-type transistor, while P The poly-depletion problem can be reduced with a type transistor. Further, as in some embodiments of the present invention, it is a general practice to form an ohmic layer non-selectively in both the NMOS region and the PMOS region and selectively remove the ohmic layer in the PMOS region using a mask. Without using the method (steps described in FIGS. 7 to 10), through a method of selectively forming an ohmic layer only in the NMOS region using one mask (steps described in FIGS. 2 to 6). Process steps can be simplified. Further, according to some embodiments, the present invention can be used when manufacturing a volatile memory such as a DRAM or when manufacturing a non-volatile memory such as a flash memory.

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art to which the present invention pertains may have other specific forms without changing the technical idea and essential features thereof. It will be understood that this can be implemented. Accordingly, it should be understood that the above-described embodiments are illustrative in all aspects and not limiting.

  The element applied to the present invention is a semiconductor element of a highly integrated circuit, a processor, a MEM's (Micro Electro Mechanical) element, an optoelectronic element, a display element, or the like.

1 is a cross-sectional view illustrating a multi-layer structure of a semiconductor device according to an embodiment of the present invention. 2 is a diagram illustrating successive stages of a method for manufacturing a gate structure in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive stages of a method for manufacturing a gate structure in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive stages of a gate structure manufacturing method in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive stages of a gate structure manufacturing method in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive stages of a method for manufacturing a gate structure in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive steps of another method of manufacturing a gate structure in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive steps of another method of manufacturing a gate structure in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive steps of another method of manufacturing a gate structure in the semiconductor device of the embodiment illustrated in FIG. 1. 2 is a diagram illustrating successive steps of another method of manufacturing a gate structure in the semiconductor device of the embodiment illustrated in FIG. 1. 5 is a graph showing a capacitance-voltage (CV) curve of a PMOS tungsten polymetal gate depending on whether an ohmic layer is provided.

Explanation of symbols

100 N-type transistor 101 P-type transistor 105 Substrate 110 Gate insulating film 120N N-type polysilicon 120P P-type polysilicon 130N N-type gate electrode 130P P-type gate electrode 132 Ohmic layer 134 Barrier layer 136 Metal layer 140 Hard mask 150 Spacer 160 Source / Drain region

Claims (28)

A semiconductor substrate;
And at least two stacked gate structures formed on the substrate;
Each of the two stack gate structures is formed on a gate insulating film formed on the substrate, a semiconductor layer formed on the gate insulating film, a reaction barrier layer formed on the semiconductor layer, and the barrier layer. With a metal layer
One of the two stack gate structures further includes an ohmic layer provided between the semiconductor layer and the reaction barrier layer,
The other one of the two stacked gate structures is a semiconductor device that does not include an ohmic layer therebetween.   2. The semiconductor device according to claim 1, wherein the reaction barrier layer is directly formed on a semiconductor layer of another one of the two stacked gate structures.   2. The structure of claim 1, wherein one structure of the two stack gate structures forms part of an N-type transistor, and another structure of the two stack gate structures forms part of a P-type transistor. Semiconductor element.   The semiconductor element according to claim 1, wherein the semiconductor layer includes silicon.   The semiconductor device according to claim 1, wherein the ohmic layer includes a metal silicide.   The semiconductor device according to claim 1, wherein the reaction barrier layer includes WN, TiN, or TaN.   The semiconductor device according to claim 1, wherein the ohmic layer has a thickness of about 30 to 200 mm.   The semiconductor device according to claim 1, wherein the reaction barrier layer has a thickness of about 50 to 100 mm. At least two stack gate structures formed on a substrate, each of the two stack gate structures including a semiconductor layer and a metal layer formed on the semiconductor layer;
One of the two stacked gate structures includes an ohmic layer, the other one of the two stacked gate structures does not include an ohmic layer, and the two stacked gate structures on the substrate have a phase structure. A semiconductor element having different intermediate layers.   The semiconductor layer includes a silicon layer, each of the stack gate structures includes a reaction barrier layer, and one of the two stack gate structures includes an ohmic layer between the silicon layer and the reaction barrier layer. The semiconductor device according to claim 9.   The semiconductor device according to claim 9, wherein one structure of the two stack gate structures forms part of an N-type transistor.   The semiconductor device according to claim 9, wherein another structure of the two stack gate structures forms part of a P-type transistor.   The structure of claim 9, wherein one structure of the two stack gate structures forms part of an N-type transistor, and another structure of the two stack gate structures forms part of a P-type transistor. Semiconductor element.   The semiconductor device according to claim 13, wherein the stacked gate structure without an ohmic layer forms a P-type transistor. Forming a gate insulating film on the semiconductor substrate;
Forming a polysilicon layer on the gate insulating film;
Defining the polysilicon layer into a first impurity type polysilicon layer and a second impurity type polysilicon layer;
Forming an ohmic layer selectively on the first impurity type polysilicon layer;
Forming a reaction barrier layer on the ohmic layer and the second impurity type polysilicon layer;
Forming a metal layer on the barrier layer;
A method of manufacturing a semiconductor device, wherein a structure including the first and second impurity type polysilicon layers is continuously patterned to form a first type gate stack and a second type gate stack, respectively.   The selective ohmic layer is formed by forming a conductive layer on the first and second impurity type polysilicon layers and forming a conductive layer on the second impurity type polysilicon layer. The method for manufacturing a semiconductor device according to claim 15, wherein the portion is removed.   The method of manufacturing a semiconductor element according to claim 15, wherein the ohmic layer is selectively formed using a selective CVD process. The CVD process is a method of manufacturing a semiconductor device according to claim 17 carried out using WF ₆ and _SiH 2 _{C l2.} WF _6: Gas flow ratio of _SiH 2 _{C l2} is about 1: 25 to 160 A method of manufacturing a semiconductor device according to claim 18.   The method of claim 17, wherein the CVD process is performed at a temperature higher than about 450 ° C.   18. The method of manufacturing a semiconductor device according to claim 17, wherein Ar gas is used as a carrier gas at a partial pressure of about 200 mTorr.   The method of claim 15, wherein the first gate stack forms an NMOS transistor, and the second gate stack forms a PMOS transistor. Forming at least two stack gate structures on the substrate;
Each of the gate structures includes a gate insulating film on the substrate, a semiconductor layer on the gate insulating film, a barrier film on the semiconductor layer, and a metal layer on the barrier layer,
One of the two stacked gate structures is a method of manufacturing a semiconductor device that selectively includes an ohmic layer.   24. The method of manufacturing a semiconductor element according to claim 23, wherein the ohmic layer is formed between the semiconductor layer and the reaction barrier layer.   24. The method of manufacturing a semiconductor device according to claim 23, wherein an ohmic layer is selectively provided in a region on the substrate where an N-type transistor is formed.   24. The method of manufacturing a semiconductor device according to claim 23, wherein an ohmic layer is selectively provided in a region on the substrate where a P-type transistor is not formed.   The method according to claim 23, wherein the ohmic layer is selectively deposited on a semiconductor layer in one region of the two stacked gate structures. The ohmic layer is deposited on a semiconductor layer in a region where the two stacked gate structures are formed, and the ohmic layer formed in a region where the other one of the two stacked gate structures is formed is The method of manufacturing a semiconductor device according to claim 23, wherein the semiconductor device is removed by selective etching.

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