JP2007048458A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which the test technique and redundancy technology can be optimized at a high level. <P>SOLUTION: An array control circuit 12 is provided which interrupts an operation of a defective element by preventing a word line state signal WLE from being received based on a signal HITL or HITR for determining whether row redundancy replacement is performed. The word line state signal is input to a plurality of memory blocks 11A-0 to 11A-31 and 11B-0 to 11B-31 in cell array units 11A and 11B via a single signal line 13-1. A signal having redundancy information is locally decoded, thereby making it possible to increase the number of arrays which are simultaneously activated and thereby reduce a test period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for optimizing a test technique and a redundancy technique.

  In recent years, the storage capacity of semiconductor memory devices has been steadily increasing, and along with this, various test techniques for testing whether or not they function normally and redundancy techniques for relieving defects are important. Occupy the right position. In a large-capacity semiconductor memory device, it is necessary to increase the test time in various functional tests, and it is indispensable to increase the efficiency and cost of a redundancy technique for relieving defects.

  However, it is difficult to optimize the test technology and the redundancy technology. If the semiconductor memory device relieved by the redundancy technology is to be tested, the test time is lengthened and difficult to test, and if the test time is to be shortened, it is highly efficient and low. There is a problem that costly redundancy technology cannot be applied.

  As described above, the conventional semiconductor memory device has a problem in that it is difficult to optimize the test technique and the redundancy technique, which leads to an increase in test time and a difficulty in the test, and that the redundancy technique with high efficiency and low cost cannot be applied. there were.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of optimizing a test technique and a redundancy technique.

  Another object of the present invention is to provide a semiconductor memory device that can shorten the test time and facilitate the function test.

  Still another object of the present invention is to provide a semiconductor memory device capable of realizing a highly efficient and low-cost redundancy technique.

  Furthermore, another object of the present invention is to provide a semiconductor memory device that can shorten the test time and facilitate the function test even when a highly efficient and low-cost redundancy technique is applied.

  The semiconductor memory device of the present invention is a semiconductor memory device having a function of activating a plurality of word lines connected to the same bit line via cell transistors together, and repairing column redundancy based on a row address. A column redundancy system for setting an area is provided, and when the relief area is set to divide the bit line, the relief area is set so that the plurality of word lines activated together belong to the same relief area It is characterized by being.

  Further, the semiconductor memory device of the present invention includes a column redundancy system for setting a column redundancy relief area based on a row address, and the scale of the column relief area is constant and linked to constitute one column relief area. In the operation mode in which the activated word line maintains its state in a plurality of successive word line selection cycles under the condition that each of the partial relief areas is constant or larger, the relief area is in the operation mode. The relief area is set so that the number of word lines that can be activated together is maximized.

  Furthermore, the semiconductor memory device of the present invention includes a column redundancy system that sets a column redundancy relief area based on a row address, and sets the relief area so as to divide the bit line. Under the condition that the scale is constant and the number of relief areas for dividing one bit line is constant or less, the activated word line maintains its state in a plurality of consecutive word line selection cycles. The relief region is set so that the number of word lines that can be activated together in the relief region in the operation mode is maximized.

  A semiconductor memory device according to the present invention includes a column redundancy system that sets a column redundancy repair area based on a row address, and the scale of the column repair area is constant, and linked portions constituting one column repair area In a plurality of consecutive word line selection cycles under the condition that the size of each relief area is constant or larger and the number of relief areas dividing one bit line is constant or less, The relief region is set so that the number of word lines that can be activated together in the relief region is maximized in the operation mode in which the activated word lines maintain their state.

  The semiconductor memory device according to the present invention further includes a column redundancy system for setting a column redundancy relief area based on a row address, and a word line activated once in a plurality of consecutive word line selection cycles. The relief area is set so that all of the word lines that can be activated together in the operation mode to be held belong to the same relief area.

  According to the above configuration, a plurality of arrays (elements) can be simultaneously activated to perform a test, so that the test time can be shortened. In addition, when the number of arrays activated simultaneously is increased, the increase in the number of wirings can be reduced, so that the increase in chip size due to the increase in the number of wirings can be suppressed, and the cost can be reduced.

  Further, in the operation mode (for example, stacked word line test mode) in which a plurality of word lines are sequentially activated at different times and the plurality of word lines are selected together, the second and subsequent cycles are selected. As for the word line, cell data can be read (bit line sense) in the same manner as the word line selected in the first cycle. Therefore, retention of redundancy repair information and reading from memory cells (bit line sensing operation) for word lines activated after two cycles can be ensured. Therefore, even after a redundancy repair product, the time is shifted. The test time can be shortened by adopting an operation mode (stacked word line test mode) in which a plurality of word lines are sequentially activated and a plurality of word lines are selected together.

  Further, the number of word lines that can be activated together in the same relief area is maximized, and the number of word lines that can be simultaneously written in the stacked word line test mode is maximized, so that the test time can be shortened.

  Therefore, a semiconductor memory device that can optimize the test technique and the redundancy technique at a high level can be obtained.

  Further, a semiconductor memory device that can shorten the test time and facilitate the function test can be obtained.

  A semiconductor memory device capable of realizing a highly efficient and low-cost redundancy technique can be obtained.

  Furthermore, even when a highly efficient and low-cost redundancy technique is applied, a semiconductor memory device that can shorten the test time and facilitate the function test can be obtained.

  As described above, according to the present invention, a semiconductor memory device capable of optimizing the test technique and the redundancy technique can be obtained.

  Further, a semiconductor memory device that can shorten the test time and facilitate the function test can be obtained.

  Furthermore, a semiconductor memory device capable of realizing a highly efficient and low-cost redundancy technique can be obtained.

  Furthermore, even when a highly efficient and low-cost redundancy technique is applied, a semiconductor memory device that can shorten the test time and facilitate the function test can be obtained.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram for explaining the outline of the semiconductor memory device according to the first embodiment of the present invention, and shows a 64-Mbit memory cell array adopting a centralized redundancy system. As shown in the figure, the memory cell array 11 is divided into a plurality of arrays 11-0 to 11-31, and the array control circuit unit 12 so as to divide each of the arrays 11-0 to 11-31 into two memory blocks. And a control signal wiring portion 13 are arranged. Thus, a 32-bit normal cell array unit (32Mb UNIT (L)) 11A and a 32-bit normal cell array unit (32Mb UNIT (R)) 11B are formed.

  In addition to the memory cell array (usually referred to as a normal cell array) 11 that is normally used, a memory cell array 14 dedicated to row redundancy (including a plurality of row redundancy elements, here referred to as a spare cell array) 14 is provided, and the array 11 in the normal cell array is provided. When a failure occurs in −0 to 11-31, a defective element (defective word line) in the defective array is replaced with a row redundancy element (spare word line) in the spare cell array 14 (spare memory blocks 14A and 14B). It comes to bail out.

  Here, in order to shorten the test time, eight arrays are simultaneously activated during the function test. For example, the hatched arrays 11-3, 11-7,..., 11-31 are simultaneously activated. It becomes.

  The control signal line wiring section 13 is provided with nine control signal lines 13-1 to 13-9. The signal line 13-1 is for the word line state signal WLE for determining the activation timing and deactivation timing of the word line. The signal lines 13-2 and 13-3 are for signals HITL and HITR indicating that replacement by redundancy has occurred. Signal lines 13-4, 13-5, and 13-6 are for addresses DWAL0 to DWAL2 for designating a memory block including a defective word line of normal cell array unit 11A. Signal lines 13-7, 13-8, and 13-9 are for addresses DWAR0 to DWAR2 for designating a memory block including a defective word line of the normal cell array unit 11B.

  When replacement of a defective element (defective word line) in the defective array and a row redundancy element (spare word line) in the spare memory block 14A or 14B occurs, the signal HITR or HITL rises and the defective replaced at that time The addresses DWAL0 to DWAL2 and DWAR0 to DWAR2 indicating the position of the defective memory block in which the element exists are switched. For the memory block at the position where the addresses DWAL0 to DWAL2 and DWAR0 to DWAR2 match, an operation is performed so as not to accept the word line state signal (activation signal) WLE.

  FIG. 2 shows an example of allocation of the addresses DWAL0 to DWAL2 and DWAR0 to DWAR2 in the normal cell array 11. A memory block in the normal cell array unit 11A is selected by the addresses DWAL0 to DWAL2, and a memory block in the normal cell array unit 11B is selected by the addresses DWAR0 to DWAR2. For example, when DWAR0 = 1, DWAR1 = 1, and DWAR2 = 1, the memory blocks 11B-28 to 11B-31 located at the upper left are selected, and when DWAR0 = 0, DWAR1 = 0, and DWAR2 = 0, the memory located at the upper right. Blocks 11B-0 to 11B-3 are selected.

  FIG. 3 is a circuit diagram showing in detail a part of the array control circuit unit 12 and the control signal wiring unit 13 (normal cell array unit 11A side) extracted from the semiconductor memory device shown in FIG. In each of the signal lines 13-2, 13-4, 13-5, and 13-6, a signal HITL indicating that redundancy replacement has occurred from the redundancy control signal output circuit 20, and which memory blocks 11A-0 to 11A-31. Are supplied with signals (addresses) DWAL0 to DWAL2 having information on whether to replace redundancy. Further, array control circuits 12-0 to 12-31 are connected to the signal lines 13-2, 13-4, 13-5, and 13-6 corresponding to the memory blocks.

  The array control circuit 12-0 includes inverters 21-0, 22-0, 23-0, 24-0 and a NAND gate 25-0. The addresses DWAL0 to DWAL2 are supplied to the input terminals of the inverters 21-0, 22-0 and 23-0, and the inverted signals bDWAL0 to bDWAL2 are generated. These signals bDWAL0 to bDWAL2 and the signal HITL are supplied to the input terminal of the NAND gate 25-0. Then, the output signal of the NAND gate 25-0 is inverted by the inverter 24-0, and a signal DWALA0 indicating whether or not to disable the corresponding memory block is generated.

  The array control circuits 12-1 to 12-31 are configured in the same way, and signals DWALA1 to DWALA31 indicating whether or not to disable each corresponding memory block are generated.

  Further, the normal cell array unit 11B is configured in the same manner as the normal cell array unit 11A, and the signal line 13-1 for the word line state signal WLE is used in common by the normal cell array units 11A and 11B.

  FIGS. 4A and 4B are diagrams for explaining the redundancy replacement operation in the semiconductor memory device shown in FIGS. 1 to 3, and show the normal cell array unit 11A as an example. In the centralized redundancy system, when there is one spare cell array, in the normal cell array unit 11A, when word lines of a plurality of memory blocks are activated simultaneously, redundancy replacement can be performed when only one of them has a defect. . At that time, the spare word line of the spare memory block 14A is selected instead, and the word line that replaces the normal cell array is controlled so as not to be selected.

  That is, as shown in the timing chart of FIG. 4B, first, the signal HITL indicating that redundancy replacement has occurred rises to "H" level, and addresses DWAL0 to DWAL2 indicating the positions of the memory blocks to be replaced are set. Is done. In this state, when the signal WLE rises to the “H” level, the word line WL_b to be replaced with the normal cell array is not selected (WL disabled), and the spare word line WL_a of the spare memory block 14A is set to the “H” level. Get up and select. When the signal WLE falls to the “L” level, the spare word line WL_a of the spare memory block 14A also falls to the “L” level and becomes a non-selected state.

As described above, in the semiconductor memory device according to the first embodiment, a plurality (2 ⁿ pieces: n is a natural number) of elements (memory blocks) are simultaneously activated in the normal cell array units 11A and 11B. One signal (HITL / HITR) for deciding whether or not to perform row redundancy replacement in the control of selectively replacing only a defective element with a row redundancy element when any of the plurality of elements is defective And n signals (addresses DWAL and DWAR) for determining which of the plurality of simultaneously activated elements is to be replaced when row redundancy is replaced. Further, a modification may be considered in which a spare cell array is provided for redundancy, and a redundancy element in the spare cell array replaces any defective element (defective word line) in the normal cell array unit.

  That is, the activation signal of the memory block is not required for the number of simultaneously activated elements (memory blocks), and the word line state signal WLE is used by unifying the activation signal and the deactivation signal. When the signal WLE rises, the word line whose address matches is activated, and when the word line state signal WLE falls, the word line is deactivated. For replacement of row redundancy, an address (DWALn, DWARn) having information on which memory block is replaced and a signal (HITL, HITR) indicating selection of redundancy are used. Furthermore, addresses DWALn and DWARn having information on which normal cell array is to be replaced are decoded locally in the array control circuit of each memory block.

Therefore, according to the configuration as described above, since a plurality of elements (memory blocks) can be activated at the same time, the test time can be shortened, and a signal having redundancy information can be locally decoded. The test time can be shortened more easily. In addition, the increase in the number of control signal lines can be minimized. For example, when the number of simultaneously active arrays is eight, for example, the necessary wirings are the signal WLE, the signals HITL and HITR, and the addresses DWAL0 to DWAL2 and DWAR0. Nine of DWAR2 are sufficient. That is, when the number of memory blocks is ^{the 2 n} is simultaneously activated, the address DWAL, DWAR may be of n. As a result, an increase in the number of wirings can be suppressed, which can contribute to cost reduction by reducing the chip size.

[Second Embodiment]
FIG. 5 to FIG. 12 are for explaining a semiconductor memory device according to the second embodiment of the present invention. The test time is shortened by adopting a stacked word line test mode (Stacked WL Test Mode). It aims to make it easier.

  Here, the stacked word line test mode (also referred to as Multiple WL Test Mode) is a word that is simultaneously activated in the memory cell array (or cell array unit) during a normal read / write operation, for example. When the number of lines is N, this is an operation mode in which N or more word lines are activated by sequentially activating word lines at different times.

  In the stacked word line test mode, there are some restrictions on the number of word lines that can be selected together to ensure reading from the memory cell. That is, only one word line can be activated for several bit line pairs and one associated sense amplifier (hereinafter collectively referred to as a memory block). When the sense amplifier is shared with the adjacent memory block (Shared Sense Amp), only one of the memory blocks that share the sense amplifier is a word line. Cannot be selected. In other words, only a maximum of N / 2 word lines can be selected in a memory cell array (or cell array unit) having N memory blocks.

  Next, the configuration of a shared sense amplifier type semiconductor memory device that realizes the stacked word line test mode will be described with reference to FIGS. FIG. 5 shows a part of a bank composed of a plurality of cell array units. One cell array unit 30 is composed of 32 memory blocks (32 memory blocks / unit), and an active memory block 31AB and a sleep memory block 31SB are Alternatingly arranged. A row decoder section 33, a word line (WL) driver section 34, array control circuits 35T and 35B, and the like are arranged adjacent to these memory blocks 31AB and 31SB. Each memory block (Array Nos. 0 to 31) is divided into two by 8K rows and selected by row addresses AR_ADD9 to AR_ADD12 as shown in the figure.

  More specifically, two active sense amplifiers 36AS are disposed on both sides of the active memory block 31AB, and a sleep sense amplifier 36SS is disposed adjacent to the sleep memory block 31SB. A row decoder section 33 and a word line driver section 34 are disposed adjacent to each memory block, and a first array control circuit (top) 35T and a second array control circuit are adjacent to the active sense amplifier 36AS. (Bottom) 35B is arranged.

  Although not shown, the memory cell array (or cell array unit) 30 includes a column decoder, a redundancy control circuit, a redriver, an X predecoder, a bank control circuit, and the like.

  FIG. 6 shows a memory block 31, a sense amplifier 36, a row decoder section 33, a word line driver section 34, and array control circuits 35T (35_n (t)), 35B (35_n (b) in the memory cell array (or cell array unit) 30. )) Is extracted and is a circuit diagram showing a specific configuration example. The memory block 31_n and the sense amplifiers 36_n (t) and 36_n (b) are coupled to each other by a plurality of bit line pairs BL / bBL. The word line WL connected to each memory block 31_n is driven by the word line driver 34A disposed in the word line driver unit 34. The word line driver 34A is supplied with a decode signal output from the row decoder 33A and signals WLDV / WLRST for controlling driving and resetting of the word line output from the WLDV driver 38. The row decoder 33A is supplied with an address signal XAdd output from the peripheral circuit and the redriver 37 and a signal TWLOFF for stopping driving of the word line output from the TWLOFF control circuit 39. The TWLOFF control circuit 39 is supplied with a signal bWLOFF for stopping driving of the word line output from the peripheral circuit and the redriver 37 and a block selection signal BLKSEL output from the block selector 43. Yes.

  On the other hand, first and second array control circuits 35_n (t) and 35_n (b) are connected to the sense amplifiers 36_n (t) and 36_n (b), respectively. These array control circuits 35_n (t) and 35_n (b) include the WLDV driver 38, the N / PSET driver 40, the sense amplifier (SA) control circuit 41, the TWLON control circuit 42, the block selector 43, and the like. It is configured. Activation / deactivation of the sense amplifier 36_n (t / b) is controlled by a signal N / PSET output from the N / PSET driver 40. The N / PSET driver 40 is supplied with the output signal SAVLD of the SA control circuit 41 and the sense amplifier enable signal SAE output from the peripheral circuit and the redriver 37. The WLDV driver 38 is supplied with a signal TWLOFF output from the TWLOFF control circuit 39 and a signal TWLON output from the TWLON control circuit 42, respectively. The driving of the word line is determined by the signal TWLON, and the driving stop is determined by the signal TWLOFF. The TWLON control circuit 42 is supplied with a signal bWLON output from the peripheral circuit and the redriver 37. Further, the SA control circuit 41 includes a signal bWLON output from the peripheral circuit and the redriver 37, a signal BLKSEL output from the block selector 43, and a signal BLKSEL output from the adjacent block selector 43 in the next stage. Are supplied respectively. The block selector 43 is supplied with a signal XAdd output from the peripheral circuit and the redriver 37.

  FIG. 7 is a circuit diagram showing an example of the configuration of the peripheral circuit in the circuit shown in FIG. 6 and the X predecoder, redundancy control circuit, and redriver in the redriver 37 extracted. This circuit includes a redundancy control circuit 50, a redriver 51, a bWLOFF latch circuit 52, a redriver 53, an SAE latch circuit 54, a redriver 55, a bRPRE latch circuit 56, an X predecoder 57, and the like.

  The signal ARAdd is supplied to the redundancy control circuit 50, and the signal bFWLON output from the redundancy control circuit 50 is supplied to the redriver 51. The redriver 51 outputs the signal bWLON.

  The signal TMWLLTC and the signal bRSTR are supplied to the bWLOFF latch circuit 52, the output signal of the bWLOFF latch circuit 52 is supplied to the redriver 53, and the signal bWLOFF is output from the redriver 53.

  The signal TMSALTC and the signal QSAE are supplied to the SAE latch circuit 54, the output signal of the SAE latch circuit 54 is supplied to the redriver 55, and the signal SAE is output from the redriver 55.

  Further, the signal bRSTR, the signal TMSALTC, and the signal QSAE are respectively supplied to the bRPRE latch circuit 56, and the output signal bRPRE and the signal ARAdd of the bRPRE latch circuit 56 are supplied to the X predecoder 57, and the X predecoder 57 A signal XAdd is output.

  FIG. 8 is a circuit diagram showing a configuration example of the bWLOFF latch circuit 52 in the circuit shown in FIG. The bWLOFF latch circuit 52 includes inverters 58 to 61 and a NAND gate 62. The signal bRSTR is supplied to the input terminal of the inverter 58, and the signal TMWLLTC is supplied to the input terminal of the inverter 59. The output signals of the inverters 58 and 59 are supplied to the NAND gate 62, and the output signal of the NAND gate 62 is output as the signal bWLOFF via the inverters 60 and 61, respectively.

  FIG. 9 is a circuit diagram showing a configuration example of the SAE latch circuit 54 in the circuit shown in FIG. The SAE latch circuit 54 includes P-channel MOS transistors Q1 and Q2, an N-channel MOS transistor Q3, and inverters 63 to 66. The current paths of the MOS transistors Q1 to Q3 are connected in series between the power supply Vcc and the ground point (or negative power supply) Vss. A signal TMSALTC is supplied to the gate of the MOS transistor Q1, and a signal QSAE is supplied to the gates of the MOS transistors Q2 and Q3. The input end of the inverter 63 is connected to the connection point of the current paths of the transistors Q2 and Q3. The output terminal of the inverter 64 is connected to the input terminal of the inverter 63, and the input terminal of the inverter 64 is connected to the output terminal. The output terminal of the inverter 63 is connected to the input terminal of the inverter 65, and the output terminal of the inverter 65 is connected to the input terminal of the inverter 66. The signal SAE is output from the output terminal of the inverter 66.

  FIGS. 10A and 10B are circuit diagrams showing configuration examples of the bRPRE latch circuit 56 and the X predecoder 57 in the circuit shown in FIG. The bRPRE latch circuit 56 shown in FIG. 10A includes inverters 67 to 69, a NOR gate 70, and a NAND gate 71. The signal TMSALTC is supplied to one input terminal of the NAND gate 71 via the inverter 67. The signal QSAE and the signal bRSTR are supplied to the input terminal of the NOR gate 70, and the output signal of the NOR gate 70 is supplied to the other input terminal of the NAND gate 71. The output of the NAND gate 71 is output as a signal bRPRE via inverters 68 and 69, respectively.

  The X predecoder 57 shown in FIG. 10B includes a P-channel MOS transistor Q4, N-channel MOS transistors Q5 to Q7, and inverters 72 to 75. The current paths of the MOS transistors Q4 to Q7 are connected in series between the power supply Vcc and the ground point Vss, and the signal bRPRE output from the bRPRE latch circuit 56 is supplied to the gates of the MOS transistors Q4 and Q5. Is supplied with an address signal AR_i, and an address signal AR_j is supplied to the gate of the MOS transistor Q7. The input end of the inverter 72 is connected to the connection point of the current paths of the transistors Q4 and Q5. The output end of the inverter 73 is connected to the input end of the inverter 72, and the input end of the inverter 73 is connected to the output end. The output terminal of the inverter 72 is connected to the input terminal of the inverter 74, and the output terminal of the inverter 74 is connected to the input terminal of the inverter 75. Then, the signal X_ADD is output from the output terminal of the inverter 75.

  The signal X_ADD (XAdd) is input to the WLDV driver 38, the row decoder 33A, and the block selector 43, respectively. For example, in the case of 8K rows and 32 memory blocks / units, X_ADD01 (AR_ADD0, AR_ADD1) is sent to the WLDV driver 38, X_ADD23, 45, 678 (AR_ADD2 to AR_ADD8) is sent to the row decoder 33A, and X_ADD910, 1112 ( AR_ADD9 to AR_ADD12) are input to the block selector 43, respectively. An 8K word line is selected using these addresses X_ADD.

  Next, the operation of the stacked word line test mode will be described with reference to the timing chart of FIG. When entry is made to the stacked word line test mode (TM ENTRY), TMSALTC = "H" and TMWLLTC = "H". In response to this, bWLOFF = “L” → “H” and bRPRE = “L” → “H”, and this state is maintained unless the test mode is exited.

  First, the first word line is selected and raised to "H" level (cycle # 1). Since there are 32 memory blocks / memory cell array (cell array unit), the maximum number of word lines that can be selected is 16 / memory cell array (cell array unit). Since only one word line in each memory block is selected, the row addresses (AR_ADD0 to AR_ADD8) for decoding in the array are fixed. On the premise of the shared sense amplifier system, in order to select 16 memory blocks without activating the adjacent memory block, the row addresses AR_ADD10, AR_ADD11, AR_ADD12 for selecting the memory block are added and fetched (row address AR_ADD9). Is fixed).

  When the bank active command BA is received, the signal bRSTR (internal RAS) changes from “L” to “H”, and the fetched row address is transferred to AR_ADD9, AR_ADD10, AR_ADD11, AR_ADD12, and X_ADD910_0, X_ADD1112_0 is activated. In response to the activated X_ADD910_0 and X_ADD1112_0, the signal BLKSEL_0 output from the block selector 43 changes from “L” to “H”. In response to this, the TWLOFF control circuit 39 changes TWLOFF = “H” → “L” to cancel the precharge of the row decoder 33A. As a result, the word line driver 34A determined by the row decoder selected by the previously activated X_ADD23, X_ADD45, and X_ADD678 is activated.

  The fetched AR_ADD is also input to the redundancy control circuit 50, and is compared with the redundancy information. That is, the input AR_ADD is compared with redundancy information prepared in advance (for example, address information determined by fuse cutting or the like). As a result, when the matching is not achieved (mismatching, hereinafter, redundancy miss or miss), the signal bFWLON becomes an “L” level pulse. On the contrary, when matching is achieved (matching, hereinafter, redundancy hit or hit), the signal bFWLON holds the “H” level.

  In the case of a redundancy miss, upon receiving an “L” level pulse of the signal bWLON, TWLON_0 (b / t) = “L” → “H”, WLDV_0 determined by X_ADD01_0 = “L” → “H”, WLRST_0 = “H” → “L”, the word line driver activated first receives WLDV_0 = “H”, WLRST_0 = “L”, changes the word line WL_0 from “L” → “H”, and is written to the memory cell The transferred data is transferred onto the bit line BL_0.

  Next, activation of the sense amplifier 36_n (t / b) will be described. When the sense amplifier control circuit 41 selected by the signal BLKSEL_0 receives bWLON = “L”, SAVLD_0 (b / t) = “L” → “H”. With the word line delay guarantee circuit arranged in the peripheral circuit section, it is estimated that WL = “H” sufficiently, and QSAE = “L” → “H”. Upon receiving QSAE = “H”, the SAE latch circuit 54 outputs SAE = “L” → “H” via the redriver 55. Since TMSALTC = "H" is currently held, SAE = "H" is held unless the test mode is exited. In response to SAE = “L” → “H”, the N / PSET driver 40 changes NSET — 0 (b / t) = “L” → “H” and bPSET — 0 (b / t) = “H” → “L” to sense The amplifier 36_n (t / b) is activated. Thereby, the sense operation of bit line pair BL / bBL is performed via sense amplifier 36_n (t / b).

  Thereafter, when a bank precharge command PR is received, bRSTR = “H” → “L” and QSAE = “H” → “L”. In the normal read / write operation, bWLSTR = “L” is received and bWLOFF = “H” → “L”, and the selected WL = “H” → “L”. In response to QSAE = "L", SAE = "L" → NSET = "L" / bPSET = "H", and the sense amplifier 36_n (t / b) is deactivated to equalize the bit line pair BL / bBL. .

  However, when the test mode is entered, bWLOFF = “H” / SAE = “H” is held, so that the word line WL is selected and activated, and the sense amplifier 36_n (t / b) is also set. In the activated state, the potential of the bit line pair BL / bBL remains latched. Since bRPRE = “H” is also held, all the selected X_ADDs are also kept in the activated state (X_ADD is not reset). Other than that, the state shifts to the same state as the state in which the bank precharge command of the normal operation is received.

  Next, the operation for selecting the next word line WL is started (cycle # 2). Similar to the first cycle, when a bank active command BA is accepted, a new row address (AR_ADD) is fetched. bRSTR (internal RAS) changes from “L” to “H”, and the fetched row address is transferred to AR_ADD9, AR_ADD10, AR_ADD11, AR_ADD12, and X_ADD910_1, X_ADD1112_1 is activated. At this time, X_ADD910_0 and X_ADD1112_0 activated in the previous cycle hold the activated state. Thereafter, the same operation as in the first cycle is performed, and the word line driver 34A determined by the selected row decoder 33A is activated. The fetched AR_ADD is also input to the redundancy control circuit, and is compared with the redundancy information.

  In the case of a redundancy miss, upon receiving an “L” level pulse of the signal bWLON, TWLON_1 (b / t) = “L” → “H”, WLDV_1 determined by X_ADD01_1 = “L” → “H”, WLRST_1 = “ The word line driver 34A, which has been activated from “H” to “L”, receives WLDV_1 = “H” and WLRST_1 = “L”, changes the word line WL_1 from “L” to “H”, and is stored in the memory cell. The transferred data is transferred onto the bit line BL_1.

  Regarding the activation of the sense amplifier 36_n (t / b), the operation differs between the first cycle and the second and subsequent cycles. When the sense amplifier control circuit 41 selected by the signal BLKSEL_1 receives bWLON = “L”, the operation is the same as that in the first cycle until SAVLD_1 (b / t) = “L” → “H”. . Since SAE = "H" is held this time, the N / PSET driver 40 receives SAVLD_1 (b / t) = "H" and immediately receives NSET_1 (b / t) = "L" → "H", bPSET_1 ( b / t) = “H” → “L”. Therefore, before the word line WL_1 is activated and the data of the memory cell is sufficiently transferred to the bit line BL_1, the sense amplifier 36_n (t / b) is activated, and the bit line sensing operation is performed with uncertain data. Since the data in the memory cell stored in the word line WL_1 may be destroyed, the operation is not guaranteed.

  Thereafter, all activated word lines are returned to the precharge state. When a command for exiting the stacked word line test mode is accepted, TMSALTC = “H” → “L” and TMWLLTC = “H” → “L”. In response, bWLOFF = “H” → “L” and bRPRE = “H” → “L”, and all the word lines and bit lines activated in the test mode return to the precharge state. However, since the equalization operation of the bit line starts simultaneously with WL = “H” → “L”, the bit line performs the equalization operation before the word line level drops (before the memory cell transistor is completely cut off). Start. Therefore, the data in the memory cell is not guaranteed.

  Next, consider a redundancy hit (see the timing chart of FIG. 12). Here, description will be made on the assumption that a redundancy hit has occurred in the second cycle. The entry up to the test mode (TM ENTRY) and the cycle active and bank precharge of cycle # 1 are the same as in the case of the redundancy miss.

  In the second cycle, the operation for selecting the next word line is started. When a bank active command BA is accepted as in the first cycle, a new row address (AR_ADD) is fetched. Then, the word line driver 34A selected by the row decoder 33A is activated by the same operation as in the first cycle. The fetched AR_ADD is also input to the redundancy control circuit and is compared with the redundancy information. In the case of a redundancy hit, since the signal bWLON is maintained at the “H” level by the redundancy control circuit, TWLON_1 (b / t) = “L” remains, and WLDV_1 = 1 ”L” determined by X_ADD01_1. WLRST_1 remains “H”. Therefore, the previously activated word line driver 34A receives WLDV_1 = “L” and WLRST_1 = “H”, the word line WL_1 = “L”, and maintains the inactive state.

  The activation of the sense amplifier 36_n (t / b) also differs depending on whether it is a miss or a hit. At the time of redundancy hit, since the signal bWLON = “H”, the sense amplifier control circuit 41 selected by the signal BLKSEL_1 also continues to output SAVLD_1 (b / t) = “L”. Therefore, since TMSALTC = “H”, SAE = “H” is held, but the N / PSET driver receives SAVLD — 1 (b / t) = “L” and NSET — 1 (b / t) = “L”, bPSET — 1 (B / t) = “H”, and the sense amplifier 36 — n (t / b) is not activated. This is the same operation as in a normal redundancy hit. That is, a desired operation is performed.

  In the third cycle (cycle # 3), the operation for selecting the next word line is started. When the bank active command BA is accepted as in the first and second cycles, a new row address (AR_ADD) is fetched, and the word line driver 34A determined by the newly selected row decoder in the same operation as in the first and second cycles. Activate. The fetched AR_ADD is also input to the redundancy control circuit and compared with the redundancy information.

  Next, consider the case of a redundancy mistake. As in the first cycle, upon receiving an “L” level pulse of the signal bWLON, TWLON_2 (b / t) = “L” → “H”, WLDV_2 determined by X_ADD01_2 = “L” → “H”, WLRST_2 = “H” → "L", the word line driver activated first receives WLDV_2 = "H", WLRST_2 = "L", changes the word line WL_2 from "L" → "H", and the data written in the memory cell Transfer on the bit line. The word line selected in this cycle is activated.

  Here, attention is paid to the word line that has been hit by redundancy in the second cycle. Even if the array control circuit hit in the second cycle and the row decoder are in the third cycle (miss), all X_ADDs that have been accessed are held. That is, even in the third cycle, X_ADD910_1 and X_ADD1112_1 accessed in the second cycle all hold the activated state. In the block selector 43, BLKSEL_1 is held. Further, since bWLOFF = "H", TWLOFF_1 = "H" is held, and the word line driver 34A selected by the row decoder 33A is in an activated state. Here, when the bWLON = “L” pulse in the third cycle is output, the signal bWLON is a global signal in the memory cell array (cell array unit), so that TWLON — 1 (b) in the array control circuit selected in the second cycle. / T) = “H” pulse is output. In response to this, the signal WLDV_1 that was inactive in the second cycle is activated, and there is a possibility that a word line that should not be selected due to a hit is selected.

  That is, the semiconductor memory device according to the second embodiment performs a desired operation that the word line / sense amplifier is inactive in the redundancy hit cycle, but the word line selected in the cycle after the next cycle. In addition, the sense amplifier is activated and the word line and the sense amplifier that were previously hit and deactivated may be activated. Under this condition, the operation is not guaranteed.

[Third Embodiment]
In the semiconductor memory device according to the second embodiment described above, in the test mode (stacked word line test mode) in which a plurality of word lines can be selected at different times, retention of redundancy relief information, and The memory cell read (bit line sense) operation for the word lines activated after the second line is not completely guaranteed. For this reason, it is impossible to apply the stacked word line test mode to a product after redundancy relief (after fuse blow), and only good products before redundancy relief or needless relief can be tested.

  Therefore, in the third embodiment, the memory cell read operation (bit line sense) for the word line activated after the second cycle and the retention of the redundancy information can be guaranteed, and the product after redundancy relief The memory cell data guarantee is also possible. However, the maximum number of word lines that can be activated for one memory block is one.

  13 to 27 are for explaining a semiconductor memory device according to the third embodiment of the present invention. FIG. 13 shows a part of a bank composed of a plurality of memory cells, and basically has the same configuration as that of the second embodiment shown in FIG.

  That is, one memory cell array (or cell array unit) 30 is composed of 32 memory blocks (32 memory blocks / unit), and active memory blocks 31AB and sleep memory blocks 31SB are alternately arranged. A row decoder section 33, a word line (WL) driver section 34, array control circuits 35T and 35B, and the like are disposed adjacent to these memory blocks. Each memory block (Array Nos. 0 to 31) is divided into two by 8K rows and is selected by addresses AR_ADD9 to AR_ADD12 as shown.

  More specifically, active sense amplifiers 36AS are disposed on both sides of the active memory block 31AB, and a sleep sense amplifier 36SS is disposed adjacent to the sleep memory block 31SB. A row decoder section 33 and a word line driver section 34 are adjacent to each memory block, and a first array control circuit (top) 35T and a second array control circuit (bottom) are adjacent to the active sense amplifier 36. ) 35B is arranged.

  Although not shown, the memory cell array (or cell array unit) 30 includes a column decoder, a redundancy control circuit, a redriver, an X predecoder, a bank control circuit, and the like.

  FIG. 14 shows a memory block 31_n, sense amplifiers 36_n (t), 36_n (b), a row decoder section 33, a word line driver section 34, and an array control circuit 35T (35_n (t) in the memory cell array (or cell array unit) 30. )), 35B (35_n (b)) is extracted and is a circuit diagram showing a specific configuration example. The memory block 31_n and the sense amplifiers 36_n (t) and 36_n (b) are coupled to each other by a plurality of bit line pairs BL / bBL. The word line WL_n connected to each memory block 31_n is driven by the word line driver 34A. The word line driver 34A is supplied with a decode signal output from the row decoder 33A and signals WLDV_n / WLRST_n for controlling driving and resetting of the word lines output from the WLDV driver 38. The row decoder 33A is supplied with the address signal XAdd output from the peripheral circuit and the redriver 37 and the latch output TRDE_n of the TRDE latch circuit 44, respectively. The TRDE latch circuit 44 includes signals TSTCWL and WLE output from the peripheral circuit and the redriver 37, a signal XBLKP_n output from the block selector 43 in the corresponding array control circuit, and a block in the array control circuit in the next stage. A signal XBLKP_n + 1 supplied from the selector is supplied.

  The sense amplifiers 36_n (t) and 36_n (b) are connected to first and second array control circuits 35_n (t) and 35_n (b), respectively. These array control circuits 35_n (t) and 35_n (b) are respectively the WLDV driver 38, the N / PSET driver 40, the sense amplifier (SA) latch circuit 45, the sense amplifier (SA) control circuit 41, the TWLON latch circuit 46, It includes a HIT control circuit 47, a latch circuit (BLKSEL latch circuit) 48, a block selector 43 and the like. Activation / deactivation of the sense amplifier 36_n (t / b) is controlled by a signal N / PSET output from the N / PSET driver 40. The N / PSET driver 40 is supplied with the latch output of the SA latch circuit 45. The SA latch circuit 45 is supplied with an output signal SAVLD_n of the SA control circuit 41 and signals bSAON and bSAOFF output from the peripheral circuit and the redriver 37, respectively.

  The WLDV driver 38 is supplied with a signal TWLON_n output from the TWLON latch circuit 46 and a signal XAdd output from the peripheral circuit and the redriver 37. The SA control circuit 41 is supplied with a signal BLKSEL_n output from the latch circuit 48 in the corresponding array control circuit and a signal BLKSEL_n + 1 output from the latch circuit 48 in the array control circuit at the next stage. Further, the TWLON latch circuit 46 is supplied with signals TSTCWL and WLE output from the peripheral circuit and the re-driver 37, respectively.

  The HIT control circuit 47 includes a signal HIT / DWA output from the peripheral circuit and the re-driver 37, a signal XBLKP_n output from the block selector 43 in the corresponding array control circuit, and a signal in the next stage array control circuit. A signal XBLKP_n + 1 output from the block selector 43 is supplied. Further, the latch circuit 48 is supplied with the signal bSAOFF output from the peripheral circuit and the redriver 37 and the output signal XBLKP_n of the block selector 43. The block selector 43 is supplied with a signal XAdd output from the peripheral circuit and the redriver 37.

  That is, in the semiconductor memory device according to the third embodiment, in the stacked word line test mode, the BLKSEL latch circuit 48 for maintaining the state of BLKSEL = “H”, NSET = “H” / SA latch circuit 45 for holding the bPSET = “L” state, a function for controlling TWLON = “L” / “H”, and a function for holding the “H” level state in the stacked word line test mode Each array control circuit includes a TWLON latch circuit 46 having both a function for controlling TRDE = "L" / "H" and a TRDE latch circuit having a function for maintaining the state of TRDE = "H" level in each array control circuit. It is provided one by one.

  FIG. 15 is a circuit diagram illustrating a configuration example of the peripheral circuit and the X predecoder, the redundancy control circuit, and the redriver in the redriver 37 extracted from the circuit shown in FIG. This circuit includes a redundancy control circuit 80, a redriver 81, a redundancy control circuit 82, a WLON / OFF control circuit 83, a redriver 84, a SAON / OFF control circuit (pulse generator) 85, a redriver 86, a bRPRE control circuit 87, X It includes a predecoder 88, an X predecoder 89, an STCRST control circuit 90, and the like.

  The signal AR_ADD is supplied to the redundancy control circuit 80, and the signal bFHIT and the signal bFDWA output from the redundancy control circuit 80 are supplied to the redriver 81. The redriver 81 outputs a signal HIT and a signal DWA.

  The signal RADLTC and the signal bFWLON output from the redundancy control circuit 82 are supplied to the WLON / OFF control circuit 83. The signal FWLE output from the WLON / OFF control circuit 83 is supplied to the redriver 84, and the signal WLE is output from the redriver.

  This signal WLE is a word line selection signal obtained by combining the signal bWLON and the signal bWLOFF in the second embodiment. The fall of the signal bWLON in the second embodiment and the rise of the word line state signal WLE in the third embodiment, the fall of the signal bWLOFF in the second embodiment and the third embodiment. The word line state signal WLE falling in the embodiment is equivalent in timing.

  Further, the signal bSTCRST and the signal QSE are supplied to the SAON / OFF control circuit 85, and the signal bFSAON and the signal bFSAOFF output from the SAON / OFF control circuit 85 are supplied to the redriver 86. The redriver 86 outputs a signal bSAON and a signal bSAOFF.

  The signal bSAON and the signal bSAOFF are obtained by dividing the signal SAE in the second embodiment into two signals. The rising edge of the signal SAE in the second embodiment is equivalent to the falling edge of the “L” pulse of the signal bSAON in the third embodiment. However, even in the stacked word line test mode, the “L” state of the signal bSAON is not maintained, and an “L” pulse is generated every cycle. The signal bSAOFF differs from the second embodiment in the following points. That is, during the normal read / write operation, the falling edge of the signal SAE and the falling edge of the “L” pulse of the signal bSAOFF in the second embodiment are equivalent in timing, but the stacked word line test In the mode, in response to bSTCRST = “H” → “L”, the signal bSAOFF outputs an “L” pulse.

  The signal QSAE and the signal RADLTC are supplied to the bRPRE control circuit 87, and the signal bRPRE and the signal AR_ADD output from the bRPRE control circuit 87 are supplied to the X predecoder 88. The X predecoder 88 outputs a signal XAdd_bank for selecting a block. The signal AR_ADD is supplied to the X predecoder 89, and the signal XAdd is output from the X predecoder 89.

  Further, the signal TMSTCWL and the signal bRSTR are supplied to the STCRST control circuit 90, and the signal bSTCRST is output from the STCRST control circuit 90. This signal bSTCRST is for delaying the signal bSAOFF in the stacked word line test mode.

  Unlike the second embodiment described above, the semiconductor memory device according to the third embodiment uses two types of X predecoders according to addresses. The X predecoder 89 is a method in which the signal X_ADD is not reset by the signal bRPRE, and is used for an address used for selection of WLDV / WLRST and row decoder. On the other hand, the X predecoder 88 is a system in which the signal X_ADD is reset by the signal bRPRE as in the second embodiment, and is used for an address used for selection of the array control circuit. The signal X_ADD is input to the WLDV driver 38 and the row decoder 33A. The signal X_ADD_bank is input to the block selector 43.

  In the case of 8K row, X_ADD01 (AR_ADD0, AR_ADD1) is WLDV driver 38, X_ADD23, X_ADD45, X_ADD678 (AR_ADD2 to AR_ADD8) is row decoder 33A, X_ADD910, X_ADD1112 (AR_ADD9 to AR_ADD12) are input to block_AR12. . An 8K word line is selected using these row address signals X_ADD.

  FIG. 16 is a circuit diagram showing a specific configuration example of the WLON / OFF control circuit 83 in the circuit shown in FIG. The WLON / OFF control circuit 83 includes inverters 91 and 92 and a NAND gate 93. The signal bFWLON is supplied to one input terminal of the NAND gate 93 via the inverter 91, and the signal RADLTC is supplied to the other input terminal of the NAND gate 93. The output signal of the NAND gate 93 is supplied to the input terminal of the inverter 92, and the signal FWLE is output from the output terminal of the inverter.

  FIG. 17 is a circuit diagram showing a specific configuration example of the SAON / OFF control circuit 85 in the circuit shown in FIG. The SAON / OFF control circuit 85 includes a NOR gate 94, NAND gates 95 and 96, inverters 97 to 102, and delay circuits 103 and 104. The signal QSAE is supplied to one input terminal of the NAND gate 95 and is supplied to the other input terminal of the NAND gate 95 via the inverter 97 and the delay circuit 103. The output signal of the NAND gate 95 is output as a signal bFSAON via inverters 99 and 100. The signal QSAE and the signal bSTCRST are supplied to the NOR gate 94. The output signal of the NOR gate 94 is supplied to one input terminal of the NAND gate 96 and also supplied to the other input terminal of the NAND gate 96 via the inverter 98 and the delay circuit 104. The output signal of the NAND gate 96 is output as the signal bFSAOFF via the inverters 101 and 102.

  FIG. 18 is a circuit diagram showing a specific configuration of the STCRST control circuit 90 in the circuit shown in FIG. The STCRST control circuit 90 includes inverters 105 and 109, a delay circuit 106, and NAND gates 107 and 108. The signal bRSTR is supplied to the input terminal of the inverter 105. The output signal of the inverter 105 is supplied to one input terminal of the NAND gate 107 and also supplied to the other input terminal of the NAND gate 107 via the delay circuit 106. The output signal of the NAND gate 107 is supplied to one input terminal of the NAND gate 108, and the signal TMSTCWL is supplied to the other input terminal of the NAND gate 108. An output signal of the NAND gate 108 is supplied to an inverter 109, and a signal bSTCRST is output from the inverter 109.

  FIGS. 19 to 24 are circuit diagrams for explaining the control circuit shown in FIG. 14 and a latch circuit for holding address and redundancy information, respectively. Next, specific configuration examples of the control circuit and the latch circuit will be described.

  FIG. 19 is a circuit diagram showing a specific configuration example of the BLKSEL latch circuit 48. The latch circuit 48 includes NAND gates 110 and 111 and inverters 112 and 113. The signal bSAOFF is supplied to one input terminal of the NAND gate 110, and the output signal of the NAND gate 111 is supplied to the other input terminal. The output signal of the NAND gate 110 is supplied to the input terminal of the inverter 113 and is also supplied to one input terminal of the NAND gate 111. The signal XBLKP_n is supplied to the other input terminal of the NAND gate 111 via the inverter 112. A signal BLKSEL_n is output from the output terminal of the inverter 113.

  FIG. 20 is a circuit diagram showing a specific configuration example of the TWLON latch circuit 46. The latch circuit 46 includes P-channel MOS transistors Q8 to Q11, N-channel MOS transistors Q12 to Q15, and inverters 114 and 115. The current paths of the MOS transistors Q8, Q9, Q12, Q13, and Q14 are connected in series between the power supply Vcc and the ground point Vss. Between the power supply Vcc and the connection point of the current paths of the MOS transistors Q9 and Q12, the current paths of the MOS transistors Q10 and Q11 are connected in series. The current path of the MOS transistor Q15 is connected between the connection point of the current paths of the MOS transistors Q13 and Q14 and the ground point Vss. A signal TSTCWL is supplied to the gate of the MOS transistor Q8, and a signal WLE is supplied to the gates of the MOS transistors Q9 and Q12. The signal bTHIT_n is supplied to the gate of the MOS transistor Q10, and the signal TSTCWL is supplied to the gate of the MOS transistor Q11. Further, the signal bTHIT_n is supplied to the gate of the MOS transistor Q13, the signal XBLKP_n is supplied to the gate of the MOS transistor Q14, and the signal XBLKP_n + 1 is supplied to the gate of the MOS transistor Q15. The input end of the inverter 114 is supplied to the connection point of the current paths of the MOS transistors Q9, Q11, Q12. The output terminal of the inverter 114 is connected to the input terminal of the inverter 115, and the output terminal of the inverter 115 is connected to the input terminal of the inverter 114. A signal TWLON_n is output from the output terminal of the inverter 114.

  FIG. 21 is a circuit diagram showing a specific configuration example of the SA control circuit 41. The control circuit 41 includes a NOR gate 200, inverters 201 to 203, a P-channel MOS transistor Q70, and N-channel MOS transistors Q71 and Q72. The current paths of the MOS transistors Q70 to Q72 are connected in series between the power supply Vcc and the ground point Vss. The signals BLKSELt and BLKSELb are supplied to the NOR gate 200, and the output signal of the NOR gate 200 is supplied to the gates of the MOS transistors Q70 and Q71 via the inverter 201. The signal TWLON is supplied to the gate of the MOS transistor Q72. The input end of the inverter 202 is connected to the connection point of the current paths of the MOS transistors Q70 and Q71. The output terminal of the inverter 202 is connected to the input terminal of the inverter 203, and the input terminal is connected to the output terminal of the inverter 203. A signal SAVLD_n is output from the output terminal of the inverter 202.

  FIG. 22 is a circuit diagram showing a specific configuration example of the SA latch circuit 45. The latch circuit 45 includes NAND gates 116 and 117. The signal SAVLD_n and the signal bSAOFF are supplied to the first and second input terminals of the NAND gate 116, respectively, and the output signal of the NAND gate 117 is supplied to the third input terminal. The output signal of the NAND gate 116 is supplied to one input terminal of the NAND gate 117, and the signal bSAON is supplied to the other input terminal of the NAND gate 117. The sense amplifier activation signal bSAE_n is output from the output terminal of the NAND gate 116.

  FIG. 23 is a circuit diagram showing a specific configuration example of the TRDE latch circuit 44. The latch circuit 44 includes NOR gates 118 and 119, inverters 120 to 122, a level shifter 123 for converting the "Vcc" level to the "Vpp" level, P channel type MOS transistors Q16 to Q18, and N channel type MOS transistors Q19 to Q21. Has been. The current paths of the MOS transistors Q16 to Q20 are connected in series between the power supply Vcc and the ground point Vss. The current path of the MOS transistor Q21 is connected between the connection point of the current paths of the MOS transistors Q18 and Q19 and the ground point Vss.

  The signal TSTCWL is supplied to one input terminal of the gate of the MOS transistor Q16 and the NOR gate 119. The signal XBLKP_n and the signal XBLKP_n + 1 are supplied to the NOR gate 118, and the output signal of the NOR gate 118 is supplied to the other input terminal of the NOR gate 119 and the gate of the MOS transistor Q20 via the inverter 120. The output signal of the NOR gate 119 is supplied to the gates of the MOS transistors Q17 and Q21.

  The input end of the inverter 121 is connected to the connection point of the current paths of the MOS transistors Q18, Q19, Q21, and the input end of the inverter 122 and the input end of the level shifter 123 are connected to the output end of the inverter 121. The output terminal of the inverter 122 is connected to the input terminal of the inverter 121. Then, the signal TRDE_n is output from the output terminal of the level shifter 123.

  FIG. 24 is a circuit diagram showing a specific configuration example of the HIT control circuit 47. The control circuit 47 includes a NAND gate 124, an inverter 125, P-channel MOS transistors Q22 and Q23, and N-channel MOS transistors Q24 to Q27. The current paths of the MOS transistors Q22 to Q25 are connected in series between the power supply Vcc and the ground point Vss. Between the connection points of the current paths of the MOS transistors Q23 and Q24 and the ground point Vss, the current paths of the MOS transistors Q26 and Q27 are connected in series.

  The signal HIT and the signal xDWA <0: 2> (where “x” represents DWA <0: 2> or bDWA <0: 2>) are supplied to the input terminal of the NAND gate 124. The output signal of the NAND gate 124 is supplied to the inverter 125. The signal DWAA_n output from the inverter 125 is supplied to the gates of the MOS transistors Q23 and Q25. A signal DWAA_n + 1 is supplied to the gates of the MOS transistors Q22 and Q27. The signal XBLKP_n is supplied to the gate of the MOS transistor Q24, and the signal XBLKP_n + 1 is supplied to the gate of the MOS transistor Q26. The signal bTHIT_n is output from the connection point of the current paths of the MOS transistors Q23, Q24, Q26.

  Next, the operation in the stacked word line test mode in the semiconductor memory device according to the third embodiment will be described with reference to the timing chart of FIG. When the entry to the stacked word line test mode (TM ENTRY) is made, TMSTCWL = “L” → “H”. This state is maintained unless exiting from the test mode. A signal indicating activation / deactivation in the array control circuit 35 is activated by X_ADD in the stacked word line test mode, but is automatically released from the hold state and activated again by the next X_ADD. The array control circuit state signal XBLKP and the array control circuit state signal BLKSEL that holds the state until the test mode is exited once XBLKP is received.

  First, the first word line is selected (cycle # 1). Since there are 32 memory blocks / memory cell array, the maximum number of word lines that can be selected is 16 / memory cell array (memory cell array) due to the limitation that the number of word lines that can be activated per memory block is one. Cell array unit). Since only one word line in the memory block is selected, the row address (AR_ADD0 to AR_ADD8) for decoding the array is fixed. Since 16 memory blocks are selected without activating the adjacent memory block on the premise of the shared sense amplifier system, the row addresses AR_ADD10, AR_ADD11, and AR_ADD12 for selecting the memory blocks are added and fetched (AR_ADD9 is fixed). ).

  When the bank active command BA is received, bRSTR (internal RAS) / RADLTC (row address latch) changes from “L” to “H”. In response to this, the latch circuit activation signal TSTCWL of the array control circuit is changed from “L” to “H”. The row address fetched by bank active is transferred to AR_ADD, and X_ADD is activated. The block selector 43 receives the activated X_ADD910_0, X_ADD1112_0 = “L” → “H” and changes XBLKP_0 = “L” → “H”. Further, this state is held in the BLKSEL latch circuit 48 in the circuit shown in FIG. The information held in the latch circuit 48 is not released (reset) after the transition of X_ADD910_ * and X_ADD1112_ *. BSAOFF = “L” is required to release the hold state. As a result, the activated state of the array control circuit is held.

  In the second embodiment, the activation state of the array control circuit is held by holding X_ADD used globally. However, in the third embodiment, a reset signal does not come into the array control circuit. By providing the latch circuit 48 that does not release the state holding, the local state holding is realized.

  In response to XBLKP = “H” and WLE = “H”, TRDE_0 of the TRDE latch circuit 44 shown in FIG. 14 is changed from “L” to “H” to release the precharge of the row decoder 33A. As a result, the word line (WL) driver determined by the row decoder selected by the previously activated X_ADD23, X_ADD45, and X_ADD678 is activated. The fetched AR_ADD is also input to the redundancy control circuit, and is compared with the redundancy information. That is, the input AR_ADD is compared with redundancy information prepared in advance (for example, address information determined by fuse cutting or the like). As a result, when the matching is not achieved (mismatch, hereinafter, redundancy miss or miss), the signal HIT is kept at the “L” level. On the other hand, when matching is achieved (matching, hereinafter, redundancy hit or hit), the signal HIT changes from “L” to “H”. Then, the word lines in the array control circuit decoded by xDWA_ * (DWA_0, DWA_1, DWA_2,..., BDWA_0, bDWA_1, bDWA_2,...) Are prevented from being activated.

  RADLTC = “L” → “H” has a delay as a trigger, and after address comparison in the redundancy control circuit is completed, WLE = “L” → “H”. This delay time is set so that WLE = “L” → “H” after HIT = “L” → “H”.

  In the case of a redundancy miss, bTHIT — 0 (t / b) = “H” is held in order to hold the HIT “L” level. When WLE = “L” → “H”, the TWLON latch circuit receives this, and TWLON — 0 (t / b) = “L” → “H”. Since TSTCWL = “H” now, this state is held in the TWLON latch circuit 46. The information held in the TWLON latch circuit (t / b) that is selected by the address and missed is not released (reset) in the transition of WLE / bTHIT — 0 / XBLKP — 0 thereafter. To cancel the holding state, TSTCWL = "L" is required. WLDV_0 = “L” → “H” determined by X_ADD01_0, WLRST_0 = “H” → “L”, and the previously activated word line driver receives WLDV_0 = “H”, WLRST_0 = “L” and receives the word line WL_0 Is changed from “L” to “H”, and the data written in the memory cell is transferred onto the bit line. As a result, the activated state of the word line WL_0 is maintained.

  Here, XBLKP_n and XBLKP_n + 1 are address information activated when selected by the input address of the cycle, and bTHIT_n is redundancy information indicating a hit / miss of the cycle, and both are reset every cycle.

  The TWLON latch circuit in FIG. 20 specifies whether or not a part of address information (XBLKP_n, XBLKP_n + 1) and the address match the address programmed in the fuse set in order to specify a word line to be selected every cycle. This is a circuit having a function of taking in redundancy information (bTHIT_n), which is selected by address information of a certain cycle, and activating and holding a word line activation signal (TWLON_n) for activating a word line if a miss occurs. . That is, TWLON_n can be said to be a word line activation signal that is a word line control signal for each memory block.

  Next, activation of the sense amplifier will be described. When the sense amplifier control circuit selected by BLKSEL_0 receives TWLON_0 (t / b) = “H”, SAVLD_0 (t / b) = “L” → “H”. That is, SAVLD_0 (t / b) is a signal that is activated when the memory block is accessed and the first miss occurs, and the state is maintained until the test mode is exited. Assuming that the word line WL_0 = “H” is sufficiently obtained by the word line delay guarantee circuit arranged in the peripheral circuit portion, QSAE = “L” → “H”. Upon receiving QSAE = “H”, bSAON = “L” pulse is output through the SAON / OFF control circuit and the redriver. This is received by the SA latch circuit 45, and NSET_0 (t / b) = “L” → “H” and bPSET_0 (t / b) = “H” → “L” via the N / PSET driver 40. This state (NSET — 0 (t / b) = “H” / bPSET — 0 (t / b) = “L”) is held in the SA latch circuit 45. The information held in the latch circuit 45 is not released (reset) even if bSAON becomes “H” thereafter. BSAOFF = “L” is required to release the hold state. In the present embodiment, the state of NSET _ * (t / b) = “H” and bPSET _ * (t / b) = “L” is held in each array control circuit unit. There is no need to hold bSAON = "L" as in the technology (SAE = "H" hold). The N / PSET driver 40 outputs NSET — 0 (t / b) = “L” → “H”, bPSET — 0 (t / b) = “H” → “L”, activates the sense amplifier, and passes through the sense amplifier. Bit line sensing operation is performed. Thereby, the activated state of the sense amplifier 36_n (t / b) is maintained.

  In response to QSAE = “L” → “H”, RADLTC = “H” → “L”, WLE = “H” → “L”, bRPRE = “H” → “L”, X_ADD _ * = “H” → It becomes “L”, and a new row address can be fetched by self-reset. In response to RADLTC = “L”, the word line delay guarantee circuit changes QSAE = “H” → “L”. Unlike the second embodiment, in the third embodiment, during the stacked word line test mode, the address of the next cycle can be fetched without the bank precharge command PR being input after the bank active command BA. Is possible.

  The operation for selecting the next word line is started (cycle # 2). The bank active command BA may be input continuously after the second cycle. When a bank active command BA is accepted as in the first cycle, a new row address (AR_ADD) is fetched. The block selector 43 receives the activated X_ADD910_1, X_ADD1112_1 = "L" → "H" and changes XBLKP_1 = "L" → "H". Further, this state is held in the BLKSEL latch circuit 48 in the array control circuit activated in the second cycle. The information held in the latch circuit 48 is not released (reset) after the transition of X_ADD910_ * and X_ADD1112_ *. BLKSEL_0 activated in the first cycle is also held in the latch circuit 48 in the array control circuit activated in the first cycle.

  In the case of a redundancy miss, bTHIT_1 (t / b) = “H” is held in order to hold the “L” level of HIT. Thereafter, as in the first cycle, TWLON_1 (t / b) = “H” is held in the TWLON latch circuit 46, and WLDV_1 determined by X_ADD01_1 is changed from “L” to “H”, and WLRST_1 is changed from “H” to “L”. Then, the word line WL_1 is changed from “L” to “H”, and the activated state of the word line WL_1 is held. Although TWLON_0 activated in the first cycle and activated in the first cycle are still held in the latch circuit 46 in the array control circuit.

  The activation of the sense amplifiers 36_n (t) and 36_n (b) will be described. When the sense amplifier control circuit selected by BLKSEL_1 receives TWLON_1 (t / b) = “H”, SAVLD_1 (t / b) = “L” → “H”. Thereafter, as in the first cycle, NSET — 0 (t / b) = “H” / bPSET — 0 (t / b) = “L” is held in the SA latch circuit 45, and the N / PSET driver 40 is NSET — 0 (t / b). = “L” → “H”, bPSET — 0 (t / b) = “H” → “L” is output, the sense amplifier is activated, and the bit line sensing operation is performed via the sense amplifier. Thereby, the activated state of the sense amplifier 36_n (t / b) is maintained. Unlike the case of the second embodiment, bSAON = “L” (SAE = “H” in the case of the technique of the second embodiment) is not held, and a bSAON pulse is generated every cycle. Therefore, the sense amplifier can be activated even after the second cycle with the delay of the word line delay guarantee circuit determined from the word line activation as in the first cycle. Thus, in this embodiment, cell data is not destroyed even for word lines activated after the second cycle.

  Next, an operation of returning all activated word lines to the precharge state will be described (see the timing chart of FIG. 26). When the bank precharge command BP is received, the bank activation signal BNK = “H” → “L”. TSTCWL = “H” → “L” after a restore delay time tRSTR determined by the bit line restore delay circuit after receiving “L” of BNK. In response to TSTCWL = “L”, the holding states of all TWLON latch circuits 46 and TRDE latch circuits 44 in the bank are released. By releasing these holding states, all the signals TWLON, TRDE, WLDV, WLRST in the bank are in a precharge state, and all the word lines activated during the test mode are changed from “H” to “L”.

  An operation for equalizing all activated bit lines will be described. In the stacked word line test mode, when all the word lines are reset, many times more charges than normal read / write operations flow from the word line to the ground point Vss. As a result, the Vss potential of the word line driver 34A rises locally, and the reset timing of the word line is delayed as compared with the normal read / write operation. Therefore, in the stacked word line test mode, after the word line reset delay time tSRST determined by the STCRST control circuit 90, the bit line equalization operation is started.

  In response to bRSTR = “L”, after the word line reset delay time tSRST, bSTCRST = “H” → “L”, and the SAON / OFF control circuit 85 outputs a bSAOFF = “L” pulse. In response to this, the holding state of the BLKSEL latch circuit 48 and the SA latch circuit 45 in all the array control circuits is released. By releasing these holding states, all NSET / bPSETs in the bank are in the precharge state, and all the bit lines activated during the test mode are equalized.

  Next, consider the case of a redundancy hit (see the timing chart of FIG. 27). Assume that a redundancy hit occurs in the second cycle. The entry up to the test mode (TM ENTRY) and the cycle active and bank precharge of cycle # 1 are the same as in the case of the redundancy miss.

  In the second cycle, the operation for selecting the next word line is started (cycle # 2). When the bank active command BA is received, RADLTC (internal RAS) changes from “L” to “H”. The row address fetched by bank active is transferred to AR_ADD and X_ADD is activated. The block selector 43 receives the activated X_ADD910_1, X_ADD1112_1 = "L" → "H" and changes XBLKP_1 = "L" → "H". Similarly, BLKSEL_1 changes from “L” to “H”, and this state is held in the BLKSEL latch circuit 48. As a result, the activated state of the array control circuit is held.

  In the case of a redundancy hit, bTHIT_1 (t / b) = “H” → “L” in response to HIT = “L” → “H”. WLE = “L” → “H” and the TWLON latch circuit 46 receives this, but maintains TWLON — 0 (t / b) = “L” because bTHIT — 1 (t / b) = “L”. In this state, WLDV / WLRST selected by X_ADD01_1 is kept at WLDV_1 = "L" and WLRST_1 = "H", and the word line WL_1 is also maintained at the "L" level. That is, the word line WL_1 maintains an inactive state.

  Next, activation of the sense amplifiers 36_n (t) and 36_n (b) will be described. Since the sense amplifier control circuit selected by BLKSEL_1 is TWLON_1 (t / b) = “L”, SAVLD_1 (t / b) = “L” is maintained. The SAON / OFF control circuit 85 outputs a bSAON = "L" level pulse at the same timing as when a miss occurs, but the SA latch circuit 45 remains inactive because SAVLD_1 (t / b) = "L". . The N / PSET driver 40 receiving it also maintains NSET_1 (t / b) = “L” and bPSET_1 (t / b) = “H” while remaining in the inactive state. The sense amplifier also remains inactive. The bSAON “L” pulse after the next cycle also does not activate the sense amplifier unless SAVLD — 1 (t / b) = “H”. Thereby, the inactivated state of the sense amplifier 36_n (t / b) is maintained.

  According to the above configuration, the stacked word line test mode can be used even in a product after redundancy relief, and the test time can be reduced in all products.

  However, in the stacked word line test mode according to the third embodiment, the number of word lines that can be selected is limited as shown in (1) and (2) below in order to guarantee reading from the memory cell. There is.

  (1) The number of word lines that can be activated for one memory block is one.

  (2) When a sense amplifier is shared with an adjacent memory block (shared sense amplifier), select a word line for only one of the memory blocks sharing the sense amplifier. (Only a maximum of N / 2 word lines can be selected in a memory cell array (cell array unit) having N memory blocks).

[Fourth Embodiment]
Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described. In the fourth embodiment, the semiconductor memory device of the third embodiment can activate M word lines (M = 2, 3, 4, 5,...) For one memory block. It is a thing. However, in the fourth embodiment, when a plurality of word lines are selected for one memory block, there is a limitation (3) below.

  (3) The contents of the memory cells connected to the plurality of word lines selected in the memory block must all be the same in the same column. This is a condition for preventing data destruction on the same column.

  The configuration of the semiconductor memory device according to the fourth embodiment in which two word lines are selected in the memory block will be schematically described with reference to FIGS. A row address for decoding the memory block in half is added for decoding the TRDE latch circuit 44 in the array control circuits 35T and 35B used in the third embodiment. In addition, the output signal TRDE is cut at the row address where the memory block half is decoded, and similarly input to the row decoder of the adjacent memory block half. Further, the same number of inputs as the inputs to the row decoder 33A of the third embodiment are input to the same number of row decoders symmetrically about the array control circuit.

  Similarly, a row address for decoding the memory block in half and a signal bTHITP having redundancy information are input to the row decoder 33A together with the signal TRDE. The signal bTHITP is a signal obtained by decoding the signal bTHIT with a row address that decodes the array in half.

  The signals TRDE_0 / bTHITP_0 and TRDE_1 / bTHITP_1 are arranged in a common wiring region and do not cross each other. This makes it possible to minimize the wiring area to be used.

  FIG. 30 is a circuit diagram showing a configuration example by extracting the memory block, sense amplifier, row decoder, and array control circuit in the memory cell array in the circuits shown in FIGS. This circuit is provided with a TRDE control circuit 130 instead of the TRDE latch circuit 44 in the circuit shown in FIG. 14, and also provided with a HIT control circuit 131 instead of the HIT control circuit 47 so that the TRDE / bTHITP is halved in each array. There is a configuration in which a row address to be decoded is cut and input to the same number of row decoders symmetrically about the array control circuit. In FIG. 30, the same components as those in FIG.

  31 and 32 are circuit diagrams for explaining modifications of the circuit shown in FIG. FIG. 31 shows an example in which signals WLDV and WLRST input to the word line driver are driven from one memory block. FIG. 32 shows an example in which signals WLDV and WLRST input to the word line driver are driven from the memory blocks on both sides. 33A shows a pattern layout of wiring from the WLDV driver to the WL driver shown in FIG. 31, and FIG. 33B is a cross section taken along line 33B-33B in FIG. 33A. FIG. 34A shows a pattern layout of wiring from the WLDV driver to the WL driver shown in FIG. 32, and FIG. 34B shows a cross section taken along line 34B-34B in FIG. 34A. FIG.

  As shown in FIGS. 31, 33A, and 33B, the wiring from the active driver (WLDV driver 38-1) to the WL driver 34A is formed by the first-layer metal wiring M0. The metal wiring M0 is connected to the drain region of the output stage transistor of the WLDV driver 38-1 via the contact CD. On the metal wiring M0, a second-layer metal wiring (word line) M1 is provided with an interlayer insulating film interposed therebetween. The metal wiring M1 is arranged along the direction intersecting with the metal wiring M0. A third-layer metal wiring M2 is provided on the metal wiring M1 with an interlayer insulating film interposed therebetween. The metal wiring M2 is arranged along a direction parallel to the metal wiring M0. The metal wiring M2 and the metal wiring M0 are stitched at the nearest point and the farthest point of the WLDV driver 38-1. That is, both ends of the metal wiring M2 and the metal wiring M0 are electrically connected via the contact portions V1 and V2. The metal wiring M2 and the metal wiring M0 serve to transfer the WLDV signal from the active WLDV driver 38-1 to the word line driver 34A. As described above, the metal wiring M2 and the metal wiring M0 are used for transferring the WLDV signal because the resistance value of the metal wiring M0 is relatively high, so that the resistance value is lowered by connecting the metal wiring M2 in parallel. Because.

  On the other hand, in the example shown in FIGS. 32 and 34A and 34B, the signals WLDV and WLRST input to the word line driver are driven from the memory blocks on both sides, and the active driver (WLDV driver 38-2). , 38-3) to the WL driver 34A is formed of only the first layer metal wiring M0. The metal wiring M0 is connected to the drain regions of the output stage transistors of the WLDV drivers 38-2 and 38-3 via the contact CD. On the metal wiring M0, a second-layer metal wiring (word line) M1 is provided with an interlayer insulating film interposed therebetween. The metal wiring M1 is arranged along the direction intersecting with the metal wiring M0. A third-layer metal wiring M2 is provided on the metal wiring M1 with an interlayer insulating film interposed therebetween. The metal wiring M2 is arranged along a direction parallel to the metal wiring M0, and is used as a signal line or a power supply line. In this example, only the metal wiring M0 works to transfer the WLDV signal from the active WLDV drivers 38-2 and 38-3 to the word line driver 34A.

  That is, by driving both sides of the metal wiring M0, the third-layer metal wiring M2 can be eliminated, and the third-layer metal wiring M1 is connected to the word line driver section on the word line which is the second-layer metal wiring M1. Since other signal lines and power supply lines can be arranged by the eye metal wiring M2, the total number of metal wirings M2 in the word line driver section and the row decoder section can be reduced, and the area of the word line driver 34A and the row decoder 33A. Can contribute to reduction.

  FIG. 35 is a circuit diagram showing a specific configuration of TRDE control circuit 130 in the circuit shown in FIG. The TRDE control circuit 130 includes a NOR gate 140, an inverter 141, a NAND gate 142, a NOR gate 143, inverters 144 and 145, a level shifter 146 that converts a "Vcc" level to a "Vpp" level, P-channel MOS transistors Q30 to Q32, and N It is composed of channel type MOS transistors Q33 to Q36. The current paths of the MOS transistors Q30 to Q35 are connected in series between the power source Vcc and the ground point Vss, and the current path of the MOS transistor Q36 is connected between the connection point of the current paths of the MOS transistors Q32 and Q33 and the ground point Vss. They are connected in series.

  The signal TSTCWL is supplied to one input terminal of the gate of the MOS transistor Q30 and the NOR gate 143. The signal X_ADD8 is supplied to one input terminal of the NAND gate 142 and the gate of the MOS transistor Q35. Further, the signal XBLKP_n + 1 and the signal XBLKP_n are supplied to the NOR gate 140, and the output signal of the NOR gate 140 is supplied to the other input terminal of the NAND gate 142 and the gate of the MOS transistor Q34 via the inverter 141. The output signal of the NAND gate 142 is supplied to the other input terminal of the NOR gate 143, and the output signal of the NOR gate 143 is supplied to the gates of the MOS transistors Q31 and Q36. The signal WLE is supplied to the gates of the MOS transistors Q32 and Q33.

  The input end of the inverter 144 is connected to the connection point of the current paths of the MOS transistors Q32 and Q33. The output terminal of the inverter 144 is connected to the input terminal of the inverter 145, and the output terminal of the inverter 145 is connected to the input terminal of the inverter 144. The input terminal of the level shifter 146 is connected to the output terminal of the inverter 144, and the signal TRDE_n is output from the output terminal.

  FIG. 36 is a circuit diagram showing a specific configuration of part of the HIT control circuit 131 in the circuit shown in FIG. The HIT control circuit 131 in FIG. 30 includes the circuit shown in FIG. 24 and the circuit shown in FIG. 36 includes an inverter 147, a NOR gate 148, inverters 149 and 150, a level shifter 151 for converting the “Vcc” level to the “Vpp” level, P-channel MOS transistors Q37 and Q38, and N-channel MOS transistors. It is comprised by Q39 and Q40. The current paths of the MOS transistors Q37 to Q40 are connected in series between the power supply Vcc and the ground point Vss.

  Signal TSTCWL is supplied to the gates of MOS transistors Q37 and Q40. The signal X_ADD8 is supplied to one input terminal of the NOR gate 148 via the inverter 147. A signal bTHIT_n is supplied to the other input terminal of the NOR gate 148, and its output signal is supplied to the gates of the MOS transistors Q38 and Q39.

  The input end of the inverter 149 and the output end of the inverter 150 are connected to the connection points of the current paths of the MOS transistors Q38 and Q39, respectively. The output terminal of the inverter 149 is connected to the input terminal of the inverter 150. Further, the input end of the level shifter 151 is connected to the connection point of the current paths of the MOS transistors Q38 and Q39, and the signal bTHITP_n is output from the output end.

  FIG. 37 is a circuit diagram showing a specific configuration of row decoder 33A in the circuit shown in FIG. The row decoder 33A is composed of a NAND gate (bRDOUT driver) 152 and an X decoder 153. The X decoder 153 is supplied with the signal TRDE and the signal XAdd, and the output signal RDOUT is supplied to one input terminal of the NAND gate 152. A signal bTHITP is supplied to the other input terminal of the NAND gate 152, and an output signal bRDOUT thereof is supplied to the word line driver 34A.

  With such a configuration, the row decoder of the adjacent memory block is also activated across the array control circuit, but the memory block adjacent to the activated memory block is always inactive. Accordingly, since the WLDV driver 38 of the adjacent memory block is always inactive, all word lines are necessarily inactive. That is, even if the row decoder 33A of the adjacent memory block is activated, it can be ignored.

  Next, the operation of the semiconductor memory device according to the fourth embodiment will be described. As in the case of the third embodiment (see FIGS. 25 to 27), the bank active command BA is accepted after entry into the stacked word line test mode (TM ENTRY).

  First, the first word line is selected (cycle # 1). Since there are 32 memory blocks / memory cell array (cell array unit), the maximum number of word lines that can be selected is 32 / memory cell array. Since two word lines are selected in the memory block, the row address (AR_ADD0 to AR_ADD7) for decoding the memory block is fixed. Also, since 16 memory blocks are selected without activating the adjacent memory block on the premise of the shared sense amplifier system, row addresses (AR_ADD10, AR_ADD11, AR_ADD12) for selecting memory blocks and row addresses for dividing the blocks in half. (AR_ADD8) is added and taken in (AR_ADD9 is fixed).

  Here, different word lines are sequentially activated in the same memory block. The state at this time depends on the redundancy state. (1) 1st-MISS / 2nd-MISS, (2) 1st-MISS / 2nd-HIT, (3) 1st-HIT / 2nd-MISS, (4) 1st-HIT / There are four types of 2nd-HIT.

  First, in the case of (1) 1st-MISS / 2nd-MISS, when a bank active command BA is accepted, BLKSEL_0 = “L” → “H” as in the third embodiment, and this state is changed to the BLKSEL latch circuit 48. Hold on.

  In the case of 1st-redundancy miss, the TRDE control circuit 130 changes TRDE_0 = “L” → “H” in response to XBLKP_0 = “H”, X_ADD8_0 = “H” and WLE = “H”, and precharges the row decoder 33A. Release the state. WLE = “L” → “H”, and the TWLON latch circuit 46 receives this, and TWLON — 0 (t / b) = “L” → “H”. Since TSTCWL = “H” now, this state is held in the TWLON latch circuit 46. Thereafter, as in the third embodiment, WLDV_0 = “L” → “H” determined by X_ADD01_0, WLRST_0 = “H” → “L”, the word line WL_0 is changed from “L” to “H”, and the word line The activation state of WL_0 is held.

  Next, activation of the sense amplifiers 36_n (t) and 36_n (b) will be described. When the sense amplifier control circuit 41 selected by BLKSEL_0 receives TWLON_0 (t / b) = “H”, SAVLD_0 (t / b) = “L” → “H”. Thereafter, as in the third embodiment, the N / PSET driver 40 outputs NSET — 0 (t / b) = “L” → “H” and bPSET — 0 (t / b) = “H” → “L”. The sense amplifiers 36_n (t) and 36_n (b) are activated, and the sense operation of the bit line pair BL / bBL is performed via the sense amplifiers 36_n (t) and 36_n (b).

  Next, a different area of AR_ADD8 in the same array is activated (cycle # 2). The bank active command BA is accepted, but BLKSEL_0 = “H” is already held by the previous bank active command.

  In the case of 2nd-redundancy miss, the TRDE control circuit 130 changes TRDE_1 = “L” → “H” in response to XBLKP_0 = “H”, X_ADD8_1 = “H” and WLE = “H”, and precharges the row decoder 33A. Release the state. The TWLON latch circuit 46 has already held TWLON — 0 (t / b) = “H”, WLDV — 0 = “H”, WLRST — 0 = “L” with the previous bank active command BA. Therefore, by releasing the precharge state of the row decoder 33A, the word line driver 34A determined by X_ADD23, X_ADD45, and X_ADD67 is activated, and the word line WL_1 changes from “L” to “H”, and the activation state is maintained. To do.

  In the second cycle, before the word line WL_1 changes from “L” to “H”, the sense amplifier has already been activated, and the sensing operation of the bit line is completed and held. That is, the contents of all memory cells connected to the second selected word line in the same memory block are written with the same contents as the contents of the memory cells connected to the first word line when the word line is selected and rises. . If the same data is written in units of bit lines, the data direction is the same, so data destruction of the memory cell does not occur.

  Next, in the case of (2) 1st-MISS / 2nd-HIT, when the bank active command BA is received, the word line WL_0 is selected in the same manner as in (1).

  Next, a different area of AR_ADD8 in the same array is activated (cycle # 2). The bank active command BA is accepted, but BLKSEL_0 = “H” is already held by the previous bank active command.

  In the case of a 2nd-redundancy hit, the TRDE control circuit 130 changes TRDE_1 = "L" → "H" in response to XBLKP_0 = "H", X_ADD8_1 = "H" and WLE = "H", and the row decoder 33A The precharge state of the X decoder unit is released. The TWLON latch circuit 46 already holds TWLON — 0 (t / b) = “H”, WLDV — 0 = “H”, and WLRST — 0 = “L” in the previous bank active command. By canceling the precharge state of the X decoder section in the row decoder 33A, RDOUT = “L” → “H” determined by X_ADD23, X_ADD45, and X_ADD67, and thereafter held. However, since bTHIT_1 is changed from “H” to “L” and bTHITP is changed from “H” to “L” because of a redundancy hit, the bRDOUT driver (NAND gate) 152 does not accept the signal RDOUT, and bRDOUT_1 is set to “H”. And the word line driver 34A is not activated. Therefore, although WLDV_1 = "H", since the word line driver 34A is inactive, the word line WL_1 = "L" and the inactive state is maintained. This signal bTHITP keeps this state as long as TSTCWL = “H”.

  That is, when the accessed word line is a defective word line, redundancy hit information (bTHITP = “L”) is continuously held during the test mode period so that the defective word line is not selected.

  Here, there are two signals for holding hit information for each memory block. By increasing the number of signals, the number of word lines that can be activated in the memory block can be increased. .

  Although the sense amplifier has already been activated and the bit line sensing operation is completed and held, the word line WL_1 is inactive, and the memory cell connected to the word line WL_1 is not accessed, so data destruction is not caused. Do not wake up.

  (3) In the case of 1st-HIT / 2nd-MISS, as in the case of the redundancy hit of the third embodiment, 1st-HIT maintains the inactive state of the word line and the sense amplifier.

  At the time of 2nd access, the word line and sense amplifier of this memory block are in an inactive state. Accordingly, the word line WL_1 is selected in response to the bank active command BA in the same manner as the first access (1) and (2), and the sense amplifier is activated in response to bSAON = “H” → “L”. A bit line sense operation is performed.

  (4) In the case of 1st-HIT / 2nd-HIT, since the redundancy hit that has been extended lasts only twice, the array control circuit is activated, but the word line and sense amplifier are not used for both 1st / 2nd access. Keep active state.

[Fifth Embodiment]
A semiconductor memory device according to the fifth embodiment of the present invention will be described. In a bank composed of two upper and lower memory cells and a sense amplifier arranged so as to share the row decoder, they are simultaneously activated in the upper and lower memory blocks sharing the row decoder in the stacked word line test mode. Redundancy can be controlled independently for each word line.

  The stacked word line test mode has the same restrictions as those in the third embodiment and the fourth embodiment.

  38 to 40 show configuration examples of the semiconductor memory device according to the fifth embodiment. In the fifth embodiment, as shown in FIGS. 38 and 39, the memory cell array (cell array unit) configuration of the third and fourth embodiments is arranged so that the row decoder is shared, and the memory is arranged on the upper and lower sides respectively. The bank configuration has blocks and sense amplifiers. That is, as shown in FIG. 40, the row decoder 33A includes a NAND gate (bRDOUT driver) 152 (low), a NAND gate (bRDOUT driver) 152 (up), and an X decoder 153. The X decoder 153 is shared by the upper and lower sides. Yes. The bRDOUT drivers 152 (low) and 152 (up) receive an output signal RDOUT from the X decoder 153 and signals bTHITP_up and bTHITP_low having redundancy information, respectively.

  The signal bTHITP is a signal output from the HIT control circuit 131 provided in the array control circuit, and has two sets of circuits corresponding to the upper and lower memory blocks. The global redundancy signals HIT_up / low and DWA_up / low output by the redundancy control circuit are also independent in the vertical direction.

  Next, the operation of the semiconductor memory device according to the fifth embodiment will be described with reference to the timing charts of FIGS. Here, the number of word lines that can be activated in the memory block is two as in the fourth embodiment. Then, as in the fourth embodiment, the entry into the stacked word line test mode (TM ENTRY) is made, after which the bank active command BA is accepted, the row address is taken in, and X_ADD is activated.

  Consider a case where the upper memory block is a redundancy hit and the lower memory block is a redundancy miss. The redundancy control circuit outputs HIT_up = “L” → “H” and HIT_low = “L”. In response to this, the HIT control circuit 131 outputs bTHITP_up = “H” → “L” and bTHITP_low = “H”. . Since TSTCWL = “H”, bTHITP_up = “L” is held, and this state is not released until TSTCWL = “L”.

  Upon receiving bTHITP_low = “L”, the bRDOUT driver 152 (up) does not accept the input of the signal RDOUT, and maintains bRDOUT_up = “H”. As a result, the word line driver 34A (up) of the upper memory block is not activated, and even if WLDV_up = “L” → “H” in the subsequent cycles, the word line WL_up = “L” and the inactive state is maintained. maintain.

  For the lower memory block, since bTHITP_low = “H”, the signal RDOUT determined by the X decoder 153 (low) is received, bRDOUT_low = “H” → “L” is output, and the word line driver 34A (low) is output. Activate. As a result, as in the fourth embodiment, WLDV_low = “L” → “H”, and the word line determined by the selected word line driver becomes the word line WL_low = “L” → “H”. The line WL_low is activated.

  The sense amplifier performs the same operation as in the fourth embodiment.

  Similarly, when the upper memory block is a redundancy miss and the lower memory block is a redundancy hit, HIT_up = “L”, HIT_low = “L” → “H” is received by the HIT control circuit 131, and bTHITP_up = “H” “BTHITP_low =“ H ”→“ L ”, the word line WL_up is activated and the word line WL_low is deactivated.

[Sixth Embodiment]
A semiconductor memory device according to the sixth embodiment of the present invention will be described. In the sixth embodiment, in the memory cell array configuration of the third to fifth embodiments described above, eight word lines can be simultaneously activated in the cell array unit in the stacked word line test mode. Is.

  The stacked word line test mode has the same restrictions as in the third and fourth embodiments.

  FIG. 43 shows the state of the memory cell array when two word lines are simultaneously activated in the cell array unit in the stacked word line test mode. This is because the number of word lines activated simultaneously is the same as the number of normal write / read. Consider a case where 16 word lines are activated in a cell array unit. Of the row addresses AR_ADD0 to AR_ADD12 that need to be input, AR_ADD0 to AR_ADD9 hold the same address while 16 word lines are activated. Each time the bank active command BA is accepted, AR_ADD10, AR_ADD11, AR_ADD12 are sequentially added, and 16 word lines can be activated by a total of eight bank active commands.

  FIG. 44 shows a state of the memory cell array when eight word lines are simultaneously activated in the cell array unit in the stacked word line test mode. In this case, the previous AR_ADD10 and AR_ADD11 information is ignored (bypassed), and the number of simultaneously activated word lines is four times that of normal write / read.

  45 and 46 respectively show row address AR_ADD / signal X_ADD / signal XBLKP / memory block ArrayNo. It is a schematic diagram which shows a response | compatibility. FIG. 45 shows the case of normal operation, and FIG. 46 shows the case of the quadruple word line test mode (TM1011MUSI entry).

  47 to 49 are diagrams for explaining the X predecoder for realizing the quadruple word line test mode. As shown in FIG. 47, the X predecoder includes a P-channel MOS transistor Q41, N-channel MOS transistors Q42 to Q45, and inverters 160 to 163. The current paths of MOS transistors Q41 to Q44 are connected in series between power supply Vcc and ground point Vss. A signal bRPRE is supplied to the gates of the MOS transistors Q41 and Q42, an address signal AR_i is supplied to the gate of the MOS transistor Q43, and an address signal AR_j is supplied to the gate of the MOS transistor Q44. The current path of the MOS transistor Q45 is connected between the connection point of the current path of the MOS transistors Q43 and Q44 and the ground point Vss, and the test mode signal TM1011MUSI is supplied to the gate thereof. The input end of the inverter 160 is connected to the connection point of the current paths of the transistors Q41 and Q42, and the input ends of the inverters 161 and 162 are connected to the output end of the inverter 160, respectively. The output terminal of the inverter 161 is connected to the input terminal of the inverter 160. The output terminal of the inverter 162 is connected to the input terminal of the inverter 163. Then, the signal X_ADD is output from the output terminal of the inverter 163. That is, the MOS pre-decoder shown in FIG. 10 is added with a MOS transistor Q45 for ignoring the input of the signal AR_j.

  The X predecoder as shown in FIG. 47 is arranged as schematically shown in FIG. 48, and a decoding operation is performed. As shown in FIG. 49, the signal X_ADD1112 and the signal X_ADD910 generated by the X predecoder are supplied to the NAND gate 164, and the output signal of the NAND gate 164 is inverted by the inverter 165 to generate the signal XBLKP.

  In the semiconductor memory device according to the sixth embodiment, in addition to the stacked word line test mode, entry into the quadruple word line test mode is performed, and xAR_ADD10 / xAR_ADD11 input to the X predecoder is ignored, and FIG. As shown in FIG. 44, all the word lines can be selected (stacked) in 1/4 time of the normal operation, and the test process time can be shortened.

[Seventh Embodiment]
In the seventh embodiment, each row decoder performs fetching of address information and redundancy / miss information and holding operation of redundancy / miss information at that time, which has been performed by the TWLON control circuit shown in FIG. . A signal bTHIT having a redundancy information and a part of address information for resetting every cycle and a signal RDOUT having address information and used for selecting a WL driver are fetched every cycle. This makes it possible to activate two or more word lines in the memory block.

  FIGS. 50 to 55 are for explaining a semiconductor memory device according to the seventh embodiment of the present invention. FIG. 50 is a block diagram showing a part of the row decoder and WL driver. 51 is a circuit diagram showing a configuration example of the TRDE control circuit. 52 is a circuit diagram showing a configuration example of the bRDOUT driver & latch circuit 152 ′ in the circuit shown in FIG. 50. FIG. 53 is a circuit diagram showing a configuration example of the X decoder 153 in the circuit shown in FIG. It is. FIG. 54 is a block diagram showing a configuration example of the word line (WL) driver 34A, and FIG. 55 is a circuit diagram showing a configuration example of each driver circuit of the word line driver 34A shown in FIG.

  As shown in FIG. 50, the row decoder 33A includes an X decoder 153 and a bRDOUT driver & latch circuit 152 '. The X decoder 153 is supplied with the signal TRDE and the signal XAdd, and the output signal RDOUT is supplied to the bRDOUT driver & latch circuit 152 '. The bRDOUT driver & latch circuit 152 'is supplied with the signal bTHIT and its output signal bRDOUT is supplied to the word line driver 34A.

  The signal bTHITP in the circuit shown in FIG. 37 is a signal for continuing to hold the hit information once the redundancy hit, whereas the signal bTHIT in the circuit shown in FIG. 50 is the redundancy information for each cycle. It is a signal indicating (whether it has been hit or missed).

  The TRDE control circuit shown in FIG. 51 is basically the same as the TRDE latch circuit shown in FIG. 23, except that the signal TSTCWL is supplied to the gate of the MOS transistor Q16 and connected to the ground point Vss. Is different. As a result, the signal TRDE is reset without being held, and the address can be taken into the row decoder 33A every cycle. Since other configurations are the same, the same reference numerals are given to the same portions, and detailed descriptions thereof are omitted.

  The bRDOUT driver & latch circuit 152 ′ in the circuit shown in FIG. 50 includes P channel type MOS transistors Q80 to Q82, N channel type MOS transistors Q83 and Q84, and a latch circuit 210 as shown in FIG. Yes. The current paths of the MOS transistors Q80, Q81, Q83, and Q84 are connected in series between the power supply Vpp and the ground point Vss. The current paths of the MOS transistors Q81 and Q82 are connected in parallel. A signal TSTCWL is supplied to the gate of the MOS transistor Q80, a signal RDOUT is supplied to the gates of the MOS transistors Q81 and Q83, and a signal bTHIT is supplied to the gates of the MOS transistors Q82 and 84. The latch circuit 210 is configured by interconnecting the input and output terminals of inverters 211 and 212 that operate at a voltage between the power supply Vpp and the ground point Vss. The current paths of the MOS transistors Q81, Q82, and Q83 are connected to each other. It is connected to the connection point. Then, a signal bRDOUT is output from the connection point of the current paths of the MOS transistors Q81, Q82 and Q83.

  It is assumed that the “H” level of signal TSTCWL / bTHIT input to this circuit is level-shifted from Vcc to Vpp.

  As shown in FIG. 53, the X decoder 153 in the circuit shown in FIG. 50 includes P-channel MOS transistors Q85 and Q86, N-channel MOS transistors Q87 to Q90, and an inverter 220. The current paths of the MOS transistors Q85 and Q87 to Q90 are connected in series between the power supplies Vpp and Vss. The current path of the MOS transistor Q86 is connected between the connection point of the current paths of the MOS transistors Q85 and Q87 and the power supply Vpp. A signal TRDE is supplied to the gates of the MOS transistors Q85 and Q90, a signal X_ADD678 is supplied to the gate of the MOS transistor Q87, a signal X_ADD45 is supplied to the gate of the MOS transistor Q88, and the MOS transistor Q89 A signal X_ADD23 is supplied to the gate. The inverter 220 operates at a voltage between the power supply Vpp and the ground point Vss, and has an input terminal connected to a connection point of the current paths of the MOS transistors Q85, Q86, and Q87, and an output terminal connected to the MOS transistor Q86. Connected to the gate. Then, the signal RDOUT is output from the output terminal of the inverter 220.

  FIG. 54 is a block diagram showing a configuration example of the word line driver 34A in the circuit shown in FIG. The word line driver 34A is composed of driver circuits 230-0 to 230-3. Signals WLDV <0> to WLDV <3> are supplied to the first input terminals WLDV_in of the driver circuits 230-0 to 230-3, respectively, and signals WLRST <0> to WLRST are respectively supplied to the second input terminals. <3> is supplied, the signal bRDOUT is commonly supplied to the third input terminal RD_in, and the drive signals WL <0> to WL <3> for the respective word lines are output from the output terminal WL_out.

  Each of the driver circuits 230-0 to 230-3 shown in FIG. 54 includes a P-channel MOS transistor Q91 and N-channel MOS transistors Q92 and Q93 as shown in FIG. One end of the current path of the MOS transistor Q91 corresponds to the first input terminal WLDV_in and is supplied with signals WLDV <0> to WLDV <3>. The current path of the MOS transistor Q92 is connected between the other end of the current path of the MOS transistor Q91 and the ground point Vss. The gates of these MOS transistors Q91 and Q92 correspond to the third input terminal RD_in and are supplied with the signal bRDOUT. The connection point of the current paths of the MOS transistors Q91 and Q92 corresponds to the output terminal WL_out and outputs signals WL <0> to WL <3>. The current path of the MOS transistor Q93 is connected between the connection point of the current path of the MOS transistors Q91 and Q92 and the ground point Vss, and the gate of the MOS transistor Q93 corresponds to the second input terminal. A signal WLRST for resetting the word line is supplied.

  Note that the X decoder 153 and the word line drivers 34A, 34A (low), and 34A (up) in the circuits shown in FIGS. 37 and 40 are the same as the X decoder shown in FIG. 53 and the words shown in FIGS. A configuration similar to that of the line driver can be used.

  Next, the operation of the semiconductor memory device according to the seventh embodiment will be described.

  After entering the test mode, TSTCWL = "H". When a bank active command is received in the first cycle, XBLKP_n = “H” (or XBLKP_n + 1 = “H” may be used), WLE = “H”, and TRDE = “H”. The address X_ADD is output from the X predecoder, and the X decoder 153 determined thereby outputs RDOUT = “H”.

  In the case of a redundancy miss, since bTHIT = “H”, the bRDOUT driver & latch circuit 152 ′ outputs bRDOUT = “L” to activate the word line driver 34A, and the latch circuit 210 detects this redundancy miss. Keep state. Then, the word line WL determined by the signal WLDV obtained by decoding the address X_ADD01 is activated. The activation and holding operations of the sense amplifier are the same as in the third embodiment.

  Similar to the third embodiment, the self-reset functions and WLE = “L” and TRDE = “L”. In response to this, the X decoder outputs RDOUT = "L". However, since TSTCWL = "H", bRDOUT = "L" is held in the latch circuit 210 in the circuit shown in FIG. That is, the generated word line activation signal bRDOUT is held. Even if a redundancy hit occurs in the next and subsequent cycles and bTHIT = “L”, once the redundancy miss state is held in the latch circuit 210, this information is held for a period of TSTCWL = “H”. . Even if WLE = “L”, since WLDV = “H” is held as in the third embodiment, the word line WL holds the activated state.

  In the second cycle, a bank active command is accepted and the next address information is accepted. WLE = “H” and TRDE = “H”. The address X_ADD is output from the X predecoder, and the X decoder 153 determined thereby outputs RDOUT = “H”. In the case of a redundancy miss, the bRDOUT driver & latch circuit 152 ′ outputs bRDOUT = “L” to activate the word line driver 34A as in the first cycle, and the latch circuit 210 holds this redundancy miss state. To do. As in the first cycle, the word line WL determined by the signal WLDV obtained by decoding the address X_ADD01 is activated.

  On the other hand, in the case of a redundancy hit, since bTHIT = “L”, the bRDOUT driver & latch circuit 152 ′ outputs bRDOUT = “H” regardless of the input of the signal RDOUT and outputs the word line driver 34A. Is deactivated. Then, WLDV = “H” obtained by decoding the address X_ADD01 is set, but the word line WL maintains the inactive state.

  Even if bTHIT = “H” after the next cycle, the output RDOUT of the X decoder hit in the past is reset to “L” level every cycle, so that the signal bRDOUT for the defective word line is erroneously set. There is no “L” level.

  Note that the output of the signal RDOUT from the X decoder 153 in the fourth to seventh embodiments described above must wait for the redundancy information to be determined. For this purpose, the activation timing of the X decoder 153 is delayed by delaying TRDE = “H”, and the confirmation of redundancy information (bTHIT = “L” or “H”) is awaited. However, delaying TRDE = “H” during normal operation delays the rise of the word line WL and degrades the access speed (performance) to the memory cell. Therefore, in the present invention, TRDE = "H" can be delayed only in the test mode.

  That is, in the TRDE control circuit shown in FIG. 35 or 51, TSTCWL = “L”, that is, in the case of normal operation, TRDE receives XBLKP_n = “H” (or XBLKP_n + 1 = “H”) and TRDE = “H”. " However, in the case of TSTCWL = “H”, that is, in the test mode, TRDE receives WLE = “H” and TRDE = “H”.

  The signal WLE is a signal that rises after the determination of X_ADD and after the determination of redundancy information. Therefore, the signal TRDE that rises after receiving the change of the signal WLE inevitably rises after the redundancy information is determined. Thus, the signal RDOUT is activated after the redundancy information is confirmed.

  The output of the signal RDOUT can obtain the same effect by delaying the activation of X_ADD as a means for waiting for confirmation of redundancy information.

  For example, the X predecoder 89 (see FIG. 15) that outputs X_ADD23, X_ADD45, and X_ADD678 input to the row decoder 33A is replaced with an X predecoder 88 that resets to the low level every cycle. Then, the precharge release timing of X_ADD23, X_ADD45, and X_ADD678 by bRPRE = “H” is set after the redundancy information is determined, and the activation of X_ADD is delayed. As a result, the signal RDOUT is activated after the redundancy information is confirmed.

  In the semiconductor memory devices according to the third to seventh embodiments described above, the following conditions (A) and (B) must be satisfied.

  (A) Only one WLDV signal is activated for one memory block (needed not to select a word line that is not originally accessed or a defective word line that should not be replaced and originally selected. Conditions).

  (B) Similarly, only one WLDV signal is activated for a memory block that is a spare cell array (originally, a spare word line that is surely not used for replacement in the stacked word line test mode is not selected). Necessary conditions).

  In order to satisfy the condition (A), it is necessary to fix the input addresses AR_ADD0 and AR_ADD1, that is, X_ADD01 for selecting WLDV.

  That is, as shown in FIGS. 37, 40, 50, and 54, the word line is selected by selecting one of a plurality of signals WLDV <0: 3> according to the input address and a plurality of row decoders. This is done by selecting one from 33A. Accordingly, in the stacked word line test mode, when a new row decoder 33A is selected with a new input address (bRDOUT = “H” → “L”) while a plurality of WLDV signals are already activated, the memory block A plurality of word lines are simultaneously activated. However, only one of these is a word line that is not originally accessed.

  When another row decoder is selected for a memory block while a certain WLDV signal and a certain row decoder are already activated, a different WLDV signal from the already activated WLDV signal is selected. As a result, the word line is activated by the already activated row decoder and the newly selected WLDV signal. However, this word line is not originally accessed. Therefore, if the word line that is not originally accessed is a defective word line, a situation may occur in which the defective word line is selected.

  Normally, when a defective word line is accessed, bRDIT = “L” in FIGS. 37 and 40, or bTHIT = “L” in FIG. 50, so that bRDOUT = “L” does not occur. The defective word line is not activated. The same applies to the case where only one WLDV signal is activated for one memory block in the stacked word line test mode.

  However, in the stacked word line test mode, a plurality of WLDV signals are activated for one memory block, and the row decoder 33A corresponding to the defective word line is different from the WLDV signal corresponding to the defective word line. The situation is different if the word line selected by the signal is not replaced by redundancy. Specifically, in FIG. 37, FIG. 40, and FIG. 50, the word lines that can be selected by one row decoder 33A are four word lines for each of the four WLDV signals. This is a case of one unit. In this case, the row decoder 33A corresponding to the defective word line and the word line selected by the WLDV signal different from the WLDV signal corresponding to the defective word line are included in the replacement unit (defective element) including the defective word line. If not, this word line can be selected and activated. This means that bRDOUT = "L" can be set at the output of the row decoder 33A corresponding to the defective word line. In other words, in the stacked word line test mode, activating a plurality of WLDV signals for one memory block means that bRDOUT = “L” in the output of the row decoder 33A corresponding to the defective word line. Since the WLDV signal corresponding to the defective word line can be activated in different cycles, the defective word line can be activated. Therefore, in order to avoid such a situation, it is necessary to activate only one WLDV signal for one memory block, and specifically, to a plurality of word lines in one memory block. When accessing, it is necessary to fix an address for selecting one WLDV signal from a plurality of WLDV signals.

  When it is assumed that the defective word line is replaced in units of two, the address for selecting one of the two spare word lines in the replacement unit is the same as the address AR_ADD0 used for the normal word line. The other address RAR_ADD1 is different from the address AR_ADD1 used for the normal word line. Therefore, in order to satisfy the condition (B), a plurality of defective word lines in a plurality of word lines that can be activated together in the stacked word line test mode are replaced with a plurality of spare cells in one spare cell array. When replacing with a word line, it is necessary to align RAR_ADD1 for a plurality of spare elements used for the replacement.

  If a plurality of defective word lines (defective elements) in a plurality of word lines that can be activated together in the stacked word line test mode are replaced with a plurality of spare word lines (spare) in a memory block that is a spare cell array. If a plurality of spare word lines (spare elements) used for replacement do not correspond to the same WLDV signal, the memory block that is a spare cell array is activated in the stacked word line test mode. In combination with a plurality of WLDV signals to be changed and a selected redundancy row decoder, spare word lines that are not used in replacement are also activated together.

[Eighth Embodiment]
FIG. 56 is a schematic diagram of a redundancy system for explaining a semiconductor memory device according to the eighth embodiment of the present invention. An address fuse for programming a defective address (FUSEn: n is an address) and an entire master fuse (FUSEM) for preventing a redundancy element from being selected when a redundancy element is not used are called a fuse set FS. A fuse latch circuit (FLATCHn) 166 in FIG. 56 is specifically a circuit constituted by a P-channel MOS transistor Q50, an N-channel MOS transistor Q51, and inverters 169 to 171 as shown in FIG. In this circuit, the output FOUTn after the fuse initialization signals FINITP and FINITN are changed as shown in FIG. 58 is determined depending on the state of the fuse (whether or not it is blown). The address comparator (ACOMPn) 167 compares the input address An and the corresponding FOUTn for each address, and the input address matches the program address for all addresses, and the master fuse is blown. For example, the signal bHIT indicating that the hit detector 168 is in the redundancy mode is activated.

  FIG. 59 is a schematic diagram of a redundancy system having a redundancy test function for testing whether a redundancy element is defective before a fuse blow. The output FOUTn (n: address) of the fuse latch circuit 166 is connected to the input terminal Ta or Tb of the address comparator 167 of each fuse set FS. Due to this difference in connection, when the corresponding output FHITn is activated before the fuse blow processing (when it becomes “H”), the input address An of the address comparator 167 of each address can be changed. That is, if the fuse latch circuit 166 is configured as shown in FIG. 57, the output FOUTn after fuse initialization is “L”. Therefore, if FOUTn is connected to the input terminal Ta, the input address An is “L”. At this time, FHITn becomes “H”, and conversely, if connected to the input terminal Tb, FHITn becomes “H” when the input address An is “H”. Then, this connection method regarding all address fuses in the fuse set is made unique to each fuse set. In the redundancy test, the master fuse is blown in a pseudo manner by setting the TEST signal to “H” to create the same state as when FOUTM becomes “H”, and is determined by the connection of the input end of the address comparator 167 The corresponding redundancy element is tested by selectively hitting only a specific fuse set by inputting the corresponding address (preprogram address).

  Next, the relationship between the redundancy area and the corresponding relief area is selected by the spare CSL by the input row address in the column redundancy system in which the defective column selection line (defective CSL) is disabled and the spare CSL is activated and replaced instead. A system in which a plurality of spare cells are divided into individual column redundancy elements will be described as an example.

  The column redundancy system is in a state where a row corresponding to an input row address in the memory cell array is accessed (in a state where a certain word line is activated), and a column address corresponding to a defect in the memory cell array is input. Instead of accessing a cell corresponding to the column address on that row (normal CSL is activated and reading / writing to a cell having the same column address as the defective cell), a spare cell for redundancy on the same row is accessed ( The spare CSL is activated to read / write to the spare cell. In general, column redundancy does not replace each cell with a spare cell, but replaces a plurality of cells including defective cells in the same column with a plurality of cells in the spare column. A set of spare cells as such a replacement unit is called a redundancy element. This column redundancy element includes cells corresponding to a plurality of rows.

  If the word line is activated and the CSL is activated, the cell specified by the activated word line and the activated CSL is read / written regardless of whether it is a normal CSL or a spare CSL. Done. Here, when a plurality of word lines are activated at the same time, and one of them includes a defect and is repaired by column redundancy, a column address corresponding to the defect is input, the column address When the spare CSL is activated instead of the normal CSL corresponding to the read / write, the cell corresponding to the input column address is not read / written to the cell corresponding to the input column address in the other word lines not including the defect. Read / write to cell.

  In this manner, when cells on the word line activated at the same time are replaced with column redundancy, they are always replaced together. Therefore, spare cells corresponding to (belonging to) rows (word lines) that are simultaneously activated and simultaneously read / written belong to the same column redundancy element. In other words, spare cells corresponding to (belonging to) rows (word lines) that are not simultaneously read / written may not belong to the same column redundancy element.

  FIG. 60 shows two memory blocks cut out from a memory cell array in which a sense amplifier is shared by bit line pairs in adjacent memory blocks. Assume that these two memory blocks are divided into four areas A, B, C, and D determined by, for example, row addresses AR8 and AR9. Now, if a row address is input and only one word line is activated in the two memory blocks, the activated word line is in one of the regions A, B, C, and D. . Since spare cells corresponding to (belonging to) a row (word line) that is not read / written simultaneously do not have to belong to the same column redundancy element, a plurality of spare cells selected by the spare CSL are divided into four by row addresses AR8 and AR9. It is possible to classify and set each spare cell as a column redundancy element. In this way, a plurality of spare cells selected by one spare CSL are configured by four redundancy elements RELEMENT <0: 3> determined by the row addresses AR8 and AR9. Therefore, such a column redundancy system can increase the number of redundancy elements without increasing the number of spare columns (spare cells) (without increasing the number of spare CSL), and thus is a redundancy system with good area efficiency.

  If the fuse set corresponds to each spare element RELEMENT <0: 3>, each redundancy element of RELEMENT <0: 3> can be programmed to replace a different column address. If all CSL addresses in the two memory blocks can be programmed in each fuse set, RELEMENT <0: 3> can replace all defective cells in regions A, B, C, and D, respectively. . Here, the area where the redundancy element programmable by the fuse set can replace any element in the area is called a relief area for the fuse set (where each fuse set corresponds to which redundancy element) Not necessarily fixed). That is, the relief areas corresponding to the fuse sets of RLEMENT <0: 3> are A, B, C, and D, respectively.

  In the memory block shown in FIG. 60, the bit line pairs that run in the same direction as the CSL in the memory block surrounded by the sense amplifier region (sense amplifier bank) are alternately connected to the left and right sense amplifiers for each bit line pair. (Not shown). Accordingly, since the four column relief areas are set using the row addresses AR8 and AR9 in the two memory blocks, a plurality of memory cells connected to one bit line pair are divided into two relief areas. become. That is, the relief area is set so as to divide the bit line.

  Further, since spare cells corresponding to rows (word lines) that are simultaneously read / written belong to the same column redundancy element, rows (word lines) that are simultaneously activated and simultaneously read / written are in the same column relief region. Will have to be inside. Conversely, since different defective column addresses may be programmed in fuse sets for column redundancy elements in different column relief areas, it is not possible to simultaneously read / write to word lines belonging to different column relief areas. In other words, the operation of inputting a defective column address in a certain column repair area and replacing the defective element with a redundancy element is different from the operation of selecting a normal element when the input address is not a defective column address in another repair area. Do not fit. This is because the actual replacement is performed by replacing the normal CSL that runs across a plurality of relief areas across the entire memory cell array with the spare CSL, so that the elements belonging to different CSL or spare CSL for each relief area can be simultaneously used. It is because it cannot be accessed.

  The actual control uses the output FSEL <0: 3> of the fuse set selection signal generation circuit as shown in FIG. 61 and corresponds to the redundancy element in the column relief region in which at least one word line is activated. A fuse set that may be hit is selected in advance (before the column address is input), and a circuit after the address comparator 167 is shared by a plurality of fuse sets by a fuse set selection circuit as shown in FIG.

  The fuse set selection signal generating circuit shown in FIG. 61 includes inverters 180 and 181 and AND gates 182 to 185. The signal AR8 is supplied to the input terminal of the inverter 180 and one input terminal of the AND gates 183 and 185, respectively. The signal AR9 is supplied to the input terminal of the inverter 181, one input terminal of the AND gate 184, and the other input terminal of the AND gate 185. The output signal of the inverter 180 is supplied to one input terminal of the AND gate 182 and the other input terminal of the AND gate 184. The output signal of the inverter 181 is supplied to the other input terminal of the AND gate 182 and the other input terminal of the AND gate 183. The fuse set selection signals FSEL <0> to FSEL <3> are output from the output terminals of the AND gates 182-185.

  The fuse set selection circuit shown in FIG. 62 includes inverters 190-0 to 190-3, P-channel MOS transistors Q60-0 to Q60-3, Q61-0 to Q61-3, and N-channel MOS transistors Q62-0 to Q62-0. It consists of Q62-3, Q63-0 to Q63-3.

  The current paths of the MOS transistors Q60-0, Q61-0, Q62-0, and Q63-0 are connected in series between the internal power supply Vint and the ground point Vss. The gates of the MOS transistors Q60-0 and Q63-0 are supplied with the output FOUTn <0> of the fuse latch circuit (FLTCHn <0>). The fuse set selection signal FSEL <0> is supplied to the gate of the MOS transistor Q62-0. Further, the fuse set selection signal FSEL <0> is supplied to the gate of the MOS transistor Q61-0 via the inverter 190-0.

  Circuit portions corresponding to the fuse latch circuits FLATCHn <1> to FLATCHn <3> are also configured similarly to the fuse latch circuit FLATCHn <0>.

  Next, a method for determining a relief area will be described with reference to FIGS. Here, it is assumed that a 16 Mbit memory cell array is assumed as a whole, and this is composed of 32 512 Kbit memory blocks. Bit line pairs in adjacent memory blocks share a sense amplifier repeated in a sense amplifier bank at the boundary of the memory block. The bit map (AR9 to AR12) of the upper row address of this memory cell array is assigned as shown in FIG. 63, and there are 16K word lines designated by the row addresses AR0 to AR12. A spare CSL of books is provided. Here, since the row address is limited to AR12 for a 16K word line, two word lines are simultaneously activated in the memory cell array during normal operation.

Here, the setting of the column redundancy relief area based on the row address proceeds in the following procedure. Assuming that a column redundancy system with a redundancy efficiency of 4 redundancy elements per 1 Mbit of relief area is required from the prediction of defect distribution in the memory cell array, the entire 16 Mbit memory cell array has 4 row address bits (2 ⁴ = 16) rows. Using the address, it is divided into 16 repair regions (Repair Region) <0:15>. The entire scale of one relief area is 1M bits.

  Further, in the special operation mode such as the test mode, the four word lines are simultaneously activated (for example, four are simultaneously activated by bypassing the AR12 information), and the CSL is activated so that the cells on the four word lines are activated. If it is required to read / write independent data at the same time, the four word lines activated simultaneously must be in the same column relief area. The simultaneously activated four word lines must not be activated in the same memory block so that data destruction does not occur, and the sense amplifier is shared by bit line pairs in the memory block. It must not be activated even in adjacent blocks.

Actually, the number of word lines that can simultaneously read / write independent data in the memory cell array is determined by the structure of the data lines in the memory cell array. This will be described by taking a hierarchical data line structure as shown in FIG. 64 as an example. For memory having a hierarchical data line structure, for example USP.No.5,546,349 and IEEE JORNAL OF SOLID-STATE CIRCUIT, VOL.31, No4.APRIL 1996, is described in ^{"A 286mm 2 256MDRAM with X32 Bath} Ends DQ" ing.

  On this memory cell array, master DQ line pairs (MDQP) for reading / writing data are MDQPa <0: 3>, MDQPb <0: 3>, MDQPc <0: 3>, There are 16 pairs in total of MDQPd <0: 3>. Therefore, 16-bit independent data can be read / written in the entire array. Each MDQP is connected to a local DQ line pair (not shown) running in the sense amplifier bank via an MDQ switch in the sense amplifier bank indicated by a black circle in the drawing. Now, assuming that the word line is activated in the leftmost 512 Kbit memory block in the quarter area a of the entire memory cell array, the sense amplifier banks on both sides of the memory block are activated, All data on the word line is amplified. Here, when CSL is activated, 4-bit data on the 4-bit line pair is transmitted to the LDQ line pair that runs two pairs (two bits) in the sense amplifier banks on both sides, and this is transmitted via the MDQ switch. It is transmitted to MDQPa <0: 3>.

  Since all the memory blocks in the area a read / write through the same MDQPa <0: 3>, even if a plurality of word lines are activated in the area a, the plurality of word lines are independently ( (Different) data cannot be read / written. Therefore, the number of word lines that can simultaneously read / write independent data in the area a is one. Considering this, the number of word lines capable of simultaneously reading / writing independent data in the entire memory cell array is four.

  Since only the minimum necessary number of data lines are arranged on the memory cell array, it is a matter of course that the data line structure capable of reading / writing independent data simultaneously on the cells on the four word lines is replaced with column redundancy. Even when the above is performed, it is required to correctly read / write independent data simultaneously in the cells on the four word lines.

  FIG. 63 shows a relief area that satisfies the above conditions. The 1M-bit relief area is composed of four linked 256K-bit partial relief areas so that one bit line is divided into two. A relief area is set. That is, the entire spare cell is divided by the column repair area setting row addresses AR11, AR10, AR9, and AR8, and each is used as a column redundancy element. In other words, cells having different combinations of column relief area setting row addresses AR11, AR10, AR9, and AR8 belong to different relief areas. Further, the redundancy element for each relief area is composed of four partial redundancy elements belonging to the same spare CSL in each of the four partial relief areas constituting the relief area, and the redundant elements constituting one redundancy element are linked. The four partial redundancy elements simultaneously replace the four partial normal elements (which belong to the same CSL and have the same column address) that constitute the defective normal element.

  As described above, the column relief area setting row address in the eighth embodiment is selected based on the data line structure, and the word line that is simultaneously activated in the memory cell array and can read / write independent data. Within the condition that they belong to the same relief area, they are assigned as relief area setting row addresses in order from the higher address. In other words, since the four word lines that are activated simultaneously while bypassing the AR12 information are in the same relief area, AR12 is removed from the column relief area setting row address, and AR11, AR10, AR9, AR8 are sequentially assigned from the other higher addresses. The column relief area setting row address is used.

  The reason why the addresses are selected in order from the higher address is to prevent the partial relief areas constituting one relief area from being linked together more than necessary. For example, in the example of FIGS. 60 and 63, the memory block on one bit line pair is divided into two different relief areas from the middle by the row address AR8. Here, for example, when there is a medium-scale defect that crosses the boundary between the two relief areas on a specific bit line pair (for example, a cluster-like defect), each relief area can be relieved from the relief area. Two redundancy elements are required one by one. If a lower address of AR7 or lower is used as the column repair area setting row address, the number of repair area boundaries on one bit line pair increases, so that there are two redundancy elements for repairing a medium-scale defect across the boundary of the repair area. The probability of need becomes high. To generalize this, unless the column relief area setting row address is assigned in order from the higher address, the partial relief area is unnecessarily subdivided, and there is a high probability that a defect will occur across the relief area. Become. As a result, the relief efficiency of the entire memory cell array is slightly reduced. Considering the above, the column relief area setting row address is assigned in order from the higher address.

[Ninth Embodiment]
Next, a semiconductor memory device according to a ninth embodiment of the invention will be described. The column redundancy relief area setting method according to the above-described eighth embodiment limits the stacked word line test mode (Multiple WL Test Mode). In other words, in the stacked word line test mode, a number of word lines to which data has been written in advance are activated sequentially over several cycles, which is realized by sequentially incrementing the upper address (stack address) in each cycle. The In the above example, AR8 is selected as the stack address because the two word lines connected to the same bit line via the cell transistor are sequentially activated (if possible, they may be activated simultaneously). is there. In practice, one word line is activated from one half and one word line from the other half in the 512 Kbit memory block.

  If the polarities of the data written in advance in the cells on the two word lines are opposite, data collision occurs on the bit line pair. Therefore, the cell transistors are connected to the same bit line pair on the two stacked word lines. The same data should be written to two cells connected via the. However, as can be seen from FIG. 65, on the word line WL_0 that is activated first, a cell in which no data is written (its column address) is replaced by a partial redundancy element for the partial relief area to which WL_0 belongs. May be the address of a partially defective element containing a defect). Since the data in this cell is indefinite, WL_0 is activated, the data from this cell is read onto the bit line pair, and then amplified (restored) by the sense amplifier, the result is also undefined. Therefore, the polarity of the restored data on this bit line pair is different from the polarity of the data written to WL_1 accessed next on this bit line pair, and the bit line is already activated when WL_1 is activated next time. A situation may occur in which the data written to WL_1 is destroyed by the reverse data restored on the pair. This is because the partial normal element in the partial relief area to which WL_1 belongs is normal and has the same column address as the partial defective element replaced by the partial redundancy element in the partial relief area to which WL_0 belongs, and the partial redundancy element for that relief area Occurs when not replaced by.

  Therefore, in the ninth embodiment, in a stacked word line test mode, for example, in a system in which a plurality of word lines connected to the same bit line pair via cell transistors can be activated together, In a column redundancy system in which a column redundancy relief area is set by an address, when the relief area is set so as to divide a bit line, the plurality of word lines activated together belong to the same relief area. The area is set.

  That is, if the column relief area setting row address is changed from AR8 to AR7 in the eighth embodiment, the word lines stacked in the same memory block can belong to the same relief area.

  In this way, as shown in FIG. 66, the stack address AR8 on the same bit line pair as the cell in which no data is written is incremented by being replaced with the partial redundancy element on the word line WL_0 that is activated first. The cells belonging to the next activated word line WL_1 are simultaneously replaced with another linked partial redundancy element, so that no data is written. Therefore, data destruction due to an indefinite cell on the word line activated first does not occur.

  In the ninth embodiment, relief areas are set in accordance with a plurality of word lines stacked in the same memory block. As already described, the stacked address cannot be freely determined due to system (layout) restrictions, but the column relief area setting row address can be freely changed. This is because it can be realized only by changing the row address input to the fuse set selection circuit as shown in FIG.

  Therefore, according to the ninth embodiment, even when the relief area is set so as to divide the bit line, two word lines connected to the same bit line pair are sequentially activated (or simultaneously) together. Can be realized.

[Tenth embodiment]
A semiconductor memory device according to a tenth embodiment of the present invention is a system capable of simultaneously activating a plurality of word lines connected to the same bit line pair via cell transistors, and column redundancy by row address. In the column redundancy system for setting the relief area, the relief area is set so that the plurality of word lines activated together belong to the same relief area when the relief area is set so as to divide the bit line. In this case, the relief area is set so that the number of linked partial relief areas constituting one relief area is minimized.

  In the ninth embodiment, a column redundancy relief area is set by a row address in a system capable of simultaneously activating a plurality of word lines connected to the same bit line pair via cell transistors. For the column redundancy system, AR8 is used as a relief area setting row address so that the plurality of word lines activated together belong to the same relief area when the relief area is set so as to divide the bit line. AR7 was used without. By doing so, each of the linked partial relief regions (or each of the linked partial redundancy elements) has a width of ¼ or less of the bit line as shown in FIG.

  However, if an address lower than the address AR7 is selected as another relief area setting row address, the following problems (4) and (5) occur.

  (4) Since the boundary of the relief area on one bit line increases, the probability that a defect straddling the relief area necessary for the relief will occur increases.

  (5) Since cells on one bit line are dispersed in four or more relief areas, four or more elements are necessary for relief of a column defect in which the entire column (bit line pair) must be replaced.

  In order to avoid this problem in the example of the bitmap as shown in FIG. 63 in which the entire memory cell array is divided into 16 relief areas by the 4-bit column relief area setting row address, a 3-bit column relief area other than AR7 is used. The set row address may be selected from the higher addresses AR12, AR11, AR10, AR9.

  AR7 is used without using AR8 as a repair area setting row address so that a plurality of word lines activated together when the repair area is set to divide the bit line belong to the same repair area. At this time, the width of each partial relief area is equal to or less than 1/4 of the bit line, so the number of linked partial relief areas constituting one relief area is 8 in the present example. That's it. This is because the entire memory cell array is divided into 16 relief areas, so that one relief area has a total width of 2 memory blocks and 2 bit lines. That is, in the tenth embodiment, the width of the partial relief area is set to 1/4 of the bit line, and the number of linked partial relief areas constituting one relief area is set to 8. Generally speaking, in a system in which a plurality of word lines connected to the same bit line pair via cell transistors can be activated together, a relief region is set so as to divide the bit line. When a relief area is set so that a plurality of word lines activated together belong to the same relief area, the number of linked partial relief areas constituting one relief area is minimized. In other words, the relief area setting row address is selected.

  This prevents the relief area from being divided into partial relief areas more finely than necessary, reduces the probability that a defect will occur across the relief area, and minimizes the number of redundancy elements required for column defect relief. As a result, a redundancy system with high relief efficiency can be constructed.

[Eleventh embodiment]
In the semiconductor memory device according to the eleventh embodiment of the present invention, when the relief area setting row address is selected in the above-described eighth or ninth embodiment, it is further determined in the memory cell array determined from the data line structure. The relief area is set so that the word lines that are activated and can read / write independent data belong to the same relief area.

  In the example of the tenth embodiment, AR11, AR10, and AR9 are selected when a 3-bit column relief area setting row address other than AR7 is selected from the upper addresses AR12, AR11, AR10, and AR9. That's what it means. In the data line structure as shown in FIG. 64, it should be possible to simultaneously read / write independent data to a total of four word lines, one from each of the areas a, b, c, and d. It is. The activation of the four word lines can be realized, for example, by bypassing the AR12 information. Therefore, the AR12 is removed from the column relief area setting row address.

  As described above, the relief area setting row address is assigned so that the word lines that are activated together in the memory cell array and can read / write independent data belong to the same relief area, as determined from the data line structure. This is to maximize the number of word lines capable of simultaneously reading / writing independent data even when replacement is performed by column redundancy. Therefore, according to the eleventh embodiment, the eighth and tenth embodiments are used. In addition to the effect of this embodiment, the number of independent data that can be read / written from one memory cell array at a time is maximized, and an effect is obtained that a memory cell array structure with a high data transfer rate can be constructed.

[Twelfth embodiment]
The semiconductor memory device according to the twelfth embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and the scale of the column relief area (determined from the defect distribution in the array) is constant, In addition, under the condition that the scale of each of the linked partial relief areas constituting one column relief area is determined, that is, the condition that each scale of the linked partial relief areas is constant or larger. Below, the relief area is set so that the number of word lines that can be activated together in the relief area in the stacked word line test mode is maximized.

  Considering replacement by row redundancy, the number of word lines that can be activated together in the memory cell array in the stacked word line test mode is limited depending on the system, and it is not possible to activate many word lines without limitation. Absent. Now, in the memory cell array as shown in FIG. 63, in the stacked word line test mode, a system capable of activating 32 word lines together in the entire array, two by two from a single 512K-bit memory block. Consider an example. This is because AR12, AR11, AR10, and AR8 are selected as the stack addresses, and as a result, it may be considered that 32 pieces of information are selected by bypassing the information of AR12, AR11, AR10, and AR8.

  Next, assuming that four redundancy elements are required for the relief area 2M bits from the defect distribution in the memory cell array, since the four spare CSLs are provided in the memory cell array, the entire memory cell array Is divided into eight column relief areas using a 3-bit column relief area setting row address.

  Also, hate that one partial relief area becomes too small, and suppose that the size of the partial relief area should not be smaller than 1/4 of the memory block. This means that an address lower than AR7 is not selected as the column relief area setting row address. That is, a 3-bit column relief area setting row address is selected from AR12, AR11, AR10, AR9, AR8, and AR7.

  Specifically, in the twelfth embodiment, when selecting a column relief area setting row address, the information is used to activate the maximum number of word lines (determined by the system) in the stacked word line test mode. This means that bypassed row addresses are avoided as much as possible. That is, when 3 bits are selected from the column repair area setting row address candidates AR12, AR11, AR10, AR9, AR8, AR7, the stack addresses AR12, AR11, AR10, AR8 are avoided as much as possible. That is, one bit is selected from the bits and AR12, AR11, AR10, and AR8.

Of the row addresses whose information is bypassed to activate the maximum number of word lines in the stacked word line test mode, the maximum number is activated when n is the number of bits of the address that is also the column relief area setting row address. The number of relief areas to which the word line belongs is ²ⁿ . Therefore, since 32 word lines are distributed to 2 ⁿ (n = 1) relief areas, the number of word lines that can be activated together in the same relief area is 16.

  With this configuration, the number of word lines that can be activated together in the same relief area is maximized, and the number of word lines that can be simultaneously written is maximized in the stacked word line test mode. Contributes to shortening.

  It should be noted here that, in the stacked word line test mode, a plurality of word lines activated together in the same relief area can be simultaneously written, but are not necessarily independent (different from each other). ) Data cannot be written. This is because in the data line structure as shown in FIG. 64, independent data can be written at the same time from only one area from each of the areas a, b, c, and d. Therefore, when a plurality of word lines are selected in each of the areas a, b, c, and d, the same data is written in the same area.

[Thirteenth embodiment]
The semiconductor memory device according to the thirteenth embodiment of the present invention is activated together in the memory cell array, which is further determined by the data line structure, when the relief area is set as in the twelfth embodiment. The relief area is determined so that word lines capable of reading / writing independent data belong to the same relief area.

  Specifically, in the data line structure as shown in FIG. 64, the word lines that are activated together in the memory cell array and can read / write independent data, which are determined from the data line structure, are defined in each region a. , B, c, d, one by one, for example, a word line selected by bypassing AR12 information. Accordingly, if AR12 is removed from the relief area setting row address, the four word lines belong to the same relief area, and independent data can be read / written. Therefore, in the thirteenth embodiment, when considered together with the twelfth embodiment, the relief area setting row address is selected from two bits AR9 and AR7 and one bit from AR11, AR10 and AR8. That is.

  Therefore, according to the thirteenth embodiment, in addition to the effects of the twelfth embodiment, the number of word lines capable of simultaneously reading / writing independent data can be maximized, and the test time can be shortened. It becomes.

[Fourteenth embodiment]
A semiconductor memory device according to a fourteenth embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and sets a relief area so as to divide a bit line. The condition of the column relief area determined from the defect distribution is constant, and the upper limit of the number of relief areas dividing one bit line is determined, that is, the number of relief areas dividing the bit line is constant or less. Under certain conditions, the relief area is set so that the number of word lines that can be activated together in the relief area is maximized in the stacked word line test mode.

  As in the twelfth embodiment, in the stacked word line test mode, an example of a system in which 32 word lines can be activated together in the entire array, two by one from a single 512K-bit memory block. Think about it. Assuming that four redundancy elements are required for the relief area 2M bits from the defect distribution in the memory cell array, the entire memory cell array is reconstructed into 8 column reliefs using a 3-bit column relief area setting row address. It will be divided into areas. Also, suppose that the number of redundancy elements necessary for relieving one column defect is not too great, and the number of relieving areas dividing one bit line is not larger than two.

  When selecting a column relief area setting row address, it is possible to avoid a row address whose information is bypassed as much as possible in order to activate the maximum number of word lines (determined by the system) in the stacked word line test mode. Since the maximum number of word lines that can be activated together in the relief area during the word line test mode can be maximized, two of the three bits are AR9 and AR7. If another bit is selected in addition to AR7 at a lower address below AR8, the bit line is not divided because it is divided into four or more relief areas. Therefore, the other bit is selected from AR12, AR11, and AR10.

  The fourteenth embodiment also contributes to shortening of the test time because the number of simultaneously writeable word lines is maximized in the stacked word line test mode.

[Fifteenth embodiment]
The semiconductor memory device according to the fifteenth embodiment of the present invention is activated together in the memory cell array, which is further determined from the data line structure, when the relief area is set as in the fourteenth embodiment. The relief area is determined so that word lines capable of reading / writing independent data belong to the same relief area.

  Specifically, in the data line structure as shown in FIG. 64, the word lines that are activated together in the memory cell array and can read / write independent data, which are determined from the data line structure, are defined in each region a. , B, c, d, one by one, for example, a word line selected by bypassing AR12 information. Accordingly, if AR12 is removed from the relief area setting row address, the four word lines belong to the same relief area, and independent data can be read / written. Therefore, when considered together with the fourteenth embodiment, the relief area setting row address is selected from two bits AR9 and AR7 and one bit from AR11 and AR10.

  In this way, in addition to the effect of the fourteenth embodiment, the number of word lines that can simultaneously read / write independent data can be maximized, and the test time can be shortened.

[Sixteenth embodiment]
The semiconductor memory device according to the sixteenth embodiment of the present invention is a combination of the techniques of the twelfth embodiment and the fourteenth embodiment, and sets a column redundancy relief area by a row address. With respect to the column redundancy system, the scale of the column repair area determined from the defect distribution in the array is constant, and the scale of each of the linked partial repair areas constituting one column repair area is constant or more. In addition, under the condition that the number of relief areas for dividing one bit line is constant or less, the number of word lines that can be activated together in the relief area in the stacked word line test mode is maximized. A relief area is set in

  According to the sixteenth embodiment, the number of word lines that can be simultaneously written in the stacked word line test mode, which is the effect of the twelfth embodiment and the fourteenth embodiment, is maximized, and the test time is increased. Can be shortened.

[Seventeenth embodiment]
The semiconductor memory device according to the seventeenth embodiment of the present invention is activated together in the memory cell array, which is further determined from the data line structure, when the relief area is set as in the sixteenth embodiment. The relief area is determined so that word lines capable of reading / writing independent data belong to the same relief area.

  Thus, in addition to the effect of the sixteenth embodiment, the number of word lines capable of reading / writing independent data at the same time can be maximized, and the test time can be shortened.

[Eighteenth embodiment]
The semiconductor memory device according to the eighteenth embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and all of the word lines that can be activated together in the stacked word line test mode are the same. The relief area is set so as to belong to the relief area.

  In the examples so far, this means that the repair area setting row address is determined while avoiding the stack addresses AR12, AR11, AR10, and AR8. By doing so, the number of word lines that can be simultaneously written in the stacked word line test mode is maximized, and the test time can be shortened.

[Nineteenth embodiment]
In the semiconductor memory device according to the nineteenth embodiment of the present invention, when a relief area is set as in the eighteenth embodiment, it is assigned as a relief area setting row address in order from the highest address as much as possible. .

  With this configuration, in addition to the effect of the eighteenth embodiment, the partial relief area is unnecessarily subdivided, and the probability of occurrence of a defect straddling the relief area increases. The possibility of slightly reducing the relief efficiency can be kept low. Further, when the relief area is set so as to divide the bit line, the number of redundancy elements necessary for relieving the column defect can be minimized, so that a redundancy system with high relief efficiency can be constructed.

[20th embodiment]
The semiconductor memory device according to the twentieth embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and is a word that should have been activated together in the stacked word line test mode. When there are defects in a plurality of lines, it is possible to deselect only the defective word line, and instead select a plurality of spare word lines used for replacement, and the plurality of replaced spare word lines can select cell transistors. This is a semiconductor memory device having a function of disabling only a spare word line in a stacked word line test mode in a system that may be connected to the same bit line pair via the same.

  In the stacked word line test mode, when there are defects in a plurality of word lines activated together, it is possible to deselect the plurality of defective word lines and select a plurality of spare word lines instead. In the system, if a plurality of word lines activated together belong to the same relief area, a plurality of spare word lines are connected to the same bit line pair via cell transistors. Even if the word line is replaced, collision (data destruction) of the cell data on the spare word line on the bit line does not occur.

  In the twentieth embodiment, only the spare word line that should replace the defective word line is disabled when all the word lines activated together in the stacked word line test mode do not belong to the same relief area. It is to make. A system in which a plurality of spare word lines used for replacement are connected to the same bit line pair via cell transistors is, for example, a case where another array for redundancy is provided for the memory cell array.

  As a DRAM test, there is a test in which a word line is continuously activated for a long time and stress is applied to cells around the word line. If the stacked word line test mode is used for such a test, the test time can be drastically reduced. In addition, during this stress, not only the word line is activated, but also the latch direction of the bit line pair is important, so data must not be latched so that the data on the word line activated together is destroyed. If a plurality of defective word lines to be replaced by a plurality of spare word lines connected to the same bit line pair via cell transistors are not in the same relief area, a cell of a cell replaced with a column redundancy element on the plurality of spare word lines. Since the column address may be different, there is a possibility that data destruction due to an indefinite cell on the previously activated spare word line may occur, so that it does not make sense for the test as it is, so the defective word line is replaced in the present invention. Disable only the spare word line.

  Note that disabling only the spare word line can be realized by using a generally known redundancy disable test mode. In this function, in the case of a redundancy hit, the function of disabling the defective word line remains valid and the corresponding spare word line is not activated.

  In this way, no stress is applied to the cells around the spare word line during the test, but the test was passed because the cells around the spare cell were not stressed for the following two reasons (6) and (7). There is almost no probability that the cell will become defective after product shipment, and this is not a problem in practical use.

  (6) The probability that a cell becomes defective by this test is inherently quite low.

  (7) A word line near a spare word line used for replacement in another array for redundancy is not always used for replacement, and there may be no problem even if no stress is applied around it. .

  Therefore, it can be seen that the twentieth embodiment expands the availability of the test mode using the stacked word line test mode.

  It should be noted that the semiconductor memory device according to the twentieth embodiment described above has a plurality of column activation systems that are activated together in the stacked word line test mode with respect to the column redundancy system that sets the column redundancy relief area by the row address. It can also be seen that this is an example of a semiconductor memory device in which only a defective word line is not selected when a defective word line is defective and a spare word line that should replace the defective word line is not activated.

[Twenty-first embodiment]
A semiconductor memory device according to a twenty-first embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and sets a bit line pair when setting a relief area so as to divide the bit line. Of the physical addresses for distinguishing each of the upper bits, they are assigned as column relief area setting addresses in order from the lowest address.

  A column redundancy system that sets a column redundancy relief area by row address can increase the number of column redundancy elements without increasing spare columns (spare cells), in other words, without increasing spare CSL. It is a good redundancy system (see FIG. 60 and the description relating to FIG. 60). In this column redundancy system, if the number of column relief area setting row addresses is increased, the relief area may have to be set so as to divide one bit line (bit line pair).

  At this time, as a method of selecting a row address for setting a relief area from physical addresses for distinguishing each bit on the bit line pair, there is a method of selecting from the upper address as much as possible. If the bit map of the physical row address is assigned in the order as shown in FIGS. 60 and 63, the physical address for distinguishing each bit on the bit line pair is AR0 to AR8. However, for example, when 2 bits are selected as the row address for setting the relief area, AR7 and AR8 are selected. In this selection method, the number of relief area boundaries on one bit line pair can be minimized. Therefore, it is possible to minimize the probability of occurrence of a defect across a repair area that requires two or more elements for the repair, and it is possible to suppress the reduction in the repair efficiency of the entire memory cell array (the tenth embodiment). See form).

  However, there may be a case where the method for selecting the column relief area setting row address as described above is problematic. When AR7 and AR8 are selected as the relief area setting row addresses, the cells on one bit line pair are dispersed into four relief areas, and the cells belonging to one relief area are within ¼ the width of the bit line. It becomes a continuous cell. Here, assuming that there is a very large defect (defect) in the direction in which the bit line extends for some reason, if the defect is within one remedy area at the time of the test before shipment, one defect is remedied. Only redundancy elements are used.

  The problem is that a defect that has been recognized as being within this single relief area may be recognized as a larger defect after shipment, that is, a market defect may occur. The following (8) and (9) can be considered as the cause of this occurrence.

(8) Limit of screening Since it is impossible to reproduce all use conditions of the user in the test, depending on the use conditions of the user, there is a case where a thing recognized as a larger defect may be missed. This is also related to not knowing what kind of test should be performed for screening since the cause of a huge defect is not known at the time of testing.

(9) Defect growth A giant defect may grow into a larger defect due to changes over time. This is related to the fact that the cause of the defect is not known, but there is no way to deal with it when this happens.

  In this embodiment, in order to solve the problem that the market failure due to the causes (8) and (9) occurs, in this embodiment, the column repair area is set from the physical addresses for distinguishing each bit on the bit line pair. When selecting an address, select from lower addresses. In other words, in this example, instead of selecting AR7 and AR8, AR0 and AR1 are selected. In this way, cells having the same AR0 and AR1 belong to the same relief area. For this reason, when a defect having a size of four or more word lines in the extending direction of the bit line is relieved by column redundancy, four column redundancy elements corresponding to the four relief areas are used. This is because, considering that cells on one bit line pair are dispersed in four relief areas, not only a part of the bit line pair including a defect is replaced, but the entire bit line pair (Full BL). Is to replace

  In other words, the idea of the present embodiment is that when the repair area is set so as to divide the bit line, when repairing a large defect, the column repair area setting address is set so that the entire bit line pair is replaced as much as possible. It is to choose. By doing so, it is possible to prevent a market failure from occurring due to the causes described in (8) and (9) above.

  If such a column repair area setting address is selected, a plurality of column redundancy elements are always used for repairing a defect that continues two or more bits in the direction in which the bit line extends. For example, four column redundancy elements are used to relieve defects that are continuous for 4 bits or more. When selecting a column relief area setting address from physical addresses for distinguishing each bit, multiple column redundancy elements are used even if it is not necessary to use multiple column redundancy elements for relief if selected from the higher address It will be. For this reason, if there is a high probability that a defect with two or more consecutive bits will occur, the repair efficiency will be reduced.

  Therefore, if the probability of market failure due to the inability to sufficiently screen the huge defects described here is small enough to be ignored, the physicality for distinguishing each bit on the bit line pair can be suppressed in order to suppress the reduction in repair efficiency. The addresses may be assigned as column relief area setting addresses in order from the higher address among the addresses. Therefore, whether to assign from the top or the bottom should be determined after thoroughly examining what kind of defect occurrence probability is high in the technology of each generation.

[Twenty-second embodiment]
A semiconductor memory device according to a twenty-second embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and sets a bit line pair when setting a relief area so as to divide the bit line. Of the physical addresses for distinguishing each of the upper bits, the addresses are assigned as column relief area setting addresses in order from the second, third, or fourth address from the lowest to the higher address.

  In the twenty-first embodiment, when the relief area is set so as to divide the bit line, it is assigned as the column relief area setting address in order from the lowest address. As described above, when such a column repair area setting address is selected, a plurality of column redundancy elements are always used for repairing a defect that continues two or more bits in the direction in which the bit line extends. Therefore, when the probability of occurrence of a defect that continues for 2 bits or more is high, the repair efficiency is lowered.

  As a failure mode in the cell array, a bit line contact for connecting an active region (diffusion region) constituting a source / drain portion of a cell transistor and a bit line is open. This failure mode will be described with reference to FIG. FIG. 67 is a schematic diagram showing a pattern layout of a ½ pitch cell array configuration of trench cells. The word line WL and the bit line pair BL / bBL are arranged so as to cross each other. In the semiconductor substrate under the bit line pair BL / bBL, active regions (diffusion regions) AA constituting the source / drain portions of the cell transistors are provided in a staggered manner between adjacent bit lines. . The bit line pair BL / bBL and the active area AA are electrically connected by a bit line contact BCN. At both ends of the active area AA, trench cells TC are formed. The trench cells TC are arranged in a back-to-back pattern as shown by being surrounded by a broken line BRK.

  Here, when an open failure of the bit line contact BCN occurs, 2 bits continuous in the direction in which the bit line extends become a defective cell. If such a defect occurs with a high probability in a certain generation of technology, as long as the least significant bit is assigned as the column repair area setting address, two elements are used to repair this defect, and the repair efficiency is significantly reduced. Resulting in.

  The physical address that distinguishes two consecutive bits that become defective due to the opening of the bit line contact BCN is only the lowest address AR0 or the lowest address AR0 and the second lowest address AR1 according to the address assignment. If these addresses are excluded from the repair area setting row address (that is, they are selected as the repair area setting row address in order from the second (AR1) or third (AR2) address from the lowest), this defect is repaired. To eliminate the need to use multiple elements.

  That is, in the twenty-second embodiment, when there is a high probability that a continuous cell is defective in a specific (clear cause) failure mode, the relief area is set so as to divide the bit line. In this case, the column relief area setting address is selected from the lower address as much as possible while removing the address for distinguishing the cells in the consecutive defects from the column relief area setting address. In this way, by basically replacing the entire bit line pair for a huge defect, it is possible to prevent a market failure due to the huge defect in the same way as in the twenty-first embodiment, and to further identify it. When there is a high probability that a continuous cell is defective in the failure mode (the cause is clear), it is possible to suppress a reduction in repair efficiency.

  As another failure mode, short-circuiting between back-to-back cells (broken line BRK) may occur frequently. As can be seen from FIG. 67, when such a failure occurs, the fail bit map becomes: pass-pass-fail-pass-pass-fail-pass-pass-. The physical address for distinguishing the two cells in this failure mode is assigned with the lowest address AR0 and the second lowest address AR1, or the lowest address AR0, the lowest second address AR1 and This is the third address AR2 from the lowest. Accordingly, when the probability of occurrence of such a failure mode is high, the repair area setting row address may be selected in order from the third (AR2) or fourth (AR3) address from the lowest.

  In the above description, the cell array configuration of 1/2 pitch of the trench cells is taken as an example, but the present embodiment can be similarly applied to other array configurations. This is because a defect occurs in several consecutive bits, such as a defect in two consecutive bits, a defect in one or two cells, or a defect in three to eight bits. This is because there are defects peculiar to each array configuration.

[Twenty-third embodiment]
A semiconductor memory device according to a twenty-third embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and sets a bit line pair when setting a relief area so as to divide the bit line. Of the physical address for distinguishing each bit above, one bit from the most significant address in the address for distinguishing each of a plurality of consecutive word lines in a plurality of word lines constituting a normal element replaced by a row redundancy element Allocation is performed so that the upper address becomes the highest address in the column relief area setting address.

  The basic idea of the semiconductor memory device according to the twenty-first and twenty-second embodiments is to replace the entire bit line pair as much as possible when repairing a giant defect that continues in the direction in which the bit line extends. However, if such a huge defect is relieved using row redundancy instead of column redundancy, this idea becomes meaningless.

  If the repair algorithm is first replaced with column redundancy, and if column redundancy becomes insufficient, row redundancy is used, such that the redundancy is prioritized, there is no big problem. However, when priority is given to row redundancy, a defect of a size that is included in a plurality of continuous word lines in a plurality of word lines constituting a normal element that is replaced by a row redundancy element is basically reduced in row redundancy. Will be replaced. For this reason, it is impossible to avoid the risk of occurrence of a market failure due to the huge defect as described above.

  Therefore, even if the lower address below the address for distinguishing each of a plurality of consecutive word lines in the plurality of word lines constituting the normal element replaced with the row redundancy element is used as the column repair area setting row address, the bit line pair Just increasing the number of boundaries of the upper relief area cannot be said to be good in terms of relief efficiency of the entire memory cell array.

  Next, a semiconductor memory device according to the twenty-third embodiment will be described using a specific example. For example, when a normal element to be replaced by row redundancy is composed of two groups of 16 consecutive word lines (that is, 32 are replaced at the same time), the address for distinguishing each of the 16 consecutive word lines is: 4 bits AR0 to AR3. At this time, in this embodiment, when the column relief area setting address is selected from the physical addresses (AR0 to AR8) for distinguishing each bit on the bit line pair, the fifth lowest address is used. Choose an AR4 and lower addresses (if more than one are needed). By doing so, a huge defect larger than 16 word lines can always be remedied by replacing the entire bit line.

  Therefore, in the twenty-third embodiment, while avoiding the risk of the occurrence of a market failure due to the huge defect described above, the reduction in the repair efficiency due to the use of a plurality of redundancy elements more than necessary is minimized. Can be suppressed.

[Twenty-fourth embodiment]
The semiconductor memory device according to the twenty-fourth embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and sets the relief area to divide the bit line as follows (a1 ) To (c1) are satisfied. (A1) Read / write word lines that are activated together in the memory cell array so that readable / writable word lines belong to the same relief area. (B1) The number of relief area regions for dividing the bit line is minimized. (C1) The column relief area setting addresses are sequentially assigned from the lowest address among the physical addresses for distinguishing each bit on the bit line pair.

  Assigning a column relief area setting row address so that word lines that are activated together in the memory cell array and can read / write independent data belong to the same relief area, determined by the data line structure, can be replaced by column redundancy. Even if it is performed, it is to maximize the number of word lines that can simultaneously read / write independent data. Therefore, the number of independent data that can be read / written from one memory cell array at a time is maximized, and an effect is obtained that a memory cell array structure with a high data transfer rate can be constructed.

  For example, in the data line structure shown in FIGS. 63 and 64, independent data can be simultaneously read / written on a total of four word lines, one from each of the regions a, b, c, and d. Is possible. Since the activation of the four word lines can be realized by bypassing the information of AR12, this AR12 is excluded from the column relief area setting row address.

  Here, specifically, the number of relief areas for dividing the bit line is minimized as follows. Assuming a 16 Mbit memory cell array as shown in FIG. 63 and assuming that a column redundancy system with a relief efficiency of 4 redundancy elements per 1 Mbit of relief area is necessary from the prediction of defect distribution in the memory cell array, the entire 16 Mbit memory cell array Are divided into 16 relief areas using a 4-bit row address. Here, if the 4-bit column relief area setting address is selected from among AR0 to AR8, which are physical addresses for distinguishing each bit on the bit line pair, 16 cells on one bit line pair are obtained. Will be distributed to the relief area. As a result, for example, 16 column redundancy elements are required for repairing a column defect in which the entire bit line pair must be replaced, and it is expected that the repair efficiency will be significantly reduced.

  In the twenty-fourth embodiment, the number of relief areas for dividing a bit line is minimized. When a column relief area setting address is selected, physical addresses (AR0 to AR8) for distinguishing each bit on a bit line pair are selected. ) As much as possible. That is, when a 4-bit column relief area setting address is selected from physical addresses below AR11, 3 bits are AR11, AR10, AR9, and only 1 bit is a physical address for distinguishing each bit on the bit line pair. Choose from AR0 to AR8. In this way, since the cells on one bit line pair are only distributed to the two relief areas, only two column redundancy elements need be used when the entire bit line pair must be replaced.

  Further, in the twenty-fourth embodiment, the column repair area setting address is assigned in order from the lowest address among the physical addresses (AR0 to AR8) for distinguishing each bit on the bit line pair. Therefore, the remaining 1 bit of the column relief area setting address is set to the least significant bit AR0. In this way, since the huge defect is always remedied by replacing the entire bit line pair, the effect of preventing the occurrence of a market defect due to the huge defect described in the twenty-first embodiment is also obtained. It is done.

[Twenty-fifth embodiment]
In the semiconductor memory device according to the twenty-fifth embodiment of the present invention, when setting a relief area so as to divide a bit line in a column redundancy system that sets a column redundancy relief area by a row address, the following (a2 ) To (c2) are satisfied. (A2) Word lines that are activated together in the memory cell array and capable of reading / writing independent data belong to the same relief area. (B2) The number of relief area regions for dividing the bit line is minimized. (C3) The physical address for distinguishing each bit on the bit line pair is assigned as the column repair area setting address in order from the second, third or fourth address from the lowest.

  In the twenty-fifth embodiment, the elements of the twenty-second embodiment are added to the twenty-fourth embodiment described above. In addition to the effects of the twenty-fourth embodiment, a specific (cause of clear Even when there is a high probability that a continuous cell is defective in the failure mode, it is possible to suppress the reduction in the repair efficiency.

[Twenty-sixth embodiment]
A semiconductor memory device according to a twenty-sixth embodiment of the present invention relates to a column redundancy system that sets a column redundancy relief area by a row address, and sets the relief area so as to divide the bit line as follows (a3 ) To (c3) are satisfied. (A3) Read / write word lines that are activated together in the memory cell array are made to belong to the same relief area. (B3) The number of relief area regions for dividing the bit line is minimized. (C3) Among the physical addresses for distinguishing each bit on the bit line pair, in the address for distinguishing each of a plurality of consecutive word lines in a plurality of word lines constituting a normal element replaced with a row redundancy element Allocation is performed so that an address one bit higher than the most significant address becomes the most significant address in the column relief area setting address.

  In the twenty-sixth embodiment, the elements of the twenty-third embodiment are added to the twenty-fourth embodiment described above. In addition to the effects of the twenty-fourth embodiment, a plurality of redundancy more than necessary is required. It is possible to minimize the reduction in the relief efficiency due to the use of the element.

[Twenty Seventh Embodiment]
In a semiconductor memory device according to a twenty-seventh embodiment of the present invention, in an operation mode in which a once activated word line maintains its state in a plurality of consecutive word line selection cycles, for example, in a stacked word line test mode In this system, a plurality of word lines connected to the same bit line via cell transistors can be activated together. In this system, regarding a column redundancy system in which a column redundancy relief area is set by a row address, the following (a4) to (d4) are satisfied when the relief area is set so as to divide the bit line. (A4) Word lines that are activated together in the memory cell array and capable of reading / writing independent data belong to the same relief area. (B4) The number of relief area regions for dividing the bit line is minimized. (C4) The same bit line that can be activated together in the same relief region in an operation mode in which the activated word line maintains its state in a plurality of consecutive word line selection cycles, for example, in the stacked word line test mode The number of word lines connected to each other through cell transistors is maximized. (D4) Allocation is performed as a column relief area setting address in order from the lowest address among the physical addresses for distinguishing each bit on the bit line pair.

  The semiconductor memory device according to the twenty-seventh embodiment is a modification of the twenty-fourth embodiment. In this semiconductor memory device, when selecting a column relief area setting address from physical addresses (AR0 to AR8) for distinguishing each bit on a bit line pair, for example, avoid bypass addresses as much as possible in the stacked word line test mode. In addition, column relief area setting addresses are selected in order from the lowest possible address. By doing so, the number of simultaneously writeable word lines is maximized in the stacked word line test mode, which contributes to shortening the test time.

[Twenty-eighth embodiment]
In the semiconductor memory device according to the twenty-eighth embodiment of the present invention, in an operation mode in which a word line once activated maintains its state in a plurality of consecutive word line selection cycles, for example, in a stacked word line test mode. In this system, a plurality of word lines connected to the same bit line via cell transistors can be activated together. In this system, regarding a column redundancy system in which a column redundancy relief area is set by a row address, the following (a5) to (d5) are satisfied when the relief area is set so as to divide the bit line. (A5) Word lines that are activated together in the memory cell array and can read / write independent data belong to the same relief area. (B5) The number of relief area regions for dividing the bit line is minimized. (C5) The same bit that can be activated together in the relief region in an operation mode in which the activated word line maintains its state in a plurality of consecutive word line selection cycles, for example, in the stacked word line test mode The number of word lines connected to the line via cell transistors is maximized. (D5) The physical address for distinguishing each bit on the bit line pair is assigned as the column relief area setting address in order from the second, third or fourth address from the lowest.

  The semiconductor memory device according to the twenty-eighth embodiment is a modification of the twenty-fifth embodiment. For example, in the stacked word line test mode, the number of simultaneously writeable word lines is maximized and the test time is reduced. Contributes to shortening.

[Twenty-ninth embodiment]
In a semiconductor memory device according to a twenty-ninth embodiment of the present invention, in an operation mode in which a once activated word line maintains its state in a plurality of consecutive word line selection cycles, for example, in a stacked word line test mode In this system, a plurality of word lines connected to the same bit line via cell transistors can be activated together. In this system, regarding a column redundancy system in which a column redundancy relief area is set by a row address, the following (a6) to (d6) are satisfied when the relief area is set so as to divide the bit line. (A6) Word lines that are activated together in the memory cell array and can read / write independent data belong to the same relief area. (B6) The number of relief area regions for dividing the bit line is minimized. (C6) The same bit that can be activated together in the relief area in an operation mode in which the activated word line maintains its state in a plurality of consecutive word line selection cycles, for example, in the stacked word line test mode The number of word lines connected to the line via cell transistors is maximized. (D6) Among the physical addresses for distinguishing each bit on the bit line pair, the addresses in the address for distinguishing each of a plurality of consecutive word lines in a plurality of word lines constituting a normal element replaced with a row redundancy element Allocation is performed so that an address one bit higher than the most significant address becomes the most significant address in the column relief area setting address.

  The semiconductor memory device according to the twenty-ninth embodiment is a modification of the twenty-sixth embodiment. For example, in the stacked word line test mode, the number of simultaneously writeable word lines is maximized and the test time is reduced. Contributes to shortening.

  Although the present invention has been described above using the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention at the stage of implementation. is there. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of problems to be solved by the invention can be solved, and described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a block diagram showing a 64 Mbit memory cell array adopting a centralized redundancy system, for explaining an outline of a semiconductor memory device according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic diagram showing an example of allocation of each address in a normal cell array of the semiconductor memory device shown in FIG. 1. FIG. 2 is a circuit diagram illustrating in detail a part of an array control circuit unit and a control signal wiring unit in the semiconductor memory device illustrated in FIG. 1. 3A and 3B are diagrams for explaining a redundancy replacement operation in the semiconductor memory device shown in FIGS. 1 to 3, in which FIG. 1A is a schematic diagram, and FIG. The block diagram which shows a part of bank for demonstrating the semiconductor memory device concerning the 2nd Embodiment of this invention. FIG. 3 is a circuit diagram illustrating a specific configuration example by extracting a memory block, a sense amplifier, a row decoder unit, a word line driver unit, and an array control circuit in a memory cell array. FIG. 7 is a circuit diagram illustrating a configuration example by extracting the peripheral circuit and the X predecoder, the redundancy control circuit, and the redriver in the redriver in the circuit illustrated in FIG. 6. FIG. 8 is a circuit diagram showing a configuration example of a bWLOFF latch circuit in the circuit shown in FIG. 7. FIG. 8 is a circuit diagram showing a configuration example of an SAE latch circuit in the circuit shown in FIG. 7. 8 is a circuit diagram showing a configuration example of a bRPRE latch circuit and an X predecoder in the circuit shown in FIG. 7, wherein (a) shows a bRPRE latch circuit, and (b) shows an X predecoder. 6 is a timing chart for explaining the operation of the stacked word line test mode (in the case of redundancy miss). 9 is a timing chart for explaining the operation (in the case of redundancy hit) in the stacked word line test mode. The block diagram which shows a part of bank for demonstrating the semiconductor memory device concerning the 3rd Embodiment of this invention. FIG. 3 is a block diagram illustrating a specific configuration example by extracting memory cells, sense amplifiers, row decoder units, word line driver units, and array control circuits in a memory cell array. FIG. 15 is a block diagram illustrating a configuration example by extracting the peripheral circuit and the X predecoder, the redundancy control circuit, and the redriver in the redriver in the circuit illustrated in FIG. 14. FIG. 16 is a circuit diagram showing a specific configuration example of a WLON / OFF control circuit in the circuit shown in FIG. 15. FIG. 16 is a circuit diagram showing a specific configuration example of a SAON / OFF control circuit in the circuit shown in FIG. 15. FIG. 16 is a circuit diagram showing a specific configuration of an STCRST control circuit in the circuit shown in FIG. 15. FIG. 15 is a circuit diagram illustrating a specific configuration example of a BLKSEL latch circuit for explaining the control circuit and the latch circuit that holds address and redundancy information illustrated in FIG. 14; The circuit diagram which shows the specific structural example of a TWLON latch circuit. The circuit diagram which shows the specific structural example of SA control circuit. The circuit diagram which shows the specific structural example of SA latch circuit. The circuit diagram which shows the specific structural example of a TRDE latch circuit. The circuit diagram which shows the specific structural example of a HIT control circuit. 9 is a timing chart for explaining an operation in a stacked word line test mode in a semiconductor memory device according to a third embodiment of the present invention. 9 is a timing chart for explaining an operation of returning all activated word lines to a precharge state in the semiconductor memory device according to the third embodiment of the present invention. 9 is a timing chart for explaining an operation when a redundancy hit occurs in the semiconductor memory device according to the third embodiment of the present invention. FIG. 9 is a block diagram for explaining a configuration of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 9 is a block diagram for explaining a configuration of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 30 is a block diagram showing a configuration example by extracting memory cells, sense amplifiers, row decoders, and array control circuits in the memory cell array in the circuits shown in FIGS. 28 and 29; FIG. 31 is a circuit diagram for explaining a modification of the circuit shown in FIG. 30 and illustrating an example in which a signal input to a word line driver is driven from a memory block on one side. FIG. 31 is a circuit diagram for explaining a modification of the circuit shown in FIG. 30 and illustrating an example in which a signal input to a word line driver is driven from memory blocks on both sides. FIG. 32 shows wiring from the WLDV driver to the WL driver shown in FIG. 31, wherein (a) is a pattern layout, and (b) is a cross-sectional view taken along line 33B-33B of FIG. FIG. 33 shows wiring from the WLDV driver to the WL driver shown in FIG. 32, where (a) is a pattern layout, and (b) is a cross-sectional view taken along line 34B-34B in FIG. FIG. 31 is a circuit diagram showing a specific configuration of a TRDE control circuit in the circuit shown in FIG. 30. FIG. 31 is a circuit diagram showing a specific configuration of part of the HIT control circuit in the circuit shown in FIG. 30. FIG. 31 is a circuit diagram showing a specific configuration of a row decoder in the circuit shown in FIG. 30. FIG. 10 is a block diagram for explaining a configuration example of a semiconductor memory device according to a fifth embodiment of the invention. FIG. 39 is a block diagram for explaining a configuration example in the vicinity of the word line driver, row decoder, and array control circuit in the semiconductor memory device shown in FIG. 38; FIG. 10 is a circuit diagram showing a configuration example by extracting a part of a row decoder and a word line driver in a semiconductor memory device according to a fifth embodiment of the present invention. 10 is a timing chart for explaining the operation of the semiconductor memory device according to the fifth embodiment of the invention. 10 is a timing chart for explaining the operation of the semiconductor memory device according to the fifth embodiment of the invention. 4 is a schematic diagram showing a state of a memory cell array when two word lines are simultaneously activated in a cell array unit in a stacked word line test mode. FIG. FIG. 6 is a schematic diagram showing a state of a memory cell array when eight word lines are simultaneously activated in a cell array unit in a stacked word line test mode. FIG. 4 is a schematic diagram showing the correspondence between a row address / signal X_ADD / signal XBLKP / memory block during normal operation; Schematic diagram showing the correspondence between row address / signal X_ADD / signal XBLKP / memory block in quadruple word line test mode (TM1011MUSI entry) The circuit diagram for demonstrating the structural example of X predecoder for implement | achieving 4 times word line test mode. The schematic diagram for demonstrating the example of arrangement | positioning of X predecoder for implement | achieving 4 times word line test mode. The circuit diagram for demonstrating the structural example of X predecoder for implement | achieving 4 times word line test mode. FIG. 25 is a block diagram for extracting and showing a part of a row decoder and a word line driver, for explaining a semiconductor memory device according to a seventh embodiment of the present invention. The circuit diagram which shows the structural example of a TRDE control circuit. FIG. 51 is a circuit diagram showing a configuration example of a bRDOUT driver & latch circuit in the circuit shown in FIG. 50. FIG. 51 is a circuit diagram showing a configuration example of an X decoder in the circuit shown in FIG. 50. FIG. 51 is a block diagram showing a configuration example of a word line driver in the circuit shown in FIG. 50. FIG. 55 is a circuit diagram showing a configuration example of each driver circuit of the word line driver shown in FIG. 54. The schematic diagram of the redundancy system for demonstrating the semiconductor memory device concerning the 8th Embodiment of this invention. FIG. 57 is a circuit diagram showing a specific configuration example of a fuse latch circuit in the circuit shown in FIG. 56. The timing chart for demonstrating a fuse initialization signal. Schematic diagram of a redundancy system having a redundancy test function for testing whether or not a redundancy element is defective before a fuse blow. FIG. 3 is a schematic diagram showing two memory blocks extracted from a memory cell array in which a sense amplifier is shared by bit line pairs in adjacent memory blocks. The circuit diagram which shows the structural example of a fuse set selection signal generation circuit. The circuit diagram which shows the structural example of a fuse set selection circuit. FIG. 20 is a schematic diagram for explaining how to determine a relief area in a semiconductor memory device according to an eighth embodiment of the present invention. FIG. 4 is a schematic diagram for explaining the number of word lines that can simultaneously read / write independent data in a memory cell array in a hierarchical data line structure. The schematic diagram for demonstrating the data destruction by the indefinite cell on the word line activated first. FIG. 20 is a schematic diagram for explaining a semiconductor memory device according to a ninth embodiment of the invention. FIG. 24 is a schematic diagram showing a pattern layout of a ½ pitch cell array configuration of trench cells for explaining a semiconductor memory device according to a twenty-second embodiment of the present invention;

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Memory cell array 11-0 to 11-31 ... Array 11A, 11B ... Normal cell array unit 11A-0 to 11A-31, 11B-0 to 11B-31 ... Memory block 12 ... Array control circuit part 12-0 to 12- DESCRIPTION OF SYMBOLS 31 ... Array control circuit 13 ... Control signal wiring part 13-1 to 13-9 ... Signal line 14 ... Spare cell array 14A, 14B ... Spare memory block 20 ... Redundancy control signal output circuit 30 ... Memory cell array (or cell array unit)
DESCRIPTION OF SYMBOLS 31 ... Memory block 31AB ... Active memory block 31SB ... Sleep memory block 31_n, 31_n + 1, 31_n-1 ... Memory block 33 ... Row decoder part 33A ... Row decoder 34 ... Word line driver part 34A ... Word line driver 35, 35T, 35B, 35_n (t), 35_n (b) ... Array control circuit 36AS ... Active sense amplifier 36SS ... Sleep sense amplifier 36_n (t), 36_n (b) ... Sense amplifier 37 ... Peripheral circuit and redriver 38 ... WLDV driver 39 ... TWLOFF control Circuit 40 ... N / PSET driver 41 ... Sense amplifier (SA) control circuit 42 ... TWLON control circuit 43 ... Block selector 44 ... TRDE latch circuit 45 ... Sense amplifier (SA) latch circuit 46 ... TWLON latch H circuit 47 ... HIT control circuit 48 ... Latch circuit (BLKSEL latch circuit)
DESCRIPTION OF SYMBOLS 50 ... Redundancy control circuit 51 ... Redriver 52 ... bWLOFF latch circuit 53 ... Redriver 54 ... SAE latch circuit 55 ... Redriver 56 ... bRPRE latch circuit 57 ... X predecoder 80 ... Redundancy control circuit 81 ... Redriver 82 ... Redundancy control Circuit 83 ... WLON / OFF control circuit 84 ... Redriver 85 ... SAON / OFF control circuit 86 ... Redriver 87 ... bRPRE control circuit 88 ... X predecoder 89 ... X predecoder 90 ... STCRST control circuit 130 ... TRDE control circuit 131 ... HIT control circuit 166... Fuse latch circuit (FLATCHn)
167: Address comparator (ACOMPn)
168 ... Hit detector WL, WL_b ... Word line WL_a ... Spare word line BL / bBL ... Bit line pair BA ... Bank active command PR ... Bank precharge command WLE ... Word line status signal XBLKP, BLKSEL ... Array control circuit status signal bRDOUT (TWLON_n) ... Word line activation signal

Claims (11)

A semiconductor memory device having a function of activating a plurality of word lines connected to the same bit line via cell transistors together,
A column redundancy system that sets a column redundancy relief area based on a row address is provided.
The relief area is set so that the plurality of word lines activated together belong to the same relief area when the relief area is set so as to divide the bit line. .   2. The semiconductor memory device according to claim 1, wherein the relief area is set so that the number of linked partial relief areas constituting one relief area is minimized.   2. The semiconductor according to claim 1, wherein the relief area is set so that word lines that are activated together in the memory cell array and can read / write independent data simultaneously belong to the same relief area. Storage device. A column redundancy system that sets a column redundancy relief area based on a row address is provided.
A plurality of consecutive word line selection cycles under the condition that the scale of the column relief area is constant and each of the linked partial relief areas constituting one column relief area is constant or larger. In the semiconductor device, the relief region is set so that the number of word lines that can be activated together in the relief region is maximized in the operation mode in which the activated word line maintains its state. Storage device.   5. The semiconductor memory device according to claim 4, wherein the relief area is determined so that word lines that are activated together in the memory cell array and can simultaneously read / write independent data belong to the same relief area. . A column redundancy system that sets a column redundancy relief area based on a row address is provided.
When the relief area is set so as to divide the bit line, it is continuous under the condition that the size of the column relief area is constant and the number of relief areas dividing one bit line is constant or less. In a plurality of word line selection cycles, the relief area is set so that the number of word lines that can be activated together in the relief area is maximized in an operation mode in which the activated word line maintains its state. A semiconductor memory device.   7. The semiconductor memory device according to claim 6, wherein the relief area is determined so that word lines that are activated together in the memory cell array and can simultaneously read / write independent data belong to the same relief area. . A column redundancy system that sets a column redundancy relief area based on a row address is provided.
The size of the column relief area is constant, the scale of each of the linked partial relief areas constituting one column relief area is constant or larger, and the relief area for dividing one bit line Words that can be activated together in the relief region in an operation mode in which the activated word lines maintain their state in a plurality of successive word line selection cycles under the condition that the number is constant or less A semiconductor memory device, wherein a relief area is set so that the number of lines is maximized.   9. The semiconductor memory device according to claim 8, wherein the relief area is further determined such that word lines that are activated together in the memory cell array and capable of simultaneously reading / writing independent data belong to the same relief area. . A column redundancy system that sets a column redundancy relief area based on a row address is provided.
In a plurality of successive word line selection cycles, the relief area is set so that all of the word lines that can be activated together in the operation mode in which the activated word line maintains its state belong to the same relief area. A semiconductor memory device.   11. The semiconductor memory device according to claim 10, wherein the semiconductor memory device is assigned as a relief area setting row address in order from a higher address.

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