JP2007043847A - Dc-dc converter - Google Patents

Dc-dc converter Download PDF

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JP2007043847A
JP2007043847A JP2005226306A JP2005226306A JP2007043847A JP 2007043847 A JP2007043847 A JP 2007043847A JP 2005226306 A JP2005226306 A JP 2005226306A JP 2005226306 A JP2005226306 A JP 2005226306A JP 2007043847 A JP2007043847 A JP 2007043847A
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triangular wave
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JP4835064B2 (en
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Tomoki Nonaka
智己 野中
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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<P>PROBLEM TO BE SOLVED: To improve responsiveness by preventing the occurrence of overshooting to an output voltage even if a duty ratio is lowered to a prescribed value from a maximum value due to the abrupt change of a heavy load to a light load, in a step-down type DC-DC converter that PWM-controls a switching element. <P>SOLUTION: An error amplifier Q1 inputs an FB signal obtained by dividing the output voltage Vo by resistors R2, R3, and a reference voltage Vref; and outputs an output signal Verr (error voltage). A comparator Q2 compares the output signal Verr and a triangular wave voltage, and generates a pulse of a duty ratio corresponding to a level of the FB signal. The maximum value of the level of a control signal from the error amplifier Q1 is set to a prescribed level slightly higher than the maximum value of the level of the triangular wave voltage by a setting means 15, and an output MOS transistor Tr1 is PWM-controlled by a duty signal from the comparator Q2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、高い直流入力電圧から低い直流出力電圧を得る降圧型のＤＣ−ＤＣコンバータに関する。   The present invention relates to a step-down DC-DC converter that obtains a low DC output voltage from a high DC input voltage.

直流を任意の電圧の直流に変換（ＤＣ−ＤＣ変換）するＤＣ−ＤＣコンバータは、様々な電気・電子機器で使用され、昇圧型のＤＣ−ＤＣコンバータや降圧型のＤＣ−ＤＣコンバータなど、使用目的に応じたＤＣ−ＤＣコンバータが提案されている。図３はこのような従来の降圧型のＤＣ−ＤＣコンバータの回路構成図である。   DC-DC converters that convert direct current into direct current of any voltage (DC-DC conversion) are used in various electrical and electronic equipment, such as step-up DC-DC converters and step-down DC-DC converters. A DC-DC converter according to the purpose has been proposed. FIG. 3 is a circuit configuration diagram of such a conventional step-down DC-DC converter.

このＤＣ−ＤＣコンバータは、制御ＩＣ１内に構成されたエラーアンプ（誤差増幅器）Ｑ１、及びエラーアンプＱ１の出力信号Ｖｅｒｒ（誤差電圧）と三角波発生器１１からの１Ｖ〜２Ｖの三角波電圧（鋸歯状の電圧）を比較して出力ＭＯＳドライバ１２に出力ＭＯＳトランジスタの時比率（デューティ）を制御するデューティ（Ｄｕｔｙ）信号を出力するコンパレータＱ２と、エラーアンプＱ１に基準電圧Ｖｒｅｆ（１Ｖ）を入力する基準電圧発生器１３、及びエラーアンプＱ１に電源電圧ＶＲＥＧを供給する内部電源１４を有している。また、出力ＭＯＳドライバ１２により駆動される出力ＭＯＳトランジスタＴｒ１には入力電圧Ｖｃｃ（５Ｖ）が供給され、出力ＭＯＳトランジスタＴｒ１がスイッチング動作すると、転流ダイオード（フライホイールダイオード）Ｄ１、インダクタＬ１、平滑コンデンサＣ１により、負荷２に入力電圧Ｖｃｃより低い出力電圧Ｖｏが供給される。また、エラーアンプＱ１のＦＢ（フィードバック）信号が入力される反転入力端子と出力端子との間には、抵抗Ｒ１とコンデンサＣ２が位相補償素子として直列に接続され、負荷２にはスイッチＳＷ１が接続されている。   The DC-DC converter includes an error amplifier (error amplifier) Q1 configured in the control IC 1, an output signal Verr (error voltage) of the error amplifier Q1, and a triangular wave voltage (sawtooth shape) of 1V to 2V from the triangular wave generator 11. Comparator Q2 for outputting a duty signal for controlling the duty ratio of the output MOS transistor to the output MOS driver 12 and a reference for inputting the reference voltage Vref (1 V) to the error amplifier Q1. A voltage generator 13 and an internal power supply 14 for supplying a power supply voltage VREG to the error amplifier Q1 are provided. The output MOS transistor Tr1 driven by the output MOS driver 12 is supplied with the input voltage Vcc (5V), and when the output MOS transistor Tr1 performs a switching operation, a commutation diode (flywheel diode) D1, an inductor L1, a smoothing capacitor The output voltage Vo lower than the input voltage Vcc is supplied to the load 2 by C1. In addition, a resistor R1 and a capacitor C2 are connected in series as a phase compensation element between an inverting input terminal to which an FB (feedback) signal of the error amplifier Q1 is input and an output terminal, and a switch SW1 is connected to the load 2. Has been.

上記エラーアンプＱ１は、出力電圧Ｖｏを抵抗Ｒ２とＲ３で分圧したＦＢ信号と基準電圧Ｖｒｅｆを比較し、ＦＢ信号が基準電圧Ｖｒｅｆより低い場合は高い方向、逆に高い場合は低い方向に出力信号Ｖｅｒｒを制御する。この出力信号ＶｅｒｒはコンパレータＱ２に入力されて、制御ＩＣ１内部で生成された三角波電圧と比較され、出力ＭＯＳトランジスタＴｒ１のオン（ＯＮ）、オフ（ＯＦＦ）のデューティ比が決定される。このとき、エラーアンプＱ１の電源電圧として、負側（Ｖ−）が０Ｖ（ＧＮＤ）、正側（Ｖ＋）がＶＲＥＧ（３Ｖ）の電圧が与えられているため、エラーアンプＱ１の出力信号Ｖｅｒｒは０Ｖ〜３Ｖまで変化し、出力電圧Ｖｏが設定出力電圧よりも高い場合には０Ｖに近づき、逆に低い場合にはＶＲＥＧ（３Ｖ）に近づく。   The error amplifier Q1 compares the FB signal obtained by dividing the output voltage Vo with the resistors R2 and R3 with the reference voltage Vref, and outputs the signal in the higher direction when the FB signal is lower than the reference voltage Vref, and conversely when it is higher. The signal Verr is controlled. This output signal Verr is input to the comparator Q2 and compared with the triangular wave voltage generated inside the control IC1, and the duty ratio of ON (ON) and OFF (OFF) of the output MOS transistor Tr1 is determined. At this time, as the power supply voltage of the error amplifier Q1, since the negative side (V−) is 0V (GND) and the positive side (V +) is VREG (3V), the output signal Verr of the error amplifier Q1 is When the output voltage Vo is higher than the set output voltage, the voltage approaches 0V, and conversely, when the output voltage Vo is low, the voltage approaches VREG (3V).

図４は図３の各部の出力波形を示す図である。ここでは、負荷電流Ｉｏ（Ａ）と、エラーアンプＱ１の出力信号Ｖｅｒｒ（Ｖ）と、出力電圧Ｖｏ（Ｖ）を示している。エラーアンプＱ１の出力信号Ｖｅｒｒに関するグラフ中に記してある２−αは、三角波電圧の最大値が２Ｖであるので、ＤＣ−ＤＣコンバータが平衡状態となっているときはエラーアンプＱ１の出力信号Ｖｅｒｒがそれ以下の電圧となることを示している。そして、出力電圧Ｖｏとして例えば４．８Ｖが得られ、負荷２に１〜０Ａの負荷電流Ｉｏが流れる。   FIG. 4 is a diagram showing output waveforms of respective parts in FIG. Here, the load current Io (A), the output signal Verr (V) of the error amplifier Q1, and the output voltage Vo (V) are shown. Since 2-α shown in the graph relating to the output signal Verr of the error amplifier Q1 has a maximum triangular wave voltage value of 2V, the output signal Verr of the error amplifier Q1 when the DC-DC converter is in a balanced state. Indicates that the voltage is lower than that. For example, 4.8 V is obtained as the output voltage Vo, and a load current Io of 1 to 0 A flows through the load 2.

また、出力電圧が出力上限電圧を上回ったときにエラーアンプの出力信号Ｖｅｒｒを、出力電圧を低下させる電圧に強制的に変化させるようにした降圧型のＤＣ−ＤＣコンバータも提案されている（例えば特許文献１参照）。これは、目標電圧より所定の電圧だけ高い出力上限電圧を設定し、この出力上限電圧と出力電圧を比較して、出力電圧が出力上限電圧より高い場合に、出力電圧を低下させるようにエラーアンプの出力を強制的に変更するものである。
特開２００４−５６９９２号公報（段落番号〔０００９〕，〔００４１〕〜〔００４６〕，〔００９７〕，図４，図５） A step-down DC-DC converter is also proposed in which the output signal Verr of the error amplifier is forcibly changed to a voltage that lowers the output voltage when the output voltage exceeds the output upper limit voltage (for example, Patent Document 1). This is an error amplifier that sets an output upper limit voltage that is higher than the target voltage by a predetermined voltage, compares this output upper limit voltage with the output voltage, and lowers the output voltage when the output voltage is higher than the output upper limit voltage. The output of is forcibly changed.
JP 2004-56992 A (paragraph numbers [0009], [0041] to [0046], [0097], FIGS. 4 and 5)

しかしながら、上記のような従来の降圧型のＤＣ−ＤＣコンバータにおいては、設定出力電圧が入力電圧Ｖｃｃとほぼ等しい場合、あるいは設定出力電圧が入力電圧Ｖｃｃより若干低く負荷が重い場合、エラーアンプＱ１の出力信号Ｖｅｒｒが正側（Ｖ＋）の電源電圧ＶＲＥＧに振り切れ、出力ＭＯＳトランジスタＴｒ１のデューティ比が１００％となることがある。特に後者の場合、負荷が重い状態（１Ａ）から急激に軽い状態（０Ａ）に移ると、負荷が軽くなった分出力電圧Ｖｏが上昇し（ΔＶ）、エラーアンプＱ１の出力も平衡条件（所定のデューティ比を実現するレベル＝２−α（Ｖ））になるまで低下する。このとき、出力信号Ｖｅｒｒは重負荷（１Ａ）時にはＶＲＥＧ（３Ｖ）であり、軽負荷（０Ａ）となり、デューティ比をコントロール可能なレベル（三角波の最大電圧＝２Ｖ以下）に低下するまである程度の時間（制御不能時間＝Δｔ）が必要となる。この間はデューティ比が１００％のままであり、出力電圧Ｖｏが設定出力電圧よりも高くなる、いわゆるオーバーシュート（ΔＶ）を生じた状態となる。   However, in the conventional step-down DC-DC converter as described above, when the set output voltage is substantially equal to the input voltage Vcc, or when the set output voltage is slightly lower than the input voltage Vcc and the load is heavy, the error amplifier Q1 In some cases, the output signal Verr is completely swung to the positive side (V +) power supply voltage VREG, and the duty ratio of the output MOS transistor Tr1 becomes 100%. Particularly in the latter case, when the load is changed from a heavy state (1A) to a light state (0A) suddenly, the output voltage Vo rises (ΔV) as the load is reduced, and the output of the error amplifier Q1 is also balanced (predetermined). The level decreases to a level that realizes a duty ratio of (2−α (V)). At this time, the output signal Verr is VREG (3 V) at the time of heavy load (1 A), becomes light load (0 A), and it takes a certain amount of time until the duty ratio is lowered to a level where the duty ratio can be controlled (maximum voltage of triangular wave = 2 V or less). (Uncontrollable time = Δt) is required. During this time, the duty ratio remains 100%, and the output voltage Vo becomes higher than the set output voltage, so-called overshoot (ΔV) occurs.

また、前者の場合でも、設定出力電圧を急激に下げても同様にデューティ比をコントロール可能なレベルになるまで時間を要し、応答性が悪いという問題がある。
また、出力電圧Ｖｏが出力上限電圧を上回ったときにエラーアンプＱ１の出力を、出力電圧Ｖｏを低下させる電圧に強制的に変化させる場合でも、負荷が急に軽くなっても出力電圧Ｖｏが出力電源電圧を上回るまで待つ必要があるとともに、エラーアンプＱ１が通常動作に戻るときに不具合が起こる可能性がある。すなわち、誤差電圧の初期値が電源電圧まで上がりきっていると、出力電圧Ｖｏが出力上限電圧を下回っても、誤差電圧がまだ三角波の最大値を上回っている可能性があり、その場合、また出力電圧Ｖｏが上昇してしまう。 Further, even in the former case, there is a problem that even if the set output voltage is suddenly lowered, it takes time until the duty ratio can be controlled to a level that is similarly controllable, and the response is poor.
Even when the output of the error amplifier Q1 is forcibly changed to a voltage that lowers the output voltage Vo when the output voltage Vo exceeds the output upper limit voltage, the output voltage Vo is output even if the load suddenly becomes lighter. There is a need to wait until the power supply voltage is exceeded, and a malfunction may occur when the error amplifier Q1 returns to normal operation. That is, if the initial value of the error voltage has risen to the power supply voltage, even if the output voltage Vo falls below the output upper limit voltage, the error voltage may still exceed the maximum value of the triangular wave. The output voltage Vo will rise.

本発明は、このような点に鑑みてなされたものであり、重負荷から軽負荷へ負荷状態が急変してデューティ比が最大値から所定値に下がる場合でも出力電圧にオーバーシュートが発生するのを抑制でき、目標電圧を急に下げた場合でも応答性が良く、また、出力電圧の変動が小さく、過電圧がなく、付属・周辺デバイスの信頼性が向上したＤＣ−ＤＣコンバータを提供することを目的とする。   The present invention has been made in view of such a point, and even when the load state suddenly changes from a heavy load to a light load and the duty ratio falls from the maximum value to a predetermined value, an overshoot occurs in the output voltage. To provide a DC-DC converter that has good responsiveness even when the target voltage is suddenly lowered, has small fluctuations in output voltage, no overvoltage, and improved reliability of attached and peripheral devices. Objective.

本発明では上記課題を解決するために、入力された直流電圧が供給されるスイッチング素子をパルス幅変調制御して前記入力電圧より低い直流電圧を出力する降圧型のＤＣ−ＤＣコンバータにおいて、出力電圧のフィードバック信号と基準電圧を比較して誤差電圧を出力するエラーアンプと、前記誤差電圧と三角波電圧を比較して前記スイッチング素子のオン時間とオフ時間のデューティ比を決定するコンパレータと、前記誤差電圧の最大値を前記三角波電圧の最大値より僅かに高い所定のレベルに設定する設定手段と、を備えたことを特徴とするＤＣ−ＤＣコンバータが提供される。   In order to solve the above-described problem, the present invention provides a step-down DC-DC converter that outputs a DC voltage lower than the input voltage by performing pulse width modulation control on a switching element to which the input DC voltage is supplied. An error amplifier that compares the feedback signal with a reference voltage and outputs an error voltage; a comparator that compares the error voltage with a triangular wave voltage to determine a duty ratio between the on time and the off time of the switching element; and the error voltage There is provided a DC-DC converter comprising: setting means for setting the maximum value of the signal to a predetermined level slightly higher than the maximum value of the triangular wave voltage.

このようなＤＣ−ＤＣコンバータによれば、重負荷から軽負荷へ負荷状態が急変してデューティ比が最大値から所定値に下がる場合でも出力電圧にオーバーシュートが発生するのを抑制でき、目標電圧を急に下げた場合でも応答性が良く、また、出力電圧の変動が小さく、過電圧がなく、付属・周辺デバイスの信頼性が向上する。   According to such a DC-DC converter, it is possible to suppress the occurrence of overshoot in the output voltage even when the load state suddenly changes from a heavy load to a light load and the duty ratio falls from the maximum value to a predetermined value. Even if the voltage is suddenly lowered, the response is good, the fluctuation of the output voltage is small, there is no overvoltage, and the reliability of attached and peripheral devices is improved.

本発明のＤＣ−ＤＣコンバータは、負荷状態が急変した場合でもＦＢ信号の変化が僅かであり、重負荷から軽負荷へ負荷状態が急変してデューティ比が最大値から所定値に下がる場合でも出力電圧にオーバーシュートが発生するのを抑制でき、目標電圧を急に下げた場合でも応答性が良く、また、出力電圧の変動が小さく、過電圧がなく、付属・周辺デバイスの信頼性が向上するという利点がある。   In the DC-DC converter of the present invention, even when the load state suddenly changes, the FB signal changes little, and even when the load state suddenly changes from heavy load to light load and the duty ratio falls from the maximum value to the predetermined value, the output is performed. Overshoot can be suppressed in the voltage, responsiveness is good even when the target voltage is suddenly lowered, output voltage fluctuation is small, there is no overvoltage, and the reliability of attached and peripheral devices is improved There are advantages.

以下、本発明の実施の形態を図面を参照して説明する。
図１は本発明の実施の形態のＤＣ−ＤＣコンバータの回路構成図であり、図３と同一符号は同一構成要素を示している。このＤＣ−ＤＣコンバータは、入力された直流電圧が供給されるスイッチング素子をＰＷＭ（パルス幅変調）制御して入力電圧より低い直流電圧を出力する降圧型のＤＣ−ＤＣコンバータであり、スイッチング素子としてＭＯＳＦＥＴを使用している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit configuration diagram of a DC-DC converter according to an embodiment of the present invention. The same reference numerals as those in FIG. 3 denote the same components. This DC-DC converter is a step-down DC-DC converter that outputs a DC voltage lower than the input voltage by PWM (pulse width modulation) control of a switching element to which an input DC voltage is supplied. MOSFET is used.

制御ＩＣ１内には、エラーアンプＱ１とコンパレータＱ２が構成されており、コンパレータＱ２からのデューティ信号によりスイッチング素子である出力ＭＯＳトランジスタＴｒ１がＰＷＭ制御される。このとき、エラーアンプＱ１は、出力電圧Ｖｏを抵抗Ｒ２とＲ３で分圧したＦＢ信号と基準電圧Ｖｒｅｆが入力され、出力信号Ｖｅｒｒ（誤差電圧）を出力する。コンパレータＱ２は、その出力信号Ｖｅｒｒと三角波電圧を比較して、ＦＢ信号のレベルに応じたデューティ比のパルスを生成する。すなわち、出力ＭＯＳトランジスタＴｒ１のオン時間とオフ時間のデューティ比を決定する。また、設定手段１５により、上記エラーアンプＱ１からの制御信号のレベルの最大値を三角波電圧のレベルの最大値より僅かに高い所定のレベルに設定する。   The control IC 1 includes an error amplifier Q1 and a comparator Q2, and the output MOS transistor Tr1, which is a switching element, is PWM-controlled by a duty signal from the comparator Q2. At this time, the error amplifier Q1 receives the FB signal obtained by dividing the output voltage Vo by the resistors R2 and R3 and the reference voltage Vref, and outputs an output signal Verr (error voltage). The comparator Q2 compares the output signal Verr and the triangular wave voltage, and generates a pulse having a duty ratio corresponding to the level of the FB signal. That is, the duty ratio between the ON time and the OFF time of the output MOS transistor Tr1 is determined. Further, the setting means 15 sets the maximum value of the level of the control signal from the error amplifier Q1 to a predetermined level slightly higher than the maximum value of the triangular wave voltage level.

図２は本実施の形態のＤＣ−ＤＣコンバータの設定手段１５の構成図である。このＤＣ−ＤＣコンバータは、上記三角波電圧の上限レベルと下限レベルを設定する複数の抵抗Ｒ１１，Ｒ１２，Ｒ１３の直列回路を有し、抵抗Ｒ１１は抵抗Ｒ１１１とＲ１１２に分割されている。設定手段１５は、この直列回路に接続された抵抗Ｒ１１１とＲ１１２によって分圧した電圧を、上述の三角波電圧のレベルの最大値より僅かに高い所定のレベルとしている。   FIG. 2 is a configuration diagram of the setting means 15 of the DC-DC converter of the present embodiment. This DC-DC converter has a series circuit of a plurality of resistors R11, R12, R13 for setting the upper limit level and the lower limit level of the triangular wave voltage, and the resistor R11 is divided into resistors R111 and R112. The setting means 15 sets the voltage divided by the resistors R111 and R112 connected to the series circuit to a predetermined level slightly higher than the maximum value of the triangular wave voltage level.

すなわち、三角波発生器１１から出力される三角波電圧の上限レベルと下限レベルの決定に、三つの抵抗Ｒ１１，Ｒ１２，Ｒ１３による分圧方式を用いており、本実施の形態では、内部電源１４に最も近い抵抗Ｒ１１を抵抗Ｒ１１１とＲ１１２に分割し、その分割点から取り出した電圧をバッファアンプＱ１１を通してエラーアンプＱ１の正側の電源電圧として供給している。この電圧レベルは、三角波電圧の上限レベル（２Ｖ）よりも僅かに高いレベル（この例では２．１Ｖ）に設定している。このため、前述のように設定出力電圧が入力電圧より若干低く、重負荷から軽負荷へ急激に変化した場合でも、エラーアンプＱ１より出力されるＦＢ信号に応じた制御信号の変化が２．１Ｖから（２−α）Ｖまでの僅か０．１Ｖ強の変化となるため、出力電圧が非常に早く設定電圧に制御される。   That is, a voltage dividing method using three resistors R11, R12, and R13 is used to determine the upper limit level and the lower limit level of the triangular wave voltage output from the triangular wave generator 11, and in this embodiment, the internal power supply 14 is the most. The near resistor R11 is divided into resistors R111 and R112, and the voltage extracted from the dividing point is supplied as the power supply voltage on the positive side of the error amplifier Q1 through the buffer amplifier Q11. This voltage level is set to a level (2.1 V in this example) slightly higher than the upper limit level (2 V) of the triangular wave voltage. For this reason, even when the set output voltage is slightly lower than the input voltage and suddenly changes from a heavy load to a light load as described above, the change in the control signal according to the FB signal output from the error amplifier Q1 is 2.1 V. The output voltage is controlled to the set voltage very quickly because the change is a little over 0.1V from to (2-α) V.

このように、本実施の形態では、エラーアンプＱ１からの制御信号のレベルの最大値を三角波電圧のレベルの最大値より僅かに高い所定のレベルに設定しているので、ＦＢ信号レベルが最大になるときの、ＦＢ信号レベルと三角波電圧の最大値の差が非常に小さくなり、出力電圧が非常に早く設定電圧に制御される。   As described above, in this embodiment, the maximum value of the level of the control signal from the error amplifier Q1 is set to a predetermined level slightly higher than the maximum value of the triangular wave voltage level, so that the FB signal level is maximized. The difference between the FB signal level and the maximum value of the triangular wave voltage becomes very small, and the output voltage is controlled to the set voltage very quickly.

このため、重負荷から軽負荷へ負荷状態が急変してデューティ比が最大値から所定値に下がる場合でも出力電圧にオーバーシュートが発生するのを抑制でき、目標電圧を急に下げた場合でも応答性が良く、また、出力電圧の変動が小さく、過電圧がなく、付属・周辺デバイスの信頼性が向上する。   For this reason, even if the load condition suddenly changes from heavy load to light load and the duty ratio falls from the maximum value to the predetermined value, it is possible to suppress the occurrence of overshoot in the output voltage, and even if the target voltage is suddenly lowered, the response In addition, the output voltage fluctuation is small, there is no overvoltage, and the reliability of attached and peripheral devices is improved.

本発明の実施の形態のＤＣ−ＤＣコンバータの回路構成図である。It is a circuit block diagram of the DC-DC converter of embodiment of this invention. 実施の形態のＤＣ−ＤＣコンバータの設定手段の構成図である。It is a block diagram of the setting means of the DC-DC converter of embodiment. 従来のＤＣ−ＤＣコンバータの回路構成図である。It is a circuit block diagram of the conventional DC-DC converter. 図３の各部の出力波形を示す図である。It is a figure which shows the output waveform of each part of FIG.

符号の説明Explanation of symbols

１ 制御ＩＣ
２ 負荷
１１ 三角波発生器
１２ 出力ＭＯＳドライバ
１３ 基準電圧発生器
１４ 内部電源
１５ 設定手段
Ｃ１ 平滑コンデンサ
Ｃ２ コンデンサ
Ｄ１ 転流ダイオード
Ｌ１ インダクタ
Ｑ１ エラーアンプ
Ｑ２ コンパレータ
Ｑ１１ バッファアンプ
Ｒ１，Ｒ２，Ｒ３，Ｒ１１，Ｒ１２，Ｒ１３，Ｒ１１１，Ｒ１１２ 抵抗
Ｔｒ１ 出力ＭＯＳトランジスタ
1 Control IC
2 Load 11 Triangular wave generator 12 Output MOS driver 13 Reference voltage generator 14 Internal power supply 15 Setting means C1 Smoothing capacitor C2 Capacitor D1 Commutation diode L1 Inductor Q1 Error amplifier Q2 Comparator Q11 Buffer amplifier R1, R2, R3, R11, R12, R13, R111, R112 Resistor Tr1 Output MOS transistor

Claims (3)

入力された直流電圧が供給されるスイッチング素子をパルス幅変調制御して前記入力電圧より低い直流電圧を出力する降圧型のＤＣ−ＤＣコンバータにおいて、
出力電圧のフィードバック信号と基準電圧を比較して誤差電圧を出力するエラーアンプと、前記誤差電圧と三角波電圧を比較して前記スイッチング素子のオン時間とオフ時間のデューティ比を決定するコンパレータと、
前記誤差電圧の最大値を前記三角波電圧の最大値より僅かに高い所定のレベルに設定する設定手段と、を備えたことを特徴とするＤＣ−ＤＣコンバータ。 In a step-down DC-DC converter that outputs a DC voltage lower than the input voltage by performing pulse width modulation control on a switching element to which an input DC voltage is supplied,
An error amplifier that compares the feedback signal of the output voltage with a reference voltage and outputs an error voltage; a comparator that compares the error voltage with a triangular wave voltage to determine the duty ratio of the on-time and off-time of the switching element;
A DC-DC converter comprising: setting means for setting the maximum value of the error voltage to a predetermined level slightly higher than the maximum value of the triangular wave voltage. 前記三角波電圧の上限レベルと下限レベルを設定する複数の抵抗の直列回路を有し、
前記設定手段は、前記直列回路に接続された抵抗によって分圧した電圧を前記所定のレベルとすることを特徴とする請求項１記載のＤＣ−ＤＣコンバータ。 A series circuit of a plurality of resistors for setting an upper limit level and a lower limit level of the triangular wave voltage;
2. The DC-DC converter according to claim 1, wherein the setting means sets the voltage divided by a resistor connected to the series circuit to the predetermined level. 前記所定のレベルを前記エラーアンプの電源電圧とすることを特徴とする請求項１または２記載のＤＣ−ＤＣコンバータ。
3. The DC-DC converter according to claim 1, wherein the predetermined level is a power supply voltage of the error amplifier.
JP2005226306A 2005-08-04 2005-08-04 DC-DC converter Expired - Fee Related JP4835064B2 (en)

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JPH11214971A (en) * 1998-01-22 1999-08-06 Rohm Co Ltd Pulse generation circuit having duty factory limiting function and dc/dc converter
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JP2004056992A (en) * 2002-05-28 2004-02-19 Matsushita Electric Ind Co Ltd Dc-dc converter

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008119264A1 (en) * 2007-03-30 2008-10-09 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Feedback controller having multiple feedback paths
AT506273B1 (en) * 2007-12-20 2012-03-15 Siemens Ag METHOD FOR OPERATING A SWITCHING TRANSFORMER
US8416589B2 (en) 2007-12-20 2013-04-09 Siemens Aktiengesellschaft Method for operating a DC-DC converter in current-mode control
JP2011045216A (en) * 2009-08-24 2011-03-03 New Japan Radio Co Ltd Switching power supply
CN102437771A (en) * 2011-11-28 2012-05-02 联合汽车电子有限公司 Passive discharging circuit of inverter input terminal
JP2015515172A (en) * 2012-02-24 2015-05-21 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Method and apparatus for load switch controller
KR101413213B1 (en) 2012-11-05 2014-08-06 현대모비스 주식회사 Vehicle Buck Converter Control Method and Apparatus
CN104901523A (en) * 2015-06-16 2015-09-09 矽力杰半导体技术(杭州)有限公司 Control circuit based on ripple control, control method based on ripple control, and switching power supply

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