JP2007043115A - Semiconductor device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a barrier property is improved; a compact size, a thin shape, and lightweight are achieved; and flexibility is provided. <P>SOLUTION: By providing a stacked body including a plurality of transistors in a space between a pair of substrates, a semiconductor device is provided in which a harmful substance is prevented from entering and a barrier property is improved. In addition, by using a pair of substrates which are thin-filmed by performing grinding and polishing, a semiconductor device is provided in which a compact size, a thin shape, and lightweight are achieved. Further, a semiconductor device is provided in which flexibility is provided and a high-added value is achieved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device corresponds to a transistor including a transistor.

Development of semiconductor devices including transistors is in progress. Among such semiconductor devices, development of a semiconductor device capable of transmitting and receiving data in a contactless manner is being actively promoted. Such a semiconductor device is called an RFID (Radio Frequency IDentification), an RF chip, an RF tag, an IC chip, an IC tag, an IC label, a wireless chip, a wireless tag, an electronic chip, an electronic tag, a wireless processor, a wireless memory, or the like. (For example, refer to Patent Document 1), introduction has already begun in some fields.
JP 2004-282050 A

An object of the present invention is to provide a semiconductor device in which reliability is improved by improving barrier properties.

Another object of the present invention is to provide a semiconductor device that realizes high added value by realizing miniaturization, thinning, and weight reduction.

Furthermore, an object of the present invention is to provide a semiconductor device that realizes high added value by providing flexibility.

The present invention is characterized in that a stacked body including a plurality of transistors is provided in a space inside a pair of substrates. With the above characteristics, entry of harmful substances can be suppressed and barrier properties can be improved. Since the pair of substrates are excellent in shielding harmful substances that enter from the outside, the barrier property can be improved. Moreover, reliability can be improved by improving barrier property.

In addition, the present invention is characterized by using a pair of substrates that are thinned (thinned) by grinding and polishing. With the above characteristics, a semiconductor device that is reduced in size, thickness, and weight can be provided.

In addition, the present invention can provide flexibility and realize high added value. Such flexibility is an added value realized by thinning the substrate.

A semiconductor device of the present invention includes a transistor provided over a first substrate, a first insulating layer provided over the transistor, and an opening provided in the first insulating layer. Or a first conductive layer (corresponding to a source wiring or a drain wiring) electrically connected to the drain, a second insulating layer provided over the first conductive layer, and a second insulating layer. A second substrate. The transistor includes a semiconductor layer, an insulating layer (corresponding to a gate insulating layer), and a conductive layer (corresponding to a gate electrode).

A semiconductor device of the present invention includes a transistor provided over a first substrate, a first insulating layer provided over the transistor, and an opening provided in the first insulating layer. Alternatively, a first conductive layer (corresponding to a source wiring or a drain wiring) electrically connected to the drain, a second insulating layer provided on the first conductive layer, and a second insulating layer are provided. A second conductive layer electrically connected to the first conductive layer through the opening, a third insulating layer provided on the second conductive layer, and on the third insulating layer And a second substrate provided. The transistor includes a semiconductor layer, an insulating layer (corresponding to a gate insulating layer), and a conductive layer (corresponding to a gate electrode).

A semiconductor device of the present invention is provided over one surface of a first substrate, and includes a transistor including a semiconductor layer, a first insulating layer, and a first conductive layer, and a second insulating layer provided over the transistor. And a second conductive layer electrically connected to the source or drain of the transistor through an opening provided in the second insulating layer, and the same layer as the first conductive layer or the second conductive layer A first terminal portion provided on the second insulating layer, a third insulating layer provided on the second insulating layer and the second conductive layer, a second substrate provided on the third insulating layer, 3 substrate, a third conductive layer provided on one surface of the third substrate, a second terminal portion provided in the same layer as the third conductive layer, and the other of the first substrate And a fourth conductive layer provided on the surface.

In the semiconductor device having the above structure, the fourth conductive layer is electrically connected to the first terminal portion through an opening provided in the first substrate and the second insulating layer. The second terminal portion is electrically connected to the fourth conductive layer through one or both of the anisotropic conductive layer and the bump. The other surface of the first substrate and the one surface of the third substrate are provided to face each other. The first terminal portion and the second terminal portion are provided so as to overlap each other.

A semiconductor device of the present invention is provided over a first substrate and includes a transistor including a semiconductor layer, a first insulating layer, and a first conductive layer, a second insulating layer provided over the transistor, The second conductive layer electrically connected to the source or drain of the transistor through the opening provided in the insulating layer and the same layer as the first conductive layer or the second conductive layer The first terminal portion, the second insulating layer, the third insulating layer provided on the second conductive layer, and the second substrate provided so that one surface is in contact with the third insulating layer A third substrate; a third conductive layer provided on one surface of the third substrate; a second terminal portion provided in the same layer as the third conductive layer; A fourth conductive layer is provided on the other surface of the substrate.

In the semiconductor device having the above structure, the fourth conductive layer is electrically connected to the first terminal portion through an opening provided in the second substrate and the third insulating layer. The second terminal portion is electrically connected to the fourth conductive layer via one or both of the anisotropic conductive layer and the bump. The other surface of the second substrate and the one surface of the third substrate are provided to face each other. The first terminal portion and the second terminal portion are provided so as to overlap each other.

In the semiconductor device having the above structure, each of the first substrate and the second substrate is a glass substrate. In addition, the thickness of each of the first substrate and the second substrate is 100 μm or less. In addition, the thickness of each of the first substrate and the second substrate is 50 μm or less. The thickness of each of the first substrate and the second substrate is 2 μm or more.

In the semiconductor device having the above structure, a sealing material is provided between the first substrate and the second substrate. In the semiconductor device having the above structure, a spacer is provided between the first substrate and the second substrate.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a transistor over one surface of a first substrate, a step of forming a first insulating layer over the transistor, and a first insulating layer. Forming a first conductive layer electrically connected to the source or drain of the transistor through the opening; forming a second insulating layer on the first conductive layer; A step of providing a second substrate on the second insulating layer so that the surface of the insulating layer and one surface of the second substrate are in contact with each other; the other surface of the first substrate and the other surface of the second substrate; Grinding the surface, polishing the other surface of the ground first substrate and the other surface of the second substrate, the first substrate, the first insulating layer, the second insulating layer, and the first And cutting the second substrate to form a stacked body including the first substrate, the transistor, and the second substrate.

In addition to the above steps, a transistor includes a step of forming a semiconductor layer, an insulating layer (corresponding to a gate insulating layer), and a conductive layer (corresponding to a gate electrode).

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a transistor over one surface of a first substrate, a step of forming a first insulating layer over the transistor, and a first insulating layer. Forming a first conductive layer electrically connected to the source or drain of the transistor through the opening; forming a second insulating layer on the first conductive layer; Forming a second conductive layer electrically connected to the first conductive layer through an opening provided in the insulating layer; and forming a third insulating layer on the second conductive layer A step of providing a second substrate on the third insulating layer such that the surface of the third insulating layer and one surface of the second substrate are in contact with each other; A step of performing grinding or polishing of the other surface of the two substrates, a first substrate, a first insulating layer, and a second insulating layer By cutting the third insulating layer and a second substrate having a first substrate, forming a laminate comprising a transistor and a second substrate.

In addition to the above steps, a transistor includes a step of forming a semiconductor layer, an insulating layer (corresponding to a gate insulating layer), and a conductive layer (corresponding to a gate electrode).

A method for manufacturing a semiconductor device of the present invention includes a step of forming a transistor including a semiconductor layer, a first insulating layer, and a first conductive layer over one surface of a first substrate, and a second step over the transistor. A step of forming an insulating layer; a second conductive layer electrically connected to a source or a drain of the transistor through an opening provided in the second insulating layer; and the same layer as the second conductive layer Forming a first terminal portion provided on the second insulating layer, forming a third insulating layer on the second insulating layer, the second conductive layer, and the first terminal portion; and a third insulating layer Providing a second substrate on the third insulating layer so that the surface of the first substrate and one surface of the second substrate are in contact with each other; and the other surface of the first substrate and the other surface of the second substrate A step of performing one or both of grinding and polishing, and a third conductive layer that overlaps the first terminal portion on the other surface of the first substrate. A step of irradiating the third conductive layer with a laser beam to form an opening that exposes the first terminal portion and filling the opening with the third conductive layer; The third surface provided with the other surface of the first substrate, the second terminal portion, and the fourth conductive layer so that the third conductive layer and the second terminal portion are electrically connected. And a step of providing a third substrate so that one surface of the substrate faces.

A method for manufacturing a semiconductor device of the present invention includes a step of forming a transistor including a semiconductor layer, a first insulating layer, and a first conductive layer over one surface of a first substrate, and a second step over the transistor. A step of forming an insulating layer; a second conductive layer electrically connected to a source or a drain of the transistor through an opening provided in the second insulating layer; and the same layer as the second conductive layer Forming a first terminal portion provided on the second insulating layer, forming a third insulating layer on the second insulating layer, the second conductive layer, and the first terminal portion; and a third insulating layer Providing a second substrate on the third insulating layer so that the surface of the first substrate and one surface of the second substrate are in contact with each other; and the other surface of the first substrate and the other surface of the second substrate A step of performing one or both of grinding and polishing, and a third conductive layer overlapping the first terminal portion on the other surface of the second substrate. A step of irradiating the third conductive layer with a laser beam to form an opening that exposes the first terminal portion, and filling the opening with the third conductive layer; The third surface provided with the second surface of the second substrate, the second terminal portion, and the fourth conductive layer so that the third conductive layer and the second terminal portion are electrically connected. And a step of providing a third substrate so that one surface of the substrate faces.

In the above method for manufacturing a semiconductor device of the present invention, the other surface of the first substrate and the other surface of the second substrate are ground until the thickness of the first substrate and the second substrate becomes 100 μm or less. To do. Further, the other surface of the ground first substrate and the other surface of the second substrate are polished until the thickness of the first substrate and the second substrate becomes 50 μm or less.

According to the present invention, it is possible to prevent entry of a harmful substance into an element between a pair of substrates, and it is possible to suppress element deterioration and element destruction. Therefore, reliability can be improved. In addition, since a thinned (thinned) substrate is used by grinding and polishing, a semiconductor device that is reduced in size, thickness, and weight can be provided. In addition, since a thinned (thinned) substrate is used, flexibility can be provided and high added value can be realized.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
A semiconductor device of the present invention will be described with reference to cross-sectional views of FIGS. 1, 2, and 3A and top views of FIGS. FIGS. 1 and 2A correspond to a top view of FIG. 3B, and FIG. 2B corresponds to a cross-sectional view from point A to point C in the top view of FIG.

First, the insulating layer 11 is formed on one surface of the substrate 10 (see FIG. 1). The substrate 10 corresponds to a glass substrate, a plastic substrate, a silicon substrate, a quartz substrate, or the like. Preferably, a glass substrate or a plastic substrate is used as the substrate 10. This is because it is easy to produce a glass substrate or a plastic substrate having a side of 1 meter or more, and it is easy to produce a substrate having a desired shape such as a square shape. Therefore, for example, when a glass substrate or a plastic substrate having a square shape and one side of 1 meter or more is used, productivity can be significantly improved. Such an advantage is a great advantage as compared with the case of using a circular silicon substrate having a diameter of about 30 cm at the maximum.

Note that a barrier film may be provided only on one surface of the substrate 10 or on the entire substrate 10. As the barrier film, Al ₂ O ₃ , MgO, SiO ₂ , SiOx (x is 0 or more), Al, SiNx (x is 0 or more), SiOxNy (x, y is 0 or more), or the like may be used. By providing the barrier film, diffusion of harmful substances included in the substrate 10 can be prevented. When a plastic substrate is used, a substrate using a material in which glass and plastic are mixed may be used, or a substrate in which a layer made of glass and a layer made of plastic are stacked may be used.

The insulating layer 11 is formed of silicon oxide, silicon nitride, silicon oxide containing nitrogen, silicon nitride containing oxygen, or the like by plasma CVD, sputtering, or the like. The insulating layer 11 serves to prevent the impurity element from the substrate 10 from entering the upper layer. The insulating layer 11 may not be formed if it is not necessary.

Next, a plurality of transistors 14 are formed over the insulating layer 11. Here, a plurality of thin film transistors are formed as the plurality of transistors 14. Each of the plurality of transistors 14 includes a semiconductor layer 50, a gate insulating layer (also referred to as an insulating layer) 51, and a conductive layer 52 that is a gate (also referred to as a gate electrode). The semiconductor layer 50 includes impurity regions 53 and 55 that function as a source (also referred to as a source electrode or a source region) or a drain (also referred to as a drain electrode or a drain region), and a channel formation region 54. An impurity element imparting N-type or P-type is added to the impurity regions 53 and 55. Specifically, an impurity element imparting N-type (for example, phosphorus (P) or arsenic (As)) and an impurity element imparting P-type (for example, boron (B)) are added. The impurity region 55 is an LDD (Lightly Doped Drain) region.

In the illustrated configuration, each of the plurality of transistors 14 has a sidewall 44 provided so as to be in contact with the side surface of the conductive layer 52. The sidewall 44 is used as a mask for doping when forming the LDD region. In each of the plurality of transistors 14, a gate insulating layer 51 is provided on the semiconductor layer 50, a top gate type in which a conductive layer 52 is provided on the gate insulating layer 51, and a gate insulating layer 51 is provided on the conductive layer 52. The bottom gate type in which the semiconductor layer 50 is provided on the gate insulating layer 51 may be used. Each of the plurality of transistors 14 may be a multi-gate transistor having two or more gate electrodes and two or more channel formation regions.

In the illustrated configuration, only the plurality of transistors 14 are formed, but the present invention is not limited to this configuration. Elements provided over the substrate 10 may be appropriately adjusted depending on the use of the semiconductor device. For example, in the case of having a function of transmitting and receiving data without contact, only a plurality of transistors may be formed over the substrate 10 or a plurality of transistors and a conductive layer functioning as an antenna may be formed over the substrate 10. In addition, in the case of having a function of storing data, a plurality of transistors and a plurality of storage elements (eg, transistors and memory transistors) may be formed over the substrate 10. In the case where the circuit has a function of controlling a circuit, a function of generating a signal, or the like (for example, a CPU or a signal generation circuit), a plurality of transistors may be formed over the substrate 10. In addition to the above, other elements such as a resistance element (resistance) and a capacitance element (capacitance) may be formed as necessary.

Next, insulating layers 15 to 17 are formed over the plurality of transistors 14. The insulating layers 15 to 17 are formed by using a plasma CVD method, a sputtering method, an SOG (spin on glass) method, a droplet discharge method, a screen printing method, or the like, using silicon oxide, silicon nitride, resin (polyimide, acrylic , Epoxy) or the like. The insulating layers 15 to 17 are formed using siloxane. Siloxane has, for example, a skeletal structure composed of a bond of silicon and oxygen, and the substituent has an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon), a fluoro group, or an organic group containing at least hydrogen. And a fluoro group. In the above configuration, three insulating layers (insulating layers 15 to 17) are formed over the plurality of transistors 14, but the present invention is not limited to this configuration. The number of insulating layers stacked on the plurality of transistors 14 is not particularly limited.

Next, openings are formed in the insulating layers 15 to 17, and conductive layers 18 to 25 connected to the sources or drains of the plurality of transistors 14 are formed. The conductive layers 18 to 25 are made of an element selected from titanium (Ti), aluminum (Al), or the like by plasma CVD or sputtering, or an alloy material or compound material containing these elements as a main component. Or it forms by lamination. The conductive layers 18 to 25 function as source wirings or drain wirings.

Next, the insulating layer 28 is formed on the insulating layer 17 and the conductive layers 18 to 25. The insulating layer 28 is formed from a resin or the like.

Next, an opening is formed in the insulating layer 28 to form conductive layers 31 to 34 connected to the conductive layers 19, 20, 23, and 24. The conductive layers 31 to 34 function as an antenna. Note that the conductive layer functioning as an antenna is not provided in the same layer as the conductive layers 31 to 34, but in the same layer as the conductive layer 52 which is a gate, or the same layers as the conductive layers 18 to 25 which are source wirings or drain wirings. It may be provided. In such a case, the conductive layers 31 to 34 need not be formed. The conductive layer functioning as an antenna is provided in a plurality of layers (for example, a plurality of layers selected from the same layer as the conductive layer 52, the same layer as the conductive layers 18 to 25, and the same layer as the conductive layers 31 to 34). May be. Note that that the first layer and the second layer are provided in the same layer corresponds to the first layer being provided on the same layer as the second layer.

Next, the insulating layer 35 is formed on the insulating layer 28 and the conductive layers 31 to 34. The insulating layer 35 is formed of silicon oxide or silicon nitride by a plasma CVD method, a sputtering method, or the like.

Next, the sealing material 36 is formed (see FIGS. 1 and 3B). The sealing material 36 is selectively formed at a predetermined location by using a method such as screen printing or drawing with a dispenser. In many cases, the sealing material 36 is formed in a rectangular frame shape. The sealing material 36 is a thermosetting resin, an ultraviolet curable resin, a vinyl acetate resin adhesive, a vinyl copolymer resin adhesive, an epoxy resin adhesive, a urethane resin adhesive, a rubber adhesive, an acrylic resin adhesive. It is formed using an adhesive such as. A material in which a spacer is mixed in these materials may be used as the sealing material 36.

Further, a material obtained by mixing fibers with the above adhesive material may be used as the sealing material 36. The sealing material 36 is formed so as not to overlap with an element such as a transistor.

Next, an insulating layer 37 and a spacer 38 are formed between the sealing materials 36. The insulating layer 37 is formed of a resin, an adhesive, or the like using a screen printing method or the like. When the insulating layer 37 is formed with an adhesive, the sealing material 36 is not necessarily provided. The spacer 38 has a shape such as a bead shape or a fiber shape, and is made of a material such as resin or silica. The spacer 38 may be an insulating layer formed using a photolithography method.

When the spacer 38 is formed by using a photolithography method, an organic insulating material such as photosensitive acrylic is formed by pattern processing. According to this method, the spacer 38 can be provided at a desired location. One or both of the sealing material 36 and the spacer 38 serve to maintain a distance between the substrate 10 and the substrate 39. Therefore, if the distance between the substrate 10 and the substrate 39 can be maintained, one or both of the sealing material 36 and the spacer 38 may not be provided. In FIG. 3B, a sealing material 36, a spacer 38, and an insulating layer 37 are illustrated.

Next, a substrate 39 is provided on the insulating layer 37 and the spacer 38. The substrate 39 may be made of a material different from that of the substrate 10. For example, the substrate 10 may be a glass substrate and the substrate 39 may be a plastic substrate. Thereafter, the substrate 10 and the substrate 39 are bonded together using the sealing material 36 as necessary. At this time, if necessary, one or both of the pressure treatment and the heat treatment are performed by a crimping machine or the like.

Note that a barrier film may be provided only on one surface of the substrate 39 or on the entire substrate 39. As the barrier film, Al ₂ O ₃ , MgO, SiO ₂ , SiOx (x is 0 or more), Al, SiNx (x is 0 or more), SiOxNy (x, y is 0 or more), or the like may be used. By providing the barrier film, diffusion of harmful substances included in the substrate 39 can be prevented. The insulating layer 37 may be injected into the pair of substrates by a vacuum injection method after the pair of substrates are bonded to each other.

Next, the other surface of the substrate 10 and the other surface of the substrate 39 are ground by a grinding means (see FIG. 2A). Preferably, grinding is performed until the thickness of the substrates 10 and 39 becomes 100 μm or less. In the grinding process, one or both of the stage to which the substrates 10 and 39 are fixed and the grinding means are rotated to grind the surfaces of the substrate 10 and the substrate 39. The grinding means corresponds to, for example, a stone to be polished.

Next, the other surface of the ground substrate 10 and the other surface of the substrate 39 are polished by a polishing means. Preferably, polishing is performed until the thickness of the substrates 10 and 39 is 2 μm or more and 50 μm or less, preferably 4 μm or more and 20 μm or less, for example, 5 μm or less. In this polishing process, similarly to the above grinding process, one or both of the stage to which the substrates 10 and 39 are fixed and the polishing means are rotated to polish the surfaces of the substrate 10 and the substrate 39. The polishing means corresponds to, for example, a grinding stone, a polishing pad, and polishing abrasive grains (for example, cerium oxide). In addition, after the grinding process and the polishing process, one or both of a cleaning process and a drying process for removing dust are performed as necessary.

In addition, the thicknesses of the substrates 10 and 39 after polishing are determined in consideration of the time required for the grinding process and the polishing process, the time required for the subsequent cutting process, the use of the semiconductor device, the strength required for the use, etc. It is good to decide appropriately. For example, when improving the productivity by shortening the time of the grinding process and the polishing process, the thickness of the substrates 10 and 39 after polishing is preferably about 50 μm. In addition, in the case where productivity is improved by shortening the time required for the cutting process performed later, the thickness of the polished substrates 10 and 39 is preferably 2 μm or more and 20 μm or less. When the semiconductor device is attached to a thin article or embedded, the thickness of the polished substrates 10 and 39 is preferably 2 μm or more and 20 μm or less.

In the above process, both the grinding process and the polishing process are performed. However, if the desired thickness can be obtained only by the grinding process or the polishing process, only the grinding process or only the polishing process is performed. Good.

Next, the substrate 10, the insulating layers 11, 15 to 17, 28, 35, the sealing material 36, and the substrate 39 are cut (see FIGS. 2B and 3C). Then, a semiconductor device including the substrate 10, the plurality of transistors 12 and the substrate 39, or the substrate 10, the plurality of transistors 13 and the substrate 39 is completed. For the cutting, a laser irradiation device, a dicing device, a scribe device or the like is used.

In the above cutting step (cutting step), either a laser irradiation device or a dicing device may be used. Preferably, the device to be used is divided according to the size of the semiconductor device. In many cases, the laser irradiation apparatus can be cut into minute sizes. Therefore, a laser irradiation device is preferably used for a small size semiconductor device, and a dicing device is preferably used for a medium size or large size semiconductor device.

In this cutting step, a laser irradiation device is preferably used. The laser is composed of a laser medium, an excitation source, and a resonator. Lasers are classified into gas lasers, liquid lasers, and solid-state lasers according to the medium. Free lasers, semiconductor lasers, and X-ray lasers are classified according to the characteristics of oscillation. In the present invention, any laser is used. Also good. A gas laser or a solid laser is preferably used, and a solid laser is more preferably used.

Gas lasers include helium neon laser, carbon dioxide laser, excimer laser, and argon ion laser. The excimer laser includes a rare gas excimer laser and a rare gas halide excimer laser. A rare gas excimer laser oscillates by three types of excited molecules, argon, krypton, and xenon. Argon ion lasers include rare gas ion lasers and metal vapor ion lasers. Liquid lasers include inorganic liquid lasers, organic chelate lasers, and dye lasers. Inorganic liquid lasers and organic chelate lasers use rare earth ions such as neodymium, which are used in solid-state lasers, as laser media. The laser medium used by the solid-state laser is obtained by doping a solid matrix with an active species that acts as a laser. The solid matrix is a crystal or glass. The crystal is YAG (yttrium / aluminum / garnet crystal), YLF, YVO ₄ , YAlO ₃ , sapphire, ruby, or alexandride. In addition, the active species having a laser action are, for example, trivalent ions (Cr ³⁺ , Nd ³⁺ , Yb ³⁺ , Tm ³⁺ , Ho ³⁺ , Er ³⁺ , Ti ³⁺ ).

As the laser used in the present invention, a continuous wave laser beam or a pulsed laser beam can be used. Laser beam irradiation conditions, such as frequency, power density, energy density, and beam profile, are adjusted as appropriate in consideration of the thickness of a stacked body including a plurality of transistors.

In the step of irradiating the laser beam, ablation processing is used. Ablation processing is processing using a phenomenon in which a molecular bond in a portion irradiated with a laser beam, that is, a portion that has absorbed the laser beam is cut, photodecomposed, vaporized and evaporated. That is, in the present invention, a laser beam is irradiated to break molecular bonds at certain portions of the substrate 10, the insulating layers 11, 15 to 17, 28, 35, the sealing material 36, and the substrate 39, photodecompose, and vaporize. Evaporate.

The laser may be a solid-state laser having a wavelength of 1 to 380 nm which is an ultraviolet region. Preferably, an Nd: YVO ₄ laser with a wavelength of 1 to 380 nm is used. The reason is that the Nd: YVO ₄ laser having a wavelength of 1 to 380 nm is more easily absorbed by the substrate than other high wavelength lasers and can be ablated. Moreover, it is because the workability is good without affecting the periphery of the processed part.

Note that in the semiconductor device having the above structure (see FIG. 2B), the stack including the plurality of transistors 12 may be further sealed with a substrate (see FIG. 3A). Specifically, a substrate may be newly provided on one or both surfaces of the substrates 10 and 39. In the configuration shown in the drawing, the substrate 41 is provided on the surface of the substrate 10 and the substrate 42 is provided on the surface of the substrate 39, whereby the stacked body including the plurality of transistors 12 is sealed with the substrates 41 and 42. By sealing with the substrates 41 and 42, the strength can be improved.

Each of the substrates (also called a substrate, a film, and a tape) 41 and 42 is a flexible substrate. Each of the substrates 41 and 42 is made of polyethylene, polypropylene, polystyrene, AS resin, ABS resin (resin in which three of acrylonitrile, butadiene and styrene are polymerized), methacrylic resin (also called acrylic), polyvinyl chloride, polyacetal, polyamide, Polycarbonate, modified polyphenylene ether, polybutylene terephthalate, polyethylene terephthalate, polysulfone, polyethersulfone, polyphenylene sulfide, polyamideimide, polymethylpentene, phenol resin, urea resin, melamine resin, epoxy resin, diallyl phthalate resin, unsaturated polyester resin It consists of materials such as polyimide and polyurethane, and fibrous materials (for example, paper). The film may be a single layer film or a film in which a plurality of films are laminated. Further, an adhesive layer may be provided on the surface. The adhesive layer corresponds to a layer containing an adhesive.

The surface of each of the substrates 41 and 42 may be coated with silicon dioxide (silica) powder. The coating can maintain waterproofness even in a high temperature and high humidity environment. Further, the surface thereof may be coated with a conductive material such as indium tin oxide. The coated material stores static electricity and can protect the stacked body including the thin film transistor from static electricity. The surface may be coated with a material containing carbon as a main component (for example, diamond-like carbon). The coating increases the strength and can suppress deterioration and destruction of the semiconductor device. The substrates 41 and 42 may be formed of a material obtained by mixing a base material (for example, resin) with silicon dioxide, a conductive material, or a material containing carbon as a main component. Sealing of the stacked body including the plurality of transistors 12 by the substrates 41 and 42 is performed by melting a surface layer of each of the substrates 41 and 42 or an adhesive layer of each surface of the substrates 41 and 42 by heat treatment. . Moreover, a pressurizing process is performed as needed.

The present invention is characterized in that a stacked body including a plurality of transistors 12 is provided in a space inside the substrate 10 and the substrate 39. With the above characteristics, entry of harmful substances can be suppressed and barrier properties can be improved. Therefore, reliability can be improved.

The thickness of each of the substrates 10 and 39 is preferably 100 μm or less, more preferably 50 μm or less, and even more preferably 20 μm or less. As described above, the present invention is characterized by using a pair of substrates that are thinned (thinned) by performing a grinding process and a polishing process. With the above features, the semiconductor device can be reduced in size, thickness, and weight. Moreover, flexibility can be given and high added value can be realized.

Note that a glass substrate is preferably used as the substrate. This is because the glass substrate has a high barrier property against oxygen, water vapor, and the like. Moreover, it is because it is excellent in chemical resistance and solvent resistance compared with a plastic substrate.

Note that although the example in which the thin film transistor is formed over the substrate has been described in the above production process, the present invention is not limited to the above example. A transistor using a semiconductor substrate (silicon substrate) as a channel portion may be formed, and the substrate may be provided so as to face the semiconductor substrate. Then, the semiconductor substrate and the substrate may be thinned.

(Embodiment 2)
Embodiments of the present invention will be described with reference to cross-sectional views of FIGS. 4 to 6 and a top view of FIG. 5A and 5B correspond to top views in FIG. 7A, and FIG. 6A corresponds to a cross-sectional view from point A to point C in the top view in FIG. 7B. FIG. 6B corresponds to a cross-sectional view taken along points A and B in the top view in FIG.

First, the insulating layer 11 is formed over one surface of the substrate 10 (see FIG. 4A). Next, a plurality of transistors 14 are formed over the insulating layer 11. Next, insulating layers 15 to 17 are formed over the plurality of transistors 14. Next, openings are formed in the insulating layers 15 to 17, and conductive layers 18 to 25 connected to the sources or drains of the plurality of transistors 14 are formed.

Next, the insulating layer 43 is formed on the insulating layer 17 and the conductive layers 18 to 25. The insulating layer 43 is formed using silicon oxide or silicon nitride by a plasma CVD method, a sputtering method, or the like. Next, the sealing material 36 is formed. Next, an insulating layer 37 and a spacer 38 are formed between the sealing materials 36. Next, a substrate 39 is provided on the insulating layer 37 and the spacer 38. At this time, the substrate 39 is provided so that the insulating layer 37 and one surface of the substrate 39 are in contact with each other. Next, the substrate 10 and the substrate 39 are bonded together using the sealing material 36.

Next, the other surface of the substrate 10 and the other surface of the substrate 39 are ground by a grinding means (see FIG. 4B). Subsequently, the other surface of the ground substrate 10 and the other surface of the substrate 39 are polished by a polishing means.

Next, conductive layers 81 to 84 are formed over the other surface of the substrate 10 (see FIGS. 5A and 7A). The conductive layers 81 to 84 are formed by a sputtering method, a CVD method, a droplet discharge method, a screen printing method, or the like. The conductive layers 81 to 84 are made of aluminum (Al) or a material containing aluminum as a main component, copper (Cu) or a material containing copper as a main component, or an alloy material thereof. It is formed with a thickness of 2 μm. In addition, one or more elements selected from germanium (Ge), tin (Sn), gallium (Ga), zinc (Zn), lead (Pb), indium (In), scandium (Sb), and the like, and Al An alloy material with Cu may be used. When an alloy material mixed with such an element is used, the melting point is lowered, and the processing temperature in the subsequent reflow process can be lowered. In addition, the conductive layers 81 to 84 are formed so as to overlap the conductive layers 18, 21, 22, and 25.

Subsequently, the conductive layers 81 to 84 are irradiated with a laser beam (see FIGS. 5B and 7A). By irradiating the laser beam, the conductive layers 81 to 84 are fluidized (reflowed), and openings 85 to 88 are formed in the substrate 10 and the insulating layers 11 and 15 to 17. And each of the opening parts 85-88 is filled with the conductive layers 81-84. Then, the conductive layers 81 to 84 are electrically connected to the conductive layers 18, 21, 22, and 25. A part of the conductive layers 18, 21, 22, and 25 that is connected to the conductive layers 81 to 84 is also called a terminal portion.

Note that the treatment for heating the conductive layers 81 to 84 may be performed by rapid thermal annealing (RTA) instead of laser beam irradiation. Instant thermal annealing uses an infrared lamp or halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature within a few minutes to several microseconds. This process is performed by applying heat. Whichever method is used, at least the conductive layers 81 to 84 have a recrystallization temperature or higher and have fluidity.

Next, the substrate 10, the insulating layers 11, 15 to 17, 43, the sealing material 36, and the substrate 39 are cut by irradiation with a laser beam (see FIGS. 6A and 7B).

Next, a substrate 59 provided with an antenna 73 and a capacitor 74 is prepared (see FIG. 7C). Each of the antenna 73 and the capacitor 74 is formed by a screen printing method, a droplet discharge method, a photolithography method, a sputtering method, a CVD method, or the like. 6B and 6C illustrate conductive layers 60 and 61 that are part of the antenna 73.

Next, the substrate 59 is provided over the substrate 10 so that the conductive layers 81 and 82 are electrically connected to the conductive layers 60 and 61 on the substrate 59 (FIGS. 6B and 7D). )reference). A portion of the conductive layers 60 and 61 that is connected to the conductive layers 81 and 82 is also referred to as a terminal portion. In the configuration shown in the figure, a layer 63 (corresponding to an anisotropic conductive layer) including conductive particles 62 is provided between the conductive layers 81 and 82 and the conductive layers 60 and 61. However, the present invention is not limited to this configuration, and one or both of a bump (projection electrode) and an anisotropic conductive layer may be provided between the conductive layers 81 and 82 and the conductive layers 60 and 61. .

In the semiconductor device having the above structure (see FIG. 6B), a stack including the plurality of transistors 14 may be sealed with a substrate (see FIG. 6C). In the configuration shown in the drawing, the substrate 41 is provided on the surface of the substrate 59 and the substrate 42 is provided on the surface of the substrate 39, whereby the stacked body including the plurality of transistors 14 is sealed with the substrates 41 and 42.

(Embodiment 3)
In the above embodiment, the conductive layers 81 to 84 are formed on the other surface of the substrate 10, but the present invention is not limited to this embodiment. Conductive layers 65 to 68 may be formed over the other surface of the substrate 39 (see FIG. 8A). The conductive layers 65 to 68 are formed so as to overlap with the conductive layers 18, 21, 22, and 25.

Next, the conductive layers 65 to 68 are irradiated with a laser beam (see FIG. 8B). By irradiation with the laser beam, the conductive layers 65 to 68 are fluidized, and openings 69 to 72 are formed in the substrate 39 and the insulating layers 37 and 43. And each of the opening parts 69-72 is filled with the conductive layers 65-68. The conductive layers 65 to 68 are electrically connected to the conductive layers 18, 21, 22, and 25.

Next, the substrate 10, the insulating layers 11, 15 to 17, 43, the sealing material 36, and the substrate 39 are cut by laser beam irradiation (see FIG. 9A).

Next, the substrate 59 is provided over the substrate 39 so that the conductive layers 65 and 66 are electrically connected to the conductive layers 60 and 61 on the substrate 59 (see FIG. 9B). In the illustrated configuration, a layer 63 containing conductive particles 62 is provided between the conductive layers 65 and 66 and the conductive layers 60 and 61.

In the semiconductor device having the above structure, a stacked body including a plurality of transistors 14 may be further sealed with a substrate (see FIG. 9C). In the illustrated configuration, the substrate 41 is provided on the surface of the substrate 10, and the substrate 42 is provided on the surface of the substrate 59.

A substrate provided with a conductive layer will be described with reference to FIGS. Examples of the substrate provided with the conductive layer include the following two. The conductive layer functions as an antenna or connection wiring.

One is a structure in which conductive layers 60 and 61 are provided over a substrate 59 (see FIG. 10A). The substrate 59 is made of polyimide, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), or the like. The conductive layers 60 and 61 are made of copper, silver, or the like. The exposed portions of the conductive layers 60 and 61 are plated with gold or the like to prevent oxidation.

The other is one in which conductive layers 60 and 61 and a protective layer 75 are provided over a substrate 59 (see FIG. 10B). As the protective layer 75, one or both of a substrate and an insulating resin are provided. The substrate corresponds to polyimide, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone). The insulating resin corresponds to a liquid resist, an epoxy resin, a silicon resin, or a synthetic rubber resin.

When the conductive layers 60 and 61 on the substrate 59 function as an antenna, the shape of the conductive layers 60 and 61 is not particularly limited. Examples of the shape include a dipole, a ring (for example, a loop antenna), a spiral, and a rectangular parallelepiped (for example, a patch antenna). The material for forming the conductive layers 60 and 61 is not particularly limited. For example, gold, silver, copper, or the like may be used as the material, and silver having a low resistance value may be used. There is no particular limitation on the manufacturing method, and a sputtering method, a CVD method, a screen printing method, a droplet discharge method (for example, an inkjet method), a dispenser method, or the like is preferably used.

When the antenna is directly attached to the metal surface, an eddy current is generated in the metal by the magnetic flux passing through the metal surface. Such an eddy current is generated in the opposite direction to the magnetic field of the reader / writer. Therefore, it is preferable to prevent the generation of eddy current by sandwiching a ferrite or metal thin film sheet having high magnetic permeability and low high-frequency loss between the antenna and the conductive layer. This embodiment can be freely combined with other embodiment modes and other embodiments.

The structure of the semiconductor device of the present invention will be described with reference to FIG. The semiconductor device 100 of the present invention includes an arithmetic processing circuit 101, a memory circuit 103, an antenna 104, a power supply circuit 109, a demodulation circuit 110, and a modulation circuit 111. The semiconductor device 100 includes the antenna 104 and the power supply circuit 109 as essential components, and other components are provided as appropriate according to the use of the semiconductor device 100.

The arithmetic processing circuit 101 performs instruction analysis, control of the storage circuit 103, output of data to be transmitted to the modulation circuit 111, and the like based on a signal input from the demodulation circuit 110.

The memory circuit 103 includes a circuit including a memory element and a control circuit that controls data writing and data reading. The memory circuit 103 stores at least an identification number of the semiconductor device itself. The identification number is used to distinguish from other semiconductor devices. The memory circuit 103 includes an organic memory, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), an FeRAM (Ferroelectric Random Access Memory), a mask ROM (Read Only Memory ROM). It has one or more types selected from EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory) and flash memory. An organic memory has a structure in which a layer containing an organic compound is sandwiched between a pair of conductive layers. Since the organic memory has a simple structure, the manufacturing process can be simplified and the cost can be reduced. In addition, since the structure is simple, the area of the stacked body can be easily reduced, and a large capacity (high integration) can be easily realized. In addition, it is non-volatile and does not require a built-in battery. Therefore, it is preferable to use an organic memory as the memory circuit 103.

The antenna 104 converts the carrier wave supplied from the reader / writer 112 into an AC electrical signal. Further, load modulation is applied by the modulation circuit 111. The power supply circuit 109 generates a power supply voltage using the AC electrical signal converted by the antenna 104 and supplies the power supply voltage to each circuit.

The demodulation circuit 110 demodulates the AC electrical signal converted by the antenna 104 and supplies the demodulated signal to the arithmetic processing circuit 101. The modulation circuit 111 applies load modulation to the antenna 104 based on the signal supplied from the arithmetic processing circuit 101.

The reader / writer 112 receives the load modulation applied to the antenna 104 as a carrier wave. Further, the reader / writer 112 transmits a carrier wave to the semiconductor device 100. The carrier wave is an electromagnetic wave emitted from the reader / writer 112. This embodiment can be freely combined with other embodiment modes and other embodiments.

The semiconductor device 125 of the present invention can be used for various articles and various systems by utilizing the function of transmitting and receiving electromagnetic waves. Articles include, for example, keys (see FIG. 12A), banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc.), books, containers (pets, etc.) 12 (B)), accessories (such as bags and glasses, see FIG. 12 (C)), packaging containers (wrapping paper, bottles, etc., see FIG. 12 (D)), recording media (discs, video tapes, etc.) Vehicles (bicycles, etc.), foods, clothing, daily necessities, electronic devices (liquid crystal display devices, EL display devices, television devices, portable terminals, etc.). The semiconductor device of the present invention is fixed by being attached or embedded on the surface of an article having various shapes as described above.

The system is a distribution / inventory management system, an authentication system, a distribution system, a production history system, a book management system, and the like. By using the semiconductor device of the present invention, the system is highly functional, multi-functional and highly functional. Value can be added. For example, a semiconductor device of the present invention is provided inside an identification card, and a reader / writer 121 is provided at the entrance of a building or the like (see FIG. 12E). The reader / writer 121 reads an authentication number in an identification card owned by each person and supplies information related to the read authentication number to the computer 122. Based on the information supplied from the reader / writer 121, the computer 122 determines whether to permit entry or exit from the room. Thus, by utilizing the function of the semiconductor device of the present invention, an entrance / exit management system that realizes high functionality and high added value can be provided. This embodiment can be freely combined with other embodiment modes and other embodiments.

The semiconductor device of the present invention includes a transistor. The semiconductor layer included in the transistor is formed through the following manufacturing steps, for example. First, an amorphous semiconductor layer is formed by sputtering, LPCVD, plasma CVD, or the like. Subsequently, the amorphous semiconductor layer is subjected to laser crystallization, RTA (rapid thermal annealing) or thermal crystallization using a furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, and crystallization is promoted. A crystalline semiconductor layer is formed by crystallization by a method combining a thermal crystallization method using a metal element to be used and a laser crystallization method. Thereafter, the obtained crystalline semiconductor layer is formed by patterning (pattern processing) into a desired shape.

Preferably, the semiconductor layer included in the transistor is formed by a combination of a crystallization method involving heat treatment and a crystallization method of irradiating a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher. By irradiation with a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher, the surface of the crystallized semiconductor layer can be made flat. Further, by planarizing the surface of the semiconductor layer, the gate insulating layer formed over the semiconductor layer can be thinned. It also contributes to improving the breakdown voltage of the gate insulating layer.

The gate insulating layer included in the transistor may be formed by oxidizing or nitriding the surface of the semiconductor layer by performing plasma treatment. For example, it is formed by plasma treatment in which a rare gas such as He, Ar, Kr, or Xe and a mixed gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen are introduced. When excitation of plasma in this case is performed by introducing microwaves, high-density plasma can be generated at a low electron temperature. The surface of the semiconductor layer can be oxidized or nitrided by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. That is, an insulating layer having a thickness of 5 to 10 nm is formed on the semiconductor layer by such treatment using high-density plasma. Since the reaction in this case is a solid-phase reaction, the interface state density between the insulating layer and the semiconductor layer can be extremely low. Such a high-density plasma treatment directly oxidizes (or nitrides) a semiconductor layer (crystalline silicon or polycrystalline silicon), so that variations in thickness of the formed gate insulating layer can be extremely reduced. . In addition, since it is not strongly oxidized even at the crystal grain boundary of crystalline silicon, a very preferable state is obtained. That is, by performing solid-phase oxidation of the surface of the semiconductor layer by the high-density plasma treatment shown here, the gate insulating layer has good uniformity and low interface state density without causing an abnormal oxidation reaction at the grain boundary. Can be formed.

Note that only an insulating layer formed by high-density plasma treatment may be used as the gate insulating layer, and in addition, a silicon oxide, silicon oxynitride, silicon nitride, or the like may be formed by a CVD method using plasma or thermal reaction. An insulating layer may be deposited and stacked. In any case, a transistor including an insulating layer formed by high-density plasma in part or all of the gate insulating layer can reduce variation in characteristics.

Further, a semiconductor layer which is crystallized by scanning in one direction while irradiating a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or more has a characteristic that crystals grow in the scanning direction of the beam. By arranging the transistor so that the scanning direction is aligned with the channel length direction (the direction in which carriers flow when a channel formation region is formed), and adopting the above method as a method for manufacturing a gate insulating layer, characteristic variation And a transistor with high field-effect mobility can be obtained.

Note that a semiconductor layer, a gate insulating layer, and other insulating layers included in the transistor may be formed by plasma treatment. Such plasma treatment is preferably performed at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, it is preferable that the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and the plasma electron temperature is 0.5 eV or more and 1.5 eV or less.

When the electron density of plasma is high and the electron temperature in the vicinity of an object to be processed (for example, a semiconductor layer included in a transistor, a gate insulating layer, or the like) is low, damage to the object to be processed can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or nitride formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a thin film formed by sputtering or the like, the film thickness is excellent in uniformity and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower by 100 degrees or more than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed.

8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention.

Claims (22)

A transistor on a first substrate;
A first insulating layer on the transistor;
A conductive layer connected to the source or drain of the transistor through an opening provided in the first insulating layer;
A second insulating layer on the conductive layer;
A second substrate on the second insulating layer,
Each of the first substrate and the second substrate has a thickness of 100 μm or less. In claim 1,
At least one of the first substrate and the second substrate is a glass substrate. In claim 1,
A semiconductor device comprising at least one of a sealant and a spacer between the first substrate and the second substrate. A transistor on a first substrate;
A first insulating layer on the transistor;
A first conductive layer connected to a source or a drain of the transistor through an opening provided in the first insulating layer;
A second insulating layer on the first conductive layer;
A second conductive layer connected to the first conductive layer through an opening provided in the second insulating layer;
A third insulating layer on the second conductive layer;
A second substrate on the third insulating layer,
Each of the first substrate and the second substrate has a thickness of 100 μm or less. In claim 4,
At least one of the first substrate and the second substrate is a glass substrate. In claim 4,
A semiconductor device comprising at least one of a sealant and a spacer between the first substrate and the second substrate. A transistor including a semiconductor layer, a first insulating layer, and a first conductive layer on one surface of the first substrate;
A second insulating layer on the transistor;
A second conductive layer connected to the source or drain of the transistor through an opening provided in the second insulating layer;
A first terminal connected to the first conductive layer or the second conductive layer;
A third insulating layer on the second insulating layer and the second conductive layer;
A second substrate on the third insulating layer;
A third substrate;
A third conductive layer on one side of the third substrate;
A second terminal connected to the third conductive layer;
A fourth conductive layer on the other surface of the first substrate,
The fourth conductive layer is electrically connected to the first terminal portion through an opening provided in the first substrate and the second insulating layer,
The second terminal portion is electrically connected to the fourth conductive layer,
The other surface of the first substrate and the one surface of the third substrate are provided to face each other,
The first terminal portion and the second terminal portion overlap,
Each of the first substrate and the second substrate has a thickness of 100 μm or less. In claim 7,
At least one of the first substrate and the second substrate is a glass substrate. In claim 7,
A semiconductor device comprising at least one of a sealant and a spacer between the first substrate and the second substrate. In claim 7,
The semiconductor device, wherein the second terminal portion is electrically connected to the fourth conductive layer through at least one of an anisotropic conductive layer and a bump. A transistor including a semiconductor layer, a first insulating layer, and a first conductive layer on one surface of the first substrate;
A second insulating layer on the transistor;
A second conductive layer connected to the source or drain of the transistor through an opening provided in the second insulating layer;
A first terminal connected to the first conductive layer or the second conductive layer;
A third insulating layer on the second insulating layer and the second conductive layer;
A second substrate provided so that one surface is in contact with the third insulating layer;
A third substrate;
A third conductive layer on one side of the third substrate;
A second terminal connected to the third conductive layer;
A fourth conductive layer on the other surface of the second substrate,
The fourth conductive layer is electrically connected to the first terminal portion through an opening provided in the second substrate and the third insulating layer,
The second terminal portion is electrically connected to the fourth conductive layer,
The other surface of the second substrate and the one surface of the third substrate are provided to face each other,
The first terminal portion and the second terminal portion overlap,
Each of the first substrate and the second substrate has a thickness of 100 μm or less. In claim 11,
At least one of the first substrate and the second substrate is a glass substrate. In claim 11,
A semiconductor device comprising at least one of a sealant and a spacer between the first substrate and the second substrate. In claim 11,
The semiconductor device, wherein the second terminal portion is electrically connected to the fourth conductive layer through at least one of an anisotropic conductive layer and a bump. Forming a transistor on one side of the first substrate;
Forming a first insulating layer on the transistor;
Forming a conductive layer connected to a source or a drain of the transistor through an opening provided in the first insulating layer;
Forming a second insulating layer on the conductive layer;
Providing the second substrate on the second insulating layer such that the surface of the second insulating layer and one surface of the second substrate are in contact with each other;
Thinning the other surface of the first substrate and the other surface of the second substrate until the thickness of each of the first substrate and the second substrate is 100 μm or less,
The first substrate, the first insulating layer, the second insulating layer, and the second substrate are cut to form a stacked body including the first substrate, the transistor, and the second substrate. A method for manufacturing a semiconductor device. In claim 15,
A method for manufacturing a semiconductor device, wherein at least one of a sealant and a spacer is formed between the first substrate and the second substrate. Forming a transistor on one side of the first substrate;
Forming a first insulating layer on the transistor;
Forming a first conductive layer connected to a source or a drain of the transistor through an opening provided in the first insulating layer;
Forming a second insulating layer on the first conductive layer;
Forming a second conductive layer connected to the first conductive layer through an opening provided in the second insulating layer;
Forming a third insulating layer on the second conductive layer;
Providing the second substrate on the third insulating layer such that the surface of the third insulating layer and one surface of the second substrate are in contact with each other;
Thinning the other surface of the first substrate and the other surface of the second substrate until the thickness of each of the first substrate and the second substrate is 100 μm or less,
The first substrate, the first insulating layer, the second insulating layer, the third insulating layer, and the second substrate are cut to form the first substrate, the transistor, and the second substrate. A method for manufacturing a semiconductor device, comprising forming a stacked body including a substrate. In claim 17,
A method for manufacturing a semiconductor device, wherein at least one of a sealant and a spacer is formed between the first substrate and the second substrate. Forming a transistor including a semiconductor layer, a first insulating layer, and a first conductive layer over one surface of the first substrate;
Forming a second insulating layer on the transistor;
A second conductive layer connected to the source or drain of the transistor and a first terminal portion connected to the second conductive layer are formed through an opening provided in the second insulating layer. And
Forming a third insulating layer on the second insulating layer, the second conductive layer, and the first terminal portion;
Providing the second substrate on the third insulating layer such that the surface of the third insulating layer and one surface of the second substrate are in contact with each other;
Thinning the other surface of the first substrate and the other surface of the second substrate until the thickness of each of the first substrate and the second substrate is 100 μm or less,
Forming a third conductive layer overlapping the first terminal portion on the other surface of the first substrate;
Irradiating the third conductive layer with a laser beam to form an opening that exposes the first terminal portion, and filling the third conductive layer in the opening;
The other surface of the first substrate, the second terminal portion, and the fourth conductive layer are provided so that the third conductive layer and the second terminal portion are electrically connected. A method for manufacturing a semiconductor device, comprising providing the third substrate so that one surface of the third substrate faces the other. In claim 19,
A method for manufacturing a semiconductor device, wherein at least one of a sealant and a spacer is formed between the first substrate and the second substrate. Forming a transistor including a semiconductor layer, a first insulating layer, and a first conductive layer over one surface of the first substrate;
Forming a second insulating layer on the transistor;
A second conductive layer connected to the source or drain of the transistor through an opening provided in the second insulating layer; and a first terminal electrically connected to the second conductive layer Forming part,
Forming a third insulating layer on the second insulating layer, the second conductive layer, and the first terminal portion;
Providing the second substrate on the third insulating layer such that the surface of the third insulating layer and one surface of the second substrate are in contact with each other;
Thinning the other surface of the first substrate and the other surface of the second substrate until the thickness of each of the first substrate and the second substrate is 100 μm or less,
Forming a third conductive layer overlying the first terminal portion on the other surface of the second substrate;
Irradiating the third conductive layer with a laser beam to form an opening that exposes the first terminal portion, and filling the third conductive layer into the opening,
The second surface of the second substrate, the second terminal portion, and the fourth conductive layer are provided so that the third conductive layer and the second terminal portion are electrically connected. A method for manufacturing a semiconductor device, comprising providing the third substrate so that one surface of the third substrate faces the other. In claim 21,
A method for manufacturing a semiconductor device, wherein at least one of a sealant and a spacer is formed between the first substrate and the second substrate.

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