JP2007043111A5 - - Google Patents
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- JP2007043111A5 JP2007043111A5 JP2006177572A JP2006177572A JP2007043111A5 JP 2007043111 A5 JP2007043111 A5 JP 2007043111A5 JP 2006177572 A JP2006177572 A JP 2006177572A JP 2006177572 A JP2006177572 A JP 2006177572A JP 2007043111 A5 JP2007043111 A5 JP 2007043111A5
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- JP
- Japan
- Prior art keywords
- conductive layer
- organic compound
- semiconductor device
- respect
- calomel electrode
- Prior art date
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- 150000002894 organic compounds Chemical group 0.000 claims 12
- 239000004065 semiconductor Substances 0.000 claims 7
- ZOMNIUBKTOKEHS-UHFFFAOYSA-L Mercury(I) chloride Chemical class Cl[Hg][Hg]Cl ZOMNIUBKTOKEHS-UHFFFAOYSA-L 0.000 claims 6
- 150000001768 cations Chemical class 0.000 claims 4
- 239000002184 metal Substances 0.000 claims 4
- 229920000547 conjugated polymer Polymers 0.000 claims 2
- 238000007493 shaping process Methods 0.000 claims 1
Claims (14)
前記第１の導電層と前記第２の導電層との間に電流を流すと、前記有機化合物が還元され、前記第１の導電層または前記第２の導電層が酸化されて一部がイオン化することを特徴とする記憶装置。 A storage element having a first conductive layer, a second conductive layer, and a layer containing at least one organic compound between the first conductive layer and the second conductive layer;
When an electric current is passed between the first conductive layer and the second conductive layer, the organic compound is reduced, and the first conductive layer or the second conductive layer is oxidized and partially ionized. And a storage device.
前記有機化合物には金属陽イオンが存在し、
前記第１の導電層と前記第２の導電層との間に電流を通すと、前記有機化合物が酸化されると共に、前記金属陽イオンが還元されることを特徴とする記憶装置。 A storage element having a first conductive layer, a second conductive layer, and a layer containing at least one organic compound between the first conductive layer and the second conductive layer;
The organic compound has a metal cation,
The storage device according to claim 1, wherein when an electric current is passed between the first conductive layer and the second conductive layer, the organic compound is oxidized and the metal cation is reduced.
前記第１の導電層と前記第２の導電層の両方、あるいは一方の標準電位が、飽和カロメル電極を基準として−３．０Ｖ以上、且つ、＋０．８Ｖ以下であることを特徴とする記憶装置。 In claim 1 or claim 2,
The memory device characterized in that the standard potential of either or both of the first conductive layer and the second conductive layer is −3.0 V or higher and +0.8 V or lower with respect to a saturated calomel electrode .
前記第１の導電層の標準電位が、飽和カロメル電極を基準として−３．０Ｖ以上、且つ、＋０．８Ｖ以下であり、前記第２の導電層の標準電位が、飽和カロメル電極を基準として＋０．８Ｖ以上であることを特徴とする記憶装置。The standard potential of the first conductive layer is −3.0 V or higher and +0.8 V or lower with respect to the saturated calomel electrode, and the standard potential of the second conductive layer is +0 with respect to the saturated calomel electrode. A storage device characterized by being 8 V or higher.
前記記憶装置は、第１の方向に延びた複数のビット線と、前記第１の方向と垂直な第２の方向に延びた複数のワード線を有することを特徴とする記憶装置。 In any one of Claims 1 thru | or 4 ,
The storage device includes a plurality of bit lines extending in a first direction and a plurality of word lines extending in a second direction perpendicular to the first direction.
前記有機化合物は、共役高分子であることを特徴とする記憶装置。 In any one of Claims 1 thru | or 5 ,
The memory device, wherein the organic compound is a conjugated polymer.
前記トランジスタのソース領域またはドレイン領域は、前記第１の導電層または第２の導電層と電気的に接続し、
前記第１の導電層と前記第２の導電層との間に電流を流すと、前記有機化合物が還元され、前記第１の導電層または前記第２の導電層が酸化されて一部がイオン化することを特徴とする半導体装置。 A memory element having a first conductive layer, a second conductive layer, a layer containing at least one organic compound between the first conductive layer and the second conductive layer, and a transistor Have
A source region or a drain region of the transistor is electrically connected to the first conductive layer or the second conductive layer;
When an electric current is passed between the first conductive layer and the second conductive layer, the organic compound is reduced, and the first conductive layer or the second conductive layer is oxidized and partially ionized. A semiconductor device comprising:
前記トランジスタのソース領域またはドレイン領域は、前記第１の導電層または第２の導電層と電気的に接続し、
前記有機化合物には金属陽イオンが存在し、
前記第１の導電層と前記第２の導電層との間に電流を通すと、前記有機化合物が酸化されると共に、前記金属陽イオンが還元されることを特徴とする半導体装置。 A first conductive layer, a second conductive layer, and a memory element having a layer containing at least one organic compound between the first conductive layer and the second conductive layer, and a transistor Have
A source region or a drain region of the transistor is electrically connected to the first conductive layer or the second conductive layer;
The organic compound has a metal cation,
A semiconductor device, wherein when an electric current is passed between the first conductive layer and the second conductive layer, the organic compound is oxidized and the metal cation is reduced.
前記第１の導電層と前記第２の導電層の両方、あるいは一方の標準電位が、飽和カロメル電極を基準として−３．０Ｖ以上、且つ、＋０．８Ｖ以下であることを特徴とする半導体装置。 In claim 8 or claim 9 ,
The semiconductor device characterized in that the standard potential of either or both of the first conductive layer and the second conductive layer is −3.0 V or higher and +0.8 V or lower with respect to a saturated calomel electrode .
前記第１の導電層の標準電位が、飽和カロメル電極を基準として−３．０Ｖ以上、且つ、＋０．８Ｖ以下であり、前記第２の導電層の標準電位が、飽和カロメル電極を基準として＋０．８Ｖ以上であることを特徴とする半導体装置。The standard potential of the first conductive layer is −3.0 V or higher and +0.8 V or lower with respect to the saturated calomel electrode, and the standard potential of the second conductive layer is +0 with respect to the saturated calomel electrode. A semiconductor device having a voltage of 8 V or more.
前記半導体装置は、アンテナを有し、該アンテナは波形整形回路または整流回路の一部を構成するトランジスタと電気的に接続していることを特徴とする半導体装置。 In any one of Claims 8 thru | or 11 ,
The semiconductor device includes an antenna, and the antenna is electrically connected to a transistor that forms part of a waveform shaping circuit or a rectifier circuit.
前記有機化合物は、共役高分子であることを特徴とする半導体装置。 In any one of Claims 8 to 12 ,
The semiconductor device, wherein the organic compound is a conjugated polymer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006177572A JP5052055B2 (en) | 2005-07-01 | 2006-06-28 | Memory device and method for manufacturing semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005194077 | 2005-07-01 | ||
| JP2005194077 | 2005-07-01 | ||
| JP2006177572A JP5052055B2 (en) | 2005-07-01 | 2006-06-28 | Memory device and method for manufacturing semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007043111A JP2007043111A (en) | 2007-02-15 |
| JP2007043111A5 true JP2007043111A5 (en) | 2009-08-06 |
| JP5052055B2 JP5052055B2 (en) | 2012-10-17 |
Family
ID=37800758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006177572A Expired - Fee Related JP5052055B2 (en) | 2005-07-01 | 2006-06-28 | Memory device and method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5052055B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101305143B1 (en) | 2011-08-04 | 2013-09-12 | 동국대학교 산학협력단 | Apparatus and method of diplaying the condition of food |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0628841A (en) * | 1992-07-08 | 1994-02-04 | Makoto Yano | Storage element using chemical reaction |
| JP2003229538A (en) * | 2002-02-05 | 2003-08-15 | Matsushita Electric Ind Co Ltd | Non-volatile memory and manufacturing method thereof |
| US6870183B2 (en) * | 2002-11-04 | 2005-03-22 | Advanced Micro Devices, Inc. | Stacked organic memory devices and methods of operating and fabricating |
| US7015504B2 (en) * | 2003-11-03 | 2006-03-21 | Advanced Micro Devices, Inc. | Sidewall formation for high density polymer memory element array |
-
2006
- 2006-06-28 JP JP2006177572A patent/JP5052055B2/en not_active Expired - Fee Related
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