JP2007043059A - Light emitting diode and light emitting diode array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an epitaxial configuration capable of preventing a short-circuit defect due to diffusion of a p-type dopant from a p-type GaAs conductive layer, even in the case of using a semi-insulating GaAs substrate made by the liquid encapsulated Czochralski (LEC) method in a light emitting diode array and a light emitting diode. <P>SOLUTION: The light emitting diode array comprises compound semiconductor layers epitaxially grown on the p-type GaAs conductive layer 11 formed on the semi-insulating GaAs substrate 30. The epitaxial layer is isolated and divided into a plurality of light emitters 1 which function as the light emitting diode. An Si-doped n-type GaAs buffer layer 31 is interposed between the semi-insulating GaAs substrate 30 and the p-type GaAs conductive layer 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light-emitting diode array using a semi-insulating GaAs substrate manufactured by a versatile LEC method, and particularly to a light-emitting diode array and a light-emitting diode having a large light-emitting output that can be suitably used for an electrophotographic printer light source. It is.

  An electrophotographic printer forms an electrostatic latent image on a photosensitive drum with light according to an image signal, and transfers the image to paper to obtain an image. As a light source for forming a latent image, a laser method and a light emitting diode array method are widely used. In particular, a light emitting diode array type light source is suitable for a small printer or a large size printing because it does not require a long optical path length unlike a laser method.

  In recent years, with higher printing speed and higher image quality and further downsizing of printers, there is a demand for light-emitting diode arrays with higher definition, higher output, and lower cost.

  FIG. 2 shows a configuration example of a conventional light emitting diode array. The light emitting portion of this light emitting diode array is formed on the n-type GaAs substrate 10 directly through the p-type GaAs conductive layer 11 in sequence, and includes a p-type AlGaAs etching stopper layer 12, a p-type AlGaAs cladding layer 13, and a p-type. It consists of an AlGaAs active layer 14, an n-type AlGaAs cladding layer 15 and an n-type GaAs cap layer 16, and has a so-called double heterostructure. The cathode electrode 2 is provided on the mesa top surface of the n-type GaAs cap layer 16, and the anode electrode 3 is provided on the p-type GaAs conductive layer 11.

  As described above, a light emitting diode array using an n-type GaAs substrate is disclosed in, for example, Japanese Patent Laid-Open No. 6-302856 (Patent Document 1). However, in order to realize the low cost of the light emitting diode array, the LEC method (liquid sealing pull-up method) is more versatile than using the n-type GaAs substrate manufactured by the VGF method (vertical temperature gradient solidification method). It is more advantageous to use a semi-insulating GaAs substrate manufactured in (1).

  Here, the VGF method is a vertical type in which a seed crystal is placed in the lower part of a pyrolytic boron nitride (PBN) crucible formed by high-temperature vapor phase growth, and a GaAs polycrystal is arranged on the crucible. A single crystal is produced by putting it in an electric furnace and growing the crystal upward from the seed crystal (see, for example, Patent Document 2). In the LEC method, a GaAs raw material melt and a liquid sealant are housed in a PBN crucible, the seed crystal is brought into contact with the raw material melt, and the seed crystal is slowly pulled up while rotating relative to the crucible. This is a method for growing a GaAs single crystal (see, for example, Patent Document 3).

Although a silicon substrate is used instead of a semi-insulating GaAs substrate, a structure in which a double heterostructure of a light emitting part is provided on one surface of the silicon substrate via a buffer layer and an ohmic contact layer is known. (For example, refer to Patent Document 4). This buffer layer is mainly composed of GaAsP, GaP or the like, and a strained superlattice layer exists in the middle of the growth layer. For example, the buffer layer is mainly composed of GaAs crystal, and the strained superlattice layer is composed of InGaAs and GaAs. It is shown to make up.
JP-A-6-302856 JP-A-5-70276 JP-A-5-24979 JP-A-6-232454 (paragraph number 0013)

  However, Patent Document 4 uses a silicon substrate and does not use a semi-insulating GaAs substrate.

  The use of a semi-insulating GaAs substrate for a light-emitting diode array means that a GaAs crystal manufactured by a versatile LEC method is used, which is very advantageous for realizing a reduction in the cost of the light-emitting diode array. is there.

  However, in the case of the conventional light emitting unit structure of FIG. 2, even if a semi-insulating GaAs substrate manufactured by the LEC method is used instead of the n-type GaAs substrate manufactured by the VGF method, the following problems are caused. There is.

  That is, the light emitting section of FIG. 2 has a configuration in which the p-type GaAs conductive layer 11 is provided directly on the GaAs substrate. Then, a p-type AlGaAs etching stopper layer 12, a p-type AlGaAs cladding layer 13, a p-type AlGaAs active layer 14, an n-type AlGaAs cladding layer 15 and an n-type GaAs cap layer 16 are sequentially formed on the p-type GaAs conductive layer 11. After the growth, it is completed through an element manufacturing process (exposed to a high temperature of 400 ° C. at the maximum). When this element fabrication process is performed, in the conventional light emitting diode array, the p-type dopant Zn doped in the p-type GaAs conductive layer 11 diffuses into the semi-insulating GaAs substrate, and the element isolation trench (second mesa etching). In some cases, the groove 20) could not be completely divided and short-circuited, and an undesired LED of the light emitting part would shine.

  Accordingly, an object of the present invention is to solve the above-described problems, and even if a LEC semi-insulating GaAs substrate is used in a light-emitting diode array, a short-circuit failure caused by p-type dopant diffusion from the p-type GaAs conductive layer is caused. There is no epitaxial structure to provide.

  In order to achieve the above object, the present invention is configured as follows.

  The light-emitting diode array according to claim 1 is a plurality of light-emitting portions that function as light-emitting diodes by epitaxially growing a plurality of compound semiconductor layers on a semi-insulating GaAs substrate via a p-type GaAs conductive layer and insulating and dividing the compound semiconductor layers. A light-emitting diode array comprising: a Si-doped n-type GaAs buffer layer inserted between the semi-insulating GaAs substrate and the p-type GaAs conductive layer.

  According to this feature, the presence of the Si-doped n-type GaAs buffer layer in the middle diffuses Zn, which is the p-type dopant of the p-type GaAs conductive layer, into the semi-insulating GaAs substrate, thereby short-circuiting the light emitting portions. Can be prevented.

  According to a second aspect of the present invention, in the light-emitting diode array according to the first aspect, the Si-doped layer is provided between the semi-insulating GaAs substrate and the p-type GaAs conductive layer under the Si-doped n-type GaAs buffer layer. A GaAs / AlGaAs superlattice buffer layer is inserted.

  According to a third aspect of the present invention, in the light-emitting diode array according to the first or second aspect, the p-type GaAs conductive layer is divided into the depths of mesa etching grooves that define a plurality of light-emitting portions for the purpose of insulation and division. The depth reaches the Si-doped n-type GaAs buffer layer.

  According to this feature, the purpose that the mesa etching groove is insulated and divided into a plurality of light emitting portions can be sufficiently exhibited.

  According to a fourth aspect of the present invention, in the light-emitting diode array according to any one of the first to third aspects, a p-type AlGaAs in which the light-emitting portion is sequentially formed on a semi-insulating GaAs substrate via a p-type GaAs conductive layer. It includes an etching stopper layer, a p-type AlGaAs cladding layer, a p-type AlGaAs active layer, an n-type AlGaAs cladding layer, and an n-type GaAs cap layer.

  According to a fifth aspect of the present invention, a light emitting portion is epitaxially grown on a semi-insulating GaAs substrate via a p-type GaAs conductive layer, an n-type electrode is formed on the light emitting portion, and the back surface of the semi-insulating GaAs substrate is not epitaxially grown. In a light emitting diode for forming a p-type electrode, a GaAs layer for preventing p-type dopant from diffusing into the semi-insulating GaAs substrate between the semi-insulating GaAs substrate and the p-type GaAs conductive layer. Is provided.

  The invention of claim 6 is characterized in that a Si-doped n-type GaAs buffer layer is inserted between the semi-insulating GaAs substrate and the p-type GaAs conductive layer.

  According to a seventh aspect of the present invention, an Si-doped GaAs / AlGaAs superlattice buffer layer is inserted between the semi-insulating GaAs substrate and the p-type GaAs conductive layer in addition to the Si-doped n-type GaAs buffer layer. Features.

  According to an eighth aspect of the present invention, a p-type AlGaAs etching stopper layer, a p-type AlGaAs cladding layer, a p-type AlGaAs active layer, wherein the light emitting portion is sequentially formed on a semi-insulating GaAs substrate via a p-type GaAs conductive layer, An n-type AlGaAs cladding layer and an n-type GaAs cap layer are included.

  According to the present invention, since the Si-doped n-type GaAs buffer layer is inserted between the light-emitting diode array and the semi-insulating GaAs substrate in the light-emitting diode and the p-type GaAs conductive layer, Zn which is a dopant of the p-type GaAs conductive layer Can be prevented from diffusing into the semi-insulating GaAs substrate and short-circuiting. Therefore, it is possible to apply a GaAs substrate by the LEC method which is versatile and inexpensive without using an expensive n-type GaAs substrate by the VGF method.

  In this regard, Zn which is a dopant of the p-type GaAs conductive layer during crystal growth or heat treatment during the process diffuses into the buffer layer, but Si-doped n-type by inserting the Si-doped n-type GaAs buffer layer. The effect of the present invention can be obtained by offsetting between the concentration of Si as a dopant in the GaAs buffer layer and the concentration of Zn in the conductive layer.

Hereinafter, the light-emitting diode array of the present invention will be described based on the illustrated embodiments.
[Structure of light-emitting diode array]
For convenience of explanation, a conventional light emitting diode array will be described first.

  FIG. 7 shows an example of the structure of a conventional 4-divided matrix array.

  In this arrangement, the light emitting units are arranged in a line. A cathode bonding pad 6c and an anode bonding pad 6a connected from the cathode electrode 2 via the common wiring 4 are also arranged in an array. FIG. 8A and FIG. 8B are cross-sectional views showing representative portions of FIG. A conventional light emitting diode array includes an n-type GaAs substrate 10 of VGF method, a plurality of light emitting portions 1 formed thereon, a cathode electrode 2 partially formed on the upper surface of each light emitting portion 1, a light extraction The anode electrode 3 formed on the p-type GaAs conductive layer 11 is provided at a position sandwiching the portion (light emitting surface). In the illustrated embodiment, each light emitting portion 1 is formed by providing a mesa etching groove in an epitaxial layer uniformly formed on an n-type GaAs substrate 10 and separating and separating it into independent epitaxial layer portions.

  The present invention is the same as the prior art except that the substrate and part of the epitaxial structure are changed.

  4 and 5 show an embodiment of a quadrant matrix array according to the present invention. Unlike the conventional example, a semi-insulating GaAs substrate 30 by the LEC method is used as a substrate, and a Si-doped n-type GaAs buffer layer 31 is inserted immediately above. Other than this, the configuration is the same as that of the conventional example.

  A comparison between the substrate-epitaxial layer according to the present invention and the conventional one is shown in FIG. 1 (the present invention) and FIG. 2 (the conventional example).

  FIG. 3 shows an application example of the present invention. In addition to the Si-doped n-type GaAs buffer layer 31, for example, a Si-doped GaAs / AlGaAs superstructure comprising three layers 41 to 43 of Si-doped AlGaAs / GaAs (50 nm / 50 nm), for example. A configuration in which a lattice buffer layer 40 is inserted is shown.

(1) Substrate Instead of the conventional n-type GaAs substrate 10 of the VGF method, in this embodiment, a semi-insulating GaAs substrate 30 of the LEC method is used as the substrate.

(2) Light-Emitting Portion A Si-doped n-type GaAs buffer layer 31 is inserted between the LEC semi-insulating GaAs substrate 30 and the p-type GaAs conductive layer 11. The type of compound semiconductor and the thickness of the crystal layer stacked on the p-type GaAs conductive layer 11 are appropriately selected depending on the desired emission wavelength, emission output, and driving voltage. GaAs / AlGaAs is used as the compound semiconductor. The light-emitting portion 1 preferably has a double heterostructure consisting of an n-type cladding layer, an active layer, and a p-type cladding layer. The epitaxial layer formed on the p-type GaAs conductive layer 11 is divided by a first mesa etching groove 19. It is preferable that Further, the depth of the second mesa etching groove 20 is set to a depth that reaches the middle of the Si-doped n-type GaAs buffer layer 31 by dividing the p-type GaAs conductive layer 11 in order to achieve isolation between the blocks.

  In the case of the illustrated embodiment, the light-emitting portion 1 of the present light-emitting diode array is sequentially formed on a semi-insulating GaAs substrate 30 of the LEC method via a Si-doped n-type GaAs buffer layer 31 and a p-type GaAs conductive layer 11. The p-type AlGaAs etching stopper layer 12, the p-type AlGaAs cladding layer 13, the p-type AlGaAs active layer 14, the n-type AlGaAs cladding layer 15, and the n-type GaAs cap layer 16. The n-type GaAs cap layer 16 is removed by etching in the region of the light extraction portion 9.

  In the light emitting portion 1, the region directly involved in light emission includes the p-type AlGaAs active layer 14 having an energy band gap corresponding to the emission wavelength, the p-type AlGaAs cladding layer 13 and the n-type AlGaAs having a larger energy band gap. It has a so-called double heterostructure sandwiched between clad layers 15.

(3) Mesa etching groove A first mesa etching groove 19 reaching the p-type GaAs conductive layer 11 is provided in order to electrically separate the light emitting portion 1 and the bonding portion 8, and each block of the light emitting portion 1 is divided. For the purpose, a second mesa etching groove 20 for removing the p-type GaAs conductive layer 11 is provided.

The first mesa etching groove 19 is preferably formed separately from the light emitting portion 1 and the bonding portion 8 independently and separately. Here, by forming the individual bonding portions 8, no short circuit occurs between the bonding pads even when the Au wiring is left on the slope of the mesa groove during Au wiring processing. Further, since the bonding portion 8 is a remaining portion of the first mesa etching groove 19, the etching area is not increased. As a result, the loading effect can be avoided, and the dimensional control of the light emitting portion which is the remaining portion of the first mesa etching groove 19 can be easily performed.
Further, the number of light emitting diodes in one block divided by the second mesa etching groove 20 is equal to the number of the common wirings 4.

(4) Electrode and wiring layer Each electrode is required to have bonding characteristics and ohmic connection characteristics with the lower layer. For example, a laminated electrode such as AuZn / Ni / Au or Ti / Pt / Au is used for the anode electrode 3, and a laminated electrode such as AuGe / Ni / Au is used for the cathode electrode 2.

  The cathode electrode 2, the anode electrode 3 and the wiring drawn from the common wiring 4, and the common wiring 4 are required to have good bonding characteristics and good adhesion with the upper layer and lower layer, and thus are composed of a plurality of metal layers. It is preferable. It is preferable that the uppermost layer / lowermost layer have a metal layer such as Ti, Mo, TiW or the like having good bonding characteristics. For example, laminated electrodes such as Ti / Au / Ti, Mo / Au / Mo, and Tiw / Au / Tiw can be used. In order to simplify the process, when the anode electrode 3 and the common wiring 4 are formed at the same time, a laminated electrode such as Ti / Pt / Au / Ti may be used.

  The metal layer of each electrode can be formed by resistance heating vapor deposition, electron beam vapor deposition, sputtering, or the like, and the oxide layer can be formed by various known film formation methods. The cathode and anode metal layers are preferably further subjected to heat treatment (alloying) in order to impart ohmic properties.

  The cathode electrode 2 on each light emitting unit 1 is connected to the common wiring 4 by the cathode lead wiring 5c. Further, the common wiring lead wiring 5k is connected to the cathode bonding pad 6c. On the other hand, the anode electrode 3 provided in a band shape for each block at a position close to each light emitting portion 1 is extended to the anode bonding portion 8a by the anode lead-out wiring 5a to form the anode bonding pad 6a.

Each lead-out wiring 5c, 5a, 5k is formed on the second insulating film 18, and is connected to each other by a contact hole 7 provided by etching the second insulating film 18.
[Method for manufacturing light-emitting diode array]
A preferred method for manufacturing the light-emitting diode array of the present invention will be described.

First, an Si-doped n-type GaAs buffer layer 31 (carrier concentration: 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ ) is formed on the upper surface of the semi-insulating GaAs substrate 30 of the LEC method by metal organic chemical vapor deposition (MOVPE). Thickness: 1 μm), p-type GaAs conductive layer 11 (carrier concentration: 4 × 10 ¹⁹ cm ⁻³ , thickness: 1 μm), p-type AlGaAs etching stopper layer 12 (carrier concentration: 3 × 10 ¹⁹ cm ⁻³⁾ , thickness Thickness: 0.1 μm), p-type AlGaAs cladding layer 13 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 1 μm), p-type AlGaAs active layer 14 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³⁾ , thickness Thickness: 1 μm), n-type AlGaAs cladding layer 15 (carrier concentration: 2 × 10 ¹⁸ cm ⁻³ , thickness: 3 μm), and n-type GaAs cap layer 16 (carrier concentration) : 1 × 10 ¹⁸ cm ⁻³ , thickness: 0.5 μm).

The carrier concentration of the Si-doped n-type GaAs buffer layer is 1 × 10 ¹⁷ cm ⁻³ or more. In the Si-doped n-type GaAs buffer layer, the p-type dopant Zn from the upper p-type GaAs conductive layer is processed during the process. In the case of diffusion through heat treatment, the value is within a range in which inconvenience due to the diffusion, that is, short-circuit failure can be prevented. In addition, the upper limit of the carrier concentration is set within a range that can be actually doped.

  The formed crystal layer is selectively wet etched. First, the n-type GaAs cap layer 16 is removed while leaving a part of the light emitting portion 1 in contact with the cathode electrode 2 and the bonding portion 8. A first mesa etching groove 19 is provided at a depth at which the p-type AlGaAs etching stopper layer is exposed to divide the epitaxial layer on the p-type GaAs conductive layer 11 into a plurality of light-emitting portions 1 and independent from the light-emitting portions 1. The bonded portion 8 is formed. Further, the region of the p-type GaAs conductive layer 11 is removed by the second mesa etching groove 20 to electrically isolate each block. If the depth of the second mesa etching groove 20 is set so that the Si-doped n-type GaAs buffer layer 31 is also slightly etched at this time, the p-type GaAs conductive layer 11 remains even if there is an etching error. Absent.

  Next, after the first insulating film 17 is grown by chemical vapor deposition (CVD) so as to cover the entire upper surface of the light emitting diode array, the cathode electrode 2 made of AuGe / Ni / Au and AuZn / Ni / Au are used. The anode electrode 3 and the common wiring 4 made of Ti / Au / Ti are repeatedly formed by vapor deposition and lift-off methods, respectively.

  Then, after the second insulating film 18 is grown, the lead wiring 5a made of Ti / Au / Ti and the like are formed by sputtering and ion milling.

  Further, after the second insulating film 18 is grown by the CVD method, contact holes 7 are formed by etching in the cathode electrode 2 and the anode electrode 3 and the four common wirings 4, and each bonding portion 8 is formed by sputtering and ion milling. An extended wiring layer made of Ti / Au / Ti is formed.

The first insulating film 17 and the second insulating film 18 on the light extraction portion 9 and the scribe area 22 are removed by dry etching using a known mixed gas such as CHF ₃ / O ₂ . Further, a third insulating film 23 and a fourth insulating film 24 are vapor-deposited for the purpose of preventing moisture and the like from entering. In particular, since the fourth insulating film 24 is final passivation, a dense film such as a nitride film is preferable. At this time, when the third insulating film 23 and the fourth insulating film 24 have different refractive indexes, it is necessary to set the film thickness so that the third insulating film 23 and the fourth insulating film 24 do not become a reflective film depending on the emission wavelength. The total film thickness is preferably set to 1 μm or less.

  Finally, at the time of bonding, the third insulating film 23 and the fourth insulating film 24 on unnecessary bonding pads are opened by etching.

Here, as another embodiment, the epitaxial structure of the light emitting portion of the light emitting diode array shown in FIG. 1 was replaced with the epitaxial structure shown in FIG. That is, Si-doped GaAs (carrier concentration: 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , thickness is formed on the upper surface of the semi-insulating GaAs substrate 30 manufactured by the LEC method by metal organic vapor phase epitaxy (MOVPE method). : 50 nm) / AlGaAs (carrier concentration: 1 × 10 ^{17 to} 3 × 10 ¹⁸ cm ⁻³ , thickness: 50 nm), a Si-doped GaAs / AlGaAs superlattice buffer layer 40 composed of three layers 41 to 43 is inserted. Similar to FIG. 1, on the top surface, a Si-doped n-type GaAs buffer layer 31 (carrier concentration: 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , thickness: 1 μm), p-type GaAs conductive layer 11 (carrier concentration: 4). × ¹⁰ 19 ^{cm -3,} thickness: 1 [mu] m), p-type AlGaAs etching stopper layer 12 (carrier concentration: 3 × ¹⁰ 19 ^{cm -3,} thickness: 0.1 [mu] m , P type AlGaAs cladding layer 13 (carrier concentration: 1 × ¹⁰ 18 ^{cm -3,} thickness: 1μm), p-type AlGaAs active layer 14 (carrier concentration: 1 × ¹⁰ 18 ^{cm -3,} thickness: 1 [mu] m), n Type AlGaAs cladding layer 15 (carrier concentration: 2 × 10 ¹⁸ cm ⁻³ , thickness: 3 μm) and n-type GaAs cap layer 16 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 0.5 μm) An epitaxial structure was obtained by sequentially growing. Even in such an epitaxial structure, the same effect as in the embodiment of FIG. 1 could be obtained. In this embodiment, the leakage current flowing from the buffer layer to the substrate can be more reliably prevented by inserting the GaAs / AlGaAs layer 40 having a different band gap.
Here, the thickness of the GaAs / AlGaAs layer is preferably about 30 to 100 nm / 30 to 100 nm, and at least one GaAs / AlGaAs layer is sufficient.

Similar to the above embodiment, the Si-doped n-type GaAs buffer layer 31 (carrier concentration: 1 × 10 ^{17 to} 5 × is formed on the upper surface of the LEC semi-insulating GaAs substrate 30 by metal organic vapor phase epitaxy (MOVPE). 10 ¹⁸ cm ⁻³ , thickness: 1 μm), p-type GaAs conductive layer 11 (carrier concentration: 4 × 10 ¹⁹ cm ⁻³ , thickness: 1 μm), p-type AlGaAs etching stopper layer 12 (carrier concentration: 3 × 10) ¹⁹ cm ⁻³ , thickness: 0.1 μm), p-type AlGaAs cladding layer 13 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 1 μm), p-type AlGaAs active layer 14 (carrier concentration: 1 × 10) ¹⁸ cm ⁻³ , thickness: 1 μm), n-type AlGaAs cladding layer 15 (carrier concentration: 2 × 10 ¹⁸ cm ⁻³ , thickness: 3 μm), and n-type GaAs cap layer 1 6 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 0.5 μm) are sequentially grown. Further, a back electrode 50 is formed on a part or the entire back surface of the semi-insulating GaAs substrate which is not epitaxially grown, and a surface electrode 51 formed of a circular partial electrode is formed at the center of the surface of the n-type cap layer. Can also be produced.

Further, as another example, the epitaxial structure of the light emitting diode shown in FIG. 6 was replaced with the epitaxial structure shown in FIG. That is, Si-doped GaAs (carrier concentration: 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , thickness is formed on the upper surface of the semi-insulating GaAs substrate 30 manufactured by the LEC method by metal organic vapor phase epitaxy (MOVPE method). : 50 nm) / AlGaAs (carrier concentration: 1 × 10 ^{17 to} 3 × 10 ¹⁸ cm ⁻³ , thickness: 50 nm), a Si-doped GaAs / AlGaAs superlattice buffer layer 40 composed of three layers 41 to 43 is inserted. Similar to FIG. 1, on the top surface, a Si-doped n-type GaAs buffer layer 31 (carrier concentration: 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , thickness: 1 μm), p-type GaAs conductive layer 11 (carrier concentration: 4). × ¹⁰ 19 ^{cm -3,} thickness: 1 [mu] m), p-type AlGaAs etching stopper layer 12 (carrier concentration: 3 × ¹⁰ 19 ^{cm -3,} thickness: 0.1 [mu] m , P-type AlGaAs cladding layer 13 (carrier concentration: 1 × ¹⁰ 18 ^{cm -3,} thickness: 1 [mu] m), p-type AlGaAs active layer 14 (carrier concentration: 1 × ¹⁰ 18 ^{cm -3,} thickness: 1 [mu] m), n Type AlGaAs cladding layer 15 (carrier concentration: 2 × 10 ¹⁸ cm ⁻³ , thickness: 3 μm) and n-type GaAs cap layer 16 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 0.5 μm) An epitaxial structure was obtained by sequentially growing. Further, a back electrode 50 is formed on a part or the entire back surface of the semi-insulating GaAs substrate which is not epitaxially grown, and a surface electrode 51 composed of a circular partial electrode is formed at the center of the surface of the n-type cap layer to produce a light emitting diode. You can also.

It is sectional drawing which shows the light emission part of the light emitting diode array which concerns on one Embodiment of this invention. It is sectional drawing which shows the light emission part of the light emitting diode array which concerns on a prior art. It is the figure which showed the laminated structure of the light emission part of the light emitting diode array which concerns on other embodiment of this invention. It is the top view which expanded and showed a part of light emitting diode array which concerns on one Embodiment of this invention. 4 shows a cross-sectional structure of the light-emitting diode array of FIG. 4 according to an embodiment of the present invention, where FIG. It is a schematic diagram which shows the cross-section of the light emitting diode which concerns on one Example of this invention. It is the top view which expanded and showed a part of light emitting diode array which concerns on a prior art. 6 shows a cross-sectional structure of the light-emitting diode array of FIG. 6 according to the prior art, where (a) is a cross-sectional view taken along line AA ′ and (b) is a cross-sectional view taken along line BB ′.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light emission part 2 Cathode electrode 3 Anode electrode 9 Light extraction part (light emission surface)
10 VGF method n-type GaAs substrate 11 p-type GaAs conductive layer 12 p-type AlGaAs etching stopper layer 13 p-type AlGaAs cladding layer 14 p-type AlGaAs active layer 15 n-type AlGaAs cladding layer 16 n-type GaAs cap layer 19 First mesa etching Groove 20 Second mesa etching groove 30 Semi-insulating GaAs substrate 31 Si-doped n-type GaAs buffer layer 40 Superlattice buffer layer 41 to 43 Si-doped AlGaAs / GaAs layer 50 Back electrode 51 Front electrode

Claims (8)

In a light-emitting diode array having a plurality of light-emitting portions that are epitaxially grown on a semi-insulating GaAs substrate via a p-type GaAs conductive layer and insulated and divided to function as light-emitting diodes,
A light-emitting diode array, wherein a Si-doped n-type GaAs buffer layer is inserted between the semi-insulating GaAs substrate and the p-type GaAs conductive layer. The light emitting diode array according to claim 1,
A light-emitting diode array comprising a Si-doped GaAs / AlGaAs superlattice buffer layer inserted in addition to a Si-doped n-type GaAs buffer layer between the semi-insulating GaAs substrate and the p-type GaAs conductive layer . The light-emitting diode array according to claim 1 or 2,
Light emission characterized in that the depth of a mesa etching groove that partitions a plurality of light emitting portions for the purpose of insulation and division is set to a depth that divides the p-type GaAs conductive layer and reaches the Si-doped n-type GaAs buffer layer Diode array. In the light emitting diode array in any one of Claims 1-3,
A p-type AlGaAs etching stopper layer, a p-type AlGaAs clad layer, a p-type AlGaAs active layer, an n-type AlGaAs clad layer, wherein the light emitting part is sequentially formed on a semi-insulating GaAs substrate via a p-type GaAs conductive layer; A light emitting diode array comprising an n-type GaAs cap layer. A light emitting diode in which a light emitting portion is epitaxially grown on a semi-insulating GaAs substrate via a p-type GaAs conductive layer, a front electrode is formed on the light emitting portion, and a back electrode is formed on a surface of the semi-insulating GaAs substrate that is not epitaxially grown In
A light emitting diode comprising a GaAs layer for preventing p-type dopant from diffusing in the semi-insulating GaAs substrate between the semi-insulating GaAs substrate and the p-type GaAs conductive layer. The light emitting diode according to claim 5, wherein
A light-emitting diode comprising a Si-doped n-type GaAs buffer layer inserted between the semi-insulating GaAs substrate and the p-type GaAs conductive layer. The light emitting diode according to claim 5, wherein
A light-emitting diode comprising a Si-doped GaAs / AlGaAs superlattice buffer layer inserted in addition to a Si-doped n-type GaAs buffer layer between the semi-insulating GaAs substrate and the p-type GaAs conductive layer. In the light emitting diode in any one of Claims 5-7,
A p-type AlGaAs etching stopper layer, a p-type AlGaAs clad layer, a p-type AlGaAs active layer, an n-type AlGaAs clad layer, wherein the light emitting part is sequentially formed on a semi-insulating GaAs substrate via a p-type GaAs conductive layer; A light emitting diode comprising an n-type GaAs cap layer.

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