JP2007042872A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure which effectively prevents parasitic elements from operating, using one potential only, thereby achieving the latch-up prevention. <P>SOLUTION: The semiconductor integrated circuit has a guard ring structure inserted between pads and an inner circuit. The guard ring structure has an n-type epitaxial layer 2 formed on a p-type substrate 1 and two p-type diffusion layers 3, 3 which sand witch the epitaxial layer 2 from both sides. The two diffusion layers 3, 3 reach the p-type substrate 1, and adjoin the epitaxial layer 2 so as to form a parasitic pnp transistor structure causing the latch up, and are electrically commonly connected to the epitaxial layer 2 mutually through a wiring layer 9 to short circuit between the base and emitter of the pnp parasitic transistor structure. The wiring layer 9 is connected to the lowest potential through pads. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a guard ring structure for preventing latch-up, and more particularly to a guard ring structure provided between a pad portion and an internal circuit of the semiconductor integrated circuit.

  Conventional examples 1 to 3 are shown in FIGS.

FIG. 5 shows an integrated circuit of Conventional Example 1 (see Patent Document 1). In this integrated circuit, as a structure for preventing latch-up, an n ⁺ -type diffusion region connected to the high-potential-side power supply V _DD is provided between the input / output transistor region 100 and the internal transistor region 101, and a low potential. A guard ring region 102 is formed by two regions of the p ⁺ type diffusion region connected to the power supply V _ss on the side.

FIG. 6 shows a semiconductor device of Conventional Example 2 (see Patent Document 2). In this semiconductor device, as a guard ring structure for preventing latch-up, a high-potential side guard band 112 connected to a high-potential-side power supply V _DD between a pad section 110 and an internal circuit section 111, and a low-potential side the low potential side guard band 113 is inserted which is connected to the power source V _SS.

FIGS. 7A and 7B show an integrated circuit of Conventional Example 3 (see Non-Patent Document 1). In this integrated circuit, as shown in FIG. 7A, a double guard ring is provided between the pad portion (pad, I / O cell) 120 and the core (internal circuit portion) 121 as a structure for preventing latch-up. 122 is formed. As shown in FIG. 7B, the double guard ring 122 is inserted between the PMOS transistor 123 and the NMOS transistor 124, and is an n ⁺ type guard ring connected to the power source V _DD on the high potential side. 125, and a connected ^{p +} -type guard ring 126. the power supply _{V SS} of the low potential side. In the example of FIG. 7B, the n ⁺ type guard ring 125 is formed adjacent to the P ⁺ type diffusion region that constitutes the source / drain in the N well on the PMOS transistor 124 side. The p ⁺ type guard ring 126 is formed adjacent to the N ⁺ type diffusion region constituting the source / drain in the P well on the NMOS transistor side.

As described above, all of the structures for preventing latch-up in the conventional examples 1 to 3 are the double guard ring using the n ⁺ type guard ring connected to the high potential and the p ⁺ type guard ring connected to the low potential. The basic structure is as follows.
Japanese Patent No. 2751891 Japanese Patent No. 3380465 Meng-Lieh Sheu, 0.35um-CMOS ESD Design Guide, National Chi-Nan university

  However, the double guard ring structure using the high potential and the low potential has the following problems.

  1) Since wirings having different potentials are used, it is necessary to use another wiring layer at the intersecting portion, and the degree of freedom of wiring is low.

2) In recent years, the number of power supplies has further increased in integrated circuits, and it is not uncommon for several types of power supplies to be used in one integrated circuit. In such a case, in the guard ring structure connected only to the highest potential, For example, there is a possibility that a parasitic element operates between an n ⁺ type diffusion region connected to a lower power supply. In order to prevent this, it is necessary to consider the layout of the n-type diffusion region for each power source to be connected, and the layout design is extremely inconvenient.

  The present invention is for overcoming the above-described problems, and provides a structure that effectively prevents the operation of a parasitic element by using only one potential and prevents latch-up.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit in which a guard ring structure for preventing latch-up is inserted between a pad portion formed on a semiconductor substrate and an internal circuit portion. In the circuit, the guard ring structure is sandwiched between two first diffusion layers of the first conductivity type formed on the semiconductor substrate and the two first diffusion layers on the semiconductor substrate. A second diffusion layer of the second conductivity type formed, and the two first diffusion layers and the second diffusion layer are adjacent to each other to form a parasitic PNP transistor structure that causes the latch-up In addition, it is electrically connected to each other through a wiring layer so as to short-circuit between the base and emitter of the parasitic PNP transistor structure, and the wiring layer is connected to the lowest potential through the pad portion. And butterflies.

  In the present invention, the semiconductor substrate is a P-type semiconductor substrate in which an N-type epitaxial region is formed, the first and second diffusion layers are formed in the N-type epitaxial region, and the first diffusion layer is It may be P-type, and the first diffusion layer depth may reach the P-type semiconductor substrate via the N-type epitaxial region, and the second diffusion layer may be N-type.

  In the present invention, the semiconductor substrate is a P-type semiconductor substrate in which a P-type epitaxial region is formed, a third diffusion layer is formed in the P-type epitaxial region, and the first and second diffusion layers are: The third diffusion layer is formed shallower than the depth of the third diffusion layer, the first diffusion layer is N-type, the second diffusion layer is P-type, and the third diffusion layer is formed. The layer may be N-type.

  In the present invention, the semiconductor substrate is a P-type semiconductor substrate in which a P-type epitaxial region is formed, a third diffusion layer is formed in the P-type epitaxial region, and the first and second diffusion layers are: The third diffusion layer is formed shallower than the depth of the third diffusion layer, the first diffusion layer is P-type, the second diffusion layer is N-type, and the third diffusion layer is formed. The layer may be N-type.

  According to the present invention, a parasitic PNP transistor structure that causes latch-up is formed as a guard ring structure inserted between a pad portion and an internal circuit portion of a semiconductor integrated circuit, and the emitter and base are short-circuited by wiring. Therefore, a situation in which a forward voltage is generated between the emitter and the base can be avoided, thereby preventing latch-up. Further, since the wiring layer to be short-circuited is one kind of the lowest potential, the inconvenience of the layout due to a plurality of power supply potentials can be eliminated as in the prior art.

  Next, the best mode for carrying out a semiconductor integrated circuit according to the present invention will be described in detail with reference to the drawings.

  First, the principle of latch-up prevention used in the semiconductor integrated circuit of the present invention will be described.

In general, in a semiconductor integrated circuit, latch-up occurs when a PNPN junction-so-called thyristor structure-exists, as shown in FIGS. In this case, the presence of the parasitic PNP transistor Tr1 and the parasitic NPN transistor Tr2 is essential. In addition, in order for latch-up to occur, when there is a trigger for starting the thyristor circuit, and when the current amplification factor of the parasitic PNP transistor Tr1 is β1, and the current amplification factor of the parasitic NPN transistor Tr2 is β2,
β1 × β2 ≧ 1 (1-1)
It is necessary to satisfy the following conditions. Here, when the base current and collector current of the parasitic PNP transistor Tr1 are Ib1 and Ic1, and the base current and collector current of the parasitic NPN transistor Tr2 are Ib2 and Ic2, the current amplification factors β1 and β2 are β1 = Ic1 / Ib1. , Β2 = Ic2 / Ib2.

  For example, when the substrate potential rises due to some trigger and the parasitic NPN transistor Tr2 is turned on, a positive feedback circuit is formed with the parasitic PNP transistor Tr1, so when the condition (1-1) is satisfied, The current continues to flow until the parasitic element is thermally destroyed. However, focusing on the fact that these parasitic elements are bipolar transistors, a forward bias voltage is required between the base and the emitter junction, and latch-up does not occur if the forward voltage is not generated by any means. .

  As a countermeasure, in the present invention, a parasitic PNP transistor structure that intentionally causes latch-up is configured, and a forward voltage is not generated by short-circuiting between the emitter and base of the PNP transistor by a wiring layer. This prevents the occurrence of latch-up.

  Embodiments of the present invention will be described below with reference to the drawings.

  The semiconductor integrated circuit according to this embodiment will be described with reference to FIGS.

This embodiment is applied to a semiconductor integrated circuit having an N-type epi (epitaxial) layer on a P-type substrate. In this integrated circuit, a guard ring structure for preventing a guard ring is inserted between the pad portion and the internal circuit portion (core portion). This guard ring structure has a P ⁺ type diffusion region for making ohmic contact, and is sandwiched between two P type diffusion regions (first diffusion layer) reaching the P type substrate and two P type diffusion regions. And an N-type diffusion region (second diffusion layer) having an N ⁺ -type diffusion region for making ohmic contact. In this configuration, the two P ⁺ -type diffusion regions and the N ⁺ diffusion region have a structure that is electrically connected to the pad portion that supplies the lowest potential by the same wiring layer.

  FIG. 4 is a layout diagram of guard rings in the semiconductor integrated circuit of this embodiment.

  In FIG. 4, 16 is a pad portion for supplying a minimum potential (minimum potential supply pad portion), 17 is a pad portion other than the minimum potential supply pad portion 16 (other pad portions), 18 is an integrated circuit (semiconductor integrated circuit), 19 Is a guard ring, and 20 is an internal circuit part (core part). In the integrated circuit 18 shown in FIG. 4, the guard ring 19 is inserted between the pad portions 16 and 17 and the internal circuit portion 20 using only the lowest potential, and is electrically connected to the lowest potential supply pad portion 16. ing.

  FIG. 1 shows a cross-sectional view of an integrated circuit 18 provided with the guard ring 19 shown in FIG.

In FIG. 1, 1 is a P-type substrate, 2 is an N-type epi region formed on the P-type substrate 1, and 3 is a P-type diffusion region for isolation (P-type diffusion region for isolation). 4 denotes a P ⁺ type diffusion region (P type diffusion region for ohmic contact) for making ohmic contact of the P type diffusion region 3, and 5 denotes an N ⁺ type diffusion region for taking ohmic contact of the N type epi region 2. (N-type diffusion region for ohmic contact). Further, 6 is a P-type diffusion part contact hole for establishing electrical connection of the P ⁺ -type diffusion part, and 7 is an N-type diffusion part contact hole for obtaining electrical connection of the N ⁺ -type diffusion part. Further, 8 is an N-type epi region (adjacent device N-type epi region) of another element, 9 is a wiring layer connected to the lowest potential via the lowest potential supply pad portion 16 (FIG. 4), and 10 is an oxide film. is there.

  In such a structure, a PNPN thyristor structure that causes latch-up includes a parasitic PNP transistor including an N-type epi region 2 sandwiched between two P-type diffusion regions 3 and 3, an N-type epi region 2, and a P-type diffusion region. 3 and a parasitic NPN transistor formed by an N-type epi region 8 of another element.

  The emitter, base, and collector of the parasitic PNP transistor are all connected to the wiring layer 9 to be short-circuited. According to such a configuration, even if the substrate potential rises due to some trigger and the parasitic NPN transistor is turned on, the parasitic PNP transistor cannot be turned on, so that latch-up does not occur.

  Therefore, according to the present embodiment, a parasitic PNP transistor structure that causes latch-up is formed, and the emitter and base are short-circuited by the wiring layer, thereby preventing latch-up. Further, since only one type of the lowest potential is used for the wiring layer to be short-circuited, the inconvenience of layout due to a plurality of power supply potentials can be eliminated as in the conventional example.

  The present embodiment will be described with reference to FIG. Since the guard ring arrangement in the semiconductor integrated circuit of this embodiment is the same as that of the first embodiment (FIG. 4), the description thereof is omitted.

This embodiment is applied to a semiconductor integrated circuit having a P-type epi layer on a P-type substrate. In this integrated circuit, a guard ring structure is inserted between the pad portion and the internal circuit portion (core portion). This guard ring structure includes two P ⁺ type diffusion regions (first diffusion layer) for making ohmic contact in an N type well (third diffusion layer) formed in the P type epi region, And an N ⁺ type diffusion region (second diffusion layer) sandwiched between two P ⁺ type diffusion regions. In this configuration, the two P ⁺ -type diffusion regions and the N ⁺ -type diffusion region have a structure that is electrically connected to the pad portion that supplies the lowest potential by the same wiring layer.

  FIG. 2 shows a commonly used CMOS structure, in which 11 is a P-type epi region, 12 is an N-type well, 13 is a P-type well, and 14 is a P-type diffusion region that forms the source and drain of a PMOS transistor. , 15 are N-type diffusion regions forming the source and drain of the NMOS transistor. Other symbols are the same as those in FIG.

  In FIG. 2, the parasitic PNP transistor includes a P-type diffusion region 14 serving as an emitter, an N-type well 12 serving as a base, a P-type epi region 11 serving as a collector, and a P-type substrate 1.

  Therefore, according to the present embodiment, the P-type diffusion region 14 that becomes the emitter of the parasitic PNP transistor and the N-type diffusion region 15 that becomes the electrode of the N-type well 12 that becomes the base are short-circuited to each other by the wiring layer 9. The generation of forward voltage between the emitter and base of the parasitic PNP transistor can be suppressed. As a result, even if the base current of the parasitic PNP transistor is generated by some trigger, latch-up does not occur.

  The present embodiment will be described with reference to FIG. Since the guard ring arrangement in the semiconductor integrated circuit of this embodiment is the same as that of the first embodiment (FIG. 4), the description thereof is omitted.

This embodiment is applied to a semiconductor integrated circuit having a P-type epi layer on a P-type substrate, as in the second embodiment. In this integrated circuit, a guard ring structure is inserted between the pad portion and the internal circuit portion (core portion). This guard ring structure includes two N ⁺ type diffusion regions (first diffusion layer) for making ohmic contact in an N type well (third diffusion layer) formed in the P type epi region, A P ⁺ type diffusion region (second diffusion layer) sandwiched between two N ⁺ type diffusion regions. In this configuration, the two N ⁺ -type diffusion regions and the P ⁺ -type diffusion region have a structure that is electrically connected to a pad that supplies the lowest potential by the same wiring layer.

  FIG. 3 shows a commonly used CMOS structure, in which 11 is a P-type epi layer, 12 is an N-type well, 13 is a P-type well, and 14 is a P-type diffusion region that forms the source / drain of a PMOS transistor. , 15 are N-type diffusion regions forming the source and drain of the NMOS transistor. Other symbols are the same as those in FIG.

  In FIG. 3, the parasitic PNP transistor includes a P-type diffusion region 14 serving as an emitter, an N-type well 12 serving as a base, a P-type epitaxial layer 11 serving as a collector, and a P-type substrate 1.

  Therefore, according to the present embodiment, the P-type diffusion region 14 serving as the emitter of the parasitic PNP transistor and the N-type diffusion region 15 serving as the electrode of the N-type well 12 serving as the base are short-circuited by the wiring, thereby forming the parasitic PNP transistor. Generation of a forward voltage between the emitter and base of the transistor can be suppressed. As a result, even if the base current of the parasitic PNP transistor is generated by some trigger, latch-up does not occur.

  The present invention can be applied to the use of a semiconductor integrated circuit in which a guard ring structure is inserted between a pad portion and an internal circuit to prevent latch-up.

It is sectional drawing of the semiconductor integrated circuit by Example 1 of this invention. It is sectional drawing of the semiconductor integrated circuit by Example 2 of this invention. It is sectional drawing of the semiconductor integrated circuit by Example 3 of this invention. FIG. 3 is a layout diagram of a guard ring used in a semiconductor integrated circuit according to first to third embodiments of the present invention. It is a figure explaining the guard ring structure of the semiconductor integrated circuit by the prior art example 1. FIG. It is a figure explaining the guard ring structure of the semiconductor device by the prior art example 2. FIG. It is a figure explaining the guard ring structure of the semiconductor integrated circuit by the prior art example 3, (a) is a top view, (b) It is sectional drawing. (A) And (b) is a figure explaining the principle of latch-up prevention used with the semiconductor integrated circuit of this invention.

Explanation of symbols

1 P-type substrate 2 N-type epilayer 3 P-type diffusion region for isolation 4 P-type diffusion region for ohmic contact 5 N-type diffusion region for ohmic contact 6 P-type diffusion portion contact hole 7 N-type diffusion portion contact hole 8 Adjacent element N-type epi layer 9 Wiring layer 10 Oxide film 11 P-type epi layer 12 N-type well 13 P-type well 14 P-type source / drain diffusion region 15 N-type source / drain diffusion region 16 Minimum potential supply pad portion 17 Other pad portion 18 Integrated circuit 19 Guard ring 20 Internal circuit

Claims (4)

In a semiconductor integrated circuit in which a guard ring structure for preventing latch-up is inserted between a pad portion formed on a semiconductor substrate and an internal circuit portion,
The guard ring structure is
Two first diffusion layers of the first conductivity type formed on the semiconductor substrate;
A second diffusion layer of a second conductivity type formed to be sandwiched between the two first diffusion layers on the semiconductor substrate,
The two first diffusion layers and the second diffusion layer are adjacent to each other so as to form a parasitic PNP transistor structure that causes the latch-up, and short-circuit between a base and an emitter of the parasitic PNP transistor structure. Electrically connected to each other through the wiring layer,
The semiconductor integrated circuit according to claim 1, wherein the wiring layer is connected to a minimum potential through the pad portion. The semiconductor substrate is a P-type semiconductor substrate in which an N-type epitaxial region is formed,
The first and second diffusion layers are formed in the N-type epitaxial region;
The first diffusion layer is P-type, and the depth of the first diffusion layer reaches the P-type semiconductor substrate via the N-type epitaxial region;
The semiconductor integrated circuit according to claim 1, wherein the second diffusion layer is N-type. The semiconductor substrate is a P-type semiconductor substrate in which a P-type epitaxial region is formed, and a third diffusion layer is formed in the P-type epitaxial region,
The first and second diffusion layers are formed in the third diffusion layer to be shallower than the third diffusion layer depth,
The first diffusion layer is N-type;
The second diffusion layer is P-type;
The semiconductor integrated circuit according to claim 1, wherein the third diffusion layer is N-type. The semiconductor substrate is a P-type semiconductor substrate in which a P-type epitaxial region is formed, and a third diffusion layer is formed in the P-type epitaxial region,
The first and second diffusion layers are formed in the third diffusion layer to be shallower than the third diffusion layer depth,
The first diffusion layer is P-type;
The second diffusion layer is N-type;
The semiconductor integrated circuit according to claim 1, wherein the third diffusion layer is N-type.