JP2007040800A - Radiation detector, and radiation inspection device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a radiation detector which precludes an erroneous counter value from being output, even when a counter in a detection signal processing circuit for processing a detection signal detected by a radiation detecting element is malfunctioned by a radiation, and also to provide a radiation inspection device using the radiation detector. <P>SOLUTION: This radiation detector has: the radiation detecting element; and the detection signal processing circuit provided with the counter in the detection signal processing circuit for processing the detection signal detected by the radiation detecting element, and also has: the three counters 41, 42, 43 provided redundantly as the counters, and a correctness determination circuit 44 for determining the correctness of outputs from the three counters; and the correctness determination circuit 44 determines the correctness of the outputs for the three counters by a majority logic to output a correct value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a radiation detection apparatus and a radiation inspection apparatus using the radiation detection apparatus, and more particularly to a radiation detection apparatus having a counter in a detection signal processing circuit that processes a detection signal detected by a radiation detection element, and the radiation detection apparatus. The present invention relates to a radiological inspection apparatus using the

  There is a positron CT (Computed Tomography) (PET) as an apparatus capable of obtaining precise information of a subject. The principle of positron CT will be described with reference to FIGS. The positron CT introduces a test drug labeled with a positron emitting nuclide in advance into the body of a subject by injection or inhalation. The test drug introduced into the body is accumulated in a specific part having a function corresponding to the test drug. For example, when a saccharide test drug is used, it is selectively accumulated at sites with high metabolism such as cancer cells. At this time, as shown in FIG. 1, positrons 11 are emitted from the positron emitting nuclide of the test agent, and when the emitted positrons and surrounding electrons 13 are combined and annihilated, the two 511 keV gamma rays are approximately equal to each other. Released in the direction of 180 degrees. Therefore, these two gamma rays are arranged around the subject 20 (in FIG. 2, two radiation detection devices are described, but in reality, many radiation detection devices are arranged around the subject 20. ) Radiation isotope distribution image data in the subject by knowing the positron annihilation site X by simultaneously detecting by the radiation detection devices 21 and 22 for detecting gamma rays and processing by the CPU (Central Processing Unit) 24. To get. The CPU 24 calculates the radiation position of the radioisotope based on the detected time data and the position data of the detection units of the radiation detection devices 21 and 22.

  A CT scan (computer tomography) device used as a precision diagnostic device can obtain structural information such as lesions in the body, whereas a positron CT device can obtain functional information in the body of a subject, and thus various intractable diseases can be obtained. Pathological elucidation is possible.

  In the positron CT apparatus, two gamma rays emitted from a positron nuclide in a direction of about 180 degrees with each other are determined as effective data when a pair of gamma ray detectors sandwiching the subject are simultaneously detected. Therefore, in a positron CT radiation detector, it is necessary to determine whether or not a pair of gamma ray detectors simultaneously detected gamma rays. The time when the radiation is detected is determined using a counter, a latch, and the like.

Further, in the technical field of radiation detection, a technique of monitoring radiation using a counter is known (see, for example, Patent Documents 1 and 2).
JP-A-7-140253 JP 2001-215277 A

  By the way, when radiation hits the counter, there is a problem that the radiation is ionized inside the counter and the operation of the electronic circuit is disturbed to output an incorrect value.

  However, the technique disclosed in Japanese Patent Application Laid-Open No. 7-140253 is a technique that removes a noise component and enables output of only a radiation signal, and is disclosed in Japanese Patent Application Laid-Open No. 2001-215277. Is intended to reduce the size of radiation measuring instruments and increase the accuracy of energy estimation, and these known documents do not give any consideration to malfunctions caused by γ rays hitting the counter.

  In order to prevent malfunction due to radiation hitting the counter, it is conceivable to block radiation by placing lead on the entire surface of the counter. However, many counters arranged around the subject are completely blocked. There is a problem that malfunction with a certain probability is unavoidable.

  The present invention has been invented in order to solve these problems in view of the above points, and a counter in a detection signal processing circuit that processes a detection signal detected by a radiation detection element malfunctions due to radiation. However, it is an object of the present invention to provide a radiation detection apparatus and a radiation inspection apparatus using the radiation detection apparatus that prevent an erroneous counter value from being output.

  To achieve the above object, a radiation detection apparatus according to the present invention includes a radiation detection element, a detection signal processing circuit that processes a detection signal detected by the radiation detection element, and includes a detection signal processing circuit including a counter. In the radiation detection apparatus having the above, there are provided A (A is a natural number of 3 or more) counters redundantly provided as the counters, and a correctness determination circuit for determining the correctness of the outputs of the A counters. The correctness / incorrectness determination circuit can be configured to determine the correctness / incorrectness of the outputs of the A counters by the majority logic and output a correct value.

  Accordingly, it is possible to provide a radiation detection apparatus that prevents an erroneous counter value from being output even if radiation hits the counter and, as a result, malfunctions occur in the counter.

  In order to achieve the above object, the radiation detection apparatus of the present invention has an error counter discrimination circuit for discriminating an erroneous counter, and the count value of the incorrect counter determined by the error counter discrimination circuit is used as the correct / incorrect value. It can be configured to be corrected by the output of the discrimination circuit.

  As a result, even if the counter malfunctions due to radiation, an incorrect counter value can be corrected.

  In order to achieve the above object, the radiation detection apparatus of the present invention is provided with a master counter separately from the A counters, and the A counters are provided at a predetermined cycle by the output of the master counter. It can be configured to reset at the same time.

  As described above, since the A counters are simultaneously reset at a predetermined cycle, even if a malfunction of the counter due to radiation occurs, the malfunctioned counter can be returned to a normal state at a subsequent reset timing. it can.

  Moreover, in order to achieve the said objective, the master counter in the radiation detection apparatus of this invention can be comprised so that it may be provided in the place where the radiation detected does not hit.

  As a result, the malfunction of the master counter due to radiation can be eliminated, and the A counters can be reset accurately. As a result, the incident time of the radiation detection element can be accurately calculated.

  In order to achieve the above object, the radiation detection apparatus of the present invention is configured such that each of the three or more counters is an N-bit counter and the master counter is an M (M> N) bit counter. Can do.

  Thereby, the size of “A counters” can be reduced, and as a result, the radiation detection apparatus can be reduced in size. Further, even if the counter malfunctions, the malfunctioning counter can be recovered in a short time.

  In order to achieve the above object, the radiation detection apparatus of the present invention may be configured to simultaneously reset the three or more counters when all the lower N bits of the master counter become 0. it can.

  Accordingly, the counter can be reset periodically and accurately, and as a result, the incident time of the radiation detection element can be accurately calculated.

  In order to achieve the above object, a semiconductor detection element of the radiation detection apparatus of the present invention includes a semiconductor crystal, one first electrode that substantially covers one surface of the semiconductor crystal, and the other surface. A plurality of striped second electrodes, and the detection signal is output from each of the second electrodes, and one block is formed by the plurality of radiation detection devices sharing the semiconductor crystal. The A counters can be configured to be provided for each block.

  Thereby, “A counters” can be shared for each block, and the radiation detection apparatus can be downsized.

  In order to achieve the above object, the detection signal processing circuit of the radiation detection apparatus of the present invention includes a plurality of comparators that compare a detection signal detected by the radiation detection element with a reference voltage, and a radiation detection time. A latch for latching the count value of the counter by the output of the comparator, and an incident time calculation circuit for calculating the time of incidence by the radiation detection element based on the output of the latch circuit The reference voltages of the plurality of comparators can be different from each other.

  Thereby, the time of incidence by the radiation detection element can be accurately calculated.

  In order to achieve the above object, the radiation detection element of the radiation inspection apparatus of the present invention is provided around the subject, and the part of the subject that has emitted radiation is detected based on the output of the radiation detection device. Can be configured.

  Thereby, even if the counter in the detection signal processing circuit that processes the detection signal detected by the radiation detection element malfunctions due to radiation, it is possible to provide a radiation inspection apparatus that prevents an erroneous counter value from being output. .

  According to the present invention, even if a counter in a detection signal processing circuit that processes a detection signal detected by a radiation detection element malfunctions due to radiation, a radiation detection device that prevents an erroneous counter value from being output, and the radiation A radiation inspection apparatus using the detection apparatus can be provided.

  Below, the radiation detection apparatus used for a radiation inspection apparatus is demonstrated.

  FIG. 3 is an example of a radiation detection apparatus. The radiation detection apparatus in FIG. 3 includes a detection element 30 and a detection signal processing circuit 29.

The detection element 30 includes a thin plate-like semiconductor crystal and electrodes formed on both sides thereof. As the material of the semiconductor crystal, for example, cadmium telluride (CdTe), Cd _1-x Zn _x Te (CZT), thallium bromide (TlBr), which is sensitive to gamma rays having an energy of 511 keV is used. The semiconductor crystal body has dimensions of, for example, a thickness of 1 mm, a width of 0.6 mm, and a depth of about 10 mm.

  A voltage (−HV) is applied between the lower electrode and the upper electrode of the detection element 30. When γ rays hit the semiconductor crystal, electrons and holes are generated. By the way, since an electric field exists between the lower electrode and the upper electrode, holes are pulled by the lower negative electrode, and electrons are pulled by the upper positive electrode. As a result, a detection signal is output from the electrode.

  The detection signal processing circuit 29 includes a preamplifier 31, comparators 32 to 34, a counter 35, latch circuits 36 and 37, and an incident time calculation circuit 38.

The preamplifier 31 amplifies the detection signal of the detection element 30. The amplified detection signal is simultaneously applied to the comparator 31, the comparator 32, and the comparator 33. The comparator 32 is compared with the reference voltage Vref1, and outputs a low level signal if the input signal is equal to or lower than the reference voltage Vref1, and outputs a high level signal if the input signal exceeds the reference voltage Vref1. Similarly, the comparator 32 and the comparator 33 compare the input signal with the reference voltage Vref2 and the reference voltage Vref3. The reference voltages Vref1, Vref2, and Vref3 are
Vref1 <Vref2 <Vref3 (1)
Have the relationship.

  A waveform shaping circuit may be provided after the preamplifier 31.

  The counter 35 is an 8-bit counter, is reset by a reset signal, outputs “00000000”, counts the clock every time the clock signal is supplied, and outputs the value. Note that the counter 35 is not limited to an 8-bit counter. An 8- to 16-bit counter may be used.

  The latch circuit 36 latches the value of the counter 35 when the output of the comparator 32 changes from the low level to the high level. Similarly, the latch circuit 37 latches the value of the counter 35 when the output of the comparator 33 changes from the low level to the high level.

  The incident time calculation circuit 38 calculates the incident time of the radiation incident on the radiation detection element 30 based on the outputs of the latch circuit 36, the latch circuit 37 and the comparator 34.

  By the way, the detection signal Y (t) output from the detection element 30 is indicated by a thick line in FIG. The comparator 34 compares the detection signal Y (t) with the reference voltage Vref1, and therefore triggers the latch 36 at time t1 in FIG. Therefore, the latch circuit 36 latches the counter value for time t1. Similarly, the comparator 33 compares the detection signal Y (t) with the reference voltage Vref2, so that the latch 37 is triggered at time t2 in FIG. The counter value is latched.

  The incident time calculation circuit 38 calculates time t0 from time t1 and time t2. Although the time t0 is the rising time of the detection signal Y (t), this time t0 can be regarded as the incident time of the radiation incident on the radiation detection element 30.

If the detection signal Y (t) can be linearly approximated from t0 to t2, the time t0 is
t0 = (Vref1 * t2-Vref2 * t1) / (Vref1-Vref2) (2)
It becomes.

  The incident time calculation circuit 38 transmits the time t0 calculated based on Expression (2) to the CPU 24.

  The comparator 32 compares the detection signal Y (t) with the reference voltage Vref3, and when the detection signal Y (t) exceeds the reference voltage Vref3, the output is changed from the low level to the high level, and the incident time calculation circuit. The calculation request signal is output to 38. On the other hand, the incident time calculation circuit 38 is configured to start calculating the incident time based on the equation (2) when the calculation request signal is received from the comparator 32. Therefore, when the maximum value Vmax of the detection signal Y (t) output from the detection element 30 is equal to or lower than the reference voltage Vref3, the incident time calculation circuit 38 receives information on the times t1 and t2 from the latch circuits 36 and 37. Is input and the incident time calculation circuit 38 calculates the rise start time based on the information of the time t1 and the time t2 only when the detection signal output from the detection element 30 exceeds the reference voltage Vref3. To do. The reference voltage Vref3 is set to a voltage corresponding to 200 keV to 300 keV in terms of gamma ray energy.

  Next, an example of another radiation detection apparatus is shown. The radiation detection apparatus in FIG. 5 includes a detection element 300 and a detection signal processing circuit 290.

The detection element 300 includes a thin plate-like semiconductor crystal and electrodes formed on both sides thereof. As the material for the semiconductor crystal, cadmium telluride (CdTe), Cd _1-x Zn _x Te (CZT), etc. sensitive to gamma rays having an energy of 511 keV are used as in FIG. The semiconductor crystal body has dimensions of, for example, a thickness of 1 mm, a width of 20 mm, and a depth of about 10 mm.

  The lower electrode of the detection element 30 is a solid electrode, and platinum is used as a material, for example. The upper electrode of the detection element 30 is a striped electrode, and for example, indium is used as the material. Thirty-two of the upper electrodes are arranged in parallel at intervals of 0.6 mm within a width of 20 mm.

  A detection signal is output from each of the 32 upper electrodes. The incident time of the radiation incident on the radiation detection element 300 is calculated for each detection signal output from the 32 electrodes.

First, the detection signals output from the leftmost electrode among the 32 upper electrodes are preamplifier 310 ₁ , comparator 320 ₁ , comparator 330 ₁ , comparator 340 ₁ , shared counter 350, latch circuit 360 ₁ , latch circuit. The circuit composed of 370 ₁ and the incident time calculation circuit 380 ₁ calculates the incident time of the radiation incident on the leftmost electrode, as in FIG.

Among them, the preamplifier 310 ₁ , the comparator 320 ₁ , the comparator 330 ₁ , the comparator 340 ₁ , the latch circuit 360 ₁ , the latch circuit 370 _1, and the incident time calculation circuit 380 ₁ (hereinafter referred to as “dedicated for calculating the incident time of the leftmost electrode”). The circuit 350 ₁ ”) is a dedicated circuit for calculating the incident time of the radiation incident on the leftmost electrode, and the shared counter 350 is incident on each of the 32 upper electrodes. A dedicated circuit for calculating the radiation incident time is a shared counter.

In addition, the detection signal output to the second electrode from the left end of the 32 electrodes is sent to the “dedicated circuit 350 ₁ for calculating the incident time of the leftmost electrode” in the same manner as the leftmost electrode. The incident time of the second electrode from the left end is calculated by the corresponding dedicated circuit for calculating the incident time of the second electrode from the left end and the common counter 350.

  Thus, the incident time of each electrode can be calculated for all 32 electrodes by the dedicated circuit for calculating the incident time of each electrode and the common counter 350.

(First embodiment)
In the first embodiment, the counter in the radiation detection apparatus is tripled with redundancy.

  That is, as shown in FIG. 6, the counter 41, the counter 42, and the counter 43 are used as the counter 35 of FIG. 3 or the shared counter 350 of FIG.

  The outputs of the counter 41, the counter 42, and the counter 43 are supplied to the majority logic circuit 44. In the majority logic circuit 44, the outputs of the counter 41, the counter 42, and the counter 43 are output by taking the majority logic for each bit.

  For example, as shown in the figure, when the count value of the counter 41 is “00000101”, the count value of the counter 42 is “00000111”, and the count value of the counter 43 is “00000101”, the majority logic circuit 44 Outputs “00000101”.

  That is, in the first bit, the count value of the counter 41 is “1”, the count value of the counter 42 is “1”, the count value of the counter 43 is “1”, and the values of all the counters are “1”. Since “1”, the majority logic circuit 44 outputs “1”.

  In the second bit, the count value of the counter 41 is “0”, the count value of the counter 42 is “1”, the count value of the counter 43 is “0”, and the count values of the counter 41 and the counter 43 are Since the count value of only the counter 42 is “1” while “0”, the result of the majority logic “0” is output from the majority logic circuit 44.

  In the third bit, the count value of the counter 41 is “1”, the count value of the counter 42 is “1”, the count value of the counter 43 is “1”, and the values of all the counters are “1”. Therefore, “1” is output from the majority logic circuit 44.

  In the fourth to eighth bits, the values of all the counters are “0”, so that “0” is output from the majority logic circuit 44.

  Since it comprised in this way, even if the counter in the detection signal processing circuit which processes the detection signal detected by the radiation detection element malfunctions due to radiation, an incorrect counter value is not output.

  Note that the majority logic circuit 44 is a circuit that determines the correctness of the output of the counter based on the majority logic, and therefore may be called a correctness determination circuit.

(Second Embodiment)
In the first embodiment, redundant counters are provided so that erroneous counter values are not output even if malfunctions occur due to radiation.

  In the second embodiment, redundant counters are provided, and when the counter malfunctions due to radiation, the counter value is corrected in error.

  A second embodiment will be described with reference to FIG. 7 includes a counter A51, a counter B52, a counter C53, and a majority logic circuit 54.

  Note that the counter A51, the counter B52, and the counter C53 are each configured to set the output of the majority logic circuit 54 as the respective count value when the load signals (LoadA, LoadB, and LoadC) are applied. .

  The outputs of the counter A51, the counter B52, and the counter C53 are supplied to the majority logic and error counter determination unit 54. In the majority logic circuit 541, as in FIG. 6, the outputs of the counter A51, the counter B52, and the counter C53 are output by taking the majority logic for each bit.

  In the case of the figure, the second bit of the counter B52 is incorrect. The error counter discriminating circuit 542 detects this error.

  When the error counter determination circuit 542 detects an error, the load signal B is supplied to the counter B52, and the correct count value “00000101”, which is the output of the majority logic circuit 54, is loaded. The error counter determination circuit 542 may determine the error counter every time a clock is input, or may determine the error counter at appropriate intervals (for example, every 8 bits).

  FIG. 8 shows an example of the error counter discrimination circuit. The error counter discriminating circuit in FIG. 8 includes exclusive OR circuits 61, 62, 63 and AND circuits 64, 65, 66.

  Here, the i-bit value of the counter A is Ai, the i-bit value of the counter B is Bi, and the i-bit value of the counter C is Ci.

The exclusive OR circuit 61 outputs “1” when the value of Ai is different from the value of Bi,
The exclusive OR circuit 62 outputs “1” when the Bi value and the Ci value are different, and the exclusive OR circuit 63 outputs “1” when the Ci value and the Ai value are different. Is output.

  Therefore, when the i-bit value (Bi) of the counter B is incorrect, the logical product circuit 64 outputs “1” (Y1), and the logical product circuit 65 outputs the i-bit value ( When Ci) is incorrect, “1” is output (Y2), and from the AND circuit 66, when the i-bit value (Ai) of the counter A is incorrect, “1” is output (Y3). ).

(Third embodiment)
The third embodiment relates to a reset signal and a clock signal. FIG. 9 shows a counter corresponding to FIG.

A set of counters A, B, and C is provided corresponding to each of the upper electrodes (32 striped electrodes) of the detection element 30. Therefore, there are 32 counter sets (350 _{1 to} 350 ₃₂ ).

  A clock signal and a reset signal are supplied to the 32 sets of the counter A, the counter B, and the counter C from the clock source 401 and the master counter 402 installed in the shielding region 400.

  The reset signal is output when the lower 8-bit 0 detector 403 detects that all the lower 8 bits of the master counter 402 are “0”. Therefore, the reset signal is output every time the lower 8 bits of the master counter 402 are all “0”. As a result, the 32 sets of the counter A, the counter B, and the counter C are periodically reset.

  Since the measurement of radiation detection takes about 2 hours, a master counter 402 that can cope with the measurement is used. Although the figure is a 48-bit master counter, a 32-bit counter may be used.

  Since the counter A, the counter B, and the counter C are 8-bit counters, the upper 40 bits of the master counter 402 are used for the time that cannot be measured by the 8-bit counter.

(Example)
FIG. 10 shows a circuit example for explaining the operation related to the i-th bit of the counter A51, the counter B52, and the counter C53 of FIG. The circuit in FIG. 10 includes counters 51, 52, 53, exclusive OR circuits 74, 75, 76, AND circuits 77, 78, 79, 86, 87, 88, and OR circuits 80, 81, 82, 89. It is configured. Circuits other than the logical sum circuits 80, 81, 82, and 89 are provided for each bit of the counter, and the circuits of the logical sum circuits 80, 81, 82, and 89 are shared by the processing circuits for each bit of the counter. Circuit. That is, circuits other than the logical sum circuits 80, 81, 82, and 89 are provided for the first bit, the second bit,... Every eighth bit when the counter 51, the counter 52, and the counter 53 are 8-bit counters. Thus, one of the OR circuits 80, 81, 82 and 89 is provided for each circuit provided for each bit.

  Assuming that the i-bit value of the counter A51 is Ai, the i-bit value of the counter B52 is Bi, and the i-bit value of the counter C53 is Ci, the logical product circuit 77 receives the counter as in the operation of FIG. “1” is output when the i-bit value (Ai) of A51 is incorrect, and the logical product circuit 78 outputs “1” when the i-bit value (Bi) of the counter B52 is incorrect. Is output from the AND circuit 79 when the i-bit value (Ci) of the counter C53 is incorrect. The outputs of the AND circuits 77, 78, 79 are inverted and supplied to the AND circuits 86, 87, 88.

  Therefore, since the i-bit value Ai of the counter A51 and the inverted output from the AND circuit 77 are input to the AND circuit 86, the output of the AND circuit 86 outputs Ai when Ai is correct. If Ai is incorrect, Ai is not output.

  Similarly, Bi and Ci are output from the outputs of the AND circuits 87 and 88 when Bi and Ci are correct, respectively, and Bi and Ci are not output when Bi and Ci are incorrect.

  As a result, the i-th correct value is output from the OR circuit 89.

  The OR circuit 80 is supplied with all 8-bit signals other than i bits. That is, a signal indicating whether the 8-bit value of the counter A is correct or incorrect is applied. If the value of a certain bit of the counter A is correct, a signal of “0” is supplied, and if it is incorrect, a signal of “1” is supplied. Therefore, if the output of the OR circuit 80 is “0”, it indicates that all the 8-bit values of the counter A are correct.

  On the other hand, if any of the 8 bits of the counter A is incorrect (at least one), the output of the OR circuit 80 is “1”.

  Therefore, the output of the OR circuit 80 being “1” indicates that there is an error in the count value of the counter A51.

  Similarly, “1” is output from the OR circuit 81 when the count value of the counter B52 is incorrect, and “1” is output from the OR circuit 82 when the count value of the counter C53 is incorrect. Is output.

  Since the output of “1” from the OR circuit 80, 81 or 82 indicates that the counter 51, 52 or 53 is malfunctioning, the output signal of “1” is loaded to each counter. It can be a signal.

  By using this load signal, an error in the counter can be detected for each bit, and a correct value can be set in the erroneous counter for each bit.

  In the above description, the case where a counter error is detected for each bit and a correct value is set for each bit has been described. However, if the counter is not frequently erroneous, the load signal may not be performed for each bit. Instead, a load signal may be supplied to the wrong counter every 8 bits, and a correct value may be set every 8 bits.

(Other)
The counter can be reset using a known technique. FIG. 11 is a diagram for explaining the reset of the asynchronous 4-bit up counter using the JK flip-flop circuit.

  When the reset signal is supplied to the clear terminals (CLR) of the counters 91, 92, 93, 94, the outputs of the counters 91, 92, 93, 94 are reset to “0000”.

  Setting the value of the counter to a predetermined value can also be realized using a known technique. FIG. 12 is a diagram for explaining a predetermined value set of an asynchronous 4-bit up counter using a JK flip-flop circuit.

  When the load signal and the count value to be loaded are supplied to the clear terminals (CLR) and preset terminals (PR) of the counters 95, 96, 97, 98, the outputs of the counters 91, 92, 93, 94 are predetermined values. Set to

  In the figure, if the set inputs D1, D2, D3, and D4 are “0101”, the outputs of the counters 95, 96, 97, and 98 are “0101” after setting.

  In the above description, the case of the counter for specifying the time of incidence by the radiation detection element has been described. However, the counter of the present invention is not limited to the counter for specifying the time, and is detected by the radiation detection element. It may be a counter in a detection signal processing circuit that processes the detected signal.

  Moreover, although the case of triple is described as the counter, the present invention can be applied to the case of triple or more.

  Although the best mode for carrying out the invention has been described above, the present invention is not limited to the embodiment described in the best mode. Modifications can be made without departing from the spirit of the present invention.

It is a figure for demonstrating the principle (the 1) of positron CT. It is a figure for demonstrating the principle (the 2) of positron CT. It is a figure for demonstrating a radiation detection apparatus (the 1). It is a figure for demonstrating the rising characteristic of a detection signal. It is a figure for demonstrating a radiation detection apparatus (the 2). It is a figure for demonstrating the structure (the 1) of a counter part. It is a figure for demonstrating the structure (the 2) of a counter part. It is a figure for demonstrating an error counter discrimination circuit. It is a figure for demonstrating a reset signal and a clock. It is a figure for demonstrating the operation | movement regarding the i-th bit. It is a figure for demonstrating reset of a counter. It is a figure for demonstrating the setting of the predetermined value to a counter.

Explanation of symbols

29, 290 Detection signal processing circuit 30, 300 Detection element 31, 310 Preamplifier 32, 33, 34, 320 Comparator 35, 41, 42, 43, 51, 52, 53, 350 Counter 36, 37, 360, 370 Latch circuit 38 380 Incident time calculation circuit 44, 541 Majority logic circuit 54 Majority logic and error counter determination unit 401 Clock source 402 Master counter 542 Error counter determination circuit

Claims (9)

In a radiation detection apparatus comprising: a radiation detection element; and a detection signal processing circuit that processes a detection signal detected by the radiation detection element and includes a counter.
A (A is a natural number of 3 or more) counters redundantly provided as the counters;
A correct / error discriminating circuit for discriminating whether the output of the A counters is correct or not,
The radiation detection apparatus according to claim 1, wherein the correctness determination circuit determines the correctness of the outputs of the A counters by a majority logic and outputs a correct value. Having an error counter discriminating circuit for discriminating an erroneous counter;
The radiation detection apparatus according to claim 1, wherein a count value of an erroneous counter determined by the error counter determination circuit is corrected by an output of the correctness determination circuit. A master counter is provided separately from the A counters,
The radiation detection apparatus according to claim 1, wherein the A counters are simultaneously reset at a predetermined cycle according to an output of the master counter.   The radiation detection apparatus according to claim 3, wherein the master counter is provided in a place where the detected radiation is not irradiated.   5. The radiation detection apparatus according to claim 3, wherein each of the A counters is an N-bit counter, and the master counter is an M (where M> N) bit counter.   6. The radiation detection apparatus according to claim 5, wherein when the lower N bits of the master counter are all 0, the A counters are simultaneously reset. The semiconductor detection element includes a semiconductor crystal body, one first electrode that substantially covers one surface of the semiconductor crystal body, and a plurality of stripe-shaped second electrodes provided on the other surface. , The detection signal is output from each of the second electrodes,
The plurality of radiation detection devices sharing the semiconductor crystal constitute one block, and the A counters are provided for each block. The radiation detection apparatus described. The detection signal processing circuit includes a plurality of comparators that compare a detection signal detected by the radiation detection element with a reference voltage, a counter for specifying a detection time of radiation, and the count value of the counter A latch circuit that latches by the output of the detector, and an incident time calculation circuit that calculates the time of incidence by the radiation detection element based on the output of the latch circuit,
The radiation detection apparatus according to claim 1, wherein reference voltages of the plurality of comparators are different from each other.   A radiation detection element in the radiation detection apparatus according to claim 1 is provided around the subject, and a part of the subject that has emitted radiation is detected based on an output of the radiation detection apparatus. Characteristic radiological examination apparatus.

Images