JP2007034520A - Information processor and information processing method for controlling configuration - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and quickly change the configurations of a plurality of FPGA without rewriting a non-volatile memory. <P>SOLUTION: As for a device for selecting a plurality of configuration memories and one of configuration data stored in the memory are selected, and for transferring them to an FPGA to perform the configuration of the FPGA, the FPGA which has received the configuration data transfers a reception completion signal, and shifts it to the configuration of the FPGA in the next stage for easily and quickly executing the configuration of the FPGA in a field. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly to a configuration control method in an information processing apparatus using an FPGA.

  The FPGA is a kind of gate array, can manage input / output terminal information as a logic circuit and internal logic function circuit information as configuration data, and can change the logic circuit in the field. Widely used in processing systems and communication systems.

  The configuration data is stored in an external memory different from the FPGA, read out from the memory as necessary, written into the FPGA, and the hardware based on the configuration data is determined by defining the configuration of the FPGA. Functions can be realized. In addition, there is a feature that the hardware function can be easily changed by writing configuration data different from the configuration data stored in the external memory into the FPGA.

  When the scale of hardware to be realized is larger than the scale of a single FPGA, a plurality of FPGAs are prepared, the configuration data is divided, and the divided configuration data is distributed to each of the plurality of FPGAs. The target hardware function can be realized.

  Configuration data is stored in a non-volatile memory such as a flash memory or EPROM, converted to an FPGA interface, and then transferred to the FPGA.

Updating the configuration of the FPGA is realized by reading the configuration data for FPAG stored in the nonvolatile memory, transferring the data to each FPGA, and writing it.
JP 2000-21867 A

  The FPGA reads the configuration data and has the convenience of realizing the hardware function based on the configuration data, but for the purpose of optimizing the hardware and correcting the function, There may be hardware changes in the field. When changing the hardware function in the field, the configuration of the FPGA is changed by transferring and writing the configuration data from the nonvolatile memory to the FPGA. However, if the amount of hardware change is large, the stored configuration data may be insufficient, and it is necessary to rewrite the configuration data itself stored in the nonvolatile memory.

  When the nonvolatile memory is composed of a flash memory, in order to rewrite the data in the memory, first, the data including the rewrite area is erased in units of sectors having a certain size, and then the data to be changed is stored. Need to write. In this case, the size of the data area that needs to be rewritten may differ from the size of the sector for batch erasure set in each flash memory. In that case, after the data of the sector unit area including the area that needs to be rewritten is temporarily saved in a memory such as another SRAM or DRAM, the entire data in the sector of the flash memory is collectively erased, It is necessary to write data saved in the memory and data obtained by rewriting a part thereof to the flash memory. For this purpose, it is necessary to manage the address space of the rewrite area and the address space of the area that does not need to be rewritten, and an extra memory such as SRAM or DRAM for temporarily storing data to be saved, A control circuit required for the address management is required.

  In addition, when the nonvolatile memory is composed of EPROM, partial erasure is not possible as with flash memory, so it is necessary to erase the entire data, and additional memory and its control circuit are required to save data. become. In addition, an erasing ultraviolet ray generator is required for erasing data in the EPROM.

  In order to rewrite the nonvolatile memory in the field, the above-described extra memory and its control circuit or device are required, and there is a problem that hardware change by the FPGA cannot be easily and quickly performed.

  The present invention solves the above-described problems, prepares a plurality of configuration memories for storing a plurality of configuration data, and without rewriting the nonvolatile memory storing the configuration data, An object of the present invention is to provide an information processing apparatus capable of easily changing a configuration of an FPGA in a field by selecting configuration data necessary for the FPGA from the configuration memory and transferring the configuration data to the FPGA. .

  In order to achieve the above object, the present invention provides an information processing apparatus that includes a plurality of configuration memories that store configuration data of a plurality of FPGAs and controls the configurations of the plurality of FPGAs. Selecting means for selecting one of a plurality of configuration memories, selecting one from a plurality of configuration data stored in the configuration memory, and transferring the selected configuration data to the FPGA; The FPGA that received the configuration data transmits a reception completion signal of the configuration data to the selection unit, and the selection unit selects configuration data of the next-stage FPGA connected to the FPGA, and The FPGA By transferring configuration data, without requiring a rewriting of the nonvolatile memory FPGA configuration in the field, it can be done efficiently and quickly.

  According to the information processing apparatus of the present invention, it is possible to easily, efficiently and quickly change the FPGA configuration in the field.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment showing an information processing system that facilitates changing the configuration of an FPGA according to the invention will be described with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of an information processing apparatus for FPGA configuration according to an embodiment of the present invention. In FIG. 1, m sets of configuration memories 1 are prepared, and a nonvolatile memory 2 and an interface conversion circuit 3 are mounted on each configuration memory 1.

  The interface conversion circuit 3 is a circuit for converting different interfaces between the nonvolatile memory 2 and the FPGA 5. The output of the interface conversion circuit 3 is connected to the selection unit 7 via the connection unit 4, and the output of the selection unit 7 is further connected to the configuration interface 8. N FPGAs 5 are connected in series to the configuration interface 8. Here, the connection unit 4 is a terminal or a contact for connecting the configuration memory 1 and the selection unit 7.

  Configuration data stored in the configuration memory 1 is selected by the selection unit 7 and supplied to the FPGA 5 via the configuration interface 8. Each output of the plurality of FPGAs 5 forms a serial daisy chain connected to the input of the next stage FPGA 5. When configuration data is supplied from the selection unit 7, the configuration data is supplied to the target FPGA 5. Each FPGA is configured.

  The selection unit 7 is connected to a switch unit 6 for supplying setting data for setting configuration data to be supplied to each FPGA 5. The switch unit 6 stores setting information as to which of the configuration data supplied from the configuration memory is applied to any of the FPGAs 5 connected in series. Based on this setting information, the selection unit 7 selects configuration data from the configuration memory 1 and supplies it to the FPGA 5 connected in series.

  When the configuration of each FPGA is completed, logic data is input to the FPGA, and the result appears at the output terminal 10 of the FPGA, thereby realizing a hardware function based on the configuration data.

  FIG. 2 is an example conceptually showing a state in which configuration data is stored in the configuration memory. In FIG. 2, data stored in the first configuration memory 21, the second configuration memory 22, and the m-th configuration memory 23 are illustrated. In order to simplify the description, a space between the second configuration memory and the mth configuration memory is omitted.

  In FIG. 2, among the FPGAs 5 connected in series to the first configuration memory 21, data 11 supplied to the first FPGA 5, data 21 supplied to the second FPGA 5, and supplied to the nth FPGA 5. Data n1 is stored. The second configuration memory 22 stores data 12 supplied to the first FPGA 5, data 22 supplied to the second FPGA 5, and data n 2 supplied to the n-th FPGA 5. In the m-th configuration memory 23, data 1m to be supplied to the first FPGA 5, data 2m to be supplied to the second FPGA 5, and data nm to be supplied to the n-th FPGA 5 are stored. .

  FIG. 3 shows an example of configuration data supplied to each FPGA. In FIG. 3, the data 12 of FIG. 2 is supplied to the first FPGA (32), the data 21 of FIG. 2 is supplied to the second FPGA (33), and the data nm of FIG. 2 is supplied to the nth FPGA. (34) is shown. Note that the data 21 and the data nm are omitted for the sake of simplicity.

  In order to supply the data to each FPGA, the data in the configuration memory in FIG. 2 is selected as follows. That is, the first configuration memory 21 selects the data 21 supplied to the second FPGA, the second configuration memory 22 selects the data 12 supplied to the first FPGA, and the mth In the configuration memory 23, data nm to be supplied to the nth FPGA is selected.

  It is also possible to select a plurality of FPGA configuration data from the same configuration memory. As an example, the first configuration memory 21 selects the data 21 supplied to the second FPGA and the data n1 supplied to the nth FPGA, and the second configuration memory 22 selects the first FPGA. Data 12 to be supplied may be selected.

  The flow of information processing will be described with reference to FIG. Information necessary for supplying configuration data to each FPGA is set in the switch unit 6. For example, information on the number of the configuration memory 1 and the number of the configuration data stored in the configuration memory 1 is set in the switch unit 6 as the first FPGA setting data. Similar information is set in the switch unit 6 for the second and subsequent FPGAs. The setting data necessary for each FPGA of the switch unit 6 can be set by providing a memory function or a register function for storing the setting data in the switch unit 6.

  When any of the configuration memories 1 is selected by the selection unit 7 for each FPGA according to the setting data set by the switch unit 6, any of the configuration data stored in the selected configuration memory 1 is selected. Is selected based on the setting data. The configuration data selected by the selection unit 7 is output to the configuration interface 8 and transferred to the FPGA 5 connected in series. Configuration data based on the setting data is stored in the target FPGA 5, and the configuration of the FPGA 5 is completed. When the configuration of the FPGA 5 is completed, a reception completion signal is transmitted from the FPGA 5 to the selection unit 7.

  Subsequently, one of the new configuration memory 1 and configuration data is selected for the FPGA 5 whose reception completion signal has not been received by the selection unit 7 based on the setting data set by the switch unit 6. To the FPGA 5, and the FPGA 5 is configured. When the configuration of the FPGA 5 is completed, a reception completion signal is transmitted from the FPGA 5 to the selection unit 7.

  On the other hand, when the selection unit 7 has already received the configuration data reception completion signal of the FPGA 5, the configuration data is not supplied to the FPGA 5, and control can be transferred to the FPGA 5 in the next stage. Efficient configuration data transfer is realized for all the FPGAs 5.

  In order to change the combination of the configuration data of each FPGA, the number of the configuration memory and the number of the configuration data in the configuration memory stored in the switch unit 6 are changed and sent to the selection unit. Based on the setting data, the selection unit 7 selects the configuration memory, selects configuration data in the configuration memory, transfers the configuration data to the FPGA, and performs configuration.

  According to the above procedure, it is not necessary to rewrite the contents of the nonvolatile memory in the configuration memory, and the FPGA can be efficiently configured. Further, since an extra memory required for rewriting the nonvolatile memory and its control circuit are unnecessary, the cost can be reduced.

  In addition, by connecting the configuration memory 1 with a detachable component such as a socket or a connector at the connection unit 4 and replacing the configuration memory 1 with a configuration memory storing other configuration data, It is possible to easily and quickly change the hardware function by the FPGA in the field.

  Further, although the FPGA has been described above, the present invention can be similarly applied to a reconfigurable circuit in that configuration can be performed. The term reconfigurable circuit is referred to as FPGA in this specification. Including explanation.

The present invention discloses the invention described in the following supplementary notes.
(Appendix 1)
An information processing apparatus having a plurality of configuration memories for storing configuration data of a plurality of FPGAs (field programmable gate arrays) and controlling the configuration of the plurality of FPGAs,
Selecting means for selecting one of the plurality of configuration memories, selecting one of the plurality of configuration data stored in the configuration memory, and transferring the selected configuration data to the FPGA;
When the FPGA that has received the configuration data completes reception of the configuration data, the selection unit selects configuration data of the next-stage FPGA connected to the FPGA, and the FPGA of the next stage receives the configuration data. An information processing apparatus for transferring configuration data.
(Appendix 2)
The information processing apparatus according to appendix 1, further comprising storage means for storing information for selecting the configuration data and supplying the information to the selection unit.
(Supplementary note 3) The information processing apparatus according to supplementary note 2, wherein the plurality of FPGAs are connected in series.
(Appendix 4)
The information processing apparatus according to appendix 3, wherein the configuration memory includes a nonvolatile memory and an interface circuit.
(Appendix 5)
An information processing method comprising a plurality of configuration memories for storing configuration data of a plurality of FPGAs (field programmable gate arrays) and controlling the configurations of the plurality of FPGAs,
Selecting one of the plurality of configuration memories, selecting one of the plurality of configuration data stored in the configuration memory, transferring the selected configuration data to the FPGA,
When the FPGA that has received the configuration data generates a reception completion signal of the configuration data, the configuration data of the next-stage FPGA connected to the FPGA is selected, and the configuration data is selected in the next-stage FPGA. An information processing method characterized by transferring data.
(Supplementary note 6) The information processing apparatus according to supplementary note 4, wherein the configuration memory is detachable.

  Hardware modification and change using FPGA can be performed easily and quickly in the field.

It is a block diagram which shows the structure of the information processing system for the configuration for FPGA of this invention. It is a figure explaining a configuration memory. It is a figure explaining the data in FPGA.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Configuration memory 2 ... Non-volatile memory 3 ... Interface conversion circuit 4 ... Connection part 5 ... FPGA
6 ... Switch unit 7 ... Selection unit 8 ... Configuration interface 10 ... Output terminal

Claims (5)

An information processing apparatus having a plurality of configuration memories for storing configuration data of a plurality of FPGAs (field programmable gate arrays) and controlling the configuration of the plurality of FPGAs,
Selecting means for selecting one of the plurality of configuration memories, selecting one of the plurality of configuration data stored in the configuration memory, and transferring the selected configuration data to the FPGA;
When the FPGA that has received the configuration data completes reception of the configuration data, the selection unit selects configuration data of the next-stage FPGA connected to the FPGA, and the FPGA of the next stage receives the configuration data. An information processing apparatus for transferring configuration data.   The information processing apparatus according to claim 1, further comprising a storage unit that stores information for selecting the configuration data and supplies the information to the selection unit. The information processing apparatus according to claim 2, wherein the plurality of FPGAs are connected in series.   4. The information processing apparatus according to claim 3, wherein the configuration memory includes a nonvolatile memory and an interface circuit. An information processing method comprising a plurality of configuration memories for storing configuration data of a plurality of FPGAs (field programmable gate arrays) and controlling the configurations of the plurality of FPGAs,
Selecting one of the plurality of configuration memories, selecting one of the plurality of configuration data stored in the configuration memory, transferring the selected configuration data to the FPGA,
When the FPGA that has received the configuration data generates a reception completion signal of the configuration data, the configuration data of the next-stage FPGA connected to the FPGA is selected, and the configuration data is selected in the next-stage FPGA. An information processing method characterized by transferring data.

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