JP2007034321A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device having a video signal driving circuit which can apply less deteriorating video signals to drain wiring while reducing the number of output pins of a driver IC and is reduced in electric power consumption. <P>SOLUTION: The video signals are outputted by time sharing from a drain driver used for the video signal driving circuit and are distributed by a distribution circuit to the corresponding drain wiring. Two distribution control signals common to another distribution circuit at each one switch used for the distribution circuit are used to raise the voltage of the gates of the switch in two stages to the distribution control signal or above, and the voltage of the gate of the switch is made sufficiently higher than the voltage amplitude of the video signal and the video signal is outputted to the drain wiring. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix display device.

  As an active matrix display device, for example, a liquid crystal display device is known.

  As an example of such an active matrix display device, a plurality of gate wirings extending in the x direction and arranged in parallel in the y direction on the substrate, and extending in the y direction so as to intersect the gate wirings. It is known that a drain wiring lined up in the x direction is formed to form a matrix. In correspondence with this matrix, pixels having active elements connected to the gate wiring and the drain wiring are arranged in a matrix. A scanning signal is applied to the gate wiring from the scanning driving circuit, thereby turning on the active element of the pixel. On the other hand, a video signal is applied to the drain wiring from the video signal driving circuit, and the video signal is written into the pixel through the active element that is turned on, and display is performed according to the signal. In the case of a liquid crystal display device, a thin film transistor (TFT) is generally used as an active element, and a video signal is generally written to a pixel electrode.

  Here, when amorphous silicon (amorphous silicon, a-Si) is used for the semiconductor layer of the thin film transistor, the scanning drive circuit and the video signal drive circuit are provided as separate driver ICs. In the case of using polycrystalline silicon (polysilicon, p-Si), all or part of the scanning drive circuit and the video signal drive circuit are integrally formed on a substrate of a display panel on which pixels are formed, not separate components. Things are known.

  FIG. 21 is a diagram showing an example of a conventional scan driving circuit. The scan driving circuit 300 includes a shift register 301, a level shifter 302, and a buffer 303. These are integrally formed on the substrate using polysilicon thin film transistors. The output of each stage of the shift register 301 is level-converted by the level shifter 302, and is applied as a scanning signal to the gate wirings GLn, GLn + 1,. The level shifter 302 is composed of a CMOS (complementary) circuit. A CMOS circuit is a circuit in which both a P-channel MOS transistor (hereinafter simply referred to as PMOS) and an N-channel MOS transistor (hereinafter simply referred to as NMOS) are mixed.

  As a document related to this prior art, for example, there is Patent Document 1. This document describes a driving circuit integrated liquid crystal display device in which a vertical driver corresponding to a scanning driving circuit and a horizontal driver corresponding to a video signal driving circuit are integrally formed on a substrate using polysilicon thin film transistors. The vertical driver includes a shift register, a level shift circuit, and a buffer. This level shift circuit is a CMOS circuit having a CMOS latch cell and a CMOS inverter.

  In addition to this, there is Patent Document 2 as a document related to the scan drive circuit. In this document, a driver circuit on the side of a gate line (gate wiring) for an active matrix and a driver circuit on the side of a data line (drain wiring) are formed (integrated) in a substrate. The scanning drive circuit is not a CMOS circuit, and the thin film transistor used is composed of only one of N-channel and P-channel polysilicon thin film transistors. Also, no level shift circuit or buffer is used. The shift register is composed of a shift register cell, and the shift register cell is composed of four transistors and one bootstrap capacitor.

  Patent Document 2 described above describes an example in which a shift register that performs a bootstrap operation is used in the data line side driving circuit. The shift register cell includes a bootstrap capacitor and three transistors. The output from the shift register cell is input to the gate of the sample and hold transistor. Since this gate input is applied with an amplitude nearly twice that of the clock signal by a bootstrap operation, it is switched at a high speed.

  In addition to this, in Patent Document 3, as an example of a video signal driving circuit, in a thin film scanning circuit configured to sequentially select gates of analog switches made of thin film transistors by a gate selection circuit made of complementary (CMOS) thin film transistors, The first electrode of the MOS capacitor having the same structure as the thin film transistor is connected to the gate of the analog switch, and the second electrode of the MOS capacitor is connected to one of the internal terminals of the thin film scanning circuit. Has been. The gate selection circuit is a logic circuit using complementary TFTs, such as a shift register. Note that the gate of this gate selection circuit does not mean the gate of the gate wiring of the active matrix panel, but the gate of the analog switch in the video signal driving circuit. Therefore, this gate selection circuit is used not in the scanning signal driving circuit but in the video signal driving circuit. With such a configuration, the gate of the analog switch is raised to nearly twice the power supply voltage by the bootstrap effect of the MOS capacitor, and the load driving capability of the analog switch is increased. Then, the video signal is applied to the video signal line (corresponding to the drain wiring) through the analog switch that is turned on.

  As another example of the video signal driving circuit, there is Patent Document 4. In this document, the video signal driving circuit is composed of a switch for transferring a video signal and a circuit for driving the switch. The circuit for driving the switch has a shift register and boosting means for boosting the output of the shift register. The boosting means is formed using a transistor, a capacitive element, and a diode. With such a configuration, the power supply voltage applied to each transistor in the shift register and the booster circuit can generate a high voltage of 12.3 V while maintaining a low voltage of 7 V, and an 11 V amplitude signal (video signal) ). This boosting means uses two or more of the shift register outputs for one switch, and a plurality of switches share a part of the same shift register output. Further, NMOS or PMOS is used for the thin film transistor. This document also describes that the active element, the transfer switch, the shift register, and the boosting means are desirably fabricated integrally on the same substrate (on the same substrate) as a semiconductor integrated circuit.

  As another example of the video signal driving circuit, there is Patent Document 5. In this document, the video signal driving circuit is composed of a driver IC disposed on a tape carrier as an external circuit of the LCD panel, and a time division switch formed on the LCD panel. A pixel signal (video signal) is output from the driver IC as a time-series signal corresponding to the number of time divisions (3 in this document). The time-series pixel signals are sampled in a time division manner by a time division switch and supplied to corresponding signal lines (drain wirings corresponding to R, G, and B in this document). Thereby, the number of output pins of the driver IC can be reduced more than the number of drain wirings. An analog switch is used as the time division switch. One set of time-division switches is composed of a transmission switch having a CMOS configuration of three PchMOS transistors and three NchMOS transistors, and is formed of polysilicon TFTs on the same substrate as the LCD panel. These are controlled by a total of six control lines comprising three selection signals and inverted signals of these three selection signals.

JP 2000-305504 A Japanese Patent Laid-Open No. 5-243777 JP-A-62-66291 JP-A-5-281517 JP 2000-275611 A

  However, the apparatuses described in these documents have the following problems.

  First, regarding the scan drive circuit, in FIG. 21 and Patent Document 1, since a CMOS circuit is used for the level shift circuit, it is necessary to form both PMOS and NMOS in the manufacturing process, which increases the number of processes. . In the gate side drive circuit of Patent Document 2, a CMOS circuit, a level shift circuit, and a buffer are unnecessary by using a bootstrap capacitor in the shift register, but the voltage once rises as a scanning signal on the gate line (gate wiring). Then, a signal that further increases the voltage by one step is applied.

  Further, regarding the video signal driving circuit, Patent Document 5 describes an example using a time division switch, but the number of manufacturing processes increases because of the CMOS configuration. In this document, it is described that it is possible to use a PMOS or NMOS transmission switch, but a specific configuration example is not described. It seems to be controlled by three control lines. However, in the case of a PMOS or NMOS configuration, that is, a single channel configuration, if the voltage of the control line inputted to the gate of the analog switch used for the time division switch is close to the voltage of the video signal, the switch is made by the transistor resistance There is a problem that the voltage of the video signal changes before and after.

  As for the video signal drive circuit, Patent Document 2, Patent Document 3 and Patent Document 4 describe an example using a bootstrap effect when an analog switch is turned on in the video signal drive circuit. Is not described, and it is premised on the use of a shift register, and the combination with a time division switch is not considered.

  A first object of the present invention is to provide a display device having a scan driving circuit with a high degree of freedom in designing a waveform of a scan signal while reducing power consumption.

  A second object of the present invention is to provide a display device having a video signal driving circuit with low power consumption that can apply a video signal with little deterioration to the drain wiring while reducing the number of output pins of the driver IC.

  A third object of the present invention is to provide a display device with a small number of manufacturing processes.

  To achieve the first object of the present invention, the shift register used in the scan drive circuit is driven at a voltage lower than the voltage amplitude of the scan signal, and a booster circuit is provided corresponding to each stage of the shift register, A common scanning signal common to other boosting circuits is input to the boosting circuit as a signal different from the shift register output, and the scanning signal is selected from the common scanning signal in a period selected by the shift register output. Output to the gate wiring.

  In order to achieve the second object of the present invention, a video signal is output in a time-sharing manner from a drain driver used in a video signal driving circuit, and is distributed to a corresponding drain wiring by a distribution circuit. For each switch used in the circuit, the voltage of the switch gate is raised to a level higher than the distribution control signal in two steps by using two common distribution control signals with other distribution circuits, and the switch gate voltage is changed to the video signal. The video signal is output to the drain wiring by making it sufficiently larger than the voltage amplitude.

  In order to achieve the third object of the present invention, the channel of the thin film transistor used in the portion of the driving circuit integrally formed on the substrate is the same as the thin film transistor of the pixel.

  A typical configuration of a display device that achieves the first object of the present invention is listed as follows. In the case of the single channel configuration, the third object of the present invention can be achieved.

(1) a substrate;
A plurality of gate wirings formed on the substrate;
A plurality of drain wirings formed on the substrate and intersecting the plurality of gate wirings;
A plurality of pixels having thin film transistors connected to the gate wiring and the drain wiring;
A scan driving circuit formed on the substrate and applying a scan signal to the gate wiring;
A display device comprising a control circuit for supplying signals necessary for the scan driving circuit,
The scan driving circuit includes: a shift register that outputs a plurality of stages corresponding to each of the plurality of gate wirings; and one of the plurality of stages of outputs of the shift register that receives the scanning signal A plurality of drive units that output to the wiring,
A common scanning signal, which is a row of a plurality of scanning signals having a voltage amplitude larger than that of the shift register output, is commonly input from the control circuit to the two or more driving units
The drive unit receives the output of the shift register and the common scanning signal input to the driving unit, and a period during which the output of the shift register is input among a plurality of scanning signal columns of the common scanning signal And a step-up circuit that selects a signal input to the output and outputs a scanning signal having a voltage amplitude larger than that of the shift register output to the corresponding gate wiring.

(2) In (1), the driving unit has one or more thin film transistors and is integrally formed on the substrate,
The thin film transistor used for the pixel and the driver is a single channel.

In (3) and (2), the booster circuit includes first and second thin film transistors having a gate electrode, a first electrode, and a second electrode, and a capacitor having a first electrode and a second electrode. And
A gate electrode of the first thin film transistor is connected to a DC voltage signal;
A first electrode of the first thin film transistor is connected to an output of the shift register;
A second electrode of the first thin film transistor is connected to a gate electrode of the second thin film transistor and a first electrode of the capacitor;
A first electrode of the second thin film transistor is connected to the common scanning signal;
The second electrode of the second thin film transistor is connected to the second electrode of the capacitor and the gate wiring.

In (4), (2), or (3), the shift register includes one or more thin film transistors and is integrally formed on the substrate.
The thin film transistors used for the pixel, the driver, and the shift register are single-channel.

  (5) In any one of (1) to (4), the drive unit applies an off potential of the thin film transistor of the pixel to the gate wiring during a period in which the output from the shift register is not input to the booster circuit. It has a reset circuit to apply.

  (6) In (5), the reset circuit includes an inverting circuit for inverting the output from the shift register.

  (7) In any one of (1) to (6), the drive unit includes a changeover switch circuit that switches between stop and permission of the operation of the booster circuit.

  (8) In (7), the first and second changeover switch signals are input to the changeover switch circuit, a ground potential is input to the first changeover switch signal, and a direct current is applied to the second changeover switch signal. The operation of the booster circuit is stopped during a period in which the voltage signal is input, and when the DC voltage signal is input to the first changeover switch signal and the ground potential is input to the second changeover switch signal, the booster circuit It is a circuit that permits the operation of

  In (9), (7) or (8), the control circuit controls the shift clock in a state in which the operation of the booster circuit is stopped by controlling the changeover switch circuit before starting the display. After at least one round of scanning, the operation of the booster circuit is permitted and display is started.

In any one of (10), (1) to (9), the common scanning signal is transmitted by the first common scanning signal wiring and the second common scanning signal wiring transmitted by the first common scanning signal wiring. A second common scanning signal having a phase different from that of the first common scanning signal;
The booster circuit is divided into a first group in which the first common scanning signal is input in common and a second group in which the second common scanning signal is input in common and does not belong to the first group. It is characterized by being.

(11) In (10), the booster circuit corresponding to the gate wiring in the odd-numbered row belongs to the first group,
The booster circuit corresponding to the gate wiring in the even-numbered row belongs to the second group.

(12) In any one of (1) to (11), a counter substrate disposed to face the substrate;
And a liquid crystal layer sandwiched between the substrate and the counter substrate.

  A typical configuration of the display device that achieves the second object of the present invention is listed as follows. In the case of the single channel configuration, the third object of the present invention can be achieved.

(13) a substrate;
A plurality of gate wirings formed on the substrate;
A plurality of drain wirings formed on the substrate and intersecting the plurality of gate wirings;
A plurality of pixels having thin film transistors connected to the gate wiring and the drain wiring;
A video signal driving circuit for applying a video signal to the drain wiring;
A display device comprising a control circuit for supplying a necessary signal to the video signal driving circuit,
The video signal driving circuit corresponds to a drain driver that outputs a video signal applied to two or more of the drain wirings to the common video signal wiring in a time division manner, and a video signal output to the common video signal wirings in a time division manner. A distribution circuit integrally formed on the substrate for distributing to the drain wiring;
The distribution circuit receives distribution control signals twice as many as the number of drain wirings corresponding to one common video signal wiring, and performs distribution control.
The distribution circuit is an n-type thin film transistor that is the same channel as the thin film transistor of the pixel, and each first electrode is connected to the common video signal line, and each second electrode is connected to a corresponding drain line. A plurality of thin film transistors in which the voltage of each gate electrode is controlled based on two corresponding ones of the distribution control signals,
The voltage of the gate electrode of the thin film transistor of the distribution circuit is increased to the first voltage based on the first of the two corresponding ones of the distribution control signals, and is higher than the first voltage based on the second. The second voltage is controlled to a voltage that is greater than the sum of the maximum value of the voltage of the video signal and the threshold voltage of the thin film transistor, and greater than the voltage of the distribution control signal,
The distribution control signal is commonly used for distribution of two or more common video signal lines.

  (14) In (13), the period in which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is longer than 50% of the period in which the voltage is higher than the first voltage. It is characterized by.

  (15) In (14), the period in which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is 75% or more of the period in which the voltage is equal to or higher than the first voltage. It is characterized by being.

  (16) In any one of (13) to (15), the distribution circuit is a circuit that distributes from one common video signal wiring to the drain wiring corresponding to each of red, green, and blue pixels. It is characterized by being.

(17) In any one of (13) to (16), a counter substrate disposed to face the substrate;
And a liquid crystal layer sandwiched between the substrate and the counter substrate.

(18) a substrate;
A plurality of gate wirings formed on the substrate;
A plurality of drain wirings formed on the substrate and intersecting the plurality of gate wirings;
A plurality of pixels having thin film transistors connected to the gate wiring and the drain wiring;
A video signal driving circuit for applying a video signal to the drain wiring;
A display device comprising a control circuit for supplying a necessary signal to the video signal driving circuit,
The video signal driving circuit corresponds to a drain driver that outputs a video signal applied to two or more of the drain wirings to the common video signal wiring in a time division manner, and a video signal output to the common video signal wirings in a time division manner. A distribution circuit integrally formed on the substrate for distributing to the drain wiring;
The distribution circuit receives distribution control signals twice as many as the number of drain wirings corresponding to one common video signal wiring, and performs distribution control.
The distribution circuit is a p-type thin film transistor that has the same channel as the thin film transistor of the pixel, and each first electrode is connected to the common video signal line, and each second electrode is connected to a corresponding drain line. A plurality of thin film transistors in which the voltage of each gate electrode is controlled based on two corresponding ones of the distribution control signals,
The voltage of the gate electrode of the thin film transistor of the distribution circuit is lowered to the first voltage based on the first of the two corresponding ones of the distribution control signals, and is lower than the first voltage based on the second. The second voltage is controlled to a voltage smaller than the sum of the minimum value of the video signal voltage and the threshold voltage of the thin film transistor and smaller than the voltage of the distribution control signal,
The distribution control signal is commonly used for distribution of two or more common video signal lines.

  (19) In (18), the period in which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is longer than 50% of the period in which the voltage is not more than the first voltage. It is characterized by.

  (20) In (18), the period in which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is 75% or more of the period in which the voltage is not more than the first voltage. It is characterized by being.

  (21) In any one of (18) to (20), the distribution circuit is a circuit that distributes from one common video signal wiring to the drain wiring corresponding to each of red, green, and blue pixels. It is characterized by being.

(22) In any one of (18) to (21), a counter substrate disposed to face the substrate;
And a liquid crystal layer sandwiched between the substrate and the counter substrate.

  Note that the present invention is not limited to the above-described configurations and examples described later, and various modifications can be made without departing from the technical idea of the present invention. Further, problems, configurations, and effects other than the above-described object will be clarified in the entire specification such as examples.

  As described above, according to the scan drive circuit of the present invention, it is possible to provide a display device having a scan drive circuit with a high degree of freedom in designing the waveform of a scan signal while reducing power consumption.

  Further, according to the video signal driving circuit of the present invention, it is possible to provide a display device having a video signal driving circuit with low power consumption that can apply a video signal with little deterioration to the drain wiring while reducing the number of output pins of the driver IC. it can.

  Furthermore, with a single channel configuration, a display device with a small number of manufacturing processes can be provided.

  Hereinafter, the present invention will be described with reference to examples and drawings. A liquid crystal display device will be described as an example of the display device according to the present invention.

[Description of overall configuration]
FIG. 1 is a plan view showing an example of a display panel used in a display device according to the present invention.

  SUB1 is a substrate, and SUB2 is a counter substrate, and glass, plastic, or the like is preferable. AR is a display area in which pixels (not shown) are arranged in a matrix, and a place other than the display area AR is called a frame area.

  On the substrate SUB1, a scanning drive circuit 10 for applying a scanning signal to a gate wiring GL (not shown) and a video signal circuit 201 for applying a video signal to a drain wiring DL (not shown) are provided. A gate-side connection terminal Tg connected to the outside is formed on the substrate SUB1, and supplies a control signal and power to the scan driving circuit 10. Further, a drain-side connection terminal Td connected to the outside is formed on the substrate SUB1, and supplies a video signal, a control signal, and power to the video signal circuit 201. The connection terminal Td is formed by bundling a plurality of lead wires at one place. An inspection circuit CC for inspecting disconnection of the drain wiring DL (not shown) is formed on the substrate SUB1.

  The substrate SUB1 and the counter substrate SUB2 are bonded to each other with a seal SL formed of, for example, an epoxy resin so as to surround the display area AR with a liquid crystal layer LC (not shown) interposed therebetween. The liquid crystal layer LC is sealed from the sealing opening INJ and sealed with, for example, an epoxy resin. The counter substrate SUB2 is smaller than the substrate SUB1, and is connected to the outside by connection terminals Td and Tg at the protruding portion of the substrate SUB1.

  FIG. 2 is a diagram showing an example of the display device according to the present invention, and is a plan view showing an example in which a circuit board is connected to the display panel.

  The circuit board PCB1 has a connector portion CJ that is connected to the outside of a power source SCC, a timing controller TCON, a personal computer, etc., and is supplied with power and signals. The circuit board PCB1 is connected to the connection terminal Tg on the gate side of the display panel via the flexible substrate GFPC on the gate side, and connected to the connection terminal Tg on the drain side of the display panel via the tape carrier package TCP. It is connected. On this tape carrier package TCP, a drain driver 200 which is a driving IC chip is mounted by a tape automated bonding method (TAB). The video signal driving circuit 20 includes the drain driver 200 and the video signal circuit 201.

  FIG. 3 is a diagram showing an example of an equivalent circuit of the display device according to the present invention.

  In the display area AR, a plurality of gate wirings GL (GL1, GL2,...) Extending in the horizontal direction in the figure and arranged in parallel in the vertical direction on the substrate SUB1 and the gate wiring GL are crossed. The drain wirings DL (DL1, DL2, DL3,...) Extending in the vertical direction and juxtaposed in the horizontal direction are formed to form a matrix. Then, pixels are arranged in a matrix corresponding to this matrix. The gate line GL is connected to the scanning drive circuit 10, and the drain line DL is connected to the video signal circuit 201 of the video signal drive circuit 20. Each pixel has a thin film transistor TFT as an active element, the gate electrode is connected to the gate wiring GL, the drain electrode is connected to the drain wiring DL, and the source electrode is connected to a pixel electrode (not shown). In this embodiment, the thin film transistor TFT is a polysilicon thin film transistor, which is an n-type TFT.

  Further, common electrode lines CL (CL1, CL2,...) Are formed on the substrate SUB1. Each pixel has a counter electrode (not shown) and is connected to the common electrode line CL. The pixel electrode and the counter electrode form a liquid crystal capacitor Clc through a liquid crystal layer CL (not shown). The common electrode line CL forms a storage capacitor Cstg with the pixel electrode, thereby holding the potential of the video signal written in the pixel electrode relatively long.

  R, G, and B correspond to red, green, and blue pixels, respectively, and pixels of the same color are arranged in the vertical direction of the figure, and R, G, B, R, G, B,. .. Repeatedly arranged in stripes. In order to realize these colors, corresponding color filters (not shown) of red, green, and blue are formed in stripes on the counter substrate SUB2.

  A scanning signal is sequentially applied to the gate wiring GL from the gate wiring GL1 in the first row to the gate wiring in the lowermost row by the scanning driving circuit 10, and thereby the thin film transistor TFT of the pixel in the scanned row is turned on. On the other hand, a video signal is applied from the video signal driving circuit 20 to the drain wiring DL, and the video signal is written into the pixel electrode via the thin film transistor TFT which is turned on. A common potential is applied to the common electrode wiring CL, and a lateral electric field in the in-plane direction is generated in the pixel due to a potential difference between the pixel electrode and the counter electrode, and thereby the liquid crystal of the liquid crystal layer LC is driven. Thus, display is performed by controlling the amount of light that enters the display panel and passes through the liquid crystal layer LC and is emitted from the display panel. A display method using such a horizontal electric field is called a horizontal electric field switching (IPS: In-Plane Switching) method.

  In this embodiment, the IPS mode is described as an example. However, instead of forming the common electrode wiring CL and the counter electrode on the substrate SUB1 side, a vertical electric field type liquid crystal display device in which the counter electrode is formed on the counter substrate SUB2 side. It is also good.

  Further, in this embodiment, both the scanning drive circuits 10 provided on both the left and right sides of the figure are provided on the gate wiring GL in order to reduce the delay of the scanning signal and the waveform being lost as the distance from the scanning drive circuit 10 increases. However, the present invention is not limited to this, and only one side may be used.

  Signals (power supply and control signal) necessary for the scan driver circuit 10, the drain driver 200 of the video signal drive circuit 20, the video signal circuit 201, and the common electrode wiring CL are supplied from the power supply circuit SCC and the timing controller TCON.

  The drain wiring DL is connected to the inspection circuit CC, and the disconnection of the drain wiring DL can be inspected using the inspection terminal CPAD provided on the substrate SUB1.

[First embodiment]
FIG. 4 is a diagram for explaining an example of the configuration of the scan driving circuit in the first embodiment of the display device according to the present invention.

  The scan drive circuit 10 used in this embodiment includes a shift register 100 and a drive unit DRV. The shift register 100 has a plurality of stages of outputs V1 (V1n, V1n + 1,...). After receiving a shift register start pulse VIN (not shown), the shift register 100 is synchronized with clocks CK1 and CK2 (not shown). Are sequentially output to outputs V1n, V1n + 1,. These outputs V1n, V1n + 1,... Are respectively input to the corresponding nth, n + 1th,... Drive units DRVn, DRVn + 1,. The scanning is performed by applying a scanning signal to the gate wirings GLn, GLn + 1,.

  Here, the drive unit DRVn has a booster circuit 101. The booster circuit 101 is supplied with a shift register output V1n and a common scanning signal V5 which is a column of a plurality of scanning signals having a voltage amplitude larger than that of the shift register output V1n. The common control signal V5 is also input in common to other drive units DRVn + 1. The booster circuit 101 has a switch 103. The switch 103 is controlled by the shift register output V1n, and selects a signal input during a period in which the shift register output V1n is input from among a plurality of scanning signal columns of the common scanning signal V5, and selects the scanning signal corresponding to the gate wiring. Output to GLn. This scanning signal has a larger voltage amplitude than the shift register output V1n. Therefore, since the drive voltage of the shift register 100 is lower than the voltage amplitude of the scanning signal, power consumption can be reduced.

  The drive unit DRVn has a reset circuit 102. The reset circuit 102 has an inverting circuit 105 that receives the shift register output V1n and outputs an inverted signal V4 thereof. Further, the reset circuit 102 receives the off potential VS of the thin film transistor TFT of the pixel connected to the gate wiring GL. The reset circuit 102 has a switch 104 controlled by the inversion signal V4, and outputs the off potential VS to the corresponding gate wiring GLn via the switch 104. In this manner, the switch 103 of the booster circuit 101 and the switch 104 of the reset circuit 102 are exclusively controlled, and the reset circuit 102 is connected to the corresponding gate wiring GLn during the period when the shift register output V1n is not input to the booster circuit 101. An off potential VS of the thin film transistor TFT is applied. In this way, the gate wiring GLn is prevented from floating during a period not being scanned. Thereby, the change in the voltage of the gate wiring GLn due to the voltage fluctuation of the drain wiring DL that occurs in the floating state can be reduced, and the influence on the image quality can be reduced. The off-potential VS is input in common to other drive units DRVn + 1.

  In this embodiment, the inversion signal V4 is generated by the inversion circuit 105 in the reset circuit 102. However, the present invention is not limited to this, and the inversion signal V4 generated separately may be input to the drive unit DRVn.

  The drive unit DRVn has been described above as an example, but the other drive units DRVn + 1 and the like have the same configuration as the drive unit DRVn.

  Note that the power and control signals necessary for these operations are supplied from the power SCC and the timing controller TCON, and the power circuit SCC and the timing controller TCON serve as a control circuit. In this embodiment, the shift clock start pulse VIN, the clocks CK1 and CK2, the common scanning signal V5, and the off potential VS are supplied from the control circuit.

  Next, an example of a specific circuit configuration will be described.

  FIG. 5 is a diagram for explaining an example of the circuit configuration of the drive unit in the first embodiment of the present invention. FIG. 6 is a waveform diagram for explaining an example of the operation of the circuit of the drive unit in FIG. FIG. 7 is a waveform diagram for explaining an example of the operation of the reset circuit in the drive unit of FIG.

  Here, the n-th drive unit DRVn will be described as an example.

  Of the drive unit DRVn, the booster circuit 101 includes transistors TR4 and TR5 and a capacitive element C2. The reset circuit 102 includes transistors TR1, TR2, TR3, TR6 and a capacitor element C1. In addition, the drive section DRVn includes transistors TR7, TR8, TR9. The transistors TR1 to TR9 used in the drive unit DRVn are n-type polysilicon thin film transistors and are integrally formed on the substrate SUB1. Since these have the same conductivity type as the thin film transistor TFT of the pixel, the pixel and the transistor of the drive unit DRV are single channel. Therefore, it can be manufactured with a small number of manufacturing processes. When the shift register 100 is constituted by a CMOS circuit, if the shift register 100 is not formed integrally on the substrate SUB1, but provided as a separate part, the substrate SUB1 has a single channel structure, so the number of manufacturing processes is small. That's it. The transistors TR1 to TR9 each have a gate electrode, a first electrode, and a second electrode. In this embodiment, the description will be made assuming that the threshold is 2V. In addition, the transistor parasitic capacitance is ignored. Further, in the present specification, the voltage and the like are described with specific numerical values raised, but this is merely an example, and can be appropriately changed without departing from the technical idea.

  The voltage V3 indicates the voltage of the gate electrode of the transistor TR1, and the voltage V6 indicates the voltage of the gate electrode of the transistor TR5. The drive unit output V7 is an output of the drive unit DRVn, and this is applied as a scanning signal to the corresponding gate wiring GLn.

  As shown in FIG. 6, the n-th shift register output V1n changes from 0V (Low) to 10V (High) at timing T1, and returns to 0V again at timing T4. The period from the timing T1 to the timing T4 is an output period of the shift register 100.

  The off output VS input to the reset circuit 102 is 0V. The clock V2 input to the reset circuit 102 has values of 0V (Low) and 10V (High). The changeover switch signal VB1 input to the drive unit DRVn is 10V, and the changeover switch signal VB2 is 0V. Details thereof will be described later. The common scanning signal V5 is a row of scanning signals having values of 0 V (Low) and 20 V (High), and the voltage amplitude thereof is 20 V, which is larger than the operating voltage of the shift register. These off output VS, clock V2, changeover switch signals VB1 and VB2, and common scanning signal V5 are supplied by the control circuit, and are also input in common to other drive units DRVn + 1.

  First, the operation of the booster circuit 101 will be described. The booster circuit 101 operates only during the period when the shift register output V1n is input.

  Since the changeover switch signal VB1 is 10V, the transistor TR7 is on. Further, since the changeover switch signal VB2 is 0V, the transistor TR9 is off.

  When the shift register output V1n is changed from 0V to 10V at the timing T1, the reset signal V4 is changed from 6V (High) to 0V (Low) in the reset circuit 102 as described later. At this time, the transistor TR6 is turned off. Therefore, during this period, the drive unit output V7 becomes the output of the booster circuit 101. The changeover switch signal VB1 is connected to the gate electrode of the transistor TR4, which is 10V. The shift register output V1n is connected to the first electrode of the transistor TR4. Here, the second electrode of the transistor TR4 is connected to the gate electrode of the transistor TR5 and the first electrode of the capacitor C2, and the voltage V6 is reduced by the threshold 2V of the transistor TR4, so the voltage V6 = 10V-2V = 8V. Saturates at. Thereby, the transistor TR5 is turned on. The first electrode of the transistor TR5 is connected to the common scanning signal V5, and the second electrode is connected to the second electrode of the capacitor C2 and the nth gate line GLn. Therefore, the output of the second electrode of the transistor TR5 becomes the drive unit output V7. Since the common scanning signal V5 is 0V at the timing T1, the drive unit output V7 = the common scanning signal V5 = 0V.

  At timing T2, the common scanning signal V5 changes from 0V to 20V. At this time, since the transistor TR5 is on, the drive unit output V7 also rises. Then, the voltage V6 of the gate electrode of the transistor TR5 also rises by the capacitive element C2. As the voltage V6 of the gate electrode of the transistor TR5 increases, the transistor TR5 can output a higher voltage to the drive unit output V7. As a result, the voltage V6 of the gate electrode further rises through the capacitive element C2. Such a bootstrap operation occurs in a short time, and finally the voltage V6 = 8V + 20V = 28V and the drive unit output V7 = 20V.

  At timing T3, the common scanning signal V5 changes from 20V to 0V. At this time, since the transistor TR5 is in the on state, the drive unit output V7 = 0V. The voltage V6 also returns from 28V to 8V.

  At timing T4, the shift register output V1n becomes 0V. Since the transistor TR4 is in the on state, the voltage V6 = shift register output V1n = 0V. Thereby, the transistor TR5 is turned off.

  Before the timing T1 and after the timing T4, the shift register output V1n is 0 V, so that the transistor TR5 is in an off state. Accordingly, although there is a period during which the common scanning signal TR5 is 20 V in this period, the booster circuit 101 does not operate and no scanning signal is output to the gate wiring GLn.

  With this configuration, the common scan signal V5 selected during the period when the shift register output V1n is input is selected and the scan signal is output to the corresponding gate line GLn. Accordingly, since the drive voltage of the shift register 100 is lower than the voltage amplitude of the scanning signal, power consumption can be reduced. In addition, since the common scanning signal V5 is prepared separately from the shift register output V1n, the length, voltage amplitude, etc. can be freely changed without depending on the waveform of the shift register output, so that the shift register is redesigned. There is a high degree of freedom in design, such as no longer necessary.

  Further, although some deterioration such as a rounded waveform occurs, the degree thereof is small, and a scanning signal having substantially the same voltage amplitude as that of the common scanning signal V5 can be output to the gate line GLn. In the case of the level shifter 302 using the CMOS circuit as shown in FIG. 21, since rounding of the waveform occurs, it is necessary to remove rounding by the buffer 303. However, according to the configuration of this embodiment, the level shifter 302 is unnecessary and the waveform Since there is little rounding, the buffer 303 becomes unnecessary. Further, since the capacitor C2 for bootstrapping is connected to the drive unit output V7, the bootstrap operation is performed with its own output.

  Next, the operation of the reset circuit 102 will be described.

  At the timing T1, as shown in FIG. 7, the shift register output V1n is changed from 0V to 10V, and the clock V2 is changed from 0V to 10V. At this time, the transistor TR2 is turned on, and the inverted signal V4 = off potential VS = 0V. The voltage V3 rises in synchronization with the clock V2 by the capacitive element C1, but the voltage V3 is saturated by 2V which is higher than the inverted signal V4 by the threshold 2V by the diode constituted by the transistor TR1, and the transistor TR1 is in the off state. It becomes.

  At timing T5, the clock V2 changes from 10V to 0V. At this time, the voltage V3 also drops due to the capacitive element C1, and becomes smaller than -2V. Then, the transistor TR3 constituting the diode is turned on, and is saturated with the voltage V3 = off voltage VS−threshold 2V = 0V−2V = −2V, and the transistor TR3 is turned off.

  At timing T4, the shift register output V1n changes from 10V to 0V, and the clock V2 changes from 0V to 10V. At this time, the transistor TR2 is turned off. Further, due to the capacitive element C1, the voltage V3 rises by 10V from −2V to 8V in synchronization with the clock V2. Then, the transistor TR1 constituting the diode is turned on, the inverted signal V4 is saturated at 6V that is lowered by 2V of the threshold value, and the transistor TR1 is turned off. The inversion signal V4 is 6V before the timing T1.

  At timing T6, the clock V2 changes from 10V to 0V. At this time, the voltage V3 drops by 10V to −2V by the capacitive element C1. At this time, the transistor TR1 forming the diode remains in the off state and the transistor TR2 is also in the off state, so that the inverted signal V4 remains 6V.

  Through the above operation, the inverted signal V4 is generated from the shift register output V1n. When the shift register output V1n is present, the inverted signal V4 is 0V, and when there is no shift register output V1n, the inverted signal V4 is 6V. When the inversion signal V4 is 6V, the transistor TR6 is turned on and the transistor TR7 is also turned on, so the off potential VS is output to the drive unit output V7 and becomes 0V. In this way, the transistor TR5 of the booster circuit 101 and the transistor TR6 of the reset circuit 102 are exclusively controlled. While the booster circuit 101 is not operating, the reset circuit 102 outputs the off potential VS, whereby the gate wiring GLn is I try not to float.

  Next, the changeover switch circuit will be described.

  FIG. 8 is a diagram illustrating an example of the circuit configuration of the changeover switch circuit of the drive unit according to the first embodiment of the present invention. FIG. 9 is a waveform diagram for explaining an example of the operation of the circuit of the drive unit of FIG.

  As shown in FIG. 8, the drive unit DRVn has a changeover switch circuit 106. The circuit shown in FIG. 8 is the same as the circuit shown in FIG. 5, and only the part corresponding to the changeover switch circuit 106 is shown. The changeover switch circuit 106 includes transistors TR4, TR6, TR7, TR8, and TR9. Among them, the transistor TR4 is shared with the booster circuit 101, and the transistor TR6 is shared with the reset circuit 102.

  Next, the operation of the changeover switch circuit will be described with reference to FIG.

  As shown in FIG. 9, before the timing T7, the changeover switch signal VB1 is 0V of the ground potential, and the changeover switch signal VB2 is 10V of the DC voltage signal. A period before the timing T7 is an OFF period in which the operation of the booster circuit 101 is stopped. On the other hand, after the timing T7, the changeover switch signal VB1 is a DC voltage signal of 10V, and the changeover switch signal VB2 is a ground potential of 0V. A period after the timing T7 is an ON period in which the operation of the booster circuit 101 is permitted.

  In the OFF period, the changeover switch signal VB1 is 0V. Accordingly, the transistor TR4 is in an off state. Accordingly, even when the shift register output V1n is input at the timing T1, the voltage V6 does not change, and the transistor TR5 remains in the off state. The transistor TR7 is also turned off because the changeover switch signal VB1 is 0V. Further, since the changeover switch signal VB2 is 10V, the transistor TR9 is turned on. Then, when the inverted signal V4 becomes 6V at timing T4, the transistor TR8 is turned on, and the voltage V6 becomes 0V which is equal to the off potential VS. As a result, the transistor TR5 is maintained in the OFF state, and the output of the common control signal V5 is not output to the drive unit output V7. Thus, the operation of the booster circuit 101 is stopped in the OFF period. Since both the transistors TR5 and TR7 are in the off state, the drive unit output V7 is in a floating state.

  On the other hand, in the ON period, the operation of the booster circuit 101 is permitted, and the operation as described with reference to FIGS. 5 to 7 is performed.

  Use of such a changeover switch circuit 106 has the following advantages. That is, immediately after the power is turned on, the output of the shift register 100 is unstable, and the output may be started from a place other than the first output. This is not limited to only one location, and there are cases where outputs are output from a plurality of output terminals. However, if the shift register 100 is scanned once or more in a state where the operation of the booster circuit 101 is stopped by the changeover switch circuit 106 before the display is started, such an abnormal output is eliminated. Thereafter, the operation of the booster circuit 101 may be permitted by the changeover switch circuit 106 and display may be started.

  Further, when such a changeover switch circuit 106 is used, when two scanning drive circuits 10 are provided as shown in FIG. 3, only one side of the scan drive circuit 10 is turned off by the changeover switch circuit, and the other side is provided. Only the scanning drive circuit 10 can be driven in the ON period. In this case, the output of the scanning drive circuit in the OFF period is in a floating state and thus does not affect the operation. Thereby, even if a problem occurs in the scanning drive circuit 10 on one side, the drive can be performed by the scanning drive circuit 10 on the other side, so that the yield is improved.

  Next, the operation of the entire scan driving circuit 10 will be described.

  FIG. 10 is a waveform diagram for explaining an example of the operation of the scan driving circuit in the first embodiment of the present invention.

  The shift register start pulse VIN has a voltage amplitude of 10V. The clocks CK1 and CK2 have a voltage amplitude of 10V and have opposite phases, and the shift operation of the shift register 100 is performed in synchronization with the clocks CK1 and CK2. The nth shift register output V1n and the (n + 1) th shift register output V1n + 1 have a voltage amplitude of 10V, and they do not overlap in time. Although it is possible to take out temporally overlapped outputs from the shift register 100 as will be described later, they are not taken out in this embodiment.

  The common scanning signal V5 has a larger voltage amplitude than the shift register output V1, and is 20V. This is because the column of the scanning signal is applied to the common scanning signal V5 even after the scanning signal is applied to the gate wiring GLn of a specific n-th row until the next n-th row. However, only the gate wiring GLn in the period in which the shift register output V1n is input is selected and output. The same applies to the gate wiring GLn + 1 in the next n + 1 row. In this way, scanning is performed sequentially from the first line.

[Second Embodiment]
FIG. 11 is a diagram for explaining an example of the circuit configuration of the shift register in the second embodiment of the present invention. FIG. 12 is a waveform diagram for explaining an example of the operation of the shift register shown in FIG.

  This embodiment is different from the first embodiment in the configuration of the shift register 100 and the waveform of its output V1. A duplicate description of the same parts as in the first embodiment is omitted.

  In FIG. 11, the shift register 100 includes a transistor TR10, a transistor TR11, and a capacitor C3 that form a diode. In addition, a transistor and a pump-up circuit 107 are provided. These transistors TR10, TR11, etc. are n-type polysilicon thin film transistors, and have the same conductivity type single channel configuration as the pixels and the drive section. The shift register 100 is integrally formed on the substrate SUB1 and has a single channel configuration, so that the manufacturing process can be reduced.

  Next, the operation of this embodiment will be described with reference to FIG.

  When the 6V amplitude shift register start pulse VIN is input to the transistor TR10 that constitutes the first diode, the output V1n becomes 4V, which is lower than 6V by the threshold 2V. At this time, the transistor TR11 is turned on. Then, the potential of the second electrode of the transistor TR11 rises in synchronization with the rise of the 6V amplitude clock CK1. Along with this, the output V1n rises to 10V by the bootstrap operation through the capacitive element C3. Then, the transistor TR11 is turned off in synchronization with the falling of the clock CK1, and the output V1n becomes 0V.

  Next, a shift to the next stage occurs in synchronization with the rising edge of the clock CK2.

  Further, a shift to the next stage occurs in synchronization with the rising edge of the clock CK1, and output to the output V1n + 1 is started.

  By using these outputs V1n and V1n + 1, a scanning signal can be applied to the gate wiring GL as in the first embodiment. In this way, a scan signal substantially the same as the waveform of the common scan signal V5 can be applied without depending on the waveform of the shift register output.

  According to the present embodiment, even when the clocks CK1 and CK2 for operating the shift register 100 are 6V, which is smaller than that of the first embodiment, the shift register output V1 is 10V which is the same as the first embodiment. Therefore, the power consumption can be further reduced as compared with the first embodiment.

[Third embodiment]
FIG. 13 is a diagram for explaining an example of the configuration of the scan driving circuit in the third embodiment of the present invention. FIG. 14 is a waveform diagram for explaining an example of the operation of the scan drive circuit of FIG.

  This embodiment is particularly different from the first embodiment shown in FIG. 4 in that two types of common scanning signals V51 and V52 are provided in place of the common scanning signal V5, and the booster circuit 101 is divided into two groups. It is. In addition, duplication description is abbreviate | omitted about the part similar to each Example demonstrated so far.

  The first common scanning signal V51 is the same as the common scanning signal V5 shown in FIG. The second common scanning signal V52 has a waveform having a phase different from that of the first common scanning signal V51. In the present embodiment, an example in which the phase is shifted by 180 degrees will be described.

  The odd-numbered output V1 (2n-1) of the shift register 100 is input to the corresponding drive unit DRV (2n-1). The booster circuit 101 operates using the first common scanning signal V51 and outputs a scanning signal to the gate wiring GL (2n−1). The other odd-numbered outputs V1 (2n + 1) and the like are similarly operated using the first common scanning signal V51, and a scanning signal is applied to the corresponding gate wiring GL (2n + 1) and the like.

  On the other hand, the even-numbered output V1 (2n) of the shift register 100 is input to the corresponding drive unit DRV (2n). The booster circuit 101 operates using the second common scanning signal V52 and outputs a scanning signal to the gate line GL (2n). Although not shown, other even-numbered outputs V1 (2n + 2) and the like are similarly operated using the second common scanning signal V52, and the scanning signal is applied to the corresponding gate wiring GL (2n + 2) and the like.

  As described above, the booster circuit 101 of each drive unit DRV has the first group to which the first common scanning signal V51 is commonly input and the first group to which the second common scanning signal V52 is commonly input. It is divided into the second group which does not belong to. In this embodiment, the booster circuit 101 corresponding to the odd-numbered gate wiring GL belongs to the first group, and the booster circuit corresponding to the even-numbered gate wiring GL belongs to the second group.

  At this time, the shift register outputs V1 (2n-1), V1 (2n), and V1 (2n + 1) are outputs that partially overlap each other as shown in FIG. This uses the output of the shift register 100 that was not used in the first embodiment. However, even in such a case, a scanning signal can be applied to the corresponding gate wirings GL (2n-1), GL (2n), and GL (2n + 1).

  According to this embodiment, even when the number of transistors used in the shift register is the same as that in the first embodiment, it is possible to scan the gate wiring GL having twice the number of rows by increasing one common scanning signal. Become.

[Fourth embodiment]
FIG. 15 is a diagram for explaining an example of the circuit configuration of the shift register in the fourth embodiment of the present invention. FIG. 16 is a waveform diagram for explaining an example of the operation of the shift register shown in FIG.

  This embodiment corresponds to an embodiment in which the third embodiment shown in FIG. 13 and the second embodiment shown in FIG. 11 are combined. However, the difference from the second embodiment shown in FIG. 11 is that the output V1 (2n) is taken out from a location not used in the shift register 100 shown in FIG. 11 as shown in FIG. It is. Thereby, even when the number of transistors used in the shift register 100 is the same, it is possible to scan twice as many gate wirings GL. In addition, since all of the shift register 100, the drive unit DRV, and the pixels have a single channel configuration, the number of manufacturing processes can be reduced when the scan drive circuit 10 is integrally formed on the substrate SUB1. Further, since the drive voltage of the shift register 100 is small, power consumption can be reduced. In addition, redundant description of the same parts as those of the embodiments described so far will be omitted.

[Fifth embodiment]
Next, the video signal driving circuit 20 will be described.

  FIG. 17 is a diagram for explaining an example of the configuration of the video signal driving circuit in the fifth embodiment of the display device according to the present invention.

  The video signal drive circuit 20 in this embodiment uses a time division method.

  The video signal drive circuit 20 includes a drain driver 200 and a video signal circuit 201. The drain driver 200 is one or more driving IC chips, and is mounted by a tape automated bonding method (TAB). However, the present invention is not limited to this, and a method of mounting an IC chip on the substrate SUB1 may be used, or a method of mounting on a place other than the substrate SUB1, for example, on the circuit board PCB1 or a flexible circuit board (FPC). On the other hand, the video signal circuit 201 is integrally formed on the substrate SUB1. The video signal circuit 201 has a distribution circuit 202. The drain wirings DL (DL1, DL2, DL3, DL4,...) Form a set of three adjacent lines, and are connected to each distribution circuit 202. One set of drain wirings DL includes one drain wiring DL corresponding to each of red (R), green (G), and blue (B).

  Each output of the drain driver 200 is input to the distribution circuit 202 via the common video signal wiring CVL (CVL1, CVL2,...). The drain driver 200 outputs video signals from the first output terminal to each of the three pixels of red (R), green (G), and blue (B) during one horizontal period of scanning the gate wiring GL for one row. The divided signal is output to the first common video signal line CVL1. Then, the distribution circuit 202 distributes the video signal output in this time division to the corresponding R, G, B drain wirings DL1, DL2, DL3. Similarly, the video signal is output from the second output terminal of the drain driver 200 to the second common video signal line CVL2 in a time-sharing manner, and is distributed to the next set of drain lines DL4, DL5, DL6 by the distribution circuit 202. The The same applies to the outputs of the third and subsequent drain drivers 200.

  In this embodiment, three drain wirings DL are used as one set, but two or more may be used as one set. The drain driver 200 outputs video signals applied to two or more drain wirings DL included in the set to the common video signal wiring CVL in a time division manner, and the distribution circuit 202 outputs the common video signal wiring CVL. The video signal output in a time division manner is distributed to the corresponding drain wiring DL.

  FIG. 18 is a diagram illustrating an example of the distribution circuit in FIG. FIG. 19 is a waveform diagram for explaining an example of the operation of the circuit shown in FIG.

  Description will be made by paying attention to the distribution circuit 202 that distributes the first common video signal line CVL1 to the three drain lines DL1, DL2, and DL3. While the scanning signal is applied to the first gate line GL1, the drain driver 200 applies video signals R1, G1, and B1 corresponding to the red, green, and blue pixels to the common video signal line CVL1, respectively. Are output in time division. In this embodiment, the maximum voltage amplitude of the video signal is assumed to be 12V.

  The distribution circuit 202 receives the distribution control signals V21 to V26 twice as many as the number (6) of the drain wirings DL1, DL2, and DL3 (3) corresponding to one common video signal wiring CVL1. Is controlled. In this embodiment, the voltage amplitude of the distribution control signal is 10V.

  The distribution circuit 202 includes transistors TR24, TR25, and TR26 that serve as switches. In each of these, the first electrodes are connected to the common video signal wiring CVL1, the second electrodes are connected to the corresponding drain wirings DL1, DL2, and DL3, and the voltages of the respective gate electrodes are distributed control signals V21 to V26. Are controlled on the basis of two corresponding to each of the two.

  Distribution to the drain wiring DL1 is controlled by the transistor TR24, the two distribution control signals V21 and V22, the transistor TR21, and the capacitive element C21.

  It is necessary to input a voltage sufficiently larger than the voltage amplitude of the video signal to the gate electrode of the transistor TR24. If this is small, a correct video signal cannot be applied to the drain latitude line DL1 due to the ON resistance of the transistor TR24. If the distribution control signal is a signal having a sufficiently large voltage, it is sufficient to use only one distribution control signal for one drain wiring DL and input it directly to the gate electrode of the transistor TR24. Then, in order to control using a distribution control signal having a voltage amplitude equal to or smaller than the sum of the maximum voltage amplitude of the video signal and the threshold voltage of the transistor TR24, the following measures are taken.

  In the transistor TR21, the DC voltage signal VB3 is input to the gate electrode, and the distribution control signal V21 is input to the first electrode. The first electrode of the capacitive element C21 is connected to the distribution control signal V22, and the second electrode is connected to the second electrode of the transistor TR21 and the gate electrode of the transistor TR24. In this embodiment, the DC voltage signal VB3 is 10 V which is the same as the distribution control signals V21 to V26.

  First, when the distribution control signal V21 is inputted, the voltage V27 of the gate electrode of the transistor TR24 becomes 8V obtained by subtracting the threshold value 2V from 10V. Next, when the distribution control signal V22 is input at the timing T21, the voltage V27 further increases via the capacitive element C21, and further increases by 10V from the current 8V to 18V. At this time, the transistor TR21 is turned off. Here, since the gate electrode of the transistor TR24 is 18V and is sufficiently larger than 14V obtained by adding the threshold voltage 2V of the transistor TR24 to 12V which is the maximum voltage amplitude of the video signal R1, the video signal R1 is applied to the drain wiring DL1. Will be. When the distribution control signal V22 becomes 0V, the voltage V27 returns to 8V via the capacitive element C21. When the distribution control signal V21 becomes 0V at the timing T22, the voltage V27 becomes 0V and the transistor TR24 is turned off.

  As described above, the voltage of the gate electrode of the transistor TR24 is raised to the first voltage 8V based on the first of the two distribution control signals V21 and V22, and is higher than the first voltage based on the second. The voltage is raised to a high second voltage 18V, which is greater than the sum of the maximum value of the voltage of the video signal R1 and the threshold voltage of the transistor TR24, and is higher than the voltages of the distribution control signals V21 and V22. Even a large voltage is controlled.

  Distribution to the drain wirings DL2 and DL3 is also controlled in the same manner as the drain wiring DL1. Here, the transistors TR24 correspond to the transistors TR25 and TR26, the transistors TR21 correspond to the transistors TR22 and TR23, respectively, and the capacitors C21 correspond to the capacitors C22 and C23, respectively. The distribution control signal V21 corresponds to the distribution control signals V23 and V25, respectively, and the distribution control signal V22 corresponds to the distribution control signals V24 and V26, respectively. Then, distribution is performed by shifting the timings of the distribution control signals V21 to V26 corresponding to the time division of the drain driver 200. The DC voltage signal VB3 is used in common.

  The same applies to the second common video signal wiring CVL2 and the subsequent common video signal wiring CVL. Here, the distribution control signals V21 to V26 are used in common for distribution circuits corresponding to two or more common video signal lines CVL.

  The transistors TR21 to TR26 are polysilicon thin film transistors that are integrally formed on the substrate SUB1 and have the same conductivity type as the thin film transistors TFT used in the pixels. Therefore, the number of manufacturing processes can be reduced because of the single channel configuration.

  In addition, about the value of a specific voltage, it can change suitably in the range which does not deviate from the technical idea of this invention. The circuit configuration and the waveforms of the distribution control signals V21 to V26 are not limited to the examples shown in FIGS. 18 and 19 and can be changed as appropriate.

  In this embodiment, since it is necessary to write video signals for three pixels in a time division manner while one scanning signal is being applied, high speed is required. Therefore, if the period during which the first voltage is 8V or more is defined as the selection period TS and the period during which the second voltage is 18V is defined as the bootstrap period TBS, the bootstrap period TBS is selected. It is desirable that the period TS be longer than 50%, and more desirably 75% or more.

  This embodiment may be combined with the first to fourth embodiments or may be used alone. Conversely, the first to fourth embodiments may be used alone or in combination with the present embodiment.

[Sixth embodiment]
FIG. 20 is an exploded perspective view showing an example of a display device according to the present invention.

  The liquid crystal display panel PNL uses one of the first to fifth embodiments, or a combination of two or more. The liquid crystal display panel PNL uses a transmissive or transflective liquid crystal display panel. On the display surface side of the liquid crystal display panel PNL, for example, a metal shield case SHD having a display window LCW is disposed. A backlight unit BLU is disposed on the back surface of the liquid crystal display panel PNL. In the backlight unit BLU, the light diffusion plate SPB, the light guide LCB, the reflection plate RM, the backlight light source BL, and the inverter circuit board PCB2 are accommodated in the backlight case LCA. The inverter circuit board PCB supplies power to the backlight light source BL. And the light from the backlight light source arrange | positioned at the side surface of the light guide LCB becomes a planar light source by the light diffusing plate SPB, the light guide LCB, and the reflection plate RM, and irradiates the liquid crystal display panel PNL from the back. .

  In the liquid crystal display module MDL, the shield case SHD, the liquid crystal display panel PNL, and the backlight unit BLU are stacked in the arrangement as shown in the figure, and the whole is fixed by claws and hooks provided in the shield case SHD.

  The configuration of the liquid crystal display module MDL and the configuration of the backlight unit BLU are not limited to this, and can be changed as appropriate, such as using a prism sheet. Further, in this embodiment, the side light type backlight unit BLU has been described as an example, but a direct type backlight unit in which a plurality of backlight light sources are arranged on the back surface of the liquid crystal display panel PNL without using the light guide LCB. A BLU may be used. In addition, a reflective liquid crystal display panel may be used as the liquid crystal display panel PNL, and a front light unit that irradiates the liquid crystal display panel PNL from the display surface side may be used instead of the backlight unit BLU.

  In each of the above embodiments, an example in which an n-type thin film transistor is used has been described. However, each circuit may be configured by a p-type thin film transistor. In this case, the circuit configuration and waveform are changed as appropriate.

  For example, regarding the fifth embodiment, in FIG. 19, the voltage V27 of the gate electrode of the transistor TR24 is the highest in the OFF state, and is based on the first of the two V21 and V22 corresponding to the distribution control signal. The voltage is lowered to the first voltage, and is lowered to a second voltage lower than the first voltage based on the second voltage. Since the lowest on-voltage is required when the voltage of the video signal takes the minimum value, this second voltage is the sum of the minimum value of the voltage of the video signal and the threshold voltage of the thin film transistor (in this case, for example -2V). And a voltage smaller than the voltages of the distribution control signals V21 and V22. As a result, the transistor TR24 can be sufficiently switched. The selection period TS is defined as a period that is lower than the first voltage, and the bootstrap period TBS is defined as a period that is the second voltage. Other changes may be made as necessary, but the contents are apparent and will not be described.

  Further, in each of the above embodiments, a specific circuit example of the shift register 100 has been described, but the present invention is not limited to this. The shift register 100 in this specification includes any circuit as long as it performs sequential scanning output.

  Further, the display device of the present invention has been described by taking a liquid crystal display device as an example.

It is a top view which shows an example of the display panel used for the display apparatus by this invention. It is a figure which shows an example of the display apparatus by this invention, and is a top view which shows an example which connected the circuit board to the display panel. It is a figure which shows an example of the equivalent circuit of the display apparatus by this invention. It is a figure explaining an example of a structure of the scanning drive circuit in the 1st Example of the display apparatus by this invention. It is a figure explaining an example of the circuit structure of the drive part in 1st Example of this invention. FIG. 6 is a waveform diagram for explaining an example of the operation of the circuit of the drive unit in FIG. 5. FIG. 6 is a waveform diagram for explaining an example of the operation of the reset circuit in the drive unit of FIG. 5. It is a figure explaining an example of the circuit structure of the changeover switch circuit of the drive part in 1st Example of this invention. FIG. 9 is a waveform diagram for explaining an example of the operation of the circuit of the drive unit in FIG. 8. It is a wave form diagram explaining an example of operation | movement of the scanning drive circuit in 1st Example of this invention. It is a figure explaining an example of the circuit structure of the shift register in the 2nd Example of this invention. FIG. 12 is a waveform diagram illustrating an example of operation of the shift register illustrated in FIG. 11. It is a figure explaining an example of a structure of the scanning drive circuit in the 3rd Example of this invention. FIG. 14 is a waveform diagram illustrating an example of the operation of the scan drive circuit of FIG. 13. It is a figure explaining an example of the circuit structure of the shift register in the 4th Example of this invention. FIG. 16 is a waveform diagram illustrating an example of the operation of the shift register illustrated in FIG. 15. It is a figure explaining an example of a structure of the video signal drive circuit in the 5th Example of the display apparatus by this invention. It is a figure explaining an example of the distribution circuit in FIG. It is a wave form diagram explaining an example of operation | movement of the circuit shown in FIG. It is an expansion | deployment perspective view which shows an example of the display apparatus by this invention. It is the figure which showed an example of the conventional scanning drive circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Scanning drive circuit, 20 ... Video signal drive circuit, 100 ... Shift register, 101 ... Boosting circuit, 102 ... Reset circuit, 103 ... Switch, 104 ... Switch, 105 ... Inversion circuit, 106 ... Changeover switch circuit, 107 ... Pump Up circuit, 200 ... Drain driver, 201 ... Video signal circuit, 202 ... Distribution circuit, 300 ... Scanning drive circuit, 301 ... Shift register, 302 ... Level shifter, 303 ... Buffer, AR ... Display area, BL ... Backlight light source, BLU ... Backlight unit, C1 to C3, C21 to C23 ... Capacitor element, Clc ... Liquid crystal capacitor, Cstg ... Holding capacitor, CC ... Inspection circuit, CJ ... Connector connection, CK1, CK2 ... Clock, CL ... Common electrode wiring, CPAD ... inspection terminal, CVL ... common video signal wiring, DL ... drain wiring, DR , DRVn, DRVn + 1 ... driving unit, GFPC ... flexible substrate, GL ... gate wiring, INJ ... enclosing port, LCA ... backlight case, LCB ... light guide, LCW ... display window, MDL ... liquid crystal display module, PCB1 ... circuit board , PCB2 ... inverter circuit board, PNL ... liquid crystal display panel, R1, G1, B1 ... video signal, RM ... reflector, SCC ... power supply, SHD ... shield case, SL ... seal, SPB ... light diffusion plate, SUB1 ... substrate, SUB2 ... counter substrate, T1 to T7, T21 to T26 ... timing, Td, Tg ... connection terminal, TBS ... bootstrap period, TCON ... timing controller, TCP ... tape carrier package, TFT ... thin film transistor, TR1 to TR11, TR21 to 26 ... Transistor, TS ... Selection period, V1 ... Sh Register output, V2, clock, V3, V6, V27 to V29 ... voltage, V4 ... inverted signal, V5, V51, V52 ... common scanning signal, V7 ... driver output, V21-V26 ... distribution control signal, VB1, VB2 ... Changeover switch signal, VB3 ... DC voltage signal, VIN ... shift register start pulse, VS ... off potential.

Claims (10)

A substrate,
A plurality of gate wirings formed on the substrate;
A plurality of drain wirings formed on the substrate and intersecting the plurality of gate wirings;
A plurality of pixels having thin film transistors connected to the gate wiring and the drain wiring;
A video signal driving circuit for applying a video signal to the drain wiring;
A display device comprising a control circuit for supplying a necessary signal to the video signal driving circuit,
The video signal driving circuit corresponds to a drain driver that outputs a video signal applied to two or more of the drain wirings to the common video signal wiring in a time division manner, and a video signal output to the common video signal wirings in a time division manner. A distribution circuit integrally formed on the substrate for distributing to the drain wiring;
The distribution circuit receives distribution control signals twice as many as the number of drain wirings corresponding to one common video signal wiring, and performs distribution control.
The distribution circuit is an n-type thin film transistor that is the same channel as the thin film transistor of the pixel, and each first electrode is connected to the common video signal line, and each second electrode is connected to a corresponding drain line. A plurality of thin film transistors in which the voltage of each gate electrode is controlled based on two corresponding ones of the distribution control signals,
The voltage of the gate electrode of the thin film transistor of the distribution circuit is increased to the first voltage based on the first of the two corresponding ones of the distribution control signals, and is higher than the first voltage based on the second. The second voltage is controlled to a voltage that is greater than the sum of the maximum value of the voltage of the video signal and the threshold voltage of the thin film transistor, and greater than the voltage of the distribution control signal,
The display device according to claim 1, wherein the distribution control signal is commonly used for distributing two or more common video signal lines.   The period during which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is longer than 50% of the period during which the voltage is equal to or higher than the first voltage. Display device.   The period in which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is 75% or more of the period in which the voltage is higher than the first voltage. The display device according to 1.   4. The distribution circuit according to claim 1, wherein the distribution circuit is a circuit that distributes the common video signal wiring to the drain wiring corresponding to each of red, green, and blue pixels. Display device. A counter substrate disposed opposite to the substrate;
The display device according to claim 1, further comprising a liquid crystal layer sandwiched between the substrate and the counter substrate. A substrate,
A plurality of gate wirings formed on the substrate;
A plurality of drain wirings formed on the substrate and intersecting the plurality of gate wirings;
A plurality of pixels having thin film transistors connected to the gate wiring and the drain wiring;
A video signal driving circuit for applying a video signal to the drain wiring;
A display device comprising a control circuit for supplying a necessary signal to the video signal driving circuit,
The video signal driving circuit corresponds to a drain driver that outputs a video signal applied to two or more of the drain wirings to the common video signal wiring in a time division manner, and a video signal output to the common video signal wirings in a time division manner. A distribution circuit integrally formed on the substrate for distributing to the drain wiring;
The distribution circuit receives distribution control signals twice as many as the number of drain wirings corresponding to one common video signal wiring, and performs distribution control.
The distribution circuit is a p-type thin film transistor that has the same channel as the thin film transistor of the pixel, and each first electrode is connected to the common video signal line, and each second electrode is connected to a corresponding drain line. A plurality of thin film transistors in which the voltage of each gate electrode is controlled based on two corresponding ones of the distribution control signals,
The voltage of the gate electrode of the thin film transistor of the distribution circuit is lowered to the first voltage based on the first of the two corresponding ones of the distribution control signals, and is lower than the first voltage based on the second. The second voltage is controlled to a voltage smaller than the sum of the minimum value of the video signal voltage and the threshold voltage of the thin film transistor and smaller than the voltage of the distribution control signal,
The display device according to claim 1, wherein the distribution control signal is commonly used for distributing two or more common video signal lines.   The period during which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is longer than 50% of the period during which the voltage is equal to or lower than the first voltage. Display device.   The period during which the voltage of the gate electrode of the thin film transistor of the distribution circuit is the second voltage is 75% or more of the period during which the voltage is lower than the first voltage. 6. The display device according to 6.   9. The distribution circuit according to claim 6, wherein the distribution circuit is a circuit that distributes the common video signal wiring to the drain wiring corresponding to each of red, green, and blue pixels. Display device. A counter substrate disposed opposite to the substrate;
The display device according to claim 6, further comprising a liquid crystal layer sandwiched between the substrate and the counter substrate.

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