JP2007028701A - Fet module and inverter for induction heating - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform high speed switching operation of high current. <P>SOLUTION: A plus side power supply wiring pattern and a minus side power supply wiring pattern are laid out on the inside of one surface of a substrate composed of an insulating material, and an output wiring pattern is laid out on the inside of the other surface of the substrate. The plus side power supply wiring pattern and the minus side power supply wiring pattern are arranged to oppose the output wiring pattern while sandwiching the insulating material. A plurality of discrete FET elements are mounted in parallel on the + side power supply wiring pattern, the minus side power supply wiring pattern and the output wiring pattern and the FET elements are switched simultaneously. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an FET module and an induction heating inverter, and more particularly to an FET module suitable for use in an inverter circuit of an induction heating high-frequency power source and an induction heating inverter using the FET module, and in particular, a high speed The present invention relates to an FET module suitable for use in a high-frequency power supply that requires switching, and an induction heating inverter using the FET module.

  In the conventional FET module, a plurality of FET chip elements are arranged in a copper foil pattern on a ceramic substrate, and the plurality of FET chip elements are connected in parallel by a plurality of aluminum wire bonding wires. By using copper plate wiring for wiring between the terminal and the control terminal and the FET chip, high voltage and large current switching can be performed.

  However, since the space wiring of the copper plate has a large wiring inductance L, the surge voltage E (E = −Ldi / dt) between the drain and the source during switching is large.

  For this reason, when high-speed switching is performed, that is, when di / dt is large, the surge voltage increases, and in order to avoid voltage breakdown of the FET element, the delay rating is reduced with respect to the rated current of the FET element. There was a need to do.

  Also in the gate wiring, due to wiring inductance, ringing occurs when the rise / fall of the gate drive signal is made high speed, which causes a malfunction when the FET element is turned on / off.

  For the above reasons, the conventional FET module has a problem that it is difficult to perform a high-speed high-speed switching operation.

  Similarly, in the induction heating inverter using the conventional FET module, there is a problem that it is difficult to perform a high-speed high-speed switching operation.

  Note that the prior art that the applicant of the present application knows at the time of filing a patent application is not an invention related to a known literature invention, so there is no prior art document information to be described.

  The present invention has been made in view of the above-described problems of the prior art, and the object of the present invention is to provide an FET module and an induction heating device that can perform a high-current high-speed switching operation. An attempt is made to provide an inverter.

  In order to achieve the above object, the invention according to claim 1 of the present invention lays out the + side power supply wiring pattern and the − side power supply wiring pattern inside one surface of the substrate made of an insulating material, The output wiring pattern is laid out inside the other side of the substrate, and the + side power wiring pattern, the − side power wiring pattern and the output wiring pattern are arranged so as to face each other with the insulating material therebetween. A plurality of discrete FET elements are mounted in parallel on the + side power supply wiring pattern, the − side power supply wiring pattern, and the output wiring pattern, and the FET elements are simultaneously switched.

  In the invention according to claim 1 of the present invention, the + side power supply wiring pattern and the − side power supply wiring pattern are laid out inside one surface of the substrate made of an insulating material, and the output wiring pattern is arranged on the substrate. The + side power supply wiring pattern, the − side power supply wiring pattern and the output wiring pattern are arranged so as to face each other with the insulating material therebetween, and the substrate is Since the insulation resistance is large because it is made of an insulating material, it is possible to reduce the wiring interval and reduce the wiring inductance, that is, the surge voltage in high-speed switching, as compared with the case where the copper plate is three-dimensionally wired in the space. become able to. Accordingly, since the derating can be set large with respect to the rated current of the FET element, high-speed switching with a large current is possible.

  According to a second aspect of the present invention, in the first aspect of the present invention, the source potential wiring pattern is laid out outside the surface of the one surface, and the gate drive wiring pattern. Is laid out outside the surface of the other surface, and the source potential wiring pattern and the gate drive wiring pattern are arranged so as to face each other with the insulating material interposed therebetween.

  In the second aspect of the present invention, the source potential wiring pattern is laid out outside the surface of the one surface, and the gate driving wiring pattern is laid out outside the surface of the other surface. Since the source potential wiring pattern and the gate drive wiring pattern are arranged so as to face each other with the insulating material interposed therebetween, wiring inductance is reduced, and the gate charge / gate discharge of the FET element is performed at high speed. The ringing phenomenon that occurs in the FET element is suppressed, and the malfunction of the FET element during turn-on / turn-off can be prevented.

  According to a third aspect of the present invention, the gate drive wiring pattern is broadened in the second aspect of the present invention.

  According to the third aspect of the present invention, by widening the gate drive wiring pattern, the substrate has a low relative dielectric constant, so that the wiring impedance is reduced, and a plurality of FET elements are simultaneously turned on / off. In this case, each gate drive current is balanced, variation in turn-on / turn-off time of each FET element is suppressed, and current concentration on a specific FET element can be avoided. It becomes possible to turn on / off simultaneously.

  According to a fourth aspect of the present invention, in the invention according to the second or third aspect of the present invention, the common pattern of the gate drive wiring pattern and the source potential wiring pattern In the meantime, a high resistance element that does not affect the switching characteristics is incorporated as a protection circuit.

  In the invention according to the fourth aspect of the present invention, the high resistance element (for example, 10 kΩ or more) that does not affect the switching characteristics between the common pattern of the gate drive wiring pattern and the source potential wiring pattern. ), The gate-source voltage is maintained at 0V and the gate of the FET element is turned off when the user accidentally applies power between the drain and source of the FET element with the gate terminal open. Since it becomes a potential, the FET element is not destroyed.

  According to a fifth aspect of the present invention, a plurality of FET elements connected in parallel are bridge-connected with a pattern on a substrate made of an insulating material, and a power supply terminal and an output terminal are arranged at the center of the substrate surface. The power supply wiring pattern and the output wiring pattern are laid out on the inner side of the substrate surface, and the gate driving wiring pattern is laid out on the outer surface of the substrate surface to constitute a half bridge circuit.

  In the invention according to claim 5 of the present invention, a plurality of FET elements connected in parallel are bridge-connected with a pattern on a substrate made of an insulating material, and a power supply terminal and an output terminal are arranged at the center of the substrate surface. By arranging and laying out the power supply wiring pattern and the output wiring pattern on the inner side of the substrate surface, and laying out the gate drive wiring pattern on the outer surface of the substrate surface to constitute a half bridge circuit, the surface current is made conductive. High-current high-speed switching operation by suppressing the phenomenon that the output current flows into the gate signal pattern and avoiding the phenomenon that the gate drive current is swayed by the output current due to the property that it flows easily in the shortest distance of the low impedance part of the body Can be performed.

  The invention according to claim 6 of the present invention is inducted by connecting a plurality of FET modules according to any one of claims 1, 2, 3, 4 or 5 of the present invention in parallel. This constitutes a heating inverter.

  In the invention according to claim 6 of the present invention, a plurality of FET modules according to any one of claims 1, 2, 3, 4 or 5 of the present invention are connected in parallel. Therefore, an induction heating inverter capable of high-speed switching with a large current can be configured.

  Further, the invention according to claim 7 of the present invention is a full bridge connection of a plurality of FET modules according to any one of claims 1, 2, 3, 4 or 5 of the present invention. An inverter for induction heating is configured.

  In the invention according to claim 7 of the present invention, a plurality of FET modules according to any one of claims 1, 2, 3, 4 or 5 of the present invention are connected in a full bridge connection. Therefore, an induction heating inverter capable of high-speed switching with a large current can be configured.

  Since the present invention is configured as described above, there is an excellent effect that a high-speed high-speed switching operation can be performed.

  Hereinafter, an example of an embodiment of an FET module and an induction heating inverter according to the present invention will be described with reference to the accompanying drawings.

FIGS. 1A, 1B, 1C, and 1D are explanatory diagrams of a configuration of an FET module according to an example of the embodiment of the present invention. FIGS. 2A and 2B show FIGS. (C) The electric circuit diagram of the FET module according to the present invention shown in (d) is shown. 1A is a front view of the FET module according to the present invention, and FIG. 1B is a plan view of the FET module according to the present invention, that is, a view showing the surface of the A surface of the substrate 12 described later. FIG. 1C is a view showing the surface of the B surface of the substrate 12 described later, and FIG. 1D is a left side view of the FET module according to the present invention.

  The FET module 10 according to the present invention is configured as an FET half-bridge module in which components described later are integrated.

  In this FET module 10, the substrate 12 is formed using a material having a high insulation resistance, that is, glass epoxy as an insulating material.

  The substrate 12 is fixed to a heat radiation block 16 via an electrically insulated resin spacer 14.

  A plurality of FET elements 18 connected in parallel are fixed to the heat radiation block 16 with screws 20, and a plurality of discrete FET elements 18 are mounted in parallel. In this embodiment, twelve FET elements 18 (6 parallel × 2 columns) are arranged, and “n = 6” in the electric circuit diagram shown in FIG.

  More specifically, the + side power supply wiring pattern and the − side power supply wiring are arranged inside one surface (referred to as “A surface” in this embodiment) 12a of the substrate 12 positioned on the upper surface side in the FET module 10. A source potential wiring pattern is laid out outside the surface of the A plane 12a.

  On the other hand, the output wiring pattern is laid out inside the other surface (referred to as “B surface” in this embodiment) 12b of the substrate 12 located on the lower surface side of the FET module 10, and the surface of the B surface 12b. A gate drive wiring pattern is laid out outside. The gate drive wiring pattern is widened.

  Then, six discrete FET elements 18 are mounted in parallel on the + side power supply wiring pattern, the − side power supply wiring pattern, and the output wiring pattern, and the six FET elements 18 are wired so that they can be switched simultaneously. At this time, the power supply terminal and the output terminal are arranged at the central portion of the A surface (B surface) of the substrate 12. A gate signal input connector and a gate resistor are mounted.

  Further, a high resistance element that does not affect the switching characteristics is incorporated as a protection circuit as a gate protection resistor between the common pattern of the gate drive wiring pattern and the source potential wiring pattern.

In the above configuration, in the FET module 10, the + side power supply wiring pattern and the − side power supply wiring pattern are laid out inside the A surface 12 a of the substrate 12, and the output wiring pattern is arranged inside the B surface 12 b of the substrate 12. The + side power supply wiring pattern, the − side power supply wiring pattern, and the output wiring pattern are arranged so as to face each other with an insulating material constituting the substrate 12, and the substrate 12 is made of an insulating material and insulated. Since the resistance is large, it is possible to reduce the wiring interval and to reduce the wiring inductance, that is, the surge voltage in high-speed switching, as compared with the case where the copper plate is three-dimensionally wired in the space. Therefore, since the derating can be set large with respect to the rated current of the FET element 18, the FET module 10 can perform high-current high-speed switching.

  In the FET module 10, the source potential wiring pattern is laid out outside the surface of the A surface 12a, and the gate driving wiring pattern is laid out outside the surface of the B surface 12b. Since the pattern is arranged so as to face the insulating material constituting the substrate 12, the wiring inductance is reduced, and the ringing phenomenon that occurs when the gate charge / gate discharge of the FET element 18 is performed at high speed. Suppressed, it is possible to prevent malfunction of the FET element 18 when it is turned on / off.

  Further, in the FET module 10, by widening the gate drive wiring pattern, the substrate 12 has a low relative dielectric constant, so that the wiring impedance is reduced. When the plurality of FET elements 18 are simultaneously turned on / off, each gate is reduced. Since the drive current is balanced, variation in turn-on / turn-off time of each FET element 18 is suppressed, and current concentration on a specific FET element 18 can be avoided, so that the six FET elements 18 are simultaneously turned on at high speed. / Can be turned off.

  Furthermore, in the FET module 10, by incorporating a high resistance element (for example, 10 kΩ or more) that does not affect the switching characteristics between the common pattern of the gate drive wiring pattern and the source potential wiring pattern. When a user accidentally applies power between the drain and source of the FET element while the gate element is in an open state, the gate-source voltage is kept at 0 V, and the gate of the FET element becomes an OFF potential. The element 18 is not destroyed.

  In the FET module 10, six FET element arrays connected in parallel are bridge-connected with a pattern on the substrate 12, and a power supply terminal and an output terminal are arranged at a central portion on the surface of the substrate 12. By laying out the output wiring pattern inside the substrate 12 and laying out the gate drive wiring pattern on the outer surface of the substrate 12 to form a half-bridge circuit, the surface current can be reduced to the shortest distance of the low impedance portion of the conductor. Due to the property of facilitating the flow, the phenomenon of the output current flowing into the gate signal pattern can be suppressed, and the phenomenon that the gate drive current is swung to the output current can be avoided, so that a high-current high-speed switching operation can be performed.

Here, when a plurality of FET modules 10 are connected in parallel, an induction heating inverter can be configured. Further, even if a plurality of FET modules 10 are connected by a full bridge, an induction heating inverter can be configured.

  That is, by connecting a plurality of FET modules 10 in parallel or by connecting a plurality of FET modules 10 in a full bridge, an induction heating inverter capable of high-current and high-speed switching can be configured.

In the above-described embodiment, a case where a material having a high insulation resistance, that is, a glass epoxy is used as the insulating material has been described as the material of the substrate 12, but the material of the substrate is not limited to the glass epoxy. Of course, for example, another material having a high insulation resistance, such as ceramic, that is, an insulating material may be used.

  INDUSTRIAL APPLICABILITY The present invention can be used for an inverter circuit of a high frequency power supply for induction heating, and in particular, can be used for a high frequency power supply that requires high speed switching.

FIGS. 1A, 1B, 1C, and 1D are explanatory views of the configuration of an FET module according to an example of the embodiment of the present invention, and FIG. 1A is a front view of the FET module according to the present invention. FIG. 1B is a plan view of the FET module according to the present invention, that is, a diagram showing a surface of the A surface of the substrate described later, and FIG. 1C is a diagram showing a surface of the B surface of the substrate described later. FIG. 1 (d) is a left side view of the FET module according to the present invention. FIG. 2 is an electric circuit diagram of the FET module according to the present invention shown in FIGS. 1 (a), (b), (c) and (d).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 FET module 12 Board | substrate 12a A surface 12b B surface 14 Resin spacer 16 Heat radiation block 18 FET element 20 Screw

Claims (7)

The + side power supply wiring pattern and the − side power supply wiring pattern are laid out inside one surface of the substrate made of an insulating material, and the output wiring pattern is laid out inside the other surface of the substrate to The wiring pattern and the negative power supply wiring pattern and the output wiring pattern are arranged so as to face each other with the insulating material interposed therebetween,
A FET module comprising a plurality of discrete FET elements mounted in parallel on the + side power supply wiring pattern, the − side power supply wiring pattern, and the output wiring pattern, and simultaneously switching the FET elements. The FET module according to claim 1,
A source potential wiring pattern is laid out outside the surface of the one surface, and a gate driving wiring pattern is laid out outside the surface of the other surface, and the source potential wiring pattern and the gate driving wiring pattern are An FET module characterized by being placed so as to face each other with an insulating material in between. The FET module according to claim 2, wherein
Widened the gate drive wiring pattern The FET module according to any one of claims 2 and 3,
A FET module comprising a high resistance element that does not affect switching characteristics as a protection circuit between the common pattern of the gate drive wiring pattern and the source potential wiring pattern. A plurality of FET elements connected in parallel are bridge-connected with a pattern on a substrate made of an insulating material, a power supply terminal and an output terminal are arranged at the center of the substrate surface, and the power supply wiring pattern and the output wiring pattern are connected to the substrate surface. An FET module comprising: a half-bridge circuit configured by laying out inside the substrate and laying out a gate drive wiring pattern on a surface outside the substrate surface.   An induction heating inverter in which a plurality of FET modules according to any one of claims 1, 2, 3, 4 or 5 are connected in parallel.   An induction heating inverter in which a plurality of FET modules according to any one of claims 1, 2, 3, 4 or 5 are connected in a full bridge.

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