JP2007026390A - System, method and program for verifying design of printed circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent omission in check of ground connection leading to a factor of deterioration of electric properties and to efficiently confirm validity of the ground connection. <P>SOLUTION: A data base in which a configuration surface, connection information, positional information and component information are associated with one another by every via, pattern and pad is created based on input design information of a printed circuit board. A via connection detection means 202 detects a connection form of a ground via by retrieving the via connected to a ground network and connectively arranged in an outer layer by referring to each data base, retrieving a pattern to be connected to the via and retrieving a pad to be connected to the via through the pattern. A via connection judgment means 203 determines existence of component information of a connection destination and a ground plane from the connection form of the ground via and when a connection destination pad of the via is a bypass capacitor and is further connected to the ground plane, performs error display by considering the fact as a ground connection error. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a printed circuit board design verification system, a printed circuit board design verification method, and a printed circuit board design verification program, and more particularly to a printed circuit board design verification system and a printed circuit board design verification method for detecting ground connection that causes deterioration of electrical characteristics. And a printed circuit board design verification program.

  When designing a current printed circuit board, various countermeasures are taken in addition to mounting noise countermeasure parts as an EMI (electromagnetic interference) countermeasure. For example, by providing a ground shield pattern to a signal pattern that causes noise such as a high-speed clock or a high-speed bus, or by attaching a ground plane to an empty space on the surface of the board, the electrical characteristics such as noise emission and clock interference are deteriorated. Measures to hold down are taken. Further, a bypass capacitor (hereinafter referred to as a bypass capacitor) is used in order to prevent power supply noise of an IC or the like.

  Patent Document 1 describes a system that prevents radiation noise from being generated from a wiring pattern on a printed circuit board by detecting EMC design conditions during printed circuit board wiring processing. The system described in Patent Document 1 extracts a clock signal wiring pattern (hereinafter referred to as a clock wiring pattern) and is wired only in two upper and lower layers of the power / ground layer, or is grounded adjacent to both sides. The clock wiring pattern that does not satisfy any of the design conditions is displayed as an error as an EMC design violation.

  Further, Patent Document 2 describes a system that detects an EMC design condition for adding a bypass capacitor at the time of printed circuit board wiring processing and adds a bypass capacitor to prevent generation of radiation noise. The system described in Patent Literature 2 extracts a power supply pin and a wiring pattern from the power supply pin to the power supply via, inspects a line length and a line width of the extracted wiring pattern, and determines whether or not a bypass capacitor can be added. . If it is impossible to add a bypass capacitor in the current routing route, the routing route to which a bypass capacitor can be added is inspected. If the bypass route can be added by changing the routing path, the routing change and the bypass capacitor are added. If a bypass capacitor cannot be added even if the wiring route is changed, an error is displayed.

JP 2000-20573 (paragraphs 0007-0009, FIG. 1) JP 2000-35976 (paragraphs 0009-0010, FIG. 1)

  However, the system described in Patent Document 1 is only intended to prevent the generation of radiation noise by detecting a ground guard that a mounting designer has forgotten to install, and is a ground for radiating noise. Is not taken into account, for example, where it is connected, for example, where it is connected, what other components are connected, and the like. Therefore, it is not always possible to effectively prevent EMI.

  Similarly, in the system described in Patent Document 2, the purpose is merely to prevent the generation of radiation noise by adding a bypass capacitor that the mounting designer has forgotten to install, and is added or originally installed. The connection from the bypass capacitor to the ground is not considered. Therefore, it is not always possible to effectively prevent EMI.

  For example, a mounting designer should connect on the surface a ground via for preventing clock noise to be connected to a ground plane originally provided in the inner layer and a ground via for a bypass capacitor for preventing power supply noise such as an IC. In the case of mounting design, on the contrary, it becomes a factor that deteriorates electrical characteristics. In order to detect such an incorrect ground connection during mounting design, the mounting designer must visually check these connections on the CAD, and the time required for checking and checking by the mounting designer. There is a problem that it takes more than necessary.

  Therefore, in the design verification of the printed circuit board, the printed circuit board design verification system capable of preventing ground connection check omission that causes deterioration of electrical characteristics and efficiently confirming the validity of the ground connection, An object of the present invention is to provide a printed circuit board design verification method and a printed circuit board design verification program.

  A printed circuit board design verification system according to the present invention includes a ground plane and a print for preventing noise of a signal pattern formed on a printed circuit board based on printed circuit board design information indicating the printed circuit board design information on which an electronic circuit is formed. Determination means for determining whether or not a ground of a power supply noise prevention element for preventing power supply noise of a component arranged on the board is connected, and the ground plane and a ground of the power supply noise prevention element are connected And an error display means for displaying an error indicating that the printed circuit board mounting design is incorrect.

  Further, as an aspect of the printed circuit board design verification system according to the present invention, the ground on the surface of the printed circuit board is determined based on the printed circuit board design information including information indicating the conductor disposed on the printed circuit board and information indicating the arrangement and wiring of the conductor. Via connection detecting means for detecting a via connected to the via and detecting a conductor physically connected to the via; and print design information including information indicating the via and the conductor detected by the via connection detecting means. Using, via connection determination means for determining whether a ground plane and the ground of the power supply noise prevention element are connected via the via based on a predetermined evaluation criterion, the error display means The via connection determination means determines that the ground plane is connected to the ground of the power supply noise prevention element. In the case, it may display an error.

  Further, as a specific aspect of the printed circuit board design verification system according to the present invention, the printed circuit board design information includes, from the printed circuit board design information, at least ground plane position information, via, pattern, and pad position information and connection destination net information, and a pad. Design information storage means for deriving the component information and storing the derived conductor information in a searchable manner, and the via connection detecting means sequentially uses each conductor information stored in the design information storage means. May detect vias connected to the ground on the substrate surface and conductors physically connected to the vias.

  Further, as a more specific aspect, the via connection detection means is physically connected to the via connected to the ground net in the outer layer and the via by sequentially using the information of each conductor stored in the design information storage means. Detecting a pad, and via connection determining means, based on the via position information stored in the design information storage means and the component information of the pad, the pad is a pad of an electrical noise prevention element, and the via When a ground plane exists in the outer layer indicated by the position information, it may be determined that the ground plane and the ground of the power supply noise prevention element are connected.

  Further, as another specific aspect, the via connection detection means detects the first via connected to the ground net in the outer layer by sequentially using the information of each conductor stored in the design information storage means, and further, A pad physically connected to the first via and one or more second vias physically connected to the first via are detected, and the via connection determination means is stored in the design information storage means Based on the position information of the second via and the component information of the pad, the pad is a pad of an electrical noise prevention element, and a ground plane exists in the outer layer indicated by the position information of the second via. In this case, it may be determined that the ground plane and the ground of the power supply noise prevention element are connected.

  Also, as an aspect of the printed circuit board design verification system according to the present invention, information on vias detected by via connection detection means and conductors physically connected to the vias are searched as being associated with the vias as via connection form information. Via information storage means for storing the information as possible, and via information display means for searching for and displaying information to be provided to the user from via connection information stored in the via information storage means.

  In the printed circuit board design verification method according to the present invention, the determination unit prevents noise in the signal pattern formed on the printed circuit board based on the printed circuit board design information indicating the printed circuit board design information on which the electronic circuit is formed. Determining whether or not a ground plane for connecting to a ground of a power supply noise prevention element for preventing power supply noise of components arranged on the printed circuit board is connected, and an error display means includes the ground plane and the power supply noise When it is determined that the ground of the prevention element is connected, an error indicating that the mounting design of the printed circuit board is incorrect is displayed.

  Further, the printed circuit board design verification program according to the present invention prevents the noise of the signal pattern formed on the printed circuit board based on the printed circuit board design information indicating the printed circuit board design information on which the electronic circuit is formed. A determination process for determining whether or not a ground plane of a power supply noise prevention element for preventing power supply noise of a component arranged on a printed circuit board is connected, and the ground plane and the power supply noise prevention element When it is determined that the ground is connected, an error display process for displaying an error indicating that the mounting design of the printed circuit board is incorrect is executed.

  According to the present invention, at the time of design verification of a printed circuit board, it is possible to prevent a check omission regarding ground connection that causes deterioration of electrical characteristics and to efficiently check the validity of ground connection.

  In addition, as an aspect of the present invention, by detecting the connection form of the via, it is determined whether or not the ground plane and the ground of the power supply noise prevention element are connected, thereby reliably deteriorating the electrical characteristics. Possible ground connections can be detected.

  Further, as another specific aspect of the present invention, it is possible to easily and reliably check the validity of ground connection by storing information relating to each conductor from the printed circuit board design information so as to be searchable and sequentially collating the information. It becomes.

  Further, as another specific aspect of the present invention, by detecting a via connected to a ground net and a pad physically connected to the via in the outer layer, a contact via of the ground plane and a ground via of the power supply noise prevention element are detected. It is possible to prevent the deterioration of electrical characteristics caused by the connection between and.

  According to another specific aspect of the present invention, a first via connected to a ground net is detected in an outer layer, and a pad physically connected to the first via and a physical connection to the first via are physically detected. Detects one or more second vias connected to a ground connection error even when the ground plane contact via and the power supply noise prevention element ground via are indirectly connected can do.

  Further, as another aspect of the present invention, by listing and displaying the ground via connection forms, the position and connection destination of the ground via can be confirmed at a glance, and the ground via connection can be corrected efficiently. Can do. Further, for example, the design data can be designed so that the mounting designer can extend the ground plane more effectively by drawing the design data and displaying it in different colors.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, CAD data refers to printed circuit board design information generated by CAD. The printed circuit board design information is information indicating design information of a printed circuit board on which an electronic circuit is formed. In the present embodiment, the printed circuit board design information is specifically information indicating information on conductors arranged on the printed circuit board and information on the arrangement and wiring of the conductors. For example, a ground plane stretched on the outer layer , Information on the configuration surface, connection destination network, and position of the via, pattern, and pad, and component information of the pad.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration example of a printed circuit board design verification system according to the first embodiment of the present invention. The printed circuit board design verification system shown in FIG. 1 includes CAD data input means 100, analysis means 200, data storage means 300, and error display means 400. The analysis unit 200 includes a CAD data analysis unit 201, a via connection detection unit 202, and a via connection determination unit 203.

  The CAD data input means 100 inputs CAD data according to a user operation. The CAD data to be input is, for example, printed circuit board design information designed in advance by a user using CAD software. Alternatively, this system may include printed circuit board design information that is provided with means equivalent to CAD software and is input by the user each time. The data storage means 300 stores information on each conductor extracted from CAD data input from the user. The error display unit 400 displays the content of the error detected by the analysis unit 200 to the user.

  The CAD data analysis unit 201 extracts via, pattern, and pad information from CAD data input by a user, and generates a via database, a pattern database, and a pad database. The via connection detection unit 202 refers to each database generated by the CAD data analysis unit 201 and detects the connection form of the ground via. In the present embodiment, the connection form is information indicating a connection state and connection destination information. The via connection determination unit 203 determines whether or not the ground via connection form detected by the via connection detection unit 202 violates a predetermined condition. If the violation is violated, the printed circuit board mounting design is incorrect. An error indicating this is detected.

  In the present embodiment, the via connection detection unit 202 and the via connection determination unit 203 detect the connection form of the ground via, and determine whether or not the ground via connection bristle position violates a predetermined condition. Thus, a ground plane for preventing noise of a signal pattern formed on the printed circuit board and a ground of a power supply noise preventing element (for example, a bypass capacitor) for preventing power supply noise of components arranged on the printed circuit board. Can be determined.

  This system may be realized by an information processing terminal such as a personal computer design verification apparatus including at least an input device, an output device, a storage device, and a CPU. In the present embodiment, the CAD data input means 100 is realized by an input device (not shown) such as a file reading device, a keyboard, and a mouse, and a CPU that operates according to a program. The data storage means 300 is realized by a storage device provided in this system. The error display means 400 is realized by, for example, a display device, an output device (not shown) such as a speaker, and a CPU that operates according to a program. The CAD data analysis unit 201, the via connection detection unit 202, and the via connection determination unit 203 are realized by a CPU that operates according to a program, for example. The program is stored in a storage device (not shown) provided in the system.

  Next, CAD data input to the CAD data input unit 100 will be described. In the present embodiment, the CAD data includes information as shown in FIG. 2 regarding the pads and vias of components arranged on the printed circuit board and patterns connecting them. FIG. 2 is an explanatory diagram showing a configuration example of CAD data in this system. As shown in FIG. 2, the CAD data includes a conductor type (A type), a configuration surface (B type), connection information (C type), position information (D type), and component information (E type). In addition to the information shown in FIG. 2, the CAD data is based on the coordinates to determine whether or not a ground plane (also called a ground shield when stretched on the surface) is stretched at least at certain coordinates on the outer layer. Contains possible information. In the present invention, a shield pattern formed by running a pattern connected to the ground in parallel with the signal pattern is also handled as a ground plane.

  The conductor type (A type) is information indicating a conductor constituting the wiring of the printed circuit board, and is information that can be classified into at least “pad”, “via”, and “pattern”. The configuration surface (B type) is information indicating a surface or a layer on which conductors classified as the A type are configured, and is information that can distinguish between layers and whether it is an outer layer or an inner layer. For example, it is information that can be classified into “component surface”, “solder surface”, “inner layer (X)”, “interlayer (XY)”, and “all layers” (X is the start layer when straddling layers, straddling layers) If there is no, information indicating the hierarchy of the layer is indicated, and Y indicates information identifying the hierarchy of the end layer when straddling the layer). In addition, information on how many layers the substrate may be given to the configuration surface (B type) after numbering the multilayer substrates for each layer, such as “Layer 1” and “Layer 2”. When the conductor type (A type) is a via, the through-hole via may be classified as “all layers”, and the pered via or blind via may be classified as “interlayer (X to Y)”. The connection information (C type) is information indicating the connection destination of the conductors classified as the A type, and is information that can be classified into “ground net”, “power source net”, and “signal net”. The position information (D type) is information indicating the position where the conductors classified as the A type are configured. The center coordinate is set in the case of a pad and a via, and the start coordinate and the end coordinate are set in the case of a pattern. Derivable information. The component information (E type) is information indicating information of a component to which the pad belongs when the conductor classified as the A type is a pad, and is information that can be classified into “pass capacitor” and “others”. Here, “others” represents a component (for example, an IC or the like) other than the bypass capacitor. The component information (E type) is information that exists only when the conductor classified as the A type is a pad.

  Next, an example of data conversion to CAD data will be described taking the printed circuit board shown in FIG. 3 as an example. FIG. 3 is an explanatory diagram showing a design example of the printed circuit board in the present embodiment. The printed circuit board shown in FIG. 3 is a multilayer board double-sided mounting printed circuit board. The conductor arranged on the component surface is represented by a solid line, and the conductor arranged on the solder surface is represented by a broken line. The surface is distinguished by a shaded line.) As shown in FIG. 3, in the multilayer board double-sided mounting printed circuit board 1 on the mounting design CAD, a bypass capacitor 4 is arranged between the IC 3 and the power source of the IC 3 on the component side, and the power source of the IC 5 and the IC 5 is connected on the solder side A bypass capacitor 6 is arranged between them.

  The signal pattern 87 from the pad 32 of the component surface side IC 3 is connected to the solder surface side signal pattern 88 through the via 75, and the signal pattern 88 is connected to the pad 53 of the solder surface side IC 5. The bypass capacitor 4 connected to the component surface side IC 3 has a pad 41 connected to the power supply pad 31 of the IC 3 via a pattern 81, a pad 41 connected to the via 71 connected to the inner power supply plane via a pattern 82, The pad 42 is connected to the via 71 connected to the inner layer ground plane through the pattern 83. Similarly, the bypass capacitor 6 connected to the solder side IC 5 has a pad 61 connected to the power supply pad 51 of the IC 5 through the pattern 84, and the pad 61 connected to the via 73 connected to the inner power supply plane through the pattern 85. The pad 62 is connected to the via 74 connected to the inner layer ground plane through the pattern 86.

  In addition, a ground plane 2 (for example, a silver foil for shielding) is stretched in an empty space on the multilayer board double-sided mounting printed board 1, as shown in FIG. 4, and vias 77, 78, By providing 79, the ground is strengthened. FIG. 4 is an explanatory diagram for illustrating an area of the ground plane 2 attached to the surface of the multilayer board double-sided mounting printed board 1 shown in FIG. Further, the pad 52 of the solder surface IC5 is connected to the ground by a via 76 connected to the inner layer ground plane through the pattern 89.

  The multilayer board double-sided mounting printed circuit board 1 arranged and wired as described above is converted into data as, for example, CAD data as shown in FIG. FIG. 5 is an explanatory diagram showing an example of CAD data of the multilayer board double-sided mounting printed board in the present embodiment. Note that the position information (D type) represents the X coordinate and the Y coordinate in the form of X_Y. For example, the pad 31 of the component surface side IC 3 has a conductor type (A type) of “pad”, a configuration surface (B type) of “component side”, connection information (C type) of “power supply net”, and position information (D type). ) As the center coordinates “5_20” and the component information (E type) as “others”. The pad 32 of the component side IC 3 has a conductor type (A type) of “pad”, a configuration surface (B type) of “component side”, connection information (C type) of “signal net”, and position information (D type). The center coordinates “5_24” and the part information (E type) are converted into data as “others”. The pad 62 of the solder surface bypass capacitor 6 has a conductor type (A type) of “pad”, a configuration surface (B type) of “solder surface”, connection information (C type) of “ground net”, and position information (D type). The center coordinates “8_14” and the component information (E type) are converted into data as “bypass”.

  The via 71 connected to the component surface bypass capacitor 3 has a conductor type (A type) of “via”, a configuration surface (B type) of “all layers”, connection information (C type) of “power supply net”, and position information (D Type) as center coordinates “9_20”. The pattern 81 for connecting the component surface IC3 and the bypass capacitor 3 has a conductor type (A type) of “pattern”, a configuration surface (B type) of “component surface”, connection information (C type) of “power supply net”, and position information. (D type) is converted into data as the leading coordinates “5_20” and the terminal coordinates “7_20”. The via 75 that connects the component surface IC3 and the solder surface IC5 via the patterns 87 and 88 has a conductor type (A type) of “via”, a component surface (B type) of “all layers”, and connection information (C type). As “signal net” and the position information (D type) as the center coordinates “14_18”. A description of data formation of other conductors is omitted.

  Next, the operation of the present embodiment will be described with reference to the flowcharts of FIGS. First, the CAD data input means 100 inputs CAD data according to a user operation. As described above, the CAD data to be input is, for example, printed circuit board design information designed in advance by a user using CAD software. Here, a case where CAD data shown in FIG. 5 is input will be described as an example. When CAD data is input by the CAD data input unit 100, the CAD data analysis unit 201 analyzes the CAD data for each of the via, the pattern, and the pad to generate a via database, a pattern database, and a pad database (Step S1, S2, S3).

  For example, as shown in FIG. 10, the via database includes at least the configuration surface (B type), the connection information (C type), and the position information (D type) from data in which the conductor type (A type) is classified into vias. These are stored in association with each other so that they can be extracted. For example, as shown in FIG. 11, the pattern database includes at least the contents of at least the configuration surface (B type), the connection information (C type), and the position information (D type) from the data in which the conductor type (A type) is sorted into patterns. Are stored in association with each other so that they can be extracted. For example, as shown in FIG. 12, the pattern database includes at least a configuration surface (B type), connection information (C type), position information (D type), and parts from data in which the conductor type (A type) is classified into patterns. The contents of the information (E type) are stored in association with each other so that they can be extracted. Since the description of each type is the same as the description of each type in CAD data, it is omitted.

  Specifically, the CAD data analyzing unit 201 extracts all data in which the conductor type (A type) is classified into “via” from the CAD data, and the configuration surface (B type) and connection information (C A via database is generated by deriving the type) and position information (D type). Also, all data in which the conductor type (A type) is classified into “pattern” is extracted from the CAD data, and the configuration surface (B type), connection information (C type), position information (D type), and the like are extracted from the extracted data. To generate a pattern database. Further, all data in which the conductor type (A type) is classified into “pad” is extracted from the CAD data, and the configuration surface (B type), connection information (C type), position information (D type), and the like are extracted from the extracted data. The component information (E type) is derived to generate a pad database.

  For example, when CAD data as shown in FIG. 5 is input, the CAD data analyzing means 201 stores a via database including data of vias 71, 72, 73, 74, 75, 76, 77, 78, 79. A pattern database including data of patterns 81, 82, 83, 84, 85, 86, 87, 88, 89 is stored, and data of pads 31, 32, 41, 42, 51, 52, 53, 61, 62 is stored. Store the containing pad database. In addition, when the CAD data includes information on an unconnected pad (a pad in which the figure number in FIG. 5 is not assigned), the connection information (C type) for the unconnected pad is not connected. The information shown may be stored in the pad database.

  Next, the via connection detection unit 202 searches for a via that is a ground via and connected to the outer layer. Specifically, the via database generated by the CAD data analysis unit 201 is sequentially referred to, and the following operations are performed on the data of each via (steps S4 to S7). Steps S4 and S7 represent the start and end of the via database analysis process. The via database analysis process is a process in which the following operation is repeatedly performed for via data that is each element of the via database until the end of analysis of all elements of the via database. Hereinafter, a via that is a target of via database analysis processing is referred to as a target via.

  First, the via connection detection unit 202 determines whether the target via is a ground via based on connection information (C type) (step S5). Here, when the connection information (C type) of the target via is “ground net”, it is determined as a ground via, and when it is other than the ground net (in this case, “power net” or “signal net”), the ground via is determined. It is determined that it is not. Next, when the target via is a ground via (YES in step S5), the via connection detection unit 202 determines whether the target via is an inner via connected between inner layers based on the configuration surface (B type). (Step S6). Here, if the constituent surface (type B) of the target via is an interlayer and only an inner layer is determined, it is determined as an inner via (in the case of an outer layer to an inner layer, it is not an inner via). If the target via is not a ground via (NO in step S5), or if the target via is a ground via and is an inner via (YES in step S6), the operation for the data of the target via is terminated and the process proceeds to the next via. move on. That is, since there is no possibility that the ground via is connected on the substrate surface, the processing is terminated.

  Conversely, if the target via is a ground via and not an inner via (NO in step S6), the operation for detecting the connection form of the detected via is advanced assuming that the via to be searched is detected. Hereinafter, the detected via is referred to as a determination target via. The via connection detection unit 202 refers to the pattern database and searches for a pattern used for ground connection on the same mounting surface as the determination target via and connected to the determination target via. Specifically, the via connection detection unit 202 sequentially refers to the pattern database generated by the CAD data analysis unit 201 and performs the following processing on the data of each pattern (steps S11 and S14). Steps S11 and S14 represent the start and end of the pattern database analysis process. The pattern database analysis process is a process in which the following operations are repeatedly performed on pattern data that is each element of the pattern database until all element analysis of the pattern database is completed. Hereinafter, a pattern that is a target of pattern database analysis processing is referred to as a target pattern.

  First, the via connection detection unit 202 determines whether the configuration surface (B type) and the connection information (C type) match between the target pattern and the determination target via (step S12). At this time, when the via configuration surface (B type) is “all layers”, all layers are handled (determine that the configuration surfaces of the patterns match each other). In addition, when the via construction surface (B type) is “interlayer (X to Y)”, the layer between the X layer and the Y layer is also included. When the target pattern has the same configuration surface (B type) and connection information (C type) as the determination target via (YES in step S12), the via connection detection unit 202 determines whether the target pattern is connected to the determination target via. Determine. Specifically, it is determined whether or not the start coordinate or the end coordinate that is the position information (D type) of the target pattern matches the center coordinate that is the position information (D type) of the determination target via (step S13).

  When the target pattern and the determination target via have the same configuration surface (B type) and connection information (C type) (NO in step S12), or when the target pattern does not match the position information (D type) of the determination target via In (NO in step S13), the operation on the data of the target pattern ends, and the process proceeds to the next pattern. That is, since the target pattern is not likely to be connected to the determination target via, the process ends.

  Conversely, when the target pattern has the same configuration surface (B type) and connection information (C type) as the determination target via and the target pattern matches the position information (D type) of the determination target via (YES in step S12). ) Advances the operation for detecting the connection destination of the detected pattern, assuming that the pattern connected to the determination target via is detected. Hereinafter, the detected pattern is referred to as a determination target pattern. The via connection detection unit 202 refers to the pad database and searches for a pad used for ground connection on the same mounting surface as the determination target pattern and connected to the determination target pattern. Specifically, the via connection detection unit 202 sequentially refers to the pad database generated by the CAD data analysis unit 201, and performs the following processing on the data of each pad (steps S21 and S24). Steps S21 and S24 represent the start and end of the pad database analysis process. The pad database analysis process is a process in which the following operation is repeatedly performed on pad data which is each element of the pad database until all element analysis of the pad database is completed. Hereinafter, a pad to be subjected to pad database analysis processing is referred to as a target pad.

  First, the via connection detection unit 202 determines whether the configuration surface (B type) and the connection information (C type) match between the target pad and the determination target pattern (step S22). When the target pattern has the same configuration surface (B type) and connection information (C type) as the determination target pad (YES in step S22), the via connection detection unit 202 determines whether the target pad is connected to the determination target pattern. Determine. Specifically, it is determined whether or not the center coordinates, which are the position information (D type) of the target pad, coincide with the start coordinates or the end coordinates, which are the position information (D type) of the determination target pattern (step S23). Here, for the position information (D type) of the determination target pattern, the coordinates on the side that does not match the determination target via are used for the determination (that is, the end coordinates are used for the determination when the leading coordinates match the center coordinates of the vias). If the end coordinates coincide with the via center coordinates, the top coordinates are used for determination.)

  When the target pad is not the same configuration surface (B type) and connection information (C type) as the determination target pattern (NO in step S22), or when the target pad does not match the position coordinates (D type) of the determination target pattern (step) If NO in S23, the operation for the data of the target pad ends, and the process proceeds to the next pad. That is, there is no possibility that the target pad is directly connected to the determination target via via the pattern, and thus the processing ends.

  When the target pad has the same configuration surface (B type) and connection information (C type) as the determination target pattern and the position coordinates (D type) of the determination target pattern match the target pad (YES in step S23) The via connection detection unit 202 instructs the via connection determination unit 203 to determine an error regarding the connection form of the determination target via, assuming that the pad connected to the determination target via through the pattern is detected.

  The via connection determination unit 203 receives an instruction from the via connection detection unit 202 and determines whether or not there is a factor that deteriorates the electrical characteristics of the connection form of the determination target via detected by the via connection detection unit 202. Judgment by comparing with. Specifically, the via connection determination unit 303 first determines whether or not the component information (E type) of the target pad connected to the determination target via is a bypass capacitor (step S31). When the part information (E type) of the target pad is not a bypass capacitor (NO in step S31), no deterioration factor is assumed. When the component information (E type) of the target pad is a bypass capacitor (YES in step S31), it is determined whether the determination target via is connected to the ground plane by referring to the data of the determination target via. Specifically, the via connection determination unit 203 determines whether or not a ground plane exists on the configuration surface (B type) and position coordinates (D type) of the determination target via (step S32). If a ground plane exists (YES in step S32), an error may occur because the ground for signal noise and the bypass capacitor for power supply noise are connected by the determination target via. Is determined.

  The via connection determination unit 303 not only determines whether or not a ground plane exists from the coordinate information of the ground plane, but also includes other vias that can be connected to the determination target via and their connection destinations. It is more preferable to determine whether or not to do so. In response to the error determination of the via connection determination unit 303, the error display unit 400 displays that the ground connection via the determination target via is an error.

  The error display means 400 displays, for example, a printed circuit board drawn on the basis of the printed circuit board design information, displays the via determined to be an error on the drawing in a color distinguished from other vias, and connects the ground. May be displayed as an error. In addition, when color-coding on the drawing, not only the via determined to be an error, but also the bypass capacitor and ground plane causing the error, and the connection path thereof may be color-coded and displayed. By visually displaying the error location to the user in this way, the user can easily identify the error location and the cause thereof, and can efficiently perform redesign such as changing their connection.

  Further, the via connection detection unit 202 continues to detect the connection form of the determination target via even after issuing an error determination instruction to the via connection determination unit 203. By detecting the pad connected to the determination target pattern, the search operation for the pad connected to the determination target pattern is terminated, and the search operation for another pattern connected to the determination target via is continued. That is, the pad database analysis process is terminated, and the process advances to the next pattern in the pattern database analysis process (returns to step S12). The via connection detection unit 202 repeats the above operation until the analysis of all the elements in the pattern database is completed. When the search operation for all patterns connected to one determination target via is completed, the process proceeds to the next via in the via database analysis process (returns to step S5). The via connection detection unit 202 repeats the above operation until the analysis of all elements in the via database is completed.

  As described above, according to the present embodiment, vias, patterns, and pad information are read from printed circuit board design information that has been converted into numerical data, and by automatically detecting connection forms of all vias that can cause errors, It is possible to efficiently and surely perform a separation check between the ground via of the bypass capacitor on the substrate and the ground via for signal noise countermeasure, which has been visually performed by the mounting designer.

  In the present embodiment, the determination unit is realized by the via connection detection unit 202 and the via connection determination unit 203. The error display means is realized by the error display means 400. Further, the via connection detection means is realized by the via connection detection means 202. The via connection determination unit is realized by the via connection determination unit 203. The design information storage unit is realized by the CAD data analysis unit 201 and the data storage unit 300.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram showing a configuration example of a printed circuit board design verification system according to the second embodiment of the present invention. The printed circuit board design verification system shown in FIG. 13 includes CAD data input means 100, analysis means 200, data storage means 300, error display means 400, and via list display means 401. The analysis unit 200 includes a CAD data analysis unit 201, a via connection detection unit 202, a via connection determination unit 203, and a via list generation unit 204. Compared with the first embodiment shown in FIG. 1, a point that a via list generation unit 204 and a via list display unit 401 are added is different.

  The via list generation unit 204 generates a ground via database based on the results of various determinations by the via connection detection unit 202 in the process in which the via connection detection unit 202 detects the ground via connection form. The via list display unit 401 refers to the ground via database generated by the via list generation unit 204 and displays ground via information, for example, the position and connection state to the user.

  In the present embodiment, the via list generation unit 204 is realized by a CPU that operates according to a program, for example. The via list display unit 401 is realized by, for example, a display device, an output device (not shown) such as a speaker, and a CPU that operates according to a program.

  The database of ground vias generated by the via list generation unit 204 can extract the contents of connection destination component information (F type) in addition to the types of via databases described in the first embodiment as shown in FIG. 14, for example. It may be stored in association with. The connection destination component information (F type) is information indicating a connection destination component of the via, and is information classified into, for example, “other than component”, “capacitor”, and “other”. Here, “non-component” refers to a via that is not directly connected to the pad in a pattern, and “capacitor” refers to a via that is connected via a pattern to a pad whose component information (E type) is a bypass capacitor. The component information (E type) indicates a via connected to a pad of a component other than a bypass capacitor (for example, an IC or the like) through a pattern.

  Next, the operation of the present embodiment will be described with reference to the flowcharts of FIGS. In the present embodiment, the operations from step S1 to S6 are the same as those in the first embodiment, and the description thereof is omitted.

  The via list generation means 204 receives the data of the target via as a ground via in response to the fact that the via connection detection means 202 has detected a ground via on the substrate surface in the via database analysis process (steps S4 to S7) (NO in step S6). Register in the database. As the data to be registered, the contents stored in the via database may be used as they are. At this time, “other than components” may be used as the initial value for the connection destination component information. Since the operations from step S6 to S31 are the same as those in the first embodiment, description thereof is omitted. In addition, the via connection detection unit 202 detects a pad connected to a determination target pattern (in this case, a pattern connected to a determination target via) in the pad database analysis process (steps S21 to S24). (YES in step S23)

  Next, the via list generation unit 204 detects that the via connection detection unit 202 has detected a pad connected to the determination target via in the pad database analysis process (steps S21 to S24) (YES in step S23), and then the ground list is generated. The connection destination component information (F type) of the determination target via is registered in the via database. At this time, the via list generation unit 204 may acquire the connection destination component information (F type) by referring to the component information (E type) of the target pad from the pad database, or the via connection determination unit 203 in step S31. The connection destination component information (F type) may be acquired from the determined result. In such a case, if the component information (E type) of the target pad is “bypass” (YES in step S31), the connection destination component information (F type) in the ground via database is registered as “capacitor”. (Step S42) When the component information (E type) of the target pad is “other” (NO in step S31), the connection destination component information (F type) in the ground via database is registered as “other” (step S43). ).

  In this embodiment, when the via connection determination unit 203 determines an error based on the connection form of the determination target via, the determination target via is different from the ground via database generated by the via list generation unit 204. An error may also be determined if the component terminal is also used.

  Next, after the via connection detection unit 202 finishes analyzing all the elements of the via database, the via list display unit 401 displays information on the ground vias registered in the ground via database (step S44). The ground via information may be displayed according to the user's request. For example, the printed circuit board to be verified for design data is the multilayer board double-sided printed circuit board shown in FIG. 3, and the CAD data input to the CAD data input means 100 has the contents shown in FIG. A ground via database as shown in FIG. 17 is generated. The via list display unit 401 may display a ground via list as shown in FIG. 18, for example. The user can view the information of ground vias at a time, and for example, when adjusting the position of the ground plane, it is possible to prevent connection leakage or to design more effectively. In addition, for example, the user can surely connect to the ground by displaying the color for each type of connection destination.

  As described above, according to the present embodiment, the position and connection destination of the ground via can be confirmed at a glance, and the ground connection can be designed reliably and effectively. For example, it is possible to more effectively suppress deterioration of electrical characteristics due to noise emission, clock interference, and the like by extending a ground plane that has a large area and is connected to the inner layer plane by more ground vias. In addition, for example, the ground vias connected to the capacitors can be checked at a glance, so it is possible to reliably connect the ground terminals of the bypass capacitors directly to the inner ground plane, and dedicated vias and patterns for each bypass capacitor. It becomes easier. By dedicating a via and a pattern to one bypass capacitor, it is possible to prevent deterioration of characteristics and electrical characteristics with respect to EMI.

  In the present embodiment, the via information storage unit is realized by the via list generation unit 204 and the data storage unit 300. The via information display unit is realized by the via list display unit 401.

  Next, the operation of the first exemplary embodiment will be described using a specific example. In this embodiment, the printed circuit board to be verified for design data is the multilayer board double-sided printed circuit board shown in FIG. 3, and the CAD data input to the CAD data input means 100 has the contents shown in FIG. A case will be described as an example. Further, it is assumed that the input CAD data includes not only the contents shown in FIG. 5 but also information that can determine based on the coordinates whether or not the ground plane 2 shown in FIG. 4 is stretched. Note that the step numbers given to the description of the operation of the present embodiment are described in correspondence with the flowcharts of FIGS. 6 to 9 showing the operation of the first embodiment.

  First, for example, CAD data as shown in FIG. 5 is input to the CAD data input means 100 from the user. When CAD data is input to the CAD data input unit 100, the CAD data analysis unit 201 analyzes the CAD data for each of the via, the pattern, and the pad, for example, the via database shown in FIG. 10 and the pattern shown in FIG. The database, the pad database shown in FIG. 12, is generated (steps S1, S2, S3).

  The via connection detection unit 202 sequentially refers to the via database generated by the CAD data analysis unit 201 and searches for vias that are ground vias and connected to the outer layer. When the elements included in the via database shown in FIG. 10 are processed one by one, the connection information (C type) of the via 72 is “ground net”. (Step S5). Next, since the configuration surface (B type) of the via 72 is “all layers”, the via connection detection unit 202 determines that the via 72 is not an inner via (step S6).

  Here, since the via 72 is a ground via and not an inner via, the via connection detection unit 202 searches for a pattern connected to the via 72 using the via 72 as a determination target via. When the elements included in the pattern database shown in FIG. 11 are processed one by one, first, the component surface (B type) “component surface” and the connection information (C type) “ground net” of the pattern 83 are the vias 72. Since the configuration surface (B type) is “all layers” and the connection information (C type) is “ground net”, the via connection detection unit 202 determines that the pattern 83 is used for ground connection on the same mounting surface as the via 72. (Step S12). At this time, since the configuration surface (B type) “all layers” of the via 72 is handled as including all layers, it can be determined that the configuration surface (B type) “component surface” of the pattern 83 matches. Next, since the end coordinates “9_18” in the position information (D type) of the pattern 83 matches the center coordinates “9_18” that is the position information (D type) of the via 72, the via connection detection unit 202 determines the via 72. And the pattern 83 are determined to be connected (step S13).

  Next, the via connection detection unit 202 searches for a pad connected to the pattern 83 because the pattern 83 connected to the determination target via 72 can be detected. When the elements included in the pad database shown in FIG. 12 are processed one by one, first, the component surface (B type) “component surface” and the connection information (C type) “ground net” of the pad 42 are the vias 83. Since it is the same as the component surface (B type) “component surface” and the connection information (C type) “ground net”, the via connection detection unit 202 determines that the pad 42 is used for ground connection on the same mounting surface ( Step S22). Next, since the center coordinate “7_18”, which is the position information (D type) of the pad 42, coincides with the first coordinate “7_18” of the position information (D type) of the pattern 83, the via connection detection unit 202 uses the pattern 83 And the pad 42 are determined to be connected (step S23). At this time, as the position information (D type) of the pattern 83, since the center coordinates of the via 72 and the end coordinates of the pattern 83 match, the start coordinates that do not match are used for determination.

  By the operation so far, the via connection detection unit 202 can detect the pad 42 connected to the determination target via 72 via the pattern 83, and thus the via connection determination unit 203 connects the via 72 as the determination target. Instructs the error judgment for. The via connection determination unit 203 determines whether the component information (E type) of the pad 42 connected to the via 72 is a bypass capacitor for the connection form of the via 72 (step S31). Since the equipment information (E type) of the pad 42 is “bypass”, it is determined whether or not the via 72 is connected to the ground plane (step S32). Here, as shown in FIG. 4, since the via 72 is not connected to the ground plane 2, it is determined that the via 72 is not a deterioration factor.

  The via connection detection unit 202 continues to detect the connection form of the via 72 that is the determination target even after issuing an error determination instruction to the via connection determination unit 203. Since the analysis operation up to the pattern 83 has been completed by the operations up to here, the process proceeds to the next pattern 84 (returns to step S12). When the elements included in the pattern database are processed one by one, there is no pattern connected to the determination target via 72, so the analysis operation for the via 72 is terminated. The via connection detection unit 202 proceeds to the next via 73 (returns to step S5). When the elements included in the via database shown in FIG. 10 are processed one by one, the via 74 is searched (steps S5 and S6).

  Next, the via connection detection unit 202 searches for a pattern connected to the via 74 using the via 74 as a determination target via. A pattern that is used for ground connection on the same mounting surface as the via 74 and is connected to the via 74 is searched with reference to the pattern database. When the elements included in the pattern database shown in FIG. 11 are processed one by one, the pattern 86 is searched (steps S12 and S13). Next, the via connection detection unit 202 searches for pads that are used for ground connection on the same mounting surface as the pattern 86 and are connected to the pattern 86 with reference to the pad database. When the elements included in the pad database shown in FIG. 12 are processed one by one, the pad 62 is searched (steps S22 and S23).

  Here, the via connection detection unit 202 detects that the connection form of the via 74 is a ground via by searching for the pad 62 used for the ground connection and connected to the pattern 86, and the via connection determination unit 203 Instruct the judgment. The via connection determination unit 203 detects that the connection destination component is a bypass capacitor for the connection form of the via 74 (step S31), and determines whether the via 74 is connected to the ground plane (step S32). . Here, as shown in FIG. 4, since the via 74 is connected to the ground plane 2, the via 74 can be a cause of deterioration, and thus is determined to be an error. The error display means 400 displays that the ground connection is an error for the via 74 determined as an error by the via connection determination means 303.

  As in the case of the via 72, the via connection detection unit 202 continues the connection type detection operation for the via 74 after issuing a determination instruction to the via connection determination unit 203. At this point, since the confirmation up to the pattern 86 has been completed, the next pattern 87 is referred to (return to step S12). When the elements included in the pattern database are processed one by one, the confirmation of the via 74 is completed because there is no pattern that is used for ground connection on the same mounting surface as the via 74 and connected to the via 74. . The via connection detection means 202 searches for a via that is a ground via and not an inner via from the next via 75 (returns to step S5). When the elements included in the via database shown in FIG. 10 are processed one by one, the via 76 is searched (steps S5 and S6).

  Next, the via connection detection means 202 searches the pattern that is used for ground connection on the same mounting surface as the via 76 and is connected to the via 76 with reference to the pattern database. When the elements included in the pattern database shown in FIG. 11 are processed one by one, the pattern 89 is searched (steps S12 and S13). Next, the via connection detection unit 202 refers to the pad database and searches for pads that are used for ground connection on the same mounting surface as the pattern 89 and that are connected to the pattern 89. When the elements included in the pad database shown in FIG. 12 are processed one by one, the pad 52 is searched (steps S22 and S23).

  Here, the via connection detection unit 202 detects that the connection form of the via 76 is a ground via by searching for the pad 52 used for the ground connection and connected to the pattern 89, and the via connection determination unit 203 Instruct the judgment. The via connection determination unit 203 determines whether or not the component information (E type) of the pad 52 connected to the via 76 is a bypass capacitor for the connection form of the via 76 (step S31). Since the equipment information (E type) of the pad 52 is “others”, it is determined that the via 76 is not a deterioration factor.

  As in the case of the via 74, the via connection detection unit 202 continues the connection type detection operation for the via 76 after issuing a determination instruction to the via connection determination unit 203. At this point, since the confirmation up to the pattern 89 has been completed, the pattern database repetitive operation is completed, and a search for vias that are ground vias but not inner vias is continued from the next via 76 (return to step S5). When the elements included in the via database shown in FIG. 10 are processed one by one, the via 77 is searched (steps S5 and S6).

  Next, the via connection detection means 202 searches the pattern that is used for ground connection on the same mounting surface as the via 77 and is connected to the via 77 with reference to the pattern database. When the elements included in the pattern database shown in FIG. 11 are processed one by one, it is detected that there is no pattern connected to the via 77 (steps S12 and S13).

  Since it has been found that there is no pattern to be connected, the via 77 can be used as a ground plane connection via, so there is no problem and the next operation is continued without causing an error. The vias 78 and 79 are the same as the via 77. Up to this point, the via database repetitive operation is completed, and the operation of the present embodiment ends.

  Next, the operation of the first embodiment will be described using another example. In this embodiment, a case where a signal layer is provided on the inner layer of a multilayer board double-sided mounting printed board will be described as an example. In this embodiment, the printed circuit board to be verified for the design data is the multilayer board double-sided mounted printed circuit board shown in FIG. 19, and the CAD data input to the CAD data input means 100 has the contents shown in FIG. Let's take an example. Further, it is assumed that the CAD data includes not only the contents shown in FIG. 20 but also information that can determine whether or not the ground plane 2 shown in FIG. 19 is stretched based on the coordinates. Note that the step numbers given to the description of the operation of the present embodiment are described in correspondence with the flowcharts of FIGS. 6 to 9 showing the operation of the first embodiment.

  FIG. 19 is an explanatory diagram showing a design example of a multilayer board double-sided mounting printed board in the present embodiment. In FIG. 19, the conductor disposed on the component surface is represented by a solid line, and the conductor disposed on the solder surface is represented by a dotted line (the pattern is distinguished from the component surface, the inner layer, and the solder surface by shading of lines. To do.) As shown in FIG. 19, the multilayer double-sided mounting printed circuit board 1 on the mounting design CAD has an IC 3 and a bypass capacitor 6 connected to its power source arranged on the component surface, and an IC 5 and its power source connected to the solder surface. A bypass capacitor 6 is arranged. Compared to the first embodiment shown in FIG. 3, the ground via 72 connected to the bypass capacitor 4 connected to the component surface side IC 3 is further connected via the via 91 connected to the inner layer ground plane and the inner layer pattern 101. The connection is different. Further, a pattern 87 in which the pads 32 of the component surface side IC 3 and the pads 53 of the solder surface side IC 5 are connected via the vias 75 is further connected via the inner layer pattern 102 to which the vias 92 and 93 are connected. The connection is different.

  FIG. 20 is an explanatory diagram showing an example of CAD data of the multilayer board double-sided printed circuit board 1 shown in FIG. In FIG. 20, the hatching of the figure number indicates a different part from the first embodiment shown in FIG. In the CAD data input in this embodiment, the inner signal layer is registered as “inner layer A”.

  Hereinafter, an operation in which the via 72 is determined to be an error will be specifically described. In this embodiment, a description will be given from the time when the via connection detection unit 202 refers to the information of the via 72. Since the operation up to that point is the same as that of the first embodiment, a description thereof will be omitted. The via connection detection unit 202 determines that the via 72 is a ground via and connected to the outer layer based on the connection information (C type) and the configuration surface (B type) of the via 72 (step S5). , S6).

  Next, the via connection detection unit 202 searches for a pattern used for ground connection on the same mounting surface as the via 72 and connected to the via 72 with reference to the pattern database. When the elements included in the pattern database are processed one by one, the pattern 83 is searched (steps S12 and S13). Next, the via connection detection unit 202 refers to the pad database and searches for pads that are used for ground connection on the same mounting surface as the pattern 83 and that are connected to the pattern 83. When the elements included in the pad database are processed one by one, the pad 42 is searched (steps S22 and S23).

  Here, the via connection detection unit 202 detects that the connection form of the via 72 is a ground via by searching for the pad 42 used for the brand connection and connected to the pattern 83, and the via connection determination unit 203 Instruct the judgment. The via connection determination unit 203 detects that the connection destination component is a bypass capacitor for the connection form of the via 72 (step S31), and determines whether the via 72 is connected to the ground plane (step S32). .

  Although it is not directly connected to the ground plane from the coordinate information which is the position information (D type) of the via 72, when the pattern database is searched for other patterns connected to the via 72, the pattern 101 is in the inner layer. To find data that is connected to the ground net. It is found that the pattern 101 is connected to the via 91 by searching the connection destination from the CAD data, the pad database, or the via database based on the position information (D type) of the pattern 101. From the configuration surface (B type) and position information (D type) of the via 91, it is found that a ground plane exists. Therefore, the via connection determination unit 203 determines that an error has occurred because the via 72 is connected to the ground plane and may cause deterioration. The error display unit 400 displays that the ground connection is an error for the via 72 determined to be an error by the via connection determination unit 303.

  Further, the via connection detection unit 202 continues the connection type detection operation for the via 72 even after issuing a determination instruction to the via connection determination unit 203. When the elements included in the pattern database are processed one by one, the pattern 101 is searched (steps S5 and S6). Next, the via connection detection unit 202 refers to the pad database and searches for pads that are used for ground connection on the same mounting surface as the pattern 101 and that are connected to the pattern 101. When the elements included in the pad database are processed one by one, it is detected that there is no pad connected to the pattern 101 (steps S22 and S23). Since it is determined that there is no pad to be connected, the next operation is continued without an error in connection with the pattern 101.

  Similarly, as for the operation of the via 91, after searching for the pattern 101 connected to the via 91, it is determined that there is no pad connected to the pattern 101, and the next operation is continued without causing an error in the via 91. .

  INDUSTRIAL APPLICABILITY The present invention can be applied to applications such as a system for verifying design and a printed circuit board wiring arrangement system using CAD when designing a printed circuit board using CAD.

It is a block diagram which shows the structural example of the printed circuit board design verification system in 1st Embodiment. It is explanatory drawing which showed the structural example of CAD data in this invention. It is explanatory drawing which shows the example of a design of a multilayer board double-sided mounting printed circuit board. It is explanatory drawing for showing the area | region of the ground plane 2 affixed on the multilayer board double-sided mounting printed circuit board 1 surface. It is explanatory drawing which shows an example of CAD data of a multilayer board double-sided mounting printed circuit board. It is a flowchart which shows operation | movement of the printed circuit board design verification system in 1st Embodiment. It is a flowchart which shows operation | movement of the printed circuit board design verification system in 1st Embodiment. It is a flowchart which shows operation | movement of the printed circuit board design verification system in 1st Embodiment. It is a flowchart which shows operation | movement of the printed circuit board design verification system in 1st Embodiment. It is explanatory drawing which shows an example of a via | veer database. It is explanatory drawing which shows an example of a pattern database. It is explanatory drawing which shows an example of a pad database. It is a block diagram which shows the structural example of the printed circuit board design verification system in 2nd Embodiment. It is explanatory drawing which shows the structural example of a ground via database. It is a flowchart which shows operation | movement of the printed circuit board design verification system in 2nd Embodiment. It is a flowchart which shows operation | movement of the printed circuit board design verification system in 2nd Embodiment. It is explanatory drawing which shows an example of a ground via database. It is explanatory drawing which shows an example of a ground via list. It is explanatory drawing which shows the example of a design of the multilayer board double-sided mounting printed circuit board in a 2nd Example. It is explanatory drawing which showed an example of the CAD data of the multilayer board double-sided mounting printed circuit board in the 2nd Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 CAD data input means 200 Analysis means 201 CAD data analysis means 202 Via connection detection means 203 Via connection determination means 300 Data storage means 400 Error display means

Claims (15)

Based on the printed circuit board design information indicating the printed circuit board design information on which the electronic circuit is formed, the ground plane for preventing the noise of the signal pattern formed on the printed circuit board and the power supply noise of the components placed on the printed circuit board are reduced. Determining means for determining whether or not the ground of the power supply noise preventing element for preventing is connected;
A printed circuit board comprising error display means for displaying an error indicating that the mounting design of the printed circuit board is incorrect when it is determined that the ground plane and the ground of the power supply noise prevention element are connected. Design verification system. The judging means is
Based on printed circuit board design information including information indicating a conductor arranged on the printed circuit board and information indicating the arrangement and wiring of the conductor, a via connected to the ground is detected on the surface of the board, and the via and the physical Via connection detecting means for detecting a conductor to be electrically connected;
Using print design information including information indicating vias and conductors detected by the via connection detection means, a ground plane and a ground of the power supply noise prevention element are connected via the vias based on a predetermined evaluation criterion. Via connection determination means for determining whether or not to be connected,
The printed circuit board design verification system according to claim 1, wherein the error display unit displays an error when the via connection determination unit determines that the ground plane and the ground of the power supply noise prevention element are connected. The judging means is
From the printed circuit board design information, derive at least ground plane position information, via, pattern, pad position information and connection destination net information, pad component information, and pad component information. Including design information storage means for storing in a searchable manner;
The via connection detection means detects the vias connected to the ground on the substrate surface and the conductors physically connected to the vias by sequentially using the information of each conductor stored in the design information storage means. 2. The printed circuit board design verification system according to 2. The via connection detection means detects the vias connected to the ground net in the outer layer and the pads physically connected to the vias by sequentially using the information of each conductor stored in the design information storage means,
The via connection determining means is based on the via position information and the pad component information stored in the design information storage means, and the pad is a pad of an electrical noise prevention element and the outer layer pointed to by the via position information. The printed circuit board design verification system according to claim 3, wherein the ground plane and the ground of the power supply noise prevention element are determined to be connected when a ground plane exists in the circuit board. The via connection detection means detects the first via connected to the ground net in the outer layer by sequentially using the information of each conductor stored in the design information storage means, and further physically connects to the first via. Detecting one or more second vias physically connected to the pad and the first via;
The via connection determination means, based on the position information of the second via stored in the design information storage means and the component information of the pad, the pad is a pad of an electrical noise prevention element, and the second The printed circuit board design verification system according to claim 3, wherein when the ground plane exists in the outer layer indicated by the via position information, the ground plane and the ground of the power supply noise prevention element are determined to be connected. Via information storage means for storing information relating to vias detected by via connection detection means and conductors physically connected to the vias as connection form information of the vias so as to be searchable in association with the vias;
6. Via information display means for searching for and displaying information to be provided to a user from via connection form information stored in the via information storage means, according to any one of claims 2 to 5. The printed circuit board design verification system described.   The printed circuit board design verification system according to any one of claims 1 to 6, wherein the printed circuit board design information stored in the design information storage means is board design information of a multilayer double-sided mounted printed circuit board. A component arranged on the printed circuit board and a ground plane for preventing noise of a signal pattern formed on the printed circuit board based on the printed circuit board design information indicating the printed circuit board design information on which the electronic circuit is formed. To determine whether the ground of the power supply noise prevention element to prevent the power supply noise of the
The error display means displays an error indicating that the mounting design of the printed circuit board is wrong when it is determined that the ground plane and the ground of the power supply noise prevention element are connected. Board design verification method. Via connection detection means included in the determination means is connected to the ground on the substrate surface based on printed circuit board design information including information indicating a conductor disposed on the printed circuit board and information indicating the arrangement and wiring of the conductor. Detecting a via and further detecting a conductor physically connected to the via;
Via connection determination means provided in the determination means uses the print design information indicating information of vias and conductors detected by the via connection detection means, based on a predetermined evaluation criterion, via the via via a ground plane And whether the ground of the power supply noise prevention element is connected or not,
The printed circuit board design verification method according to claim 8, wherein the error display unit displays an error when the via connection determination unit determines that the ground plane and the ground of the power supply noise prevention element are connected. The design information storage means included in the judging means derives from the printed circuit board design information at least the position information of the ground plane stretched on the outer layer, the position information of vias, patterns, pads, connection destination net information, and pad component information. The information of each derived conductor is stored in a searchable manner,
The via connection detection means detects the vias connected to the ground on the substrate surface and the conductors physically connected to the vias by sequentially using the information of each conductor stored in the design information storage means. 9. The printed circuit board design verification method according to 9. Via connection detection means detects information on each conductor stored in the design information storage means in order to detect vias connected to the ground net in the outer layer and pads physically connected to the vias;
Based on the via position information and the pad component information stored in the design information storage means by the via connection determination means, the pad is a pad of an electrical noise prevention element and the outer layer pointed to by the via position information The printed circuit board design verification method according to claim 10, wherein the ground plane and the ground of the power supply noise prevention element are determined to be connected when a ground plane exists in the circuit board. The via connection detection means detects the first via connected to the ground net in the outer layer by sequentially using the information of each conductor stored in the design information storage means, and further physically connects to the first via. Detecting one or more second vias physically connected to the pad and the first via;
Via connection determination means, based on the position information of the second via stored in the design information storage means and the component information of the pad, the pad is a pad of an electrical noise prevention element, and the second The printed circuit board design verification method according to claim 10, wherein, when a ground plane exists in an outer layer indicated by via position information, the ground plane and the ground of the power supply noise prevention element are determined to be connected. Via information storage means stores information on vias detected by via connection detection means and conductors physically connected to the vias as connection form information of vias so as to be searchable in association with the vias;
The via information display means searches for and displays information to be provided to the user from via connection form information stored in the via information storage means, and displays the information provided in any one of claims 9 to 12. Printed circuit board design verification method. On the computer,
Based on the printed circuit board design information indicating the printed circuit board design information on which the electronic circuit is formed, the ground plane for preventing the noise of the signal pattern formed on the printed circuit board and the power supply noise of the components placed on the printed circuit board are reduced. A determination process for determining whether or not the ground of the power supply noise prevention element is connected to prevent the printed circuit board when it is determined that the ground plane and the ground of the power supply noise prevention element are connected A printed circuit board design verification program for executing an error display process that displays an error that indicates that the mounting design is incorrect. On the computer,
In the determination process, based on the printed circuit board design information including information indicating the conductor disposed on the printed circuit board and information indicating the arrangement and wiring of the conductor, a via connected to the ground is detected on the surface of the circuit board; Via connection detection processing for detecting a conductor physically connected to the via, and print design information indicating information of the detected via and conductor, the via is determined based on a predetermined evaluation criterion. The via connection determination process for determining whether or not the ground plane and the ground of the power supply noise prevention element are connected is executed,
The printed circuit board design verification program according to claim 14, wherein an error is displayed when it is determined in the error display process that the ground plane and the ground of the power supply noise prevention element are connected.

Images