JP2007025777A - Data error detection/correction method and memory device with data error detection/correction function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain universal data error detection/correction by simplifying processing, and reducing hard quantity. <P>SOLUTION: This memory device is provided with a non-volatile memory 10 for storing control data to which an error detection bit is added, a volatile memory 40 to be used for the operation of a device 1, a data reading circuit 20 for reading the control data stored in the memory 10, and for detecting the error of the read control data, a data writing circuit 30 for writing data with little error among the control data read by the circuit 20 in the memory 40, an error detection circuit 50 for reading the data written in the memory 40, and for successively detecting the error of the data in a timing in the non-operation of the memory 40 and a history writing circuit 60. When the error of data is detected by the circuit 50, the circuit 20 is controlled, and the data are read again from the memory 10, and written again in the memory 40 so that the data can be restored. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention provides a data error detection / correction method and a data error detection / correction function for memory data that operates by exchanging control data depending on the use mode in a device with sufficient memory access, such as voice call processing. The present invention relates to a memory device.

  Conventionally, for error detection / correction of data, a parity or an error correction code is added to the data. As such data error detection / correction techniques, for example, there are those described in the following documents.

JP 2004-7217 A JP 2001-6386 A

  FIG. 1 and the like of Patent Document 1 describe a technique related to a byte error correction / detection method and apparatus. This byte error correction / detection device performs error detection / correction using a Hamming code based on information theory, and an error correction bit is added to data by an encoding circuit on the transmission side, and a syndrome provided on the reception side. The generation circuit and the error correction circuit are checked to detect errors and correct errors that can be corrected.

  FIG. 1 of Patent Document 2 describes a technique related to an EPROM with an error correction function in which an error correction function is provided to an ultraviolet erasable memory (Erasable and Programmable Read Only Memory, hereinafter referred to as “EPROM”) for data storage. ing. In this EPROM with an error correction function, error correction bits are generated at the time of data writing, and error detection / correction is performed by data check by reading (reading).

  However, the conventional technique of Patent Document 1 causes an increase in the amount of hardware and an increase in arithmetic processing in the syndrome generation circuit and the error correction circuit, such as generation of a parity matrix such as a syndrome by information theory, and the like. There is a problem that it is difficult to apply to an apparatus with few.

  Further, in the technique of Patent Document 2, since the memory is limited to EPROM as a component, there is a problem that there is a case where it cannot be used practically due to lack of versatility, and an error detection / arrangement for an arbitrary bit. There was a problem that correction was not possible.

  The present invention provides a data error detection / correction method and a memory device with a data error detection / correction function that solve the above-described conventional problems, have a simple hardware for error detection / correction, have a small amount of hardware, and are versatile. For the purpose.

  In order to solve the above problems, the data error detection / correction method according to the present invention stores the data with the error detection bit added in a nonvolatile memory, and then reads the data stored in the nonvolatile memory and volatilizes the data. In the device that writes to the volatile memory and reads and uses the data written to the volatile memory during the operation of the volatile memory, the device is written to the volatile memory at a timing when the volatile memory is not operating. The data is read and the error of the data is continuously detected, or the data written in the volatile memory is read to monitor the error of the data as needed.

  The memory device with a data error detection / correction function according to the present invention includes a nonvolatile memory for storing data to which an error detection bit is added and a volatile memory for writing the data. The volatile memory to be read and used, the data stored in the nonvolatile memory, a data reading circuit for detecting an error in the read data, and the data read by the data reading circuit A data writing circuit for writing error-free data into the volatile memory, and reading out the data written in the volatile memory at a timing when the volatile memory is not operated, and continuously detecting errors in the data. An error detection circuit to detect (or read the data written in the volatile memory and read this data. And a error detection circuit) from time to time monitors the error data.

  According to the data error detection / correction method and memory device with data error detection / correction function of the present invention, error detection is performed on a plurality of data, and the original data can be restored only by error detection such as simple parity check. It becomes possible. In addition, it is highly possible that detection / recovery can be performed when the volatile memory is not in operation, and the failure of a device in which this data error detection / correction method or memory device with a data error detection / correction function is mounted can be reduced. In addition, by storing that an error has occurred, maintenance of the mounted device is facilitated. Therefore, it is possible to realize a data error detection / correction method or a memory device with a data error detection / correction function that is simple in error detection / correction, has a small amount of hardware, and is versatile.

  The memory device with a data error detection / correction function according to the best embodiment of the present invention includes a nonvolatile memory for storing data to which an error detection bit is added and a volatile memory for writing data, which are written during operation. The volatile memory that is used by reading the data, the data stored in the non-volatile memory, the data reading circuit that detects an error in the read data, and the data reading circuit A data writing circuit for writing data without error in the data to the volatile memory, and reading out the data written in the volatile memory at a timing when the volatile memory is not operating, And an error detection circuit for detecting continuously.

  The memory device is provided with a rewrite control means and an error information write circuit. In the rewrite control means, when the error detection circuit detects an error in the data, the data read circuit is controlled so that the data is read again from the non-volatile memory and rewritten into the volatile memory. Further, in the error information writing circuit, when the error detection circuit detects an error in the data, the error information is written in the nonvolatile memory.

(Configuration of Example 1)
FIG. 1 is a schematic configuration diagram of a memory device with a data error detection / correction function according to a first embodiment of the present invention.

  This memory device with a data error detection / correction function is for storing control data of the device 1 having sufficient memory access, such as voice call processing, and a data writing device from the outside of the device 1 2 includes a non-volatile memory (for example, a control data holding memory) 10 connected via a wireless or wired communication medium 3. The control data holding memory 10 is a memory that holds control data D1, D2, D3,... Sent from the data writing device 2, and is an EPROM that stores data even when the power is turned off. Storage areas 11, 12, 13,..., Each of which includes a memory (Electrically EPROM, hereinafter referred to as “EEPROM”), a flash memory, etc., and stores a plurality of control data D1, D2, D3,. And a storage area 14 for storing error information PB.

  Connected to the memory 10 is a data reading circuit 20 for reading control data D1, D2, D3,... Stored therein. A volatile memory (for example, an operation memory) 40 into which the control data D1, D2,... Are written by the data writing circuit 30 is connected to the data reading circuit 20 via the data writing circuit 30. The operation memory 40 includes a static random access memory (Static Random Access Memory, hereinafter referred to as “SRAM”), a dynamic random read / write memory (Dynamic RAM, hereinafter referred to as “DRAM”), and the like. And storage areas 41, 42,... For storing a plurality of control data D1, D2,.

  The memory 40 is connected to an operation data reading circuit 4 for operation in the apparatus 1 and an error detection circuit 50 for detecting data errors. The error detection circuit 50 has a function as a rewrite control means for giving a reread control signal S50 to the data reading circuit 20 when data is written again according to the operation after error detection. . The error detection circuit 50 is connected to a history writing circuit 60 that is an error information writing circuit. The history writing circuit 60 is a circuit for writing the error information PB to the memory 10 when the error detection information is stored after the error detection by the error detection circuit 50.

(Data error detection / correction method of Embodiment 1)
By downloading from the data writing device 2 from outside the device 1 via the communication medium 3 by a general communication method or a direct cable connection method, the storage areas 11, 12, 13 is written with control data D1, D2, D3,. At this time, an error detection bit such as a parity bit is already added to the control data D1, D2, D3,. Since the error detection bits can be handled as a part of the control data D1, D2, D3,..., The storage areas 11, 12, 13,. An error detection bit suitable for the length can be provided.

  For example, when the memory 10 having a data width of 8 bits is used, even if the control data D1 is 12 bits, the control data D2 is 4 bits, etc., the storage area 11 of the control data D1 is the first bit of the even address and the control data D2 is stored. The area 12 may be defined at the time of writing by using the first bit of each address as an error detection bit. Actually, the position of the error detection bit may be anywhere other than the original data.

  When the apparatus 1 is activated, the control data D1,... Are read from the memory 10 by the data reading circuit 20, and the error detection circuit 21 performs a check using an error detection bit. If there is no error, the data writing circuit 30 writes the data in the storage areas 41, 42,. At this time, the error detection bit stored in the memory 10 is also written in the memory 40 as it is. If an error in the data is detected by the error detection circuit 21, for example, control data is written again from the data writing device 2 to the memory 10 by a control signal (not shown), and the control data is read from the data. The data is read by the circuit 20 and written to the memory 40 by the data writing circuit 30.

  The control data D1, D2,... Written in the memory 40 are read by the operation data reading circuit 4 according to the operation of the device 1 and used for controlling the device 1. Here, a time during which the device 1 does not read the memory 40 occurs in a specific state. For example, a state in which reading from the memory 40 is not performed occurs when a voice call is not performed. When such a state where the memory 40 is not accessed occurs, the error detection circuit 50 reads the control data D1, D2,... In the memory 40 and performs error detection.

  Here, when an error is detected, the reread control signal S50 is given from the error detection circuit 50 to the data reading circuit 20, and the control data is restored from the memory 10 to the memory 40 again, thereby restoring the control data (ie, Error correction). Note that the apparatus 1 can be stopped only by detecting a data abnormality, not by data recovery. The error information PB, which is the content of the data abnormality, is stored in the storage area 14 of the memory 10 by the history writing circuit 60, so that the abnormality content can be saved.

(Effect of Example 1)
According to the first embodiment, error detection is performed on a plurality of control data D1, D2,..., And it is possible to restore the original data only by error detection such as a simple parity check. Moreover, there is a high possibility that detection and recovery can be performed in a situation where the device 1 is not operating, and failure of the device 1 can be reduced. Moreover, maintenance of the apparatus 1 is facilitated by storing the fact that an error has occurred.

(Configuration of Example 2)
FIG. 2 is a schematic configuration diagram of a memory device with a data error detection / correction function according to a second embodiment of the present invention. Elements common to those in FIG. Has been.

  In the memory device with data error detection / correction function of the second embodiment, the operation data reading circuit 4A and the error detection circuit 50A having different configurations are used instead of the operation data reading circuit 4 and the error detection circuit 50 of the first embodiment. Is provided. The operation memory 40 similar to that of the first embodiment is connected to the operation data reading circuit 4A for the operation in the apparatus 1, but is also connected to the error detection circuit 50A at the same time. The error detection circuit 50A has a function as a rewrite control means for giving a reread control signal S50A to the data reading circuit 20 when data is written again according to the operation after error detection. Similar to the first embodiment, a history writing circuit 60 is connected to the error detection circuit 50A. Other configurations are the same as those of the first embodiment.

(Data error detection / correction method of embodiment 2)
As in the first embodiment, the control data is stored in the storage areas 11, 12, 13,... Of the control data holding memory 10 by downloading from the data writing device 2 from the outside of the device 1 via the communication medium 3. Data D1, D2, D3,... Are written. At this time, an error detection bit is already added to the control data D1, D2, D3,. Since the error detection bits can be handled as a part of the data, even in the control data D1, D2, D3,... Having different bit lengths in the storage areas 11, 12, 13,. An error detection bit suitable for the length can be provided. For example, when the memory 10 having a data width of 8 bits is used, even if the control data D1 is 12 bits, the control data D2 is 4 bits, etc., the storage area 11 of the control data D1 is the first bit of the even address and the control data D2 is stored. The area 12 may be defined at the time of writing by using the first bit of each address as an error detection bit. Actually, the position of the error detection bit may be anywhere other than the original data.

  When the apparatus 1 is activated, the control data D1, D2, D3,... Are read from the memory 10 by the data reading circuit 20, and the error detection circuit 21 checks using the error detection bit. If there is no error, the data writing circuit 30 writes the data in the storage areas 41, 42,. At this time, the error detection bits stored in the memory 10 are also written in the memory 40 as they are. If a data error is detected by the error detection circuit 21, the control data is written again from the data writing device 2 to the memory 10 as in the first embodiment, and the control data is written to the memory 40. It is.

  The control data D1, D2,... Written in the memory 40 are read by the operation data reading circuit 4A according to the operation of the apparatus 1. At this time, unlike the first embodiment, error detection is performed in real time by the error detection circuit 50A when data is read by the operation data reading circuit 4A. When an error is detected and there is no effect on the state of the apparatus 1, a reread control signal S50A is given from the error detection circuit 50A to the data reading circuit 20, and the data is read again from the memory 10 as soon as it is detected. Can recover data.

  In the device 1 used in the second embodiment, a time during which the memory 10 is not read occurs in a specific state. For example, a state in which reading from the memory 40 is not performed occurs when a voice call is not performed. Therefore, it is possible to store the error information PB up to this state and re-read it from the memory 10 as soon as the memory 40 is no longer used. It is also possible to stop the apparatus 1 only by detecting a data abnormality rather than restoring the data. The error information PB, which is the content of the data abnormality, is written to the storage area 14 of the memory 10 by the history writing circuit 60, so that the abnormality content can be saved.

(Effect of Example 2)
The second embodiment has the following effects (a) to (c).

  (A) As in the first embodiment, error detection is performed on a plurality of control data D1, D2, D3,..., And the original data can be restored only by error detection such as a simple parity check. Moreover, there is a high possibility that detection and recovery can be performed in a situation where the device 1 is not operating, and failure of the device 1 can be reduced. Moreover, maintenance of the apparatus 1 is facilitated by storing the fact that an error has occurred.

  (B) In the first embodiment, since error detection is continuously performed when a specific situation occurs, a memory control circuit for error detection (for example, an address or read control circuit) is provided on the operation data reading circuit 4 side. Etc.) is additionally required. On the other hand, in the second embodiment, since error detection is performed simultaneously during normal operation, a memory control circuit is unnecessary.

  (C) In the first embodiment, there may be a case where the control data D1, D2, D3,... In 2, an abnormality can be recognized during the operation of the apparatus 1, and a response according to the state at that time can be performed. For example, since a data error in the storage area 11 of the memory 10 has little influence on the operation of the apparatus 1, the control data D1 is read again to recover, and an error in the control data D2 in the storage area 12 Therefore, the operation at the time of error detection can be changed according to the situation, for example, the operation of the apparatus 1 is stopped.

  The present invention is not limited to the first and second embodiments, and various modifications can be made. As a third embodiment which is this modification, for example, there are the following (A) to (C).

  (A) In the first and second embodiments, the example of the device 1 in which reading from the operation memory 40 does not occur in a specific state has been described. However, as another example, a device that periodically performs processing. In the case of 1, the present invention can be applied by controlling the timing so that the reading of the similar operation memory 40 does not occur at a specific time.

  (B) In the first embodiment, an example in which data is read from the operation memory 40 and error detection is performed when the operation memory 40 has not been read has been described. By limiting the error detection area of the memory 40, it is possible to increase the frequency of error detection.

  (C) The memory device of FIGS. 1 and 2 may be changed to a configuration other than that shown in the drawing, and the data error detection / correction method in the memory device can be changed according to the configuration.

1 is a schematic configuration diagram of a memory device with a data error detection / correction function according to a first embodiment of the present invention. It is a schematic block diagram of the memory device with a data error detection / correction function showing Embodiment 2 of the present invention.

Explanation of symbols

1 Device 10 Control Data Holding Memory 20 Data Reading Circuit 21, 50, 50A Error Detection Circuit 30 Data Writing Circuit 40 Operation Memory 60 History Writing Circuit

Claims (9)

After the data with the error detection bit added is stored in the non-volatile memory, the data stored in the non-volatile memory is read and written to the volatile memory, and is written to the volatile memory during operation of the volatile memory. In a device that reads and uses the data,
A data error detection / correction method comprising: reading out the data written in the volatile memory at a timing when the volatile memory is not operating, and continuously detecting errors in the data. After the data with the error detection bit added is stored in the non-volatile memory, the data stored in the non-volatile memory is read and written to the volatile memory, and is written to the volatile memory during operation of the volatile memory. In a device that reads and uses the data,
A data error detection / correction method comprising: reading out the data written in the volatile memory, monitoring the error of the data as needed, and notifying the occurrence of the error when detecting the error of the data. After the data with the error detection bit added is stored in the non-volatile memory, the data stored in the non-volatile memory is read and written to the volatile memory, and is written to the volatile memory during operation of the volatile memory. In a device that reads and uses the data,
The data written in the volatile memory is read to monitor the error of the data as needed, and when the data error is detected, the error occurrence is stored until the non-operation timing of the volatile memory. Data error detection and correction method. The data error detection / correction method according to any one of claims 1 to 3,
A method for detecting and correcting a data error, wherein when an error in the data is detected, the data is read again from the non-volatile memory and rewritten in the volatile memory. The data error detection / correction method according to any one of claims 1 to 3,
A data error detection / correction method comprising: storing error information in the nonvolatile memory when an error in the data is detected. A non-volatile memory for storing data with an error detection bit added thereto;
A volatile memory for writing data, wherein the written data is read and used during operation;
A data reading circuit for reading the data stored in the nonvolatile memory and detecting an error in the read data;
A data writing circuit for writing, into the volatile memory, error-free data among the data read by the data reading circuit;
An error detection circuit that reads the data written in the volatile memory at a timing when the volatile memory is not operating and continuously detects an error in the data;
A memory device with a data error detection / correction function. A non-volatile memory for storing data with an error detection bit added thereto;
A volatile memory for writing data, wherein the written data is read and used during operation;
A data reading circuit for reading the data stored in the nonvolatile memory and detecting an error in the read data;
A data writing circuit for writing, into the volatile memory, error-free data among the data read by the data reading circuit;
An error detection circuit for reading out the data written in the volatile memory and monitoring an error of the data as needed;
A memory device with a data error detection / correction function. The memory device with a data error detection / correction function according to claim 6 or 7,
When the error detection circuit detects an error in the data, rewrite control means for controlling the data reading circuit, reading the data again from the nonvolatile memory, and writing the data again into the volatile memory,
A memory device with a data error detection / correction function. The memory device with a data error detection / correction function according to any one of claims 6 to 8,
When the error detection circuit detects an error in the data, an error information writing circuit for writing the error information to the nonvolatile memory,
A memory device with a data error detection / correction function.

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