JP2007019756A - Synchronous detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous detection circuit or the like in which a circuit scale is small, there is no characteristic fluctuation, in-phase components are not detected from input signals and group delay is fixed. <P>SOLUTION: A sample-and-hold circuit 14 samples and holds the input signals IN at the rise of a clock CLK from a waveform shaping circuit 11. That is, the sample-and-hold circuit 14 samples and holds the input signals IN when the rise of carriers S1 crosses zero. A sample-and-hold circuit 15 samples and holds inversion signals S3 from an inversion circuit 13 at the fall of the clock CLK. That is, the sample-and-hold circuit 15 samples and holds the inversion signals S3 when the fall of the carriers S1 crosses zero. An addition circuit 16 adds the output S5 of the sample-and-hold circuit 14 and the output S6 of the sample-and-hold circuit 15 and outputs the added result as detection signals OUT. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a synchronous detection circuit that detects a signal component synchronized with a carrier wave from an input signal, and more particularly to a synchronous detection circuit that removes noise with a simple circuit configuration and obtains a highly accurate output. is there.

As a conventional synchronous detection circuit, a circuit that detects a signal synchronized with a carrier wave by full-wave rectifying an input signal using a rectangular wave whose carrier phase is shifted by 90 degrees is known.
As shown in FIG. 11, this specific synchronous detection circuit has a rectangular shape by shaping the waveform of the phase shifter 1 that delays the phase of the carrier wave S <b> 1 by about 90 degrees (that is, a quarter period) and the output S <b> 2 of the phase shifter 1. The waveform shaping circuit 2 for generating the wave clock CLK, the inverting circuit 3 for inverting the input signal IN, and the input signal IN and the inverted signal S3 from the inverting circuit 3 are selectively used by the clock CLK from the waveform shaping circuit 2. A selector circuit 4 for outputting, and a low-pass filter (LPF) 5 for removing the noise other than the detection signal included in the output S4 of the selector circuit 4 and outputting the detection signal OUT, and a signal synchronized with the carrier wave from the input signal It can be detected.
Here, the phase shifter 1 is formed by a group delay characteristic of a low-pass filter (LPF) including, for example, a second order resistor and capacitor. The LPF 5 is formed of, for example, an LPF based on the second order RC or SCF.

Next, a specific example of signal processing of the conventional circuit shown in FIG. 11 will be described with reference to FIGS.
Here, FIG. 12 is an example of detecting an input wave having a signal synchronized with a carrier wave and an offset. FIG. 12A shows an example of the waveform of the signal at each part. FIG. 12B shows the frequency characteristics (frequency spectrum) of the signals of the respective parts, where the horizontal axis represents frequency and the vertical axis represents amplitude.

As shown in FIG. 12A, the phase of the carrier wave S1 is shifted by 90 degrees by the phase shifter 1, and its output S2 becomes as shown in the figure. The output S2 is shaped by the waveform shaping circuit 2 as shown in the figure. Clock CLK. On the other hand, an input signal IN that is synchronized with the carrier wave S1 and has an offset is inverted by the inverting circuit 3 to become an inverted signal S3 as shown.
Since the selector circuit 4 selects the input signal IN and the inverted signal S3 using the clock CLK, the output S4 of the selector circuit 4 is as illustrated. The output 4 of the selector circuit 4 is smoothed by the LPF 5 to obtain a detection signal OUT as shown in the figure.

Next, the above signal processing will be described using the frequency characteristics shown in FIG.
Assuming that the frequency of the carrier wave S1 is fs, the frequency components of the input signal IN and its inverted signal S3 are in the vicinity of the frequency fs of the carrier wave S1, as shown in the upper part of FIG.
The output S4 of the selector circuit 4 is the result of multiplying the input signal IN having an offset by the clock CLK. For this reason, the frequency component of the output S4 is as shown in the middle part of FIG. That is, as shown in the figure, the component of the input signal IN having an offset is decomposed into a low frequency component and a high frequency component centered on the frequency 2fs. The offset is CLK having an amplitude twice that of the offset, and a frequency fs component is generated.
Therefore, unnecessary noise components generated at the frequencies fs and 2fs are removed by the attenuation characteristics of the LPF 5, and only the necessary low frequency components are output as the detection signal OUT.
In addition, synchronous detection can remove in-phase components generated by crosstalk or the like.

FIG. 13 is an example of removing the in-phase component from the input wave having the in-phase component.
In this case, the waveform of each part is as shown in FIG. 13A, the output S4 of the selector circuit 4 is as shown, and the signal amount above and below the common is the same. For this reason, the common-mode signal is output from the detection signal OUT smoothed by the LPF 5 as shown in FIG.

Next, the above signal processing will be described using the frequency characteristics shown in FIG.
The frequency components of the input signal IN and its inverted signal S3 are the same as the frequency fs of the carrier wave S1, as shown in the upper part of FIG.
The output S4 of the selector circuit 4 is the result of multiplying the input signal IN and the clock CLK, and the frequency component of the output S4 has a frequency 2fs as shown in the middle stage of FIG. Since such a component of frequency 2fs is removed by the LPF 5, there is no signal of the detection signal OUT as shown in the lower part of FIG.

However, in the selector circuit 4, since the signal change at the time of selection is very steep, an error occurs when the slew rate of the input signal IN and its inverted signal S3 is insufficient. In order to avoid this error, as shown in Patent Document 1, a special process is required for a sharp signal change portion.
As another example of the prior art, a synchronous detection circuit using a switched capacitor circuit (SFC) is known (see Patent Document 2).
Japanese Patent Laid-Open No. 10-93430 Japanese Patent Laid-Open No. 2005-20434

However, the above prior art has the following problems.
(1) The band-pass filter of the phase shifter 1 and the low-pass filter 5 are normally active filters. However, the circuit scale is large, and the frequency characteristics are degraded due to element characteristic fluctuations. In particular, the influence of the phase shifter 1 is great, and when the phase is greatly shifted, the in-phase component of the input signal cannot be removed.
(2) When detecting the in-phase component of the input signal, a means for avoiding an error caused by a sharp signal change is required.
(3) The group delay due to the low-pass filter 5 is large. In addition, the characteristics deteriorate due to the group delay difference.
(4) When a switched capacitor filter (SCF) is used, a clock CLK earlier than the carrier wave is required.
Therefore, in view of the above points, an object of the present invention is to provide a synchronous detection circuit or the like that has a small circuit scale, has no characteristic fluctuation, does not detect an in-phase component from an input signal, and can maintain a constant group delay. is there.

In order to solve the above problems and achieve the object of the present invention, the present invention has the following configuration.
That is, the invention according to claim 1 is a synchronous detection circuit for detecting a signal component synchronized with a carrier wave from an input signal, and the first sample hold for sampling and holding the input signal at a zero-cross timing of rising of the carrier wave. A second sample-and-hold circuit that samples and holds an inverted signal of the input signal at a zero-cross timing of the falling edge of the carrier wave, an output signal of the first sample-and-hold circuit, and an output of the second sample-and-hold circuit And an adder circuit that adds the signals and outputs the result.

  According to a second aspect of the present invention, there is provided a synchronous detection circuit for detecting a signal component synchronized with a carrier wave from an input signal, wherein the input signal is sampled and held at a zero-cross timing of rising of the carrier wave; A second sample-and-hold circuit that samples and holds the input signal at a zero-cross timing at the falling edge of the carrier; and a difference between an output signal of the first sample-and-hold circuit and an output signal of the second sample-and-hold circuit. And a subtracting circuit for outputting.

  The invention according to claim 3 is a synchronous detection circuit that detects a signal component synchronized with a carrier wave from an input signal, a selector circuit that selects the input signal and an inverted signal of the input signal, and an output from the selector circuit A first sample-and-hold circuit that samples and holds a signal at a zero-cross timing of the carrier; a second sample-and-hold circuit that samples and holds an output signal of the first sample-and-hold circuit at a zero-cross timing of the carrier; And an adder circuit for adding and outputting the output signal of the second sample hold circuit and the output signal of the second sample hold circuit.

According to a fourth aspect of the present invention, in the synchronous detection circuit according to any one of the first to third aspects, the first sample hold circuit, the second sample hold circuit, or the selector circuit is operated. A waveform shaping circuit for generating an operation signal; and the waveform shaping circuit receives the carrier wave and generates a rectangular wave that changes sharply at the rising and falling edges of the carrier wave as the operation signal. Yes.
According to a fifth aspect of the present invention, an AM demodulator that demodulates an AM modulated wave is provided with the synchronous detection circuit according to any one of the first to fourth aspects.

According to a sixth aspect of the present invention, an FM demodulator that demodulates an FM modulated wave includes the synchronous detection circuit according to any one of the first to fourth aspects.
According to a seventh aspect of the present invention, a PM demodulator that demodulates a PM modulated wave includes the synchronous detection circuit according to any one of the first to fourth aspects.
The invention according to claim 8 is a detection circuit of a vibration sensor that detects an operation generated in a direction different from that of the vibrator, and includes an oscillation circuit that vibrates the vibrator and a reception circuit that receives a vibration state of the vibrator. And a synchronous detection circuit according to any one of claims 1 to 4 for performing synchronous detection on an output signal from the receiving circuit and detecting the generated operation.

  The invention according to claim 9 is a synchronous detection circuit for detecting a signal component synchronized with a carrier wave from an input signal, a selector circuit for selecting the input signal and an inverted signal of the input signal, and an output signal from the selector circuit An integration circuit for integrating the carrier wave at zero cross timing, a sample hold circuit for sampling and holding the output signal of the integration circuit, and a control signal for performing output control of the integration circuit and sample hold control of the sample hold circuit, And a counter generated based on the carrier wave.

According to the present invention having such a configuration, since a phase shifter and a low-pass filter are not required as in the prior art, the circuit scale is reduced and characteristic fluctuations are eliminated.
In the present invention, since the input signal is detected at the timing when the carrier wave crosses zero, that is, when the in-phase component of the input signal crosses zero, the in-phase component of the input signal is not detected. For this reason, a special means for avoiding a problem required when detecting the in-phase component is unnecessary.
Further, according to the present invention, the group delay of the detection signal can be made constant at 1/2 of the carrier wave period.
Furthermore, according to the present invention, the clock necessary for detection may be based on the carrier wave, and is unnecessary otherwise.

The best mode for carrying out the present invention will be specifically described below with reference to the drawings.
(First embodiment of synchronous detection circuit)
The configuration of the first embodiment of the synchronous detection circuit of the present invention will be described with reference to FIG.
One embodiment of this synchronous detection circuit detects a signal component synchronized with a carrier wave from an input signal. As shown in FIG. 1, a waveform shaping circuit 11, an inverting circuit 12, and an inverting circuit 13 are used. A sample hold circuit 14, a sample hold circuit 15, and an adder circuit 16.

The waveform shaping circuit 11 is a circuit that shapes the carrier wave S1 to generate the clock CLK, and the clock CLK is supplied to the sample hold circuit 14 and the inverting circuit 12, respectively.
The inverting circuit 12 is a circuit that inverts the clock CLK generated by the waveform shaping circuit 11, and the inverted clock is supplied to the sample hold circuit 15.

The inversion circuit 13 is a circuit that inverts the input signal IN and outputs an inversion signal S3, and the inversion signal S3 is supplied to the sample hold circuit 15.
The sample hold circuit 14 is a circuit that samples and holds the input signal IN at the rising timing of the clock CLK from the waveform shaping circuit 11, and the sample hold output S 5 is supplied to the adder circuit 16. ing. That is, the sample hold circuit 14 samples and holds the input signal IN at the zero cross timing of the rising of the carrier wave S1.

The sample hold circuit 15 is a circuit that samples and holds the inverted signal S3 from the inversion circuit 13 at the falling timing of the clock CLK from the waveform shaping circuit 11, in other words, at the rising edge of the clock from the inversion circuit 12. The sample hold output S6 is supplied to the adder circuit 16. That is, the sample hold circuit 15 samples and holds the inverted signal S3 at the zero cross timing of the falling of the carrier wave S1.
The adder circuit 16 is a circuit that adds the output S5 of the sample hold circuit 14 and the output S6 of the sample hold circuit 15 and outputs the addition result as a detection signal OUT.

Next, an operation example of the first embodiment of the synchronous detection circuit having such a configuration will be described with reference to FIG.
FIG. 2 shows an example of synchronous detection of an input signal (input wave) having a signal synchronized with a carrier wave and an offset.
When a carrier wave S1 as shown in FIG. 2A is input to the waveform shaping circuit 11, the waveform shaping circuit 11 shapes the carrier wave S1 to generate a clock CLK as shown. That is, as shown in the figure, the waveform shaping circuit 11 generates a rectangular wave that changes sharply at the rising zero cross timing and the falling zero cross timing of the carrier wave S1 as the clock CLK. The generated clock CLK is supplied to the sample hold circuit 14, inverted by the inversion circuit 12, and supplied to the sample hold circuit 15.

  Further, as shown in FIG. 2A, an input signal IN that is synchronized with the carrier wave S1 and has an offset is sampled and held by the sample hold circuit 14 at the rising edge of the clock CLK from the waveform shaping circuit 11. . For this reason, the output S5 of the sample hold circuit 14 is a signal obtained by adding an offset to the staircase wave that changes at the rising edge of the clock CLK as shown in the figure.

  On the other hand, as shown in FIG. 2A, the input signal IN is inverted by the inverting circuit 13 to become an inverted signal S3. This inverted signal S3 is sampled and held at the falling edge of the clock CLK from the waveform shaping circuit 11. Sampled and held by the circuit 15. For this reason, the output S6 of the sample hold circuit 15 is a signal obtained by subtracting the offset from the staircase wave that changes at the falling edge of the clock CLK as shown in the figure.

Thus, the outputs from the sample and hold circuits 14 and 15 are the result of half-wave rectification of the upper and lower waveforms with the system ground as a threshold value.
In such an operation, as can be seen from FIG. 2A, the clock CLK changes when the carrier wave S1 crosses zero, so even if a signal having the same phase component as the carrier wave S1 exists in the input signal IN, It can be seen that in-phase component signals are not sampled (detected).

Therefore, unlike the conventional circuit, a means for avoiding an error caused by a sharp signal change is not required for signal processing.
When the outputs S5 and S6 of the sample hold circuits 14 and 15 are added by the adder circuit 16, the detection signal OUT of the adder circuit 16 cancels the offset in the outputs S5 and S6 and the rising edge of the clock CLK as shown in the figure. And a staircase wave that changes at a cycle that is twice the cycle of the clock CLK.

Next, the above signal processing will be described using the frequency characteristics shown in FIG.
As shown in FIG. 2B, the frequency component of the input signal IN and its inverted signal S3 is the same as the frequency fs of the carrier wave S1, and includes an offset (DC component).
In the outputs S5 and S6 of the sample hold circuits 14 and 15, as shown in the figure, the detection signal is generated in the low frequency range, and the noise generated in the vicinity of the frequency fs is reduced by the sample hold effect. However, offsets still remain in the outputs S5 and S6.

The detection signal OUT output from the adder circuit 16 has its offset removed due to the average effect of the adder circuit 16, and the detected component is interpolated by double sampling due to this moving average effect. This is the same utility as the interpolator.
As described above, in the detection signal OUT from the adder circuit 16, the noise near the frequency fs of the carrier synchronized with the carrier is skipped to 2fs, and the level thereof is reduced to about 1/2 (see FIG. 2B). . Further, the group delay of this circuit is as small as 1/2 of the carrier wave period as shown in the figure and is constant, and there is no group delay difference.

(Second Embodiment of Synchronous Detection Circuit)
The configuration of the second embodiment of the synchronous detection circuit of the present invention will be described with reference to FIG.
The two embodiments of the synchronous detection circuit detect a signal component synchronized with a carrier wave from an input signal. As shown in FIG. 3, a waveform shaping circuit 11, an inverting circuit 12, and a sample and hold circuit are used. 14, a sample hold circuit 15, and a subtraction circuit 17.
In the second embodiment, the inverting circuit 13 is omitted from the first embodiment shown in FIG. 1 and the adding circuit 16 is replaced with a subtracting circuit 17.

More specifically, the waveform shaping circuit 11 and the inverting circuit 12 operate in the same manner as the waveform shaping circuit 11 and the inverting circuit 12 shown in FIG.
The sample hold circuit 14 is a circuit that samples and holds the input signal IN at the rising timing of the clock CLK from the waveform shaping circuit 11, and the sample hold value is supplied to the subtraction circuit 17. Yes. That is, the sample hold circuit 14 samples and holds the input signal IN at the zero cross timing of the rising of the carrier wave S1.

  The sample hold circuit 15 samples and holds the input signal IN at the falling timing of the clock CLK from the waveform shaping circuit 11, in other words, at the rising edge of the clock from the inverting circuit 12, and the sample hold value is It is supplied to the subtraction circuit 17. In other words, the sample hold circuit 15 samples and holds the input signal at the zero cross timing of the fall of the carrier wave S1.

The subtraction circuit 17 is a circuit that outputs a difference between the output S5 of the sample hold circuit 14 and the output S6 of the sample hold circuit 15, that is, performs the subtraction and outputs the subtraction result as the detection signal OUT.
According to the second embodiment of the synchronous detection circuit having such a configuration, the sample and hold circuits 14 and 15 can obtain the same effects as the sample and hold circuits 14 and 15 shown in FIG. The same detection signal OUT as that of the adding circuit 16 can be obtained.
Therefore, according to the second embodiment, the same effect as that of the first embodiment shown in FIG. 1 can be obtained.

(Third embodiment of synchronous detection circuit)
The configuration of the third embodiment of the synchronous detection circuit of the present invention will be described with reference to FIG.
The third embodiment of the synchronous detection circuit detects a signal component synchronized with a carrier wave from an input signal. As shown in FIG. 4, a waveform shaping circuit 11, an inverting circuit 12, and an inverting circuit 13 are used. A selector circuit 18, a sample and hold circuit 19, a sample and hold circuit 20, and an adder circuit 21.

The waveform shaping circuit 11 is a circuit that shapes the carrier wave S1 to generate a clock CLK. The clock CLK is supplied to the selector circuit 18, the sample hold circuit 19, and the inverting circuit 12, respectively. .
The inverting circuit 12 is a circuit that inverts the clock CLK generated by the waveform shaping circuit 11, and the inverted clock is supplied to the sample hold circuit 20.

The inversion circuit 13 is a circuit that inverts the input signal IN and outputs an inversion signal S3. The inversion signal S3 is supplied to the selector circuit 18.
The selector circuit 18 is a circuit that selects and outputs the input signal IN and the inverted signal S3 from the inverting circuit 13 in accordance with the clock CLK from the waveform shaping circuit 11, and supplies the selected signal to the sample hold circuit 19. It has come to be.

  The sample hold circuit 19 samples and holds the output from the selector circuit 18 at the rising timing of the clock CLK from the waveform shaping circuit 11, and the sample hold output S 7 is sent to the sample hold circuit 20 and the adder circuit 21. Each is supplied. That is, the sample hold circuit 19 samples and holds the output from the selector circuit 18 at the zero cross timing of the rising of the carrier wave S1.

The sample hold circuit 20 samples and holds the output S7 of the sample hold circuit 19 at the falling timing of the clock CLK from the waveform shaping circuit 11, in other words, at the rising edge of the clock from the inverting circuit 12. The sample hold output S8 is supplied to the adder circuit 21. That is, the sample and hold circuit 20 samples and holds the output S7 of the sample and hold circuit 19 at the zero crossing timing of the fall of the carrier wave S1.
The adder circuit 21 is a circuit that adds the output S7 of the sample hold circuit 19 and the output S8 of the sample hold circuit 20 and outputs the addition result as a detection signal OUT.

Next, an operation example of the third embodiment of the synchronous detection circuit having such a configuration will be described with reference to FIG.
FIG. 5 shows an example of synchronous detection of an input signal (input wave) having a signal synchronized with a carrier wave and an offset.
When a carrier wave S1 as shown in FIG. 5A is input to the waveform shaping circuit 11, the waveform shaping circuit 11 shapes the carrier wave S1 to generate a clock CLK as shown. The clock CLK is supplied to the selector circuit 18 and the sample hold circuit 19, respectively, inverted by the inversion circuit 12, and supplied to the sample hold circuit 20.

Further, as shown in FIG. 5A, an input signal IN that is synchronized with a carrier wave and has an offset, and an inverted signal S3 obtained by inverting the input signal IN by an inverting circuit 13 are alternately generated by a selector circuit 18. Is output.
Therefore, the sample hold circuit 19 samples and holds the input signal IN at the rising edge of the clock CLK from the waveform shaping circuit 11, and samples and holds the inverted signal S3 at the falling edge of the clock CLK. Therefore, the output S7 of the sample hold circuit 19 is as shown in the figure.

Further, the sample hold circuit 20 samples and holds the output S7 of the sample hold circuit 19 at the rise and fall of the clock CLK from the waveform shaping circuit 11. Therefore, the output S8 of the sample hold circuit 20 is as shown in the figure.
The outputs S7 and S8 of the sample hold circuits 19 and 20 are added by the adder circuit 21, and the detection signal OUT is as shown in the figure. That is, the detection signal OUT of the adder circuit 21 is a staircase wave in which the offsets in the outputs S7 and S8 are canceled and the clock CLK rises and falls, that is, changes in a cycle twice the cycle of the clock CLK.

Next, the above signal processing will be described using the frequency characteristics shown in FIG.
As shown in FIG. 5B, the frequency component of the input signal IN having an offset and its inverted signal S3 includes an offset (DC component) in addition to the component in the vicinity of the frequency fs of the carrier wave S1.
The outputs S7 and S8 of the sample hold circuits 19 and 20 are the result of double sampling the input signal IN having an offset and its inverted signal S3 with the clock CLK. As a result, the components of the outputs S7 and S8 are decomposed into a low-frequency component and a component centered at the frequency 2fs as shown in the figure. As for the offset, a component having an amplitude twice the offset and having a frequency fs is generated.

However, the noise of the frequency 2fs component is considerably reduced by the sample and hold effect of the sample and hold circuits 19 and 20.
Further, the component due to the offset generated in the frequency fs is removed by the moving average effect obtained by the addition to the sample hold circuits 19 and 20.
As described above, according to the third embodiment, the same effect as that of the first embodiment can be realized.

(AM demodulator)
2 and 5, the level (amplitude) of the input signal IN fluctuates as shown in the figure, and waveform examples of each part when the level is detected at this time and the frequency characteristics (frequency spectrum). ).
That is, the input signal IN corresponds to the amplitude modulation (AM modulation) of the carrier wave S1 with the baseband signal, and the operation corresponds to the demodulation of the baseband signal from the input signal.
Therefore, the synchronous detection circuit according to each embodiment shown in FIGS. 1, 3, and 4 is used as an AM demodulator that receives an AM modulated wave as the input signal IN and detects a baseband signal from the input signal. This AM demodulator can be provided.

(FM demodulator, PM demodulator)
As described above, the first to third embodiments have an advantage that the group delay is as small as 1/2 of the carrier wave period, is constant, and has no group delay difference. As an application example utilizing such advantages, there is phase detection.
Although it is generally known that the phase of an input signal can be detected using a synchronous detection circuit, in the conventional circuit, the delay amount changes depending on the frequency of the detection signal due to the group delay difference of the subsequent low-pass filter. was there.
However, in the first to third embodiments, the high frequency noise is eliminated by the sample hold effect and the moving average effect as described above, so that the group delay is constant in any frequency region.

FIG. 6 shows, for example, the waveform and frequency characteristics of each part when phase detection is realized in the first embodiment of FIG.
As an input signal IN shown in FIG. 6A, a signal having a frequency higher by Δf than the frequency fs of the carrier wave S1, that is, a signal having a frequency (fs + Δf) is input to the sample hold circuit.
The input signal IN is sampled and held by the sample hold circuit 14 at the rising edge of the clock CLK. Therefore, the output S5 of the sample and hold circuit 14 operates at the frequency Δf and becomes a staircase wave sampled and held at the rising edge of the clock CLK.

On the other hand, the inverted signal S3 obtained by inverting the input signal IN by the inverting circuit 13 is sampled and held at the falling edge of the clock CLK. For this reason, the output S6 of the sample and hold circuit 15 operates at a frequency Δf as shown in the figure, and becomes a staircase wave sampled and held at the falling edge of the clock CLK.
Since the adder circuit 16 adds the outputs S5 and S6 of the sample and hold circuits 14 and 15, the detection signal OUT operates at the frequency Δf and is a staircase wave sampled and held at twice the frequency of the carrier wave S1. It becomes.

Next, the above signal processing will be described using the frequency characteristics shown in FIG.
As shown in FIG. 6B, the frequency of the input signal IN and its inverted signal S3 is a frequency (fs + Δf).
As shown in the figure, the frequency components of the outputs S5 and S6 of the sample hold circuits 14 and 15 are respectively decomposed into a frequency Δf component, a frequency (fs−Δf) component, and a frequency (fs + Δf). However, noise generated in the frequency (fs−Δf) component and the frequency (fs + Δf) component is reduced by the sample and hold effect.

The detection signal OUT output from the adder circuit 16 causes noise generated at the frequency (fs−Δf) and the frequency (fs + Δf) due to the use of the interpolator to be skipped to the frequency (2fs−Δf) and the frequency (2fs + Δf). The level is also reduced to about 1/2.
With the above operation, the circuits according to the first to third embodiments shown in FIGS. 1, 3, and 4 can be used as a demodulator of a modulation signal subjected to FM modulation or PM modulation.

(Vibration sensor detection circuit)
Conventionally, a vibration sensor detection circuit that can detect signals such as acceleration and angular velocity using a synchronous detection circuit is generally known.
However, in the conventional circuit, special means for avoiding crosstalk of the vibrator, a phase shifter, and a low-pass filter are required.
FIG. 7 is a block diagram showing a configuration of a vibration sensor detection circuit to which one of the first to third embodiments is applied.
As shown in FIG. 7, the vibration sensor detection circuit includes a vibrator 31 for detecting acceleration and angular velocity, an oscillation circuit 32 that vibrates the vibrator 31, and a reception circuit 33 that receives the vibration state of the vibrator 31. And a synchronous detection circuit 34 that performs synchronous detection on the signal from the receiving circuit 33 and extracts (detects) only signal components related to detection of acceleration and angular velocity.

The vibrator (vibration sensor) 31 is made of, for example, a crystal, a piezoelectric element, or a ceramic. Since the vibrator 31 has a high Q value, stable oscillation can be obtained by the oscillation circuit 32. When acceleration is applied or when the vibrator 31 is rotated, a change occurs in vibration due to a generated Coriolis force or the like. Therefore, the receiving circuit 33 monitors the oscillation state of the vibrator 31.
The monitor signal of the receiving circuit 33 is obtained by adding signals such as acceleration and angular velocity to be detected to a signal when the oscillator 31 is stably vibrated. Since the in-phase component is deleted from the monitor signal of the receiving circuit 33 by synchronous detection, the synchronous detection circuit 34 deletes the stable vibration signal of the vibrator after the synchronous detection, and detects only signals such as acceleration and angular velocity. The

(Synchronous detection circuit with variable amplification function)
An embodiment of a synchronous detection circuit having a variable amplification function will be described as an application example of the synchronous detection circuit of the present invention.
The embodiment of the synchronous detection circuit having the variable amplification function detects a signal component synchronized with the carrier wave from the input signal. As shown in FIG. 8, the waveform shaping circuit 11 and the inverting circuit 13 are detected. A selector circuit 18, an integration circuit 22, a sample hold circuit 23, and a counter 24.
The waveform shaping circuit 11 is a circuit that shapes the carrier wave S1 to generate the clock CLK, and the clock CLK is supplied to the selector circuit 18, the integration circuit 22, and the counter 24, respectively.

The inversion circuit 13 is a circuit that inverts the input signal IN and outputs an inversion signal S3. The inversion signal S3 is supplied to the selector circuit 18.
The selector circuit 18 is a circuit that selects and outputs the input signal IN and the inverted signal S3 from the inverting circuit 13 in accordance with the clock CLK from the waveform shaping circuit 11, and the selected signal is supplied to the integrating circuit 22. It has become so.

The integrating circuit 22 is a circuit that integrates the output from the selector circuit 18 at the rising timing of the clock CLK from the waveform shaping circuit 11, and the output S9 of the integrating circuit 22 is supplied to the sample and hold circuit 23. It has become.
That is, the integration circuit 22 samples and holds the output from the selector circuit 18 at the zero cross timing of the rising of the carrier wave S1. Since the integration circuit 22 samples and holds only the output from the selector circuit 18 when the control signal S10 from the counter 24 is at "L" level, the integration value is reset.

The sample hold circuit 23 samples and holds the output S9 of the integration circuit 22 at the rising timing of the control signal S10 from the counter 24, and the sample hold output becomes the synchronous detection output OUT.
The counter 24 generates a control signal S10 as shown in FIG. 10 based on the clock CLK from the waveform shaping circuit 11. The control signal S10 is supplied to the integrating circuit 22 for output control and supplied to the sample hold circuit 23 for sample hold control.
The “L” level period in one cycle of the control signal S10 generated by the counter 24 is the same as the “L” level period in one cycle of the clock CLK. Then, by changing the period of one cycle of the control signal S10, the amplification factor of the synchronous detection circuit shown in FIG. 8 can be changed.

Next, a specific configuration of the integrating circuit 22 in FIG. 8 will be described with reference to FIG.
As shown in FIG. 9, the integration circuit 22 includes an adder 221, a sample hold circuit 222, and a switch 223.
The adder 221 adds the output of the selector circuit 18 and the output of the sample hold circuit 222 and outputs the added value to the sample hold circuit 222.

The sample hold circuit 222 samples and holds the output of the adder 221 at the rising timing of the clock signal CLK from the waveform shaping circuit 11, and outputs this sample hold value as the output signal S9.
The switch 223 is composed of, for example, an electronic switch, and is connected between the output terminal of the sample hold circuit 222 and the adder 221. The switch 223 uses the control signal S10 from the counter 24 as the reset signal RESET, and the opening / closing control is performed by the control signal S10.

  In the integrating circuit 22 having such a configuration, when the control signal S10 from the counter 24 is at “L” level, the switch 223 is turned off, so that the sample hold circuit 222 samples and holds only the output of the selector circuit 18. On the other hand, when the control signal S10 is at the “H” level, the switch 223 is turned on, and the sample hold circuit 222 samples the added value of the output of the selector circuit 18 added by the adder 221 and the output of the sample hold circuit 222. Hold. Therefore, the integrated value of the output of the selector circuit 18 is output from the sample hold circuit 222.

Next, an operation example of the synchronous detection circuit having the variable amplification function having such a configuration will be described with reference to FIG.
FIG. 10 shows an example of performing synchronous detection by amplifying an input signal (input wave) having a signal synchronized with a carrier wave by a factor of four.
When a carrier wave S1 as shown in FIG. 10 is input to the waveform shaping circuit 11, the waveform shaping circuit 11 shapes the carrier wave S1 to generate a clock CLK as shown. The clock CLK is supplied to the selector circuit 18, the integrating circuit 22, and the counter 24, respectively.

As shown in FIG. 10, the input signal IN synchronized with the carrier wave and the inverted signal S3 obtained by inverting the input signal IN by the inverting circuit 13 are alternately output by the selector circuit 18.
The integration circuit 22 samples and holds only the input signal IN selected by the selector circuit 18 at the rising edge of the clock CLK from the waveform shaping circuit 11 when the control signal S10 from the counter 24 is at "L" level.

  On the other hand, when the control signal S10 is at “H” level, the integration circuit 22 samples and holds the addition value of the input signal IN selected by the selector circuit 18 and the output S9 of the integration circuit 22 at the rising edge of the clock CLK. At the falling edge of the clock CLK, the addition value of the inverted signal S3 selected by the selector circuit 18 and the output of the integrating circuit 22 is sampled and held. Therefore, the output S9 of the integrating circuit 22 is as shown in FIG.

Further, the sample hold circuit 23 samples and holds the output S9 of the integration circuit 22 at the rising edge of the control signal S10 from the counter 24. For this reason, the detection signal OUT of the sample hold circuit 23 is amplified to four times the input signal as shown in FIG.
Here, since the cycle of the control signal S10 of the counter 24 is proportional to the amplification factor of the synchronous detection circuit, the cycle of the control signal S10 of the counter 24 (frequency division ratio with the clock CLK) is controlled. The amplification factor can be varied.

It is a block diagram which shows the structure of 1st Embodiment of the synchronous detection circuit of this invention. It is a figure explaining the operation example of the 1st Embodiment, (a) is a figure of the time waveform of each part, (b) It is a figure of the frequency characteristic. It is a block diagram which shows the structure of 2nd Embodiment of the synchronous detection circuit of this invention. It is a block diagram which shows the structure of 3rd Embodiment of the synchronous detection circuit of this invention. It is a figure explaining the operation example of the 3rd Embodiment, (a) is a figure of the time waveform of each part, (b) It is a figure of the frequency characteristic. It is a figure explaining the example of operation when phase detection is realized in a 1st embodiment, (a) is a figure of a time waveform of each part, and (b) is a figure of the frequency characteristic. It is a block diagram which shows the structure of a vibration sensor detection circuit. It is a block diagram which shows the structure of embodiment of the synchronous detection circuit provided with the variable amplification function of this invention. FIG. 9 is a block diagram showing a specific configuration of the integration circuit of FIG. 8. It is a figure explaining the operation example of the synchronous detection circuit of FIG. It is a block diagram which shows the structure of the conventional circuit. It is a figure explaining the 1st example of operation | movement of the conventional circuit, (a) is a figure of the time waveform of each part, (b) It is a figure of the frequency characteristic. It is a figure explaining the 2nd example of operation | movement of the conventional circuit, (a) is a figure of the time waveform of each part, (b) It is a figure of the frequency characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Waveform shaping circuit 12, 13 Inversion circuit 14, 15 Sample hold circuit 16, 21 Adder circuit 17 Subtraction circuit 18 Selector circuit 19, 20 Sample hold circuit 22 Integration circuit 23 Sample hold circuit 24 Counter

Claims (9)

A synchronous detection circuit for detecting a signal component synchronized with a carrier wave from an input signal,
A first sample-and-hold circuit that samples and holds the input signal at a zero-cross timing of rising of the carrier wave;
A second sample-and-hold circuit that samples and holds an inverted signal of the input signal at a zero-cross timing of a falling edge of the carrier wave;
An adding circuit for adding and outputting the output signal of the first sample and hold circuit and the output signal of the second sample and hold circuit;
A synchronous detection circuit comprising: A synchronous detection circuit for detecting a signal component synchronized with a carrier wave from an input signal,
A first sample-and-hold circuit that samples and holds the input signal at a zero-cross timing of rising of the carrier wave;
A second sample-and-hold circuit that samples and holds the input signal at a zero-cross timing at the falling edge of the carrier wave;
A subtraction circuit that outputs a difference between an output signal of the first sample and hold circuit and an output signal of the second sample and hold circuit;
A synchronous detection circuit comprising: In a synchronous detection circuit that detects a signal component synchronized with a carrier wave from an input signal,
A selector circuit for selecting the input signal and an inverted signal of the input signal;
A first sample-and-hold circuit that samples and holds an output signal from the selector circuit at a zero-cross timing of the carrier wave;
A second sample-and-hold circuit that samples and holds an output signal of the first sample-and-hold circuit at a zero-cross timing of the carrier wave;
An addition circuit for adding and outputting the output signal of the first sample and hold circuit and the output signal of the second sample and hold circuit;
A synchronous detection circuit comprising: A waveform shaping circuit for generating an operation signal for operating the first sample hold circuit, the second sample hold circuit, or the selector circuit;
4. The waveform shaping circuit according to claim 1, wherein the waveform shaping circuit receives the carrier wave and generates a rectangular wave that changes sharply at the rising and falling edges of the carrier wave as the operation signal. The synchronous detection circuit according to claim 1. In an AM demodulator that demodulates an AM modulated wave,
An AM demodulator comprising the synchronous detection circuit according to any one of claims 1 to 4. In an FM demodulator that demodulates an FM modulated wave,
An FM demodulator comprising the synchronous detection circuit according to any one of claims 1 to 4. In a PM demodulator that demodulates a PM modulated wave,
A PM demodulator comprising the synchronous detection circuit according to any one of claims 1 to 4. A detection circuit of a vibration sensor that detects an operation that has occurred in a direction different from the vibrator,
An oscillation circuit for vibrating the vibrator;
A receiving circuit for receiving a vibration state of the vibrator;
Synchronous detection is performed on the output signal from the receiving circuit, and the generated operation is detected, and the synchronous detection circuit according to any one of claims 1 to 4,
A vibration sensor detection circuit comprising: In a synchronous detection circuit that detects a signal component synchronized with a carrier wave from an input signal,
A selector circuit for selecting the input signal and an inverted signal of the input signal;
An integration circuit for integrating the output signal from the selector circuit at the zero cross timing of the carrier;
A sample-and-hold circuit that samples and holds the output signal of the integrating circuit;
A counter for generating a control signal for performing output control of the integration circuit and sample-hold control of the sample-hold circuit based on the carrier;
A synchronous detection circuit having a variable amplification function.

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