JP2007019664A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify the structure for transferring charges vertically in a solid state imaging device. <P>SOLUTION: The solid state imaging device 100 comprises a pixel array region 1 where a plurality of photoelectric converting portions 2 are arranged to constitute rows and columns, vertical CCDs 30 arranged for respective columns of the pixel array region 1, transfer electrodes 3-1 through 3-4 arranged for respective rows of the pixel array region 1, and a vertical drive circuit 4 for driving the transfer electrodes 3-1 through 3-4 such that charges in the photoelectric converting portions 2 are transferred to the vertical CCD 30 and then charges are transferred vertically in the vertical CCD 30. After charges in the photoelectric converting portions 2 are transferred to the vertical CCD 30, the vertical drive circuit 4 applies a vertical transfer pulse to the transfer electrodes 3-1 through 3-4 sequentially starting from the transfer electrode 3-1 on the most downstream side in the vertical transfer direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  Conventionally, as a solid-state imaging device, a CCD is often used because of its good SN ratio. However, on the other hand, so-called amplification type solid-state imaging devices have also been developed, which have advantages such as ease of use and low power consumption. An amplification type solid-state imaging device is a type that guides signal charges accumulated in a photoelectric conversion unit to a control electrode of a transistor provided in a pixel unit, and outputs an amplified signal from a main electrode. There are SIT type image sensors using SIT (Non-Patent Document 1), CMDs using JFETs whose control electrodes are depleted (Non-Patent Document 2), CMOS sensors using MOS transistors (Non-Patent Document 3), and the like.

  In particular, the CMOS sensor is well-matched with the CMOS process, and the peripheral CMOS circuit can be made on-chip, so that much effort is put into development. However, a drawback common to these amplifying solid-state imaging devices is that fixed pattern noise (FPN) is carried as an image sensor signal because the output offset of the amplifying transistor provided in each pixel is different for each pixel. That is. Various signal readout circuits have been devised to eliminate the FPN.

  One of the essential drawbacks of the amplification type solid-state imaging device, not limited to the CMOS sensor, relates to the operation timing. The pixel signal reading operation of this type of image sensor is performed row by row, and the horizontal transfer operation continues after reading this row. For this reason, the signal accumulation operation timing of the pixels is shifted for each row. This is because the pixel signal accumulation operation in one field is completed with pixel signal readout. Therefore, the timing shift between the first row and the last row is almost one field time. On the other hand, in the CCD, all pixel signals are transferred to the vertical CCD all at once, but the CCD pixel accumulation operation ends and starts with this simultaneous transfer, so the CCD pixel accumulation operation is simultaneous. This operation timing shift of the amplification type image sensor appears as distortion of the image when a subject operating at high speed is photographed.

  Regarding the improvement of the disadvantage of the non-simultaneous accumulation operation, Patent Document 1 and Patent Document 2 propose an image sensor including an analog frame memory composed of memory cells formed by MOS switches and capacitors. Yes. In these proposals, a pixel signal is transferred to a memory cell in a short time without a horizontal transfer operation, and thereafter, reading of the memory signal with horizontal transfer is performed using almost one field period. Thereby, the deviation of the operation timing is remarkably shortened. However, since it is difficult to increase the capacity of the memory constituting the analog frame memory, noise is added once the signal is stored in the analog frame memory, and the S / N ratio of the sensor signal is significantly reduced. Accompany.

  Yet another drawback of CMOS sensors is that pixel size reduction is difficult compared to CCDs.

  In addition to the photodiode, the CCD pixel includes a vertical CCD and a transfer gate for transferring signal charges from the photodiode to the vertical CCD. On the other hand, a general CMOS sensor selects a floating diffusion (hereinafter referred to as FD), a signal amplifying MOS transistor, a MOS transistor for resetting the FD, and pixel signal reading in addition to the photodiode and the transfer gate. MOS transistors are included. Although proposals have been made to reduce some of the MOS transistors constituting the pixels of such a CMOS sensor, they are still disadvantaged over CCDs in terms of pixel reduction.

  On the other hand, one of the drawbacks of CCD is the reading speed of horizontal CCD. As the number of pixels increases, higher-speed horizontal scanning is required, but the operation of the horizontal CCD cannot cope with the increase in speed. In the CMOS sensor, it is easy to divide the horizontal readout line into a plurality of parts and reduce the scanning frequency of one horizontal output line. On the other hand, since the serial transfer of charges is fundamental in a CCD, it is difficult to transfer signal charges from a vertical CCD to a plurality of horizontal CCDs, and it is difficult to reduce the horizontal scanning frequency by using a plurality of horizontal CCDs. Furthermore, since the horizontal CCD operates by driving a large capacity at high speed, there is also a problem that it requires a large amount of power consumption compared to a CMOS sensor.

  Another disadvantage of a general CCD is that the implementation of an operation (so-called progressive operation) method of reading out signals of all pixels within one field period while keeping the signal charges of each pixel independently is particularly reduced. This is difficult with the pixels made. In order to realize the progressive operation, a vertical CCD capable of receiving the signal charges of each pixel independently is necessary. For this purpose, the required number of transfer electrodes of the vertical CCD is 3 to 4 per pixel. Become. However, it is difficult to form such a vertical CCD with a reduced pixel, and the number of signals accepted by the vertical CCD at a time is less than the number of pixels. I have to. In general, the number of transfer electrodes of a vertical CCD is two per pixel, and the signal that the vertical CCD accepts at one time is half the number of pixels.

  On the other hand, the CMOS sensor reads the signal voltage amplified by the amplifying transistor of the pixel from the signal output line, so the progressive method is a general reading method.

  A solid-state imaging device has been proposed in which the pixel part is composed of an interline CCD and the readout circuit part is composed of a MOS transistor circuit in order to complement the disadvantages of the CCD and the CMOS sensor as described above and take advantage of both. ing. Among these proposals, Patent Document 4 is a proposal that eliminates the problem of speed limitation of the horizontal CCD by providing a voltage amplifying means for each vertical CCD column and outputting a voltage. Further, Patent Document 3 enables independent readout of two rows at the time of interlaced operation by transferring vertical CCDs within one horizontal scanning period, and is equivalent to being able to perform a progressive operation. In Patent Documents 5 and 6, in order to realize a drive circuit in which the electrodes of the vertical CCD for the above operation can be independently controlled for each row, the well structure of the drive circuit is changed to a well of another circuit. It is a proposal that is different from the structure. Further, Patent Document 7 is a proposal to make the thickness of the gate oxide film of the drive circuit different from that of other circuits. Patent Document 8 proposes further improvements to the above series of proposals in order to cope with higher integration and higher speed of the solid-state imaging device.

Further, Patent Document 9 is a proposal for providing an FD for converting a signal charge output from a vertical CCD into a voltage for each vertical CCD and outputting a signal by a CMOS readout circuit.
A. Yusa, J. et al. Nishizawa et al. "SIT image sensor: Design considence and characteristics," IEEE trans. Vol. ED-33, pp. 735-742, June 1986. ), BASIS using bipolar transistors (N. Tanaka et al., “A 310K pixel bipolar imager (BASIS),” IEEE Trans. Electron Devices, vol. 35, pp. 646-902, May 19). Nakamura et al. “Gate Storage Type MOS Phototransistor Image Sensor”, Journal of Television Society, 41, 11, pp. 1075-1082 Nov. , 1987 S. K. Mendis, S.M. E. Kemeny and E.M. R. Fossum, “A 128 × 128 CMOS active image sensor for high integrated imaging systems,” in IEDM Tech. Dig. 1993, pp. 583-586. Furumiya et al. "A 1 / 3-inch 1.3M-Pixel Single-Layer Electrode CCD With a High-Frame-Rate Skip Mode" IEEE Transactions on Electron Devices. pp 1915-1921, Vol. 48, no. 9, September 2001 A. J. et al. P. Theeussen et al. "A 400K pixels 1/2 inch CCD CCD-imager." Digest Technical Papers ISSCC 88, pp. 48-49, San Francisco, February 17-19, 1988. JP 58-125982 A Japanese Patent Laid-Open No. 02-65380 JP 61-184975 A Japanese Patent Laid-Open No. 60-500396 JP 61-234670 A JP-A 61-145974 JP-A-1-103861 JP 09-51485 A JP 2002-135656 A JP 2003-51989

  However, there is a big problem in realizing the above proposal in an actual imaging apparatus. That is, while a general CMOS sensor manufacturing process is a process for forming a miniaturized MOS transistor corresponding to a low-voltage power supply of 5 V or less and a single-layer polysilicon electrode, a general CCD manufacturing process However, this is a process for forming a CCD that requires a drive voltage amplitude of 20 V or more, and for a two-layer polysilicon electrode, because both processes are greatly different and there are not many common elements.

  That is, when the pixel portion is simply composed of a CCD and the readout circuit and the drive circuit are composed of a CMOS, the two processes are added, as can be seen from the descriptions in Patent Document 5, Patent Document 6, and Patent Document 7. Such a redundant manufacturing process is used, resulting in a significant increase in manufacturing cost.

  Considering the realization of the sensor in one of the processes for CCD or CMOS, for example, the CCD process is not supposed to form both NMOS and PMOS transistors, and is compatible with high power supply voltage. With a MOS transistor, it is difficult to form a reduced, high-speed circuit necessary for signal reading. On the other hand, when a CCD pixel is formed by a CMOS process, the vertical CCD of the pixel portion is formed by a single-layer polysilicon electrode driven at a low voltage.

  As is well known, in a CCD that supports a general interline interlace operation, two transfer electrodes are formed per pixel for a vertical CCD, and one unit of signal charge exists for every four transfer electrodes of two pixels. A potential well is formed. At this time, in the case of a two-layer polysilicon electrode, since two electrodes having different layers are arranged so as to overlap each other for one pixel, the area ratio occupied by the transfer electrode wiring can be suppressed to be small on the planar layout. .

  However, if it is intended to realize two transfer electrodes per pixel with a single layer of polysilicon electrode, the two electrodes are separated from each other on the plane layout, and the two transfer electrode wirings and their transfer electrodes are arranged. Since the total area with the space between them is large, the photodiode area is compressed, and important sensor characteristics such as sensitivity and saturation are greatly deteriorated.

  Further, in the vertical CCD, the area for the potential well in which one unit of signal charge exists is pressed due to the space between the electrodes, and therefore the maximum amount of charge accepted by the vertical CCD is further greatly reduced. Also, the maximum amount of charge accepted by the vertical CCD is reduced by the condition of low voltage driving.

  For the reasons described above, a sensor element that combines a CCD pixel, a CMOS readout circuit, and a CMOS drive circuit has a larger problem and disadvantage than taking advantage of both the CCD and the CMOS. It is difficult to realize such a sensor. Moreover, although the proposal of Patent Document 3 enables progressive operation, it conversely suffers from the disadvantage of the CMOS sensor that the storage operation is not synchronized.

  Further, the proposal of Patent Document 9 still has problems of inconsistency in the manufacturing process and difficulty in progressive operation of the CCD.

  The present invention has been made on the basis of the above problem recognition, and an object thereof is, for example, to simplify a structure for vertical charge transfer in a solid-state imaging device.

  The solid-state imaging device according to the present invention relates to a solid-state imaging device having a pixel array region in which a plurality of photoelectric conversion units are arranged to form rows and columns, and the solid-state imaging device includes one column of the pixel array region. A plurality of vertical CCDs arranged one by one, a plurality of transfer electrodes arranged one by one with respect to one row of the pixel array region, and the charges of the plurality of photoelectric conversion units A vertical drive circuit that drives the plurality of transfer electrodes so that charges are transferred vertically in the plurality of vertical CCDs, and the vertical drive circuit includes the pixel array region and Arranged on the same semiconductor substrate, after the charges of the plurality of photoelectric conversion units are transferred to the plurality of vertical CCDs, the plurality of transfer electrodes are vertically arranged in order from the most downstream transfer electrode in the vertical transfer direction. And applying a pulse for transmission.

  According to the present invention, for example, a structure for vertical transfer of charges in a solid-state imaging device can be simplified.

  This embodiment is an application example of the present invention, in a solid-state imaging device having a pixel array region in which a plurality of photoelectric conversion units are arranged to form rows and columns, with respect to one row of the pixel array region. A structure in which one transfer electrode is arranged is provided. This structure is a CCD pixel that is capable of progressive operation while maintaining operation with no high SNR, high dynamic range, and accumulation timing that are the advantages of a CCD, and a CMOS readout circuit that has advantages in high-speed readout and low power consumption Can be included.

In order to make the drive voltage of the transfer electrode in the pixel array region including the photoelectric conversion unit (photodiode) and the vertical CCD equal to the CMOS circuit power supply voltage (for example, 5 V), an insulating film below the transfer electrode in the pixel array region It is preferable to make the thickness of the gate insulating film the same as that of the gate insulating film of the CMOS circuit. This can be realized by simultaneously forming the insulating film under the transfer electrode and the gate insulating film of the CMOS circuit in the same process.
The signal charge transfer structure from the photoelectric conversion unit (photodiode) to the vertical CCD is similar to the signal charge transfer structure from the photodiode to the floating diffusion (FD) in the CMOS sensor. The gate electrode of the circuit portion is preferably the same layer. This can be realized by simultaneously forming the transfer electrode in the pixel array region and the gate electrode of the CMOS circuit portion in the same process.

  The transfer electrode of the vertical CCD is preferably formed by one conductive layer (for example, a polysilicon layer), and the transfer of the vertical CCD is performed so that one unit of potential well is formed by one transfer electrode. Along the direction, a potential barrier and a potential well are preferably formed under one transfer electrode. By forming the insulating film under the transfer electrode as the same layer as the gate oxide film of the CMOS circuit with the same thickness, the amplitude of the transfer pulse of the vertical CCD can be reduced.

  The vertical CCD can be driven by an accordion drive system by a CMOS vertical drive circuit. The CMOS vertical drive circuit is configured so that a vertical transfer pulse can be independently applied to a plurality of transfer electrodes of a vertical CCD. The CMOS vertical drive circuit applies vertical transfer pulses to the plurality of transfer electrodes in order from the most downstream transfer electrode in the vertical transfer direction for accordion drive.

  Among the wells of the N-type MOS transistor (NMOS) and the P-type MOS transistor (PMOS) constituting the CMOS circuit around the pixel array region including the drive circuit such as the vertical drive circuit, the pixel for the electronic shutter operation The well of the same conductivity type as the substrate to which the high voltage pulses for simultaneously resetting the photodiodes are applied is surrounded by a diffusion layer of the opposite conductivity type, and the high voltage pulse is generated during the electronic shutter operation. It is electrically separated from the substrate to be applied.

  Hereinafter, more specific embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, the same components are denoted by the same reference numerals.

[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device as a first embodiment of the present invention. The solid-state imaging device 100 includes a pixel array region 1 in which a plurality of pixels 2 are arranged so as to form rows and columns. In FIG. 1, for convenience of explanation, the pixel array region 1 is composed of 4 × 4 pixels. The pixel 2 includes a photodiode (photoelectric conversion unit) that converts an optical signal into a signal charge and stores it. A vertical CCD 30 is arranged along each column of a plurality of pixels 2.
One transfer electrode 3 (3-1, 3-2, 3-3, 3-4) is arranged for one row composed of a plurality of pixels 2. That is, the number of transfer electrodes 3 (3-1, 3-2, 3-3, 3-4) is equal to the number of rows of pixels 2 in the pixel array region 1.

Each transfer electrode 3 (3-1, 3-2, 3-3, 3-4) has a comb shape in a plan view, and each comb tooth portion (a portion extending in the vertical direction in FIG. 1 (second portion) Part)) is a transfer electrode for transferring charges in the vertical CCD 30 in the vertical direction (direction from top to bottom in FIG. 1) and a signal charge accumulated in the pixel 2 in the well region of the vertical CCD 30 (potential for receiving charges). It functions as a transfer electrode for transferring to a diffusion region for forming a well).
In each transfer electrode 3 (3-1, 3-2, 3-3, 3-4), a portion (first portion) extending along the row of the pixels 2 connects a plurality of comb-tooth portions. It has a function. The transfer electrode 3 can be composed of one wiring layer (for example, one polysilicon wiring layer), preferably the same layer (for example, a polysilicon gate layer) as the gate layer of the CMOS circuit.

Each transfer electrode 3 (3-1, 3-2, 3-3, 3-4) is driven by a vertical drive circuit (for example, shift register) 4, and the signal charge accumulated in the pixel 2 is transferred to the vertical CCD 30. The operation of transferring to the well region and the operation of transferring charges in the vertical CCD 30 in the vertical direction (direction from top to bottom in FIG. 1) are controlled.
A floating diffusion (FD) unit 5 is disposed on the most downstream side (a destination where charges are vertically transferred) of each vertical CCD 30. The FD unit 5 converts the signal charge vertically transferred by the vertical CCD 30 into a voltage. The voltage signals respectively generated by the plurality of FD units 5 are amplified by the reading circuit 6 and temporarily held.
The readout circuit 6 includes a number of amplifier circuits (for example, MOS transistor amplifiers) corresponding to the number of FD sections 5 (the number of columns in the pixel array region 1), a line memory that holds amplified signals output from the amplifier circuits, and the like. Can be done.
The horizontal drive circuit (for example, shift register) 8 selects a selection signal (a plurality of columns in order) from the readout circuit 6 so that the signals of the plurality of columns in the pixel array region 1 are sequentially transferred to the horizontal output line 7. Signal). The signal transferred to the horizontal output line 7 is amplified by the amplifier 9 and output from the output terminal 10.

  FIG. 2 is a cross-sectional view showing a signal charge transfer structure in the pixel (photodiode) 2, the vertical CCD 30, and the FD portion 5 along the line AB in FIG. 1.

  In FIG. 2, a pixel (photodiode) 2 is formed above an N-type diffusion layer 11 for accumulating electrons as signal charges and a diffusion layer 11 for suppressing dark current generated at a semiconductor interface. And a P-type diffusion layer.

  The vertical CCD 30 includes an N-type diffusion layer (well region) 13, a diffusion layer 14, and a transfer electrode 15. The N-type diffusion layer (well region) 13 is disposed below the transfer electrode 3 (3-1 and 302 in FIG. 2), and forms a potential well that receives the signal charge transferred from the pixel 2. The diffusion layer 14 forms a potential barrier in the charge transfer path in the gap between the adjacent transfer electrodes 3 (between 3-2 and 3-1 in FIG. 2). The diffusion layer 14 determines the direction of vertical charge transfer. The transfer electrode 15 transfers signal charges from the vertical CCD 30 to the FD unit 5.

  In FIG. 2, reference numeral 16 denotes an N-type semiconductor substrate, and 17 denotes an impurity concentration for forming a potential barrier between the N-type diffusion layer 11 and the N-type substrate 16 disposed at least over the entire pixel array region 1. It is a low P-type diffusion layer. 18 electrically separates the charge transfer path of the vertical CCD 30 and the pixel (photodiode) 2 and also connects the charge transfer path of the vertical CCD 30 and the N semiconductor substrate 16 in the simultaneous reset operation of the pixel (photodiode) 2. A P-type diffusion layer for electrical isolation.

  FIG. 3 is a diagram showing a cross-sectional structure (cross-section CC ′ of FIG. 1) of the vertical CCD 30 of the solid-state imaging device 100 shown in FIG. 1 and a potential diagram of its charge transfer path. First, a positive potential pulse is applied to all the transfer electrodes 3 (3-1, 3-2, 3-3, 304) by the vertical drive circuit 4, and the signal charges of all the pixels (photodiodes) 2 are changed. After being transferred to the corresponding potential well region 13 of the vertical CCD 30, the potentials of all transfer electrodes 3 return to the intermediate level (typically the ground level). This state is shown as (P0).

In the (P0) state, electrons are held in the well region 13 having a low potential for electrons as signal charges. The signal charges of each pixel are represented by S1, S2, S3, and S4. The position having the highest potential along the charge transfer path in the (P0) state is the potential barrier layer 14, and the potential of the region without the diffusion layer between the region 13 and the potential barrier layer 14 is the potential of the region 13. It is in the middle of the potential of the potential barrier layer 14. The potential of the transfer electrode 15 is always at an intermediate level. When a negative pulse is applied to the transfer electrode 3 (3-1, 3-2, 3-3, 304) of the vertical CCD 30 from this state, the signal charge is transferred toward the FD unit 5 due to the above potential relationship. I understand that. The transfer electrode 3 for charge transfer can be constituted by one wiring layer (for example, one polysilicon wiring layer). Further, the transfer electrode 3 for charge transfer can be formed by a pulse having a low voltage amplitude that can be driven by the power supply voltage of the CMOS circuit. For example, the transfer electrode 3 can be formed simultaneously in the same layer (for example, the first polysilicon layer) as the gate electrode of the vertical drive circuit 4, the signal readout circuit 6, and / or the horizontal drive circuit 8. Further, the insulating film under the transfer electrode 3 can be formed simultaneously in the same process as the gate insulating film of the vertical driving circuit 4, the signal readout circuit 6, and / or the horizontal driving circuit 8.
For example, Non-Patent Document 4 describes a CCD using a transfer electrode made of one layer of polysilicon.

  Low voltage driving can be achieved by forming the gate oxide film under the transfer electrode 3 thinner than a general CCD device. In this case, the maximum amount of charge that can be received and transferred by one potential well is smaller than that of a general CCD. However, the charge that one potential well of a general interlaced vertical CCD must accept is the sum of signal charges generated by two photodiodes, whereas the vertical CCD of this embodiment is described below. By adopting such accordion transfer, one potential well only needs to receive the signal charge of one photodiode. Therefore, a decrease in saturation performance can be suppressed by employing accordion transfer.

The accordion transfer by the vertical CCD 30 is started from the initial state shown in (P0). The accordion transfer is described in Non-Patent Document 5, for example.
In the accordion transfer, in the vertical CCD 30 having a plurality of storage regions 13, signal charges stored in the well region 13 on the most downstream side (a destination to which charges are vertically transferred) are transferred to the downstream side in order. This is a system in which all of the plurality of signal charges respectively stored in the plurality of storage regions 13 are finally sent out from the vertical CCD 30 while repeating the operation of transferring the signal charge of the next pixel to the well region 13 that becomes empty. .
In this embodiment, after the charge of each pixel 2 in the pixel array region 1 is transferred to the corresponding vertical CCD 30, it is transferred vertically to the transfer electrodes 3-1, 3-2, 3-3 and 3-4. Accordion driving is realized by applying vertical transfer pulses in order from the most downstream transfer electrode in the direction (that is, in the order of 3-1, 3-2, 3-3, 3-4).
From the initial state shown in (P0), first, a negative potential is applied to the transfer electrode 3-1 in the first row of pixels (the row closest to the FD unit 5, the readout signal circuit 6, or the horizontal scanning circuit 8 is the first row). Are applied. This state is shown as (P1). By this operation, the signal charges S1 of the pixels in the first row are transferred from the potential well 13 in the first row to the FD unit 5.

  Next, after the transfer electrode 3-1 in the first row is returned to the intermediate potential by the vertical transfer circuit 4, a pulse having a negative potential is applied to the transfer electrode 3-2 in the second row. This state is shown as (P2). By this operation, the signal charges S2 of the pixels in the second row are transferred from the potential well 13 in the second row to the potential well 13 in the first row.

  Next, after the transfer electrode 3-2 in the second row is returned to the intermediate potential by the vertical transfer circuit 4, a negative potential pulse is applied to the transfer electrode 3-3 in the third row, so that the pixel in the third row Are transferred from the potential well 13 in the third row to the potential well 13 in the second row. This state is shown as (P3).

  Next, after the transfer electrode 3-3 in the third row is returned to the intermediate potential by the vertical transfer circuit 4, a pulse of a negative potential is applied to the transfer electrode 304 in the fourth row, and the signal of the pixel in the fourth row The charge S4 is transferred from the potential well 13 in the fourth row to the potential well 13 in the third row. This state is shown as (P4).

  Thus, in the accordion transfer, the signal charges of the pixels in each column are shifted downstream by one pixel by the vertical CCD 30 through the states shown in (P0) to (P4). In the accordion transfer, such an operation is repeatedly executed, and finally, all the signal charges of the pixels in each column are sent out from the vertical CCD 30 to the FD unit 5. According to such an operation, the signal charges of all the pixels 2 are independently transferred to the corresponding FD units 5 and a progressive operation is realized.

Since the accordion operation is not simultaneous driving of transfer electrodes like a general CCD, but selects a plurality of rows in order, the vertical driving circuit 4 can be designed with a shift register as a basic configuration. Such a vertical drive circuit 4 can be easily realized by a CMOS circuit and can be easily incorporated in the solid-state imaging device 100.
The signal charges sequentially transferred to the FD unit 5 by the operation as described above are converted into a voltage in the FD unit 5 and provided to the readout circuit 6 including a source follower amplifier whose gate is connected to the FD unit 5, for example. The The readout circuit 6 can be composed of a CMOS circuit. A configuration example of the readout circuit is disclosed in, for example, Patent Document 9. The read circuit 6 can include, for example, a clamp capacitor, a gain amplifier, and a circuit for removing offset variation of the gain amplifier for each column. Such a readout circuit using a CMOS circuit generally has the advantages of high speed and low power consumption as compared with a horizontal CCD.

  In progressive driving, the signal charges of one row of pixels transferred to the FD unit 5 are transferred, and in interlaced driving, signal charges of two rows of pixels transferred to the FD unit 5 are transferred to one horizontal block. Conversion is performed in the readout circuit 6 within the ranking period, and then video signals for one or two lines are output in the horizontal scanning period. According to this embodiment, since the signal charges of each pixel are transferred independently, signals for two rows can be output independently in interlaced driving. After the predetermined signal charge is transferred to the FD unit 5 within one horizontal blanking period, how many rows of the signal charge are transferred in the vertical CCD 30, that is, in FIG. After the data is transferred to 5, what kind of accordion drive mode is adopted as to whether to prepare for the second horizontal blanking period in the states of (P2), (P3), (P4). Dependent.

  FIG. 4 is a diagram exemplarily showing a cross-sectional structure of a CMOS circuit used in the readout circuit 6 and the vertical drive circuit 4 (accordion drive circuit). In FIG. 4, 19 is a P-type well, 20 is a P-type diffusion layer for determining the potential of the P-type well 19, and 21 is an N-type MOS transistor formed in the P-type well 19 and comprising a gate, a drain, and a source. , 22 is an N-type well, 23 is an N-type diffusion layer for determining the potential of the N-type well 22, 24 is a P-type MOS transistor formed in the N-type well 21, and includes a gate, a drain, and a source, 25 A P-type well 26 is a P-type diffusion layer for determining the potential of the P-type well 19. The periphery of the N-type well 22 is surrounded by a P-type well, and a P-type diffusion layer 18 for separation and a P-type diffusion layer 17 for potential barrier are disposed below the N-type well 22. Electrically separated.

  With such a structure, even when a high voltage is applied to the N-type substrate 16 in the simultaneous reset of the pixel (photodiode) 2 for the electronic shutter, both the P-type and N-type MOS transistors are not affected. Can keep the state.

  Since the solid-state imaging device according to the first embodiment of the present invention having the structure described above is based on a CMOS manufacturing process and has a pixel array region 1 as a CCD, a high SN ratio, which is a characteristic of a CCD, Maintains high dynamic range and simultaneous operation. Further, according to this embodiment, since the vertical CCD is formed by only one transfer electrode (for example, polysilicon transfer electrode) per pixel, in order to increase the photodiode area and further improve the S / N ratio. It is advantageous, and the design of the microlens is facilitated as compared with a normal CCD two-layer polysilicon structure. Further, according to this embodiment, progressive operation is realized by accordion driving, and high-speed horizontal scanning is realized by configuring the readout circuit with CMOS.

[Second Embodiment]
FIG. 5 is a block diagram showing a schematic configuration of a solid-state imaging apparatus as the second embodiment of the present invention. The solid-state imaging device 200 of the second embodiment shown in FIG. 5 is the same as the imaging device 100 of the first embodiment with respect to the pixel array region 1, the vertical CCD including the transfer electrode 3, and the vertical drive circuit 4. In the solid-state imaging device 200 shown in FIG. 5, 27 is a horizontal CCD, and 28 is an amplifier for amplifying the signal charge transferred by the horizontal CCD 27.

  In applications where high-speed scanning is not required, horizontal scanning using a horizontal CCD as in the second embodiment may be employed. When high speed is not required for the accordion operation drive circuit, it is not necessary to adopt a CMOS manufacturing process, and a high voltage drive circuit as in a normal CCD may be adopted. Further, if a circuit such as a shift register required for accordion driving can be formed, it is not particularly necessary to be a CMOS circuit. In this case, a normal CCD structure can be adopted as the structure of the transfer part from the photodiode to the vertical CCD, and the driving voltage of the vertical CCD can be increased. Therefore, one potential well is normally assigned to two photodiodes. As compared with the CCD, a saturation charge amount approximately twice as large as one pixel can be realized.

1 is a block diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a signal charge transfer structure in a pixel (photodiode), a vertical CCD, and an FD portion along line AB in FIG. 1. 2 is a diagram illustrating a cross-sectional structure of a vertical CCD (cross-section CC ′ in FIG. 1) of the solid-state imaging device 100 illustrated in FIG. 1 and a potential diagram of its charge transfer path. It is a figure which shows the cross-section of the CMOS circuit used for the read-out circuit 6 and the vertical drive circuit 4 (accordion drive circuit). It is a block diagram which shows schematic structure of the solid-state imaging device as 2nd Embodiment of this invention.

Explanation of symbols

1: pixel array region, 2: pixel (photodiode), 3: transfer electrode, 4: vertical drive circuit, 5: floating diffusion (FD) section, 6: readout circuit (for example, CMOS circuit), 7: horizontal output line 8: horizontal scanning circuit (for example, shift register), 9: amplifier, 10: output terminal, 11: signal charge storage layer, 12: interface impurity layer of photodiode, 13: diffusion layer for potential well (well region), 14: Potential barrier diffusion layer, 15: Transfer gate, 16: Semiconductor substrate, 17: Potential barrier diffusion layer, 18: Photodiode isolation diffusion layer, 19: P-type well, 20: Well contact diffusion layer, 21 : N-type MOS transistor, 22: N-type well, 23: Diffusion layer for well contact, 24: P-type MOS transistor, 25: P Well, 26: well contact diffusion layer, 27: horizontal CCD, 28: amplifier

Claims (6)

A solid-state imaging device having a pixel array region in which a plurality of photoelectric conversion units are arranged to form rows and columns,
A plurality of vertical CCDs arranged one by one for one column of the pixel array region;
A plurality of transfer electrodes arranged one by one for one row of the pixel array region;
A vertical driving circuit for driving the plurality of transfer electrodes so that the charges of the plurality of photoelectric conversion units are transferred to the plurality of vertical CCDs, and then the charges are vertically transferred in the plurality of vertical CCDs. Prepared,
The vertical driving circuit is disposed on the same semiconductor substrate as the pixel array region, and after the charges of the plurality of photoelectric conversion units are transferred to the plurality of vertical CCDs, a vertical transfer direction with respect to the plurality of transfer electrodes Applying a pulse for vertical transfer in order from the transfer electrode on the most downstream side of
A solid-state imaging device. Each of the transfer electrodes includes a first portion extending along a row of the pixel array region, and a second portion extending from the first portion along a plurality of columns in the pixel array region,
Each of the vertical CCDs includes a diffusion region that forms a potential well for receiving a charge provided from the photoelectric conversion unit under the second portion, and determines a vertical transfer direction between the adjacent diffusion regions. Including a potential barrier to
The solid-state imaging device according to claim 1.   The vertical drive circuit includes a first well having the same conductivity type as a semiconductor region to which a voltage for simultaneously resetting the plurality of photoelectric conversion units is applied, and a second well having a conductivity type opposite to the first well. The solid-state imaging device according to claim 1, wherein the first well has a structure surrounded by the second well and a diffusion region of the same conductivity type as the second well.   2. The gate electrode of the vertical drive circuit is in the same layer as the transfer electrode, and the gate oxide film of the vertical drive circuit is in the same layer as an insulating film under the transfer electrode. The solid-state imaging device according to claim 3. A plurality of floating diffusion sections for converting charges transferred from the plurality of vertical CCDs into voltages, respectively;
A read circuit for reading a signal from the floating diffusion section;
The gate and gate insulating film constituting the readout circuit are in the same layer as the gate and gate insulating film constituting the vertical transfer circuit, respectively.
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided.   The solid-state imaging device according to claim 5, wherein the vertical drive circuit and the readout circuit are configured by a CMOS circuit.

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