JP2007013122A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a radio chip in small size with small power consumption where excessively high voltage is suppressed as generated inside even in high magnetic field disposed closer to an antenna or the like. <P>SOLUTION: The radio chip is realized by using a resonant circuit having a MOS capacitative element of predetermined threshold voltage. This allows variations of parameters in the resonant circuit to be prevented, and the radio chip to be away from resonant status if voltage amplitude exceeds a predetermined value in the high magnetic field. As a result, this allows the generation of excessive voltage to be suppressed without using a limiter circuit or constant voltage generation circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device capable of wirelessly transmitting or receiving data.

In recent years, development of a semiconductor device capable of wirelessly transmitting or receiving data has been advanced. Such a semiconductor device is called an RFID (Radio Frequency Identification), an RF chip, an RF tag, an IC chip, an IC tag, a wireless chip, a wireless tag, an electronic chip, an electronic tag, a wireless processor, a wireless memory, or the like. The one that is currently in practical use is one in which a built-in integrated circuit is formed on a single crystal silicon substrate (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-133860

A semiconductor device capable of wirelessly transmitting or receiving data (hereinafter referred to as a wireless chip) is a transistor that constitutes a circuit due to excessively high internal voltage in a strong magnetic field such as when approaching an antenna. There is a problem that elements such as the above are destroyed.

On the other hand, there is a method of suppressing the generation of an excessively high voltage by adding a circuit such as a limiter circuit or a constant voltage generation circuit (see Japanese Patent Application Laid-Open No. 2005-322899). However, in this method, the circuit area may be increased due to the addition of an extra circuit.

In addition, the power to be absorbed is the same as when excessive voltage is generated, and there is a problem that power consumption is large.

The present invention has been made in view of the above. Even in a strong magnetic field such as when approaching an antenna, the internal generated voltage is prevented from becoming excessively high, and no extra circuitry such as a limiter circuit or constant voltage generation circuit is added, resulting in high reliability and chip area. It is an object to realize a wireless chip with low power consumption and low power consumption.

As a means for realizing the above-described problem, the inventor, when the voltage generated in the resonance circuit exceeds a predetermined voltage, changes the parameter of the resonance circuit to move away from the resonance state, thereby generating an excessive voltage. I thought about holding it down. Also, in order to construct a resonant circuit having such a function, attention was paid to the non-linear nature of the MOS capacitor element.

The present invention can suppress the generation of an excessive voltage without using a limiter circuit or a constant voltage generation circuit by using a resonance circuit having a MOS capacitance element having a predetermined threshold voltage. A new wireless chip is provided.

The MOS capacitor element used in the present invention will be described with reference to FIG. The capacitor element is formed by laminating a conductive film, an insulating film, and a conductive film, and has two terminals (hereinafter, also referred to as a normal capacitor element in distinction from a MOS capacitor element). As shown in FIG. 2C, such a normal capacitor element has a constant capacitance value regardless of the voltage.
When a resonant capacitor is provided inside the chip as in the present invention, it is necessary to operate as a capacitive element regardless of whether a positive or negative signal is input to both ends of the capacitive element. Therefore, a conductive film, an insulating film, and a conductive film are stacked. It is preferable to use a capacitor having a structure.

On the other hand, the MOS capacitor element is a capacitor element formed by stacking a conductive film, an insulating film, and a semiconductor region. It has two terminals: an electrode on the conductive film side (voltage Vm) and an electrode on the semiconductor region side (voltage Vs). In the following description, the electrode on the conductive film side may be referred to as a gate electrode, and the semiconductor region overlapping with the conductive film side electrode through an insulating film may be referred to as a channel formation region.

An N-type MOS capacitor element has a threshold voltage Vthn, and when Vm> Vs + Vthn is established, an N-type inversion layer is formed in the channel formation region. As a result, when Vm> Vs + Vthn, the channel formation region has conductivity and behaves as a normal capacitor. A P-type MOS capacitor element has a threshold voltage Vthp, and when Vm <Vs + Vthp is satisfied, a P-type inversion layer is formed in the channel formation region. As a result, when Vm <Vs + Vthp, the channel formation region has conductivity and behaves as a normal capacitor. Under conditions other than the above, the capacitance value is almost zero.

This is shown in FIGS. 2 (A) and 2 (B). FIG. 2A shows the relationship 201 between the capacitance value C and the voltage V of the N-type MOS capacitor element having the threshold voltage Vthn1, and the relationship between the capacitance value C and the voltage V of the N-type MOS capacitor element having the threshold voltage Vthn2. 202 is shown. FIG. 2B shows the relationship 203 between the capacitance value C and the voltage V of the P-type MOS capacitor having the threshold voltage Vthp1, and the relationship between the capacitance value C and the voltage V of the P-type MOS capacitor having the threshold voltage Vthp2. 204 is shown. In the figure, the case of Vthn2 <Vthn1 and Vthp1 <Vthp2 is shown.

The wireless chip of the present invention includes a resonance circuit having a MOS capacitor having a predetermined threshold voltage as shown in FIGS.

As a method for controlling the threshold voltage of the MOS capacitor element to be a predetermined value, a method of controlling the impurity element concentration contained in the channel formation region of the MOS capacitor element by ion doping or ion implantation can be mentioned. . In addition, it can be controlled to some extent by appropriately selecting materials for the conductive film, the insulating film, and the semiconductor region.

Note that the resonance circuit included in the wireless chip of the present invention has an N-type MOS capacitor having a negative threshold voltage or a P-type MOS capacitor element having a positive threshold voltage.

In the present invention, the MOS capacitance element has a constant capacitance value under the condition that no high voltage is generated. On the other hand, an AC voltage is applied to the MOS capacitor used in the present invention, and both positive and negative voltages are applied between the two terminals of the capacitor. Therefore, in order to have a constant capacitance value, an N-type MOS capacitor The threshold voltage of the element needs to be negative (Vthn <0), and the threshold voltage of the P-type MOS capacitor element needs to be positive (Vthp> 0).

The present invention is also excellent in power consumption. In the case of using a limiter circuit or a constant voltage generation circuit, the absorbed power does not change even when these circuits function and suppress excessive voltage generation. Since the resonance circuit of the present invention suppresses excessive voltage generation by shifting the resonance point, the power absorption itself can be suppressed. As a result, power consumption can be reduced.

This is particularly effective when reading a plurality of chips. When a plurality of chips enter a magnetic field, the power absorption of each chip affects the magnetic field, and the resonance point of the chip shifts. As a result, there is a problem that the performance of reading a plurality of chips deteriorates. The present invention can suppress the power absorption of the chip particularly under the condition of large power absorption, and exhibits excellent characteristics even when reading a plurality of chips.

In the present invention, since a circuit such as a limiter circuit or a constant voltage generation circuit is not added, the circuit area can be reduced. Further, when a gate insulating film is used as an insulating film of a MOS capacitor element, the gate insulating film is thin and has a good film quality, so that the area of the capacitor element is smaller than that of a capacitor element using another insulating film. it can.

The wireless chip of the present invention may be formed on a single crystal silicon substrate, or may be formed on a glass substrate or a flexible substrate such as plastic.

In particular, the form formed on a flexible substrate is advantageous in various applications such as embedding in paper or pasting on a curved surface because of the added value that the wireless chip itself is flexible. In these applications, the performance of reading a plurality of chips is often important, and the configuration of the present invention is preferable.

In particular, a form formed on a glass substrate or a form in which a chip formed on a glass substrate is transferred onto a flexible substrate is superior in cost compared to a form formed on a single crystal silicon substrate. This is because the glass substrate is much larger than the single crystal silicon substrate. On the other hand, the form formed on the glass substrate has a problem that the chip area becomes large. However, since the area of the MOS capacitor element is small and the limiter and the constant voltage generation circuit do not need to be provided, The configuration is preferable.

The specific configuration of the present invention is shown below.

One embodiment of a semiconductor device of the present invention is characterized in that it has a resonance circuit including an N-type MOS capacitor element having a negative threshold voltage, and transmits and receives data wirelessly via an antenna.

In particular, the threshold voltage of the N-type MOS capacitor element is preferably in the range of −24 V to −0.1.

The absolute value of the threshold voltage of the N-type MOS capacitor element is preferably not less than 1/2 of the minimum operating power supply voltage and not more than twice the maximum operating power supply voltage.

The semiconductor region of the N-type MOS capacitor element preferably contains an N-type impurity element at a concentration of 1 × 10 ¹⁷ or more and 1 × 10 ²⁰ atoms / cm ³ or less.

Another embodiment of the semiconductor device of the present invention is characterized in that it has a resonance circuit having a P-type MOS capacitor having a positive threshold voltage, and transmits and receives data wirelessly via an antenna.

In particular, the threshold voltage of the P-type MOS capacitor is preferably in the range of 0.1 to 24V.

In addition, the absolute value of the threshold voltage of the P-type MOS capacitor element is preferably not less than 1/2 of the minimum operating power supply voltage and not more than twice the maximum operating power supply voltage.

The semiconductor region of the P-type MOS capacitor element preferably contains a P-type impurity element at a concentration of 1 × 10 ¹⁷ or more and 1 × 10 ²⁰ atoms / cm ³ or less.

The semiconductor device of the present invention may include an integrated circuit provided over a glass substrate or a flexible substrate.

The semiconductor device of the present invention may have an integrated circuit including a thin film transistor.

Another embodiment of the present invention is a banknote, a coin, a securities, a certificate, a bearer bond, a packaging container, a book, a recording medium, a vehicle, food, clothing, health supplies, or daily items on which the semiconductor device described above is mounted. It is characterized by being a medicine or an electronic device.

The present invention can realize a highly reliable wireless chip by suppressing an excessively high voltage generated inside even in a strong magnetic field such as when approaching an antenna.

In addition, since an extra circuit such as a limiter circuit or a constant voltage generation circuit is not added, a wireless chip with a small chip area can be realized.

Furthermore, since the resonance circuit of the present invention suppresses excessive voltage generation by shifting the resonance point, unlike the case where a limiter circuit or a constant voltage generation circuit is used, power absorption itself can be suppressed. As a result, power consumption can be reduced. In particular, the effect is great in applications where it is necessary to read a plurality of chips.

In particular, the form formed on a flexible substrate can be used in various applications. However, the configuration of the present invention that suppresses power absorption is effective when reading a plurality of chips, and has a synergistic effect in various applications. Can be obtained.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a resonance circuit used in the present invention will be described. This can be considered as the most simplified form of the wireless chip of the present invention.

First, a conventional resonance circuit will be described with reference to FIG. FIG. 3A shows a coil antenna having an inductance L, a resistance element having a resistance value R, a resonance circuit in which a capacitance element having a capacitance value C is connected in series, and an antenna for supplying electric power thereto ( Inductance LR, current iR) are shown. This can be considered as a simplified model representing a conventional wireless chip and a device (hereinafter referred to as a reader) that transmits and receives data to and from the wireless chip. In FIG. 3A, when the mutual inductance between the two antennas is M and the angular frequency is ω, the amplitude V of the AC voltage induced at both ends of the capacitive element is given by Equation 1. In particular, the case where ω ² LC = 1 holds is called a resonance state, and the voltage amplitude V becomes maximum.

FIG. 3B shows the relationship between the capacitance value C and the voltage amplitude V. The curve (2) and the curve (1) have different mutual inductance values, and the curve (2) has a larger mutual inductance. The mutual inductance changes when the distance and arrangement of the wireless chip and the reader are changed. For example, the mutual inductance increases as the distance between the wireless chip and the reader decreases. FIG. 3C shows the relationship between the mutual inductance M and the voltage amplitude V. As shown in FIG. 3C, the voltage amplitude V is proportional to the mutual inductance M.

Next, the resonance circuit used in the present invention will be described with reference to FIG. 4A shows a coil antenna having an inductance L, a resistance element having a resistance value R, a resonance circuit in which an N-type MOS capacitance element 401 is connected in series, and an antenna (inductance for supplying power) to the resonance circuit. LR, current iR). This can be thought of as a simplified model representing the wireless chip and reader of the present invention.

In FIG. 4 (A), the mutual inductance between the two antennas M, the angular frequency omega, in the case where the capacitance value of the N-type MOS capacitor element 401 and the C _MOS the AC voltage induced across the capacitive element The amplitude V is given by Equation 1 as in FIG.

On the other hand, when an AC voltage is induced in the semiconductor device 400 shown in FIG. 4A, the behavior of the capacitance value C _MOS with respect to the voltage amplitude V is expressed as shown in FIG. The capacitance value C _MOS of the N-type MOS capacitance element 401 varies depending on whether the voltage amplitude V is larger than the absolute value (−Vthn) of the threshold voltage. When the voltage amplitude V does not exceed the absolute value of the threshold voltage (V <−Vth), the N-type MOS capacitor element 401 behaves as a normal capacitor element (capacitance value C1). When the voltage amplitude V exceeds the absolute value of the threshold voltage (V> −Vth), the capacitance value of the N-type MOS capacitor element 401 becomes a value between C1 and 0. As the voltage amplitude V increases, the period during which the inversion layer is formed becomes shorter and the capacitance value approaches zero.

From the above, the AC voltage amplitude V induced when the capacitance value C1 satisfies the resonance condition (ω ² LC1 = 1) is expressed as shown in FIG. In FIG. 4 (C), the solid line represents the relationship between the alternating voltage amplitude V and the capacitance value _{C MOS.} The dotted line represents the relationship between the AC voltage amplitude V and the capacitance value when the capacitance value is changed.

The solid line in FIG. 4C corresponds to the locus of voltage amplitude when the mutual inductance is changed. When the mutual inductance is small (dotted line (1)), the voltage amplitude V is smaller than the absolute value of the threshold voltage of the N-type MOS capacitor 401, and the capacitance value C _MOS matches the capacitance value C1 (point A). ). On the other hand, when the mutual inductance is increased by bringing the wireless chip closer to the reader (dotted line (2)), a voltage of the peak value (point C) of the dotted line (2) is generated if it is a normal capacitive element. However, since the voltage amplitude V at the point C is larger than the absolute value of the threshold voltage of the N-type MOS capacitance element 401, the capacitance value C _MOS decreases. As a result, the induced voltage is deviated from the resonance condition (point B).

FIG. 4D shows the relationship between the mutual inductance M and the voltage amplitude V. When the voltage amplitude V exceeds the absolute value of the threshold voltage of the N-type MOS capacitor 401, the capacitance value _CMOS changes and deviates from the resonance condition, so that the induced voltage is suppressed. As a result, the proportional relationship between the voltage amplitude V and the mutual inductance M is lost.

In the present invention, when an alternating voltage with a small amplitude is applied to the MOS capacitor, it is necessary to function as a normal capacitor, so that the threshold voltage of the N-type MOS capacitor is negative (Vth <0). ).

From the behavior of FIGS. 4C and 4D described above, the present invention realizes a wireless chip that can suppress generation of an excessive voltage in the chip, that is, has a limiter function. Further, the power supply voltage supplied to the logic circuit inside the wireless chip is generated based on the AC voltage generated in the capacitor element. Therefore, by setting the threshold voltage of the MOS capacitance element to an appropriate value, it is possible to suppress an excessive increase in the power supply voltage supplied to the internal logic circuit.

In this way, the present invention suppresses an excessive increase in the power supply voltage supplied to the internal logic circuit even when approaching the antenna, etc., by using the MOS capacitor element in which the threshold voltage is controlled. A highly reliable wireless chip is realized. In addition, since an extra circuit such as a limiter circuit or a constant voltage generation circuit is not added, a wireless chip with a small chip area can be realized.

Furthermore, since the resonance circuit of the present invention suppresses excessive voltage generation by shifting the resonance point, unlike the case where a limiter circuit or a constant voltage generation circuit is used, power absorption itself can be suppressed. As a result, power consumption can be reduced.

In the embodiment shown in FIG. 4, an N-type MOS capacitor element is used as the MOS capacitor element. However, in the present invention, a P-type MOS capacitor element can also be used. In that case, it is represented by a circuit diagram having a P-type MOS capacitor element 801 as shown in FIG. Also, if the absolute value (−Vthn) of the threshold voltage of the N-type MOS capacitor is read as the absolute value (Vthp) of the threshold voltage of the P-type MOS capacitor, FIGS. ), (D), and the description of the present embodiment are valid as they are. In particular, in the present invention, when a P-type MOS capacitor is used, the threshold voltage is positive (Vthp> 0).

(Embodiment 2)
In this embodiment mode, a wireless chip of the present invention will be described with reference to FIG. In FIG. 1A, an antenna 102 having an inductance L, a parasitic resistance ra, and a parasitic capacitance Ca, a resonant capacitor 103 having an N-type MOS capacitor 105, a resistance element having a resistance value RL, and a capacitance value CL are shown. A circuit in which capacitive elements are connected in parallel and an antenna (inductance LR, current iR) for supplying power to the circuit are shown. The resistive element having the resistance value RL and the capacitive element having the capacitance value CL represent the circuit portion 104 of the wireless chip, and can be considered as a simplified model representing the semiconductor device 100 and the reader 101 of the present invention. it can.

In FIG. 1A, the mutual inductance between two antennas is M, the angular frequency is ω, the parasitic capacitance value Ca of the antenna, the capacitance value of the N-type MOS capacitance element 105, and the capacitance value CL of the circuit portion is the capacitance value. In the case of Ctot, the amplitude V of the AC voltage induced at both ends of the capacitive element is given by Equation 2.

On the other hand, when an AC voltage is induced in the semiconductor device 100 shown in FIG. 1A, the behavior of the capacitance value Ctot with respect to the voltage amplitude V is expressed as shown in FIG. The capacitance value of the N-type MOS capacitor element 105 varies depending on whether the voltage amplitude V is larger than the absolute value (−Vthn) of the threshold voltage. When the voltage amplitude V does not exceed the absolute value of the threshold voltage (V <−Vthn), the N-type MOS capacitor 105 behaves as a normal capacitor (when V <−Vthn and Ctot is C1, N The capacitance value of the type MOS capacitor 105 is (C1-Ca-CL). When the voltage amplitude V exceeds the magnitude of the threshold voltage (V> −Vth), the capacitance value of the N-type MOS capacitor 105 becomes a value between (C1−Ca−CL) and 0. As the voltage amplitude V increases, the period during which the inversion layer is formed becomes shorter and the capacitance value approaches zero. As a result, Ctot approaches Ca + CL.

From the above, when the capacitance value C1 satisfies the resonance condition, the induced AC voltage amplitude V is expressed as shown in FIG. In FIG. 1C, the solid line represents the relationship between the AC voltage amplitude V and the capacitance value Ctot. The dotted line represents the relationship between the AC voltage amplitude V and the capacitance value when the capacitance value is changed.

A solid line in FIG. 1C corresponds to a locus of voltage amplitude when the mutual inductance is changed. When the mutual inductance is small (dotted line (1)), the voltage amplitude V is smaller than the absolute value of the threshold voltage of the N-type MOS capacitance element 105, and the capacitance value Ctot matches the capacitance value C1 (point A). . On the other hand, when the mutual inductance is increased by bringing the wireless chip closer to the reader (dotted line (2)), a voltage of the peak value (point C) of the dotted line (2) is generated if it is a normal capacitive element. However, since the voltage amplitude V at the point C is larger than the absolute value of the threshold voltage of the N-type MOS capacitor 105, the capacitance value Ctot decreases. As a result, the induced voltage is deviated from the resonance condition (point B).

FIG. 1D shows the relationship between the mutual inductance M and the voltage amplitude V. When the voltage amplitude V exceeds the absolute value of the threshold voltage of the N-type MOS capacitor element 105, the capacitance value Ctot changes and deviates from the resonance condition, so that the induced voltage is suppressed. As a result, the proportional relationship between the voltage amplitude V and the mutual inductance M is lost.

From the behavior of FIGS. 1C and 1D described above, the present invention realizes a wireless chip that can suppress generation of an excessive voltage in the chip, that is, has a limiter function. Further, the power supply voltage supplied to the logic circuit inside the wireless chip is generated based on the AC voltage generated in the capacitor element. Therefore, by setting the threshold voltage of the MOS capacitance element to an appropriate value, it is possible to suppress an excessive increase in the power supply voltage supplied to the internal logic circuit.

In this way, the present invention suppresses an excessive increase in the power supply voltage supplied to the internal logic circuit even when approaching the antenna, etc., by using the MOS capacitor element in which the threshold voltage is controlled. A highly reliable wireless chip is realized. In addition, since an extra circuit such as a limiter circuit or a constant voltage generation circuit is not added, a wireless chip with a small chip area can be realized.

Furthermore, since the resonance circuit of the present invention suppresses excessive voltage generation by shifting the resonance point, unlike the case where a limiter circuit or a constant voltage generation circuit is used, power absorption itself can be suppressed. As a result, power consumption can be reduced.

In the embodiment shown in FIG. 1, an N-type MOS capacitive element is used as the MOS capacitive element. However, in the present invention, a P-type MOS capacitive element can also be used. In that case, a circuit diagram including a semiconductor device 900 having an antenna 902, a resonance circuit 903, and a circuit portion 904 and a reader 901 as shown in FIG. The resonance circuit 903 has a P-type MOS capacitor element 905. Further, if the absolute value (−Vthn) of the threshold voltage of the N-type MOS capacitor element is read as the absolute value (Vthp) of the threshold voltage of the P-type MOS capacitor element, FIG. ), (D), and the description of the present embodiment are valid as they are.

(Embodiment 3)
FIG. 5 shows the structure of the semiconductor device of the present invention. The semiconductor device 501 of the present invention receives power supply from an electromagnetic wave emitted from the reader 509 and transmits / receives data to / from the reader wirelessly. Although not shown, the reader may be connected to a computer via a communication line, and may transmit / receive data to / from the semiconductor device under the control of the computer.

The semiconductor device 501 includes a resonance circuit 502 having a MOS capacitor, a power supply circuit 503, a clock generation circuit 504, a demodulation circuit 505, a control circuit 506, a memory unit 507, and an encoding and modulation circuit 508. In the resonance circuit, the MOS capacitor element and the antenna are electrically connected. The antenna may be either an antenna built in the semiconductor device 501 or an external antenna electrically connected to the MOS capacitor element via a connection terminal or the like.

When the resonance circuit 502 receives an electromagnetic wave emitted from the reader 509, an alternating voltage is induced. The AC voltage includes data transmitted from the reader, and also serves as a power source and a clock signal for the semiconductor device 501.

The power supply circuit 503 rectifies the AC voltage generated in the resonance circuit 502 with a rectifying element, and supplies a stabilized power supply using a capacitive element to each circuit. The clock generation circuit 504 generates a clock signal having a predetermined frequency based on the AC voltage generated in the resonance circuit 502. The demodulation circuit 505 demodulates data from the AC voltage generated in the resonance circuit 502. The control circuit 506 controls the memory unit 507 and performs reading from the memory and writing to the memory according to the demodulated data. The memory unit 507 is configured by a nonvolatile EEPROM, FeRAM, volatile SRAM, or the like, but preferably has at least a nonvolatile memory. The nonvolatile memory holds data unique to the semiconductor device 501 and the like. An encoding and modulation circuit 508 converts data to be transmitted into an encoded signal and modulates a carrier wave.

Note that the semiconductor device 501 may have a built-in antenna or may have a terminal for connecting the antenna. The semiconductor device 501 is not limited to the above configuration, and may include an information determination circuit, a central processing unit (CPU), a congestion control circuit, and the like. Although a passive configuration without a battery has been described, an active configuration with a battery may be used.

The power supply circuit 503 generates a power supply VDD and supplies it to each circuit. The wireless chip has a range Vmin to Vmax of the power supply voltage VDD in which reliable operation is guaranteed. The values of the minimum operating power supply voltage Vmin and the maximum operating power supply voltage Vmax depend on the technology of the integrated circuit, but in the case of an integrated circuit formed on single crystal silicon, Vmin is about 0.2 to 1 V, and Vmax is 1 to It is about 5V. In the case of an integrated circuit formed on a glass substrate or a flexible substrate, Vmin is about 1 to 4 V, and Vmax is about 3 to 12 V.

Corresponding to such a range of power supply voltage, the present invention uses a MOS capacitance element having a predetermined threshold voltage, so that the internal voltage is excessively high without providing a limiter circuit or a constant voltage generation circuit. A wireless chip capable of suppressing the above is realized. The predetermined threshold is effective when it is in the range of −24 V or more and −0.1 or less for the N-type MOS capacitor element and 0.1 to 24 V or less for the P-type MOS capacitor element. In particular, when a MOS capacitor is formed on a glass substrate or a flexible substrate having an integrated circuit with a gate length of 2 μm or less, −2 to −15 V (N-type MOS capacitor) and 2 to 15 V (P Type MOS capacitor).

Examples of power supply circuits included in the wireless chip of the present invention will be described with reference to FIGS.

FIG. 6A illustrates a configuration example of a half-wave rectification power supply circuit. The power supply circuit includes two input terminals connected to both ends of the antenna or via a capacitive element, two output terminals that output GND and VDD, two diodes 601 and 602, and a capacitive element 603. One terminal of the two inputs and one terminal of the two outputs are directly connected and are at the ground voltage GND. In the power supply circuit of this configuration, when the input AC signal is as shown in FIG. 6B, the output is as shown in FIG. 6C, which is lower than the power supply voltage VDD (2 × V−2 × Vthd). . Vthd represents the threshold voltage of the diode.

FIG. 7A illustrates a configuration example of a full-wave rectification power supply circuit. The power supply circuit includes two input terminals connected to both ends of the antenna or via a capacitive element, two output terminals for outputting GND and VDD, four diodes 611, 612, 613, and 614, and a capacitive element 615. And have. In the power supply circuit of this configuration, when the input AC signal is as shown in FIG. 7B, the output is as shown in FIG. 7C, and the power supply voltage VDD is about (V−2 × Vthd). Vthd represents the threshold voltage of the diode.

The wireless chip has a power supply voltage interval Vmin to Vmax in which reliable operation is guaranteed. When the resonance circuit of the present invention is used, the AC voltage amplitude V has a suppressing action when it becomes equal to or larger than the absolute value Vth of the threshold voltage of the MOS capacitor, so that the voltages Vmin to Vmax and the threshold voltage The absolute value Vth preferably has the following relationship.

First, in order to perform highly reliable operation without damaging the circuit portion, it is necessary to suppress the generated power supply voltage to Vmax or less. Therefore, it is preferable that 2 × Vth−2 × Vthd <Vmax in the power supply circuit shown in FIG. 6 and Vth−2 × Vthd <Vmax in the power supply circuit shown in FIG.

In addition, if the generated voltage is suppressed by the MOS capacitor and becomes equal to or lower than the operation guarantee voltage, there is a case where the wireless chip does not operate even if it is brought close to the reader. In order to avoid such a situation, it is preferable that Vmin <2 × Vth−2 × Vthd in the power supply circuit shown in FIG. 6 and Vmin <Vth−2 × Vthd in the power supply circuit shown in FIG.

In other words, MOS capacitors each having Vth satisfying Equation 3 for a wireless chip having a half-wave rectification type power supply circuit and Vth satisfying Equation 4 for a wireless chip having a full-wave rectification type power supply circuit, respectively. It can be said that it is preferable to use an element. Vth represents the absolute value of the threshold value of the MOS capacitor.

In other words, when the relationship of VDD = c × V is established between the amplitude V of the AC voltage and the power supply voltage VDD, it can be said that it is preferable to use a MOS capacitor element having Vth that satisfies Equation 5. Since the coefficient c is typically in a range of ¼ to 1, it is preferable to use a MOS capacitor having Vth that satisfies Equation 6.

Depending on the technology of the integrated circuit, in the case of an integrated circuit formed on single crystal silicon, Vmin is about 0.2 to 1V and Vmax is about 1 to 5V. In the case of an integrated circuit formed on a glass substrate, Vmin is about 1 to 4V, and Vmax is about 3 to 12V. Therefore, the threshold voltage of the MOS capacitor element according to the present invention is -24V to -0.1 (N-type MOS capacitor element) and 0.1 to 24V (P-type MOS capacitor element). preferable. In particular, when formed on a single crystal silicon substrate, it is preferably −24 V or more and −0.1 or less (N-type MOS capacitor element) and 0.1 or more and 10 V or less (P-type MOS capacitor element). When formed on a glass substrate or a flexible substrate, −0.5 to −24 V (N-type MOS capacitor) and 0.5 to 24 V (P-type MOS capacitor) It is preferable that In particular, when a MOS capacitor is formed on a glass substrate or a flexible substrate having an integrated circuit with a gate length of 2 μm or less, −2 to −15 V (N-type MOS capacitor) and 2 to 15 V (P Type MOS capacitor).

Another configuration example of the present invention will be described with reference to FIG. The example shown in FIG. 10A is an example in which a resonance circuit is configured using a normal capacitor element 1005 and an N-type MOS capacitor element 1006 (threshold voltage Vthn <0), and the circuit shown in FIG. And the configuration of the capacitive element is different. FIG. 10A illustrates a semiconductor device 1000 including an antenna 1002, a resonance circuit 1003, and a circuit portion 1004, and a reader 1001. The total of the parasitic capacitance value Ca of the antenna, the capacitance value of the normal capacitance element 1005, the capacitance value of the N-type MOS capacitance element 1006, and the capacitance value CL of the circuit portion is represented as Ctot.

When the two types of capacitive elements 1005 and 1006 shown in FIG. 10A are used, the relationship between the capacitance value Ctot and the AC voltage amplitude V is expressed as shown in FIG. The capacitance value Ctot is a capacitance value C0 having a constant value represented by the sum of the parasitic capacitance value Ca of the antenna, the capacitance value of the normal capacitance element 1005, and the capacitance value CL of the circuit portion, and the capacitance of the N-type MOS capacitance element 1006. It can be divided into values (C1-C0). Here, C1 is the capacitance value of Ctot when the voltage amplitude V does not exceed the absolute value of the threshold voltage of the N-type MOS capacitor element 1006 (V <−Vthn). When compared with FIG. 1A, it is understood that the qualitative behavior is the same as that in FIG. 1B because only the component of C0 is different.

As shown in FIG. 10B, the capacitance value Ctot varies depending on whether or not the voltage amplitude V is larger than the absolute value (−Vthn) of the threshold voltage of the N-type MOS capacitor element 1006. When the voltage amplitude V does not exceed the absolute value of the threshold voltage of the N-type MOS capacitor element 1006 (V <−Vthn), the N-type MOS capacitor element 1006 behaves as a normal capacitor element (capacitance value (C1-C0)). ). When the voltage amplitude V exceeds the absolute value of the threshold voltage (V> −Vthn), the capacitance value of the N-type MOS capacitor element 1006 becomes a value between (C1−C0) and 0. As the voltage amplitude V increases, the period during which the inversion layer is formed becomes shorter and the capacitance value approaches zero. As a result, Ctot approaches C0.

10B, when the capacitance value C1 satisfies the resonance condition of the semiconductor device 1000 illustrated in FIG. 10A, the resonance condition is satisfied when the induced voltage amplitude V is small. It can be seen that when the amplitude V increases and exceeds the absolute value of the threshold voltage of the MOS capacitance element, the capacitance value changes and deviates from the resonance condition. As a result, the induced voltage amplitude is suppressed.

As described above, the semiconductor device 1000 illustrated in FIG. 10A realizes a wireless chip that can suppress generation of an excessive voltage in the chip, that is, has a limiter function. Further, the power supply voltage supplied to the logic circuit inside the wireless chip is generated based on the AC voltage generated in the capacitor element. Therefore, by setting the threshold voltage of the MOS capacitance element to an appropriate value, it is possible to suppress an excessive increase in the power supply voltage supplied to the internal logic circuit.

In this way, the present invention suppresses an excessive increase in the power supply voltage supplied to the internal logic circuit even when approaching the antenna, etc., by using the MOS capacitor element in which the threshold voltage is controlled. A highly reliable wireless chip is realized. In addition, since an extra circuit such as a limiter circuit or a constant voltage generation circuit is not added, a wireless chip with a small chip area can be realized.

In this embodiment, an N-type MOS capacitor is used as the MOS capacitor. However, in the present invention, a P-type MOS capacitor can also be used. In this case, if -Vthn in FIG. 10B is read as Vthp, the graph in FIG. 10B also holds for a P-type MOS capacitor.

In this embodiment, an example in which an N-type MOS capacitor and a normal capacitor are connected in parallel as the capacitor is shown. Of course, a plurality of N-type MOS capacitors and a plurality of ordinary capacitors may be connected in parallel.

Another configuration example of the present invention will be described with reference to FIG. The example shown in FIG. 11A is an example in which a resonance circuit is configured by using two N-type MOS capacitor elements 1105 and 1106 having different threshold voltages. The circuit shown in FIG. The configuration is different. FIG. 11A illustrates a semiconductor device 1100 including an antenna 1102, a resonance circuit 1103, and a circuit portion 1104, and a reader 1101. N-type MOS capacitor element 1105 has threshold voltage Vthn1, N-type MOS capacitor element 1106 has threshold voltage Vthn2, and Vthn2 <Vthn1 <0 holds. The total of the parasitic capacitance value Ca of the antenna, the capacitance values of the N-type MOS capacitance elements 1105 and 1106, and the capacitance value CL of the circuit portion is represented as Ctot.

When two N-type MOS capacitor elements 1105 and 1106 having different threshold voltages shown in FIG. 11A are used, the relationship between the capacitance value Ctot and the AC voltage amplitude V is expressed as shown in FIG. The The capacitance value Ctot is a capacitance value C0 having a constant value represented by the sum of the parasitic capacitance value Ca of the antenna and the capacitance value CL of the circuit portion, the capacitance value (C1-C2) of the N-type MOS capacitance element 1105, N It can be divided into the capacitance value (C2-C0) of the type MOS capacitor element 1106. Here, C1 is the capacitance value C0 when the voltage amplitude V does not exceed the absolute value of the threshold voltage of the N-type MOS capacitor element 1105 (V <−Vthn1), the capacitance value of the N-type MOS capacitor element 1105, the N-type MOS transistor The total capacitance value of the capacitance element 1106, that is, the capacitance value of Ctot, and C2 is the capacitance value when the voltage amplitude V does not exceed the absolute value of the threshold voltage of the N-type MOS capacitance element 1106 (V <−Vthn2). This is the sum of the capacitance values of C0 and the N-type MOS capacitor element 1106.

The capacitance value of the N-type MOS capacitor element 1105 varies depending on whether or not the voltage amplitude V is larger than the absolute value (−Vthn1) of the threshold voltage. When the voltage amplitude V does not exceed the magnitude of the threshold voltage (V <−Vthn1), the N-type MOS capacitor element 1105 behaves as a normal capacitor element (capacitance value (C1-C2)). When the voltage amplitude V exceeds the magnitude of the threshold voltage (V> −Vthn1), the capacitance value of the N-type MOS capacitor element 1105 becomes a value between (C1−C2) and 0. As the voltage amplitude V increases, the period during which the inversion layer is formed becomes shorter and the capacitance value approaches zero. As a result, Ctot approaches C2.

Similarly, the capacitance value of the N-type MOS capacitor element 1106 varies depending on whether the voltage amplitude V is larger than the absolute value (−Vthn2) of the threshold voltage. When the voltage amplitude V does not exceed the threshold voltage (V <−Vthn2), the N-type MOS capacitor element 1106 behaves as a normal capacitor element (capacitance value (C2−C0)). When the voltage amplitude V exceeds the magnitude of the threshold voltage (V> −Vthn2), the capacitance value of the N-type MOS capacitor element 1106 becomes a value between (C2−C0) and 0. As the voltage amplitude V increases, the period during which the inversion layer is formed becomes shorter and the capacitance value approaches zero. As a result, Ctot approaches C0.

From the above, it is understood that the relationship between the capacitance value Ctot and the AC voltage amplitude V is as shown in FIG.

From the behavior of FIG. 11B, when the capacitance value C1 satisfies the resonance condition of the semiconductor device 1100 shown in FIG. 11A, the resonance condition is satisfied when the induced voltage amplitude V is small. It can be seen that when the amplitude V increases and exceeds the absolute value of the threshold voltage of the N-type MOS capacitor element 1105, the capacitance value changes and deviates from the resonance condition. When the voltage amplitude V further increases and exceeds the absolute value of the threshold voltage of the N-type MOS capacitor element 1106, the capacitance value further changes and moves away from the resonance condition. As a result, the induced voltage amplitude is suppressed.

As described above, the semiconductor device 1100 illustrated in FIG. 11A realizes a wireless chip that can suppress generation of excessive voltage in the chip, that is, has a limiter function. Further, the power supply voltage supplied to the logic circuit inside the wireless chip is generated based on the AC voltage generated in the capacitor element. Therefore, by setting the threshold voltage of the MOS capacitance element to an appropriate value, it is possible to suppress an excessive increase in the power supply voltage supplied to the internal logic circuit.

In this embodiment, an N-type MOS capacitor is used as the MOS capacitor. However, in the present invention, a P-type MOS capacitor can also be used. In this case, if −Vthn1 and −Vthn2 in FIG. 11B are read as Vthp1 and Vthp2, the graph in FIG. 11B also holds for the P-type MOS capacitor.

In the present invention, both an N-type MOS capacitor element and a P-type MOS capacitor element can be used. Further, a plurality of N-type MOS capacitor elements, a plurality of P-type MOS capacitor elements, or a plurality of normal capacitor elements may be connected in parallel.

A layout example of the MOS capacitor of the present invention will be described. FIG. 12 shows a layout example of the MOS capacitor element used in the present invention.

In FIG. 12, a region 1201 represents a semiconductor region, and a region 1202 represents a gate electrode. Regions 1203 and 1204 are wiring regions, which are connected to the semiconductor region and the gate electrode, respectively. The region 1205 is a region to which an impurity element is added. An N-type impurity element is added to the N-type MOS capacitor element, and a P-type impurity element is added to the P-type MOS capacitor element.

By using the MOS capacitor element having such a layout, the semiconductor device of the present invention can be realized.

A method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. More specifically, a method for manufacturing a semiconductor device including N-type and P-type thin film transistors, an N-type MOS capacitor, and a conductive layer functioning as an antenna will be described with reference to drawings. Note that a thin film transistor is an element included in each circuit included in a semiconductor device such as a power supply circuit.

A separation layer 702 is formed over one surface of a substrate 701 (also referred to as a base) (see FIG. 13A). The substrate 701 has an insulating surface. In the case where the substrate 701 is made of plastic, it is necessary to use heat-resistant plastic that can withstand the processing temperature of the manufacturing process. As will be described later, preferably, after a thin film transistor is provided over a substrate 701 made of glass, the thin film transistor may be peeled off and provided over a plastic substrate.

Note that in this step, the separation layer 702 is provided over the entire surface of the substrate 701. However, if necessary, a separation layer is provided over the entire surface of the substrate 701, and then processed by photolithography, etching, or the like, that is, patterning. Then, it may be selectively provided. In addition, although the separation layer 702 is formed so as to be in contact with the substrate 701, an insulating layer serving as a base is formed so as to be in contact with the substrate 701 as necessary, and the separation layer 702 is formed so as to be in contact with the insulation layer. May be.

The separation layer 702 is formed by sputtering, plasma CVD, or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium. An element selected from (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), silicon (Si), etc. A layer made of an alloy material or a compound material is formed as a single layer or a stacked layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

Next, an insulating layer 703 serving as a base is formed so as to cover the separation layer 702. The insulating layer 703 is formed as a single layer or a stacked layer including a silicon oxide or a silicon nitride by a sputtering method, a plasma CVD method, or the like. The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxide containing nitrogen, and the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon nitride containing oxygen, and the like. The insulating layer serving as a base functions as a blocking film that prevents impurities from entering from the substrate 701.

Next, an amorphous semiconductor layer 704 is formed over the insulating layer 703. The amorphous semiconductor layer 704 is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. Subsequently, the amorphous semiconductor layer 704 is subjected to laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, and metal elements that promote crystallization. A crystalline semiconductor layer is formed by crystallization by a method combining a thermal crystallization method and a laser crystallization method. After that, the obtained crystalline semiconductor layer is patterned into a desired shape to form crystalline semiconductor layers 706 to 708 (see FIG. 13B).

An example of a manufacturing process of the crystalline semiconductor layers 706 to 708 will be described below. First, an amorphous semiconductor layer is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. Thereafter, laser light is irradiated as necessary, and crystalline semiconductor layers 706 to 708 are formed by a patterning process using a photolithography method, an etching method, or the like. In the case of forming a crystalline semiconductor layer by a laser crystallization method, a gas laser or a solid laser is used. The gas laser and solid-state laser may be either continuous wave or pulsed.

Note that when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, crystallization can be performed in a short time at a low temperature and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method in which argon can be contained at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

Next, a gate insulating layer 705 is formed to cover the crystalline semiconductor layers 706 to 708. The gate insulating layer 705 is formed by a single layer or a stack of layers containing silicon oxide or silicon nitride by a plasma CVD method, a sputtering method, or the like.

In particular, a high-quality gate insulating film can be formed by using high-density plasma treatment. The high-density plasma treatment means that the plasma density is 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ to 9 × 10 ¹⁵ cm ⁻³ , such as a microwave (for example, a frequency of 2.45 GHz). This is plasma processing using high frequency. When plasma is generated under such conditions, the low electron temperature is changed from 0.2 eV to 2 eV. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects. In the case where a formation object and a gate insulating film are to be formed, a substrate on which a patterned semiconductor film is formed is placed in a film formation chamber capable of such plasma treatment. Then, a film forming process is performed with a distance between an electrode for plasma generation, a so-called antenna, and an object to be formed being 20 mm to 80 mm, preferably 20 mm to 60 mm. Such a high-density plasma treatment can realize a low-temperature process (substrate temperature of 400 ° C. or lower). Therefore, a film can be formed over a plastic substrate which has lower heat resistance than a glass substrate or a single crystal silicon substrate.

Such an insulating film can be formed in a nitrogen atmosphere or an oxygen atmosphere. The nitrogen atmosphere is typically a mixed atmosphere of nitrogen and a rare gas, or a mixed atmosphere of nitrogen, hydrogen, and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used. The oxygen atmosphere is typically a mixed atmosphere of oxygen and a rare gas, a mixed atmosphere of oxygen, hydrogen, and a rare gas, or a mixed atmosphere of dinitrogen monoxide and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used.

The insulating film formed in this way has little damage to other films and becomes dense. In addition, an insulating film formed by high-density plasma treatment can improve an interface state in contact with the insulating film. For example, when the gate insulating film is formed using high-density plasma treatment, the interface state with the semiconductor film can be improved. As a result, the leakage current of the gate insulating film is reduced, and the electrical characteristics of the thin film transistor can be improved. In addition, since the gate insulating film can be made thinner, it is possible to suppress the short channel effect, to suppress threshold value variation, to improve the driving current of the thin film transistor, and the like. Further, the thin film transistor can be miniaturized as the gate insulating film becomes thinner.

Further, in the MOS capacitor element of the present invention, the leakage current of the MOS capacitor element is reduced by using the gate insulating film formed by the high-density plasma treatment as described above. In addition, the gate insulating film can be thinned, and the area of the MOS capacitor element can be reduced or the capacitance value can be increased.

Note that although the case of using high-density plasma treatment for manufacturing the gate insulating film has been described, the present invention is not limited to the gate insulating film or the like, and may be used for manufacturing other insulating films such as an interlayer insulating film. Further, the semiconductor film may be subjected to high density plasma treatment. The semiconductor film surface can be modified by high-density plasma treatment. As a result, the interface state can be improved, and the electrical characteristics of the thin film transistor can be improved.

Next, a resist mask is formed by photolithography, and an impurity element imparting N-type conductivity is added to the crystalline semiconductor layer 708 by ion doping or ion implantation, so that an impurity region 709 is formed. . The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As).

The crystalline semiconductor layer 708 will later become a semiconductor layer of an N-type MOS capacitor element. Therefore, the threshold voltage of the N-type MOS capacitor can be controlled by the concentration of the impurity element added to the crystalline semiconductor layer 708. In the present invention, the dose may be adjusted so that the impurity element is contained at a concentration of 1 × 10 ¹⁷ atoms / cm ^{3 to} 1 × 10 ²⁰ atoms / cm ³ . By setting to such a range, the threshold voltage can be set to an appropriate value, and the semiconductor device of the present invention that can suppress the occurrence of an excessive power supply voltage can be realized. In the following, in accordance with the name of the thin film transistor, the first electrode of the N-type MOS capacitor is called a gate electrode, and the region where the inversion layer is formed is called a channel formation region.

Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer 705 (see FIG. 13C). The first conductive layer is formed with a thickness of 20 to 100 nm by a plasma CVD method, a sputtering method, or the like. The second conductive layer is also formed with a thickness of 100 nm to 400 nm by a plasma CVD method, a sputtering method, or the like. The first conductive layer and the second conductive layer are made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), etc. A selected element or an alloy material or a compound material containing these elements as a main component is formed. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. As examples of the combination of the first conductive layer and the second conductive layer, a layer made of tantalum nitride and a layer made of tungsten, a layer made of tungsten nitride and a layer made of tungsten, a layer made of molybdenum nitride and a layer made of molybdenum Layer and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a layer made of molybdenum, a layer made of aluminum, and a layer made of molybdenum may be adopted.

Next, a resist mask is formed by photolithography, and etching treatment for forming gate electrodes and gate lines is performed, so that conductive layers 716 to 721 functioning as gate electrodes are formed.

Next, a resist mask is formed by photolithography, and an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 706 and 708 by ion doping or ion implantation at a low concentration. Regions 711 and 713 and channel formation regions 780 and 782 are formed. The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As).

Next, a resist mask is formed by photolithography, and an impurity element imparting p-type conductivity is added to the crystalline semiconductor layer 707 to form an impurity region 712 and a channel formation region 781. For example, boron (B) is used as the impurity element imparting P-type.

Next, an insulating layer is formed so as to cover the gate insulating layer 705 and the conductive layers 716 to 721. The insulating layer is formed by a single layer or a stack of layers including an inorganic material such as silicon, silicon oxide, or silicon nitride, or an organic material such as an organic resin, by plasma CVD or sputtering. To do. Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction to form insulating layers (also referred to as sidewalls) 739 to 741 in contact with the side surfaces of the conductive layers 716 to 721 (see FIG. 14 (A)). At the same time as the formation of the insulating layers 739 to 741, the gate insulating layer 705 is etched to form insulating layers 734 to 736. The insulating layers 739 to 741 are used as a mask for doping when an LDD (Lightly Doped Drain) region is formed later.

Next, a resist mask is formed by photolithography, and an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 706 and 708 using the resist mask and the insulating layers 739 to 741 as a mask. First impurity regions (also referred to as LDD regions) 727 and 729 and second impurity regions 726 and 728 are formed. The concentration of the impurity element in the first impurity regions 727 and 729 is lower than the concentration of the impurity element in the second impurity regions 726 and 728. Through the above steps, an N-type thin film transistor 744, a P-type thin film transistor 745, and an N-type MOS capacitor element 746 are completed.

In this embodiment, the case where an N-type MOS capacitor is manufactured is shown. In the case of manufacturing a P-type MOS capacitor element, P-type impurity elements having different polarities may be used as impurity elements for the MOS capacitor element. Specifically, in the step of forming the impurity region 709 after the gate insulating layer 705 is formed, an impurity element imparting p-type conductivity is added to the crystalline semiconductor layer 708. The dose may be adjusted so that the impurity element is contained at a concentration of 1 × 10 ¹⁷ atoms / cm ^{3 to} 1 × 10 ²⁰ atoms / cm ³ . In addition, the impurity region 713 and the channel formation region 782 may be formed by adding an impurity element imparting P-type at the same time as the formation of the impurity region 712 and the channel formation region 781. Further, when the first impurity region 727 and the second impurity region 726 are formed, the crystalline semiconductor layer 708 is covered with a resist mask, and the impurity regions 728 and 729 are not formed. FIG. 18 shows a drawing corresponding to FIG. 14A when the P-type MOS capacitor is formed in this way.

After the N-type thin film transistor 744, the P-type thin film transistor 745, and the N-type MOS capacitor element 746 are completed, an insulating layer is formed as a single layer or a stacked layer so as to cover them (see FIG. 14B). The insulating layer covering the thin film transistors 744 to 745 and the N-type MOS capacitor element 746 is formed of an inorganic material such as silicon oxide or silicon nitride, polyimide, polyamide, benzocyclobutene, by an SOG method or a droplet discharge method. A single layer or a stacked layer is formed using an organic material such as acrylic, epoxy, or siloxane. Siloxane corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Further, a fluoro group may be used as a substituent. Further, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

For example, when the insulating layer covering the thin film transistors 744 and 745 and the N-type MOS capacitor element 746 has a three-layer structure, a layer containing silicon oxide is formed as the first insulating layer 749 and the second insulating layer 750 is formed. A layer including a resin may be formed, and a layer including silicon nitride may be formed as the third insulating layer 751.

Note that before the insulating layers 749 to 751 are formed or after one or more of the insulating layers 749 to 751 are formed, the crystallinity of the semiconductor layer is restored and the impurity element added to the semiconductor layer is activated. Heat treatment for the purpose of hydrogenating the semiconductor layer is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

Next, the insulating layers 749 to 751 are etched by photolithography or etching to form openings that expose the second impurity regions 726 and 728 and the impurity region 712. Subsequently, a conductive layer is formed, and the conductive layer is patterned to form conductive layers 752 to 758 that function as wirings.

The conductive layers 752 to 758 are formed using an element selected from titanium (Ti), aluminum (Al), neodymium (Nd), or the like, or an alloy material or compound containing these elements as a main component by plasma CVD, sputtering, or the like. The material is a single layer or a laminate. The alloy material containing aluminum as a main component is, for example, a material containing aluminum as a main component and containing nickel, a material containing aluminum as a main component and containing silicon, and one type selected from nickel, carbon and silicon. Or it corresponds to the material containing multiple types. For example, the conductive layers 752 to 758 may have a stacked structure of a barrier layer, an aluminum layer containing silicon, and a barrier layer, or a stacked structure of a barrier layer, an aluminum layer containing silicon, a titanium nitride layer, and a barrier layer. Note that silicon contained in aluminum silicon is 0.1 wt% to 5 wt%. The barrier layer corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum containing aluminum or silicon is suitable as a material for forming the conductive layers 752 to 758 because it has low resistance and is inexpensive. In addition, when the upper and lower barrier layers are provided, generation of hillocks of aluminum containing aluminum or silicon can be prevented. Further, when a barrier layer made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the crystalline semiconductor layer and the barrier are reduced in order to reduce the natural oxide film. Occurrence of poor connection of layers can be suppressed.

Next, an insulating layer 762 is formed so as to cover the conductive layers 752 to 758 (see FIG. 15A). The insulating layer 762 is formed as a single layer or a stacked layer using an inorganic material or an organic material by an SOG method, a droplet discharge method, or the like. The insulating layer 762 is preferably formed with a thickness of 0.75 μm to 3 μm.

Subsequently, the insulating layer 762 is etched by photolithography to form an opening through which the conductive layer 758 is exposed. Subsequently, a conductive layer is formed so as to fill the opening. The conductive layer is formed using a conductive material by a plasma CVD method, a sputtering method, or the like. Next, the conductive layer is patterned to form a conductive layer 765. The conductive layer 765 is preferably formed with a single layer or a stacked layer using titanium or an alloy material or a compound material containing titanium as a main component. In the photolithography process for forming the conductive layer 765, wet etching is preferably performed in order to prevent damage to the thin film transistors 744 and 745 and the N-type MOS capacitor 746 in the lower layer. Hydrogen fluoride or ammonia perhydration may be used.

Next, an insulating layer 766 is formed so as to cover the conductive layer 765. The insulating layer 766 is formed as a single layer or a stacked layer using an inorganic material or an organic material by an SOG method, a droplet discharge method, or the like. The insulating layer 766 is preferably formed with a thickness of 0.75 μm to 3 μm. Subsequently, the insulating layer 766 is etched to form an opening 769 that exposes the conductive layer 765.

Next, a conductive layer 777 which is in contact with the conductive layer 765 and functions as an antenna is formed (see FIG. 15B). The conductive layer 777 is formed using a conductive material by a plasma CVD method, a sputtering method, a printing method, a droplet discharge method, or the like. Preferably, the conductive layer 777 is an element selected from aluminum (Al), titanium (Ti), silver (Ag), and copper (Cu), or an alloy material or a compound material containing these elements as a main component. It is formed by layer or lamination. Specifically, the conductive layer 777 is formed using a paste containing silver by a screen printing method, and then heat-treated at 50 to 350 ° C. Alternatively, an aluminum layer is formed by a sputtering method, and the aluminum layer is formed by patterning. For the pattern processing of the aluminum layer, wet etching processing is preferably used, and after the wet etching processing, heat treatment at 200 to 300 ° C. is preferably performed.

Next, an insulating layer 772 functioning as a protective layer is formed by an SOG method, a droplet discharge method, or the like so as to cover the conductive layer 777 functioning as an antenna. The insulating layer 772 is formed using a layer containing carbon such as DLC (diamond-like carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, or an organic material (preferably an epoxy resin).

Next, the insulating layers 703, 749, 750, and 751 are etched so that the peeling layer 702 is exposed to form openings 773 and 774 (see FIG. 16A).

Next, an etchant is introduced into the openings 773 and 774 to remove the separation layer 702 (see FIG. 16B). As the etchant, a gas or a liquid containing halogen fluoride is used. For example, there are chlorine trifluoride (ClF ₃ ), nitrogen trifluoride (NF ₃ ), bromine trifluoride (BrF ₃ ), and hydrogen fluoride (HF). Note that in the case where hydrogen fluoride is used as the etching agent, a layer made of silicon oxide is used as the peeling layer 702. Through the above steps, the thin film integrated circuit 791 including the thin film transistors 744 and 745, the N-type MOS capacitor 746, and the conductive layer 777 functioning as an antenna is peeled from the substrate 701.

The substrate 701 from which the thin film integrated circuit 791 is peeled is preferably reused for cost reduction. The insulating layer 772 is provided so that the thin film integrated circuit 791 is not scattered after the separation layer 702 is removed. Since the thin film integrated circuit 791 is small and thin, the thin film integrated circuit 791 is likely to be scattered after being removed from the substrate 701 after the peeling layer 702 is removed. However, by forming the insulating layer 772 over the thin film integrated circuit 791, the thin film integrated circuit 791 is weighted and scattering from the substrate 701 can be prevented. In addition, although the thin film integrated circuit 791 is thin and light, the insulating layer 772 is formed, so that a certain shape of strength can be secured without forming a wound shape.

Next, one surface of the thin film integrated circuit 791 is bonded to the first substrate 776 and completely peeled from the substrate 701 (see FIG. 17). Subsequently, the other surface of the thin film integrated circuit 791 is bonded to the second substrate 775, and then one or both of heat treatment and pressure treatment are performed, so that the thin film integrated circuit 791 is bonded to the first substrate 776 and the first substrate 776. The second substrate 775 is sealed. The first substrate 776 and the second substrate 775 are a film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, a paper made of a fibrous material, a base film (polyester, polyamide, inorganic vapor deposition film, Paper) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film and the object to be processed are bonded together by thermocompression bonding. When performing the heat treatment and the pressure treatment, the adhesive layer provided on the outermost surface of the film or the layer (not the adhesive layer) provided on the outermost layer is melted by the heat treatment and adhered by the pressure. Further, an adhesive layer may be provided on the surfaces of the first substrate 776 and the second substrate 775, or the adhesive layer may not be provided. Adhesive layer is thermosetting resin, UV curable resin, vinyl acetate resin adhesive, vinyl copolymer resin adhesive, epoxy resin adhesive, urethane resin adhesive, rubber adhesive, acrylic resin adhesive, etc. This corresponds to a layer containing an adhesive.

In the case where the first substrate 776 and the second substrate 775 are made of plastic, the first substrate 776 and the second substrate 775 are thin, lightweight, and can be bent. Moreover, it is excellent in impact resistance, and can be easily affixed or embedded in various articles, and can be used in various fields.

  In this embodiment, a layout example of a circuit included in a wireless chip is described.

As described in Embodiment 5, the semiconductor layer is formed over a substrate having an insulating surface with a base film or the like interposed therebetween. Then, the pattern formed on the photomask is transferred to a resist or the like formed on the semiconductor layer by a photolithography technique to form a pattern. By etching the semiconductor layer using the mask pattern, an island-shaped semiconductor region having a specific shape including a source region, a drain region, and a channel formation region of the thin film transistor can be formed.

In many cases, a pattern on a photomask for forming a semiconductor region has a square shape. In the present invention, a square corner portion (convex portion) is rounded off. Specifically, a right triangle with a side of 10 μm or less is removed and rounded, or a part of a right triangle with a side of 10 μm or less is removed to remove a region containing a polygon or a curve. Shape.

The pattern on the photomask for forming the semiconductor region is not only square, but also when the opening region is secured wider than the channel width, or a thin film transistor having a different channel width is formed in one semiconductor region. In general, it takes various shapes and has a corner portion composed of an outer side (convex portion) and an inner side (concave portion). In the present invention, square corners (projections and recesses) are formed by rounding.

Specifically, when the corner portion is a concave portion, a polygon or a curve is formed by adding a right triangle with a side of 10 μm or less to be chamfered, or a part of a right triangle with a side of 10 μm or less. Add a region to include a rounded shape.

FIG. 19 shows a semiconductor region formed by transferring this mask pattern. In FIG. 19, dotted lines represent gate electrodes and wirings to be formed later. Note that the corner of the semiconductor region formed by transferring the mask pattern may be formed to be more rounded than the corner of the photomask pattern. That is, the corner of the semiconductor region may be provided with a rounder shape that is smoother than the corner of the photomask pattern.

Next, a gate insulating film is formed after forming the semiconductor region. Then, a gate electrode and a gate wiring overlapping with a part of the semiconductor region are formed at the same time. For the gate electrode or gate wiring, a metal layer or a semiconductor layer is formed, a pattern formed on the photomask is transferred to a resist or the like by a photolithography technique, and the metal layer or the semiconductor layer is etched using the mask pattern. It can be formed by processing.

The pattern on the photomask for forming the gate electrode or the gate wiring is a corner formed by a convex portion (outer side) or a concave portion (inner side), or a convex portion (outer side) or a concave portion (inner side). Side). The bent portion refers to a portion formed by bending a pattern. In the present invention, the corner portion or the bent portion is formed by rounding off.

Specifically, when the corner or the bent portion is a convex portion, one side is 10 μm or less, or a shape that is rounded by removing a right triangle having a size that is 1/2 to 1/5 of the line width, or one side Is a part of a right-angled triangle region of 10 μm or less or 1/2 to 1/5 of the line width, and a region including a polygon or a curve is removed to obtain a rounded shape.

In addition, when the corner portion or the bent portion is formed of a concave portion, one side is 10 μm or less or a shape that is chamfered by adding a right triangle of 1/2 to 1/5 of the line width, or one side is 10 μm or less or the line width A part of a 1/2 to 1/5 right triangle area is added to an area including a polygon or a curve to form a rounded shape.

FIG. 20 shows a gate electrode and a gate wiring formed by transferring this mask pattern. In FIG. 20, a dotted line represents a wiring to be formed later. Note that corners of the gate electrode or gate wiring formed by transferring the mask pattern may be formed to be more rounded than corners of the pattern of the photomask. That is, the corner of the gate electrode or the gate wiring may be provided with rounding that has a smoother shape than the corner of the photomask pattern.

In such a gate electrode or gate wiring, the rounded convex portion can suppress generation of fine powder due to abnormal discharge during dry etching by plasma. Further, in the rounded concave portion, even when fine powder adheres to the substrate during cleaning, the cleaning liquid can be washed away without staying on the convex portion of the wiring pattern.

Next, an insulating layer or the like is formed after the formation of the gate electrode or the gate wiring. Then, after forming an opening at a predetermined position on the insulating layer, a wiring is formed. This opening is provided in order to establish electrical connection between the semiconductor layer or gate wiring layer located in the lower layer and the wiring layer. The wiring can be formed by depositing a metal layer, transferring a pattern formed on the photomask by photolithography to a resist or the like, and etching the metal layer using the mask pattern. .

The pattern on the photomask for forming this wiring consists of a corner portion consisting of a convex portion (outer side) and a concave portion (inner side), or a convex portion (outer side) and a concave portion (inner side). Has a bend. The bent portion refers to a portion formed by bending a pattern. In the present invention, the corner portion or the bent portion is formed by rounding off.

Specifically, when the corner or the bent portion is a convex portion, one side is 10 μm or less, or a shape that is rounded by removing a right triangle having a size that is 1/2 to 1/5 of the line width, or one side Is a part of a right-angled triangle region of 10 μm or less or 1/2 to 1/5 of the line width, and a region including a polygon or a curve is removed to obtain a rounded shape.

In addition, when the corner portion or the bent portion is formed of a concave portion, one side is 10 μm or less or a shape that is chamfered by adding a right triangle of 1/2 to 1/5 of the line width, or one side is 10 μm or less or the line width A part of a 1/2 to 1/5 right triangle area is added to an area including a polygon or a curve to form a rounded shape.

FIG. 21 shows wiring formed by transferring this mask pattern. Note that the corners of the wiring formed by transferring the mask pattern may be formed to be more rounded than the corners of the photomask pattern. That is, the corners of the wiring may be provided with rounding that is smoother than the corners of the pattern of the photomask.

In such a wiring, rounded convex portions can suppress generation of fine powder due to abnormal discharge during dry etching by plasma. Also, in the rounded recess, even if there is fine powder that can be produced during washing, it can be washed away that it tends to collect at the corner. In particular, it is very advantageous to be able to wash away dust in wiring such as a drive circuit section provided with a large number of parallel wirings. As a result, there is an effect that the problem of dust and fine powder in the manufacturing process can be solved, and the yield can be greatly improved. Moreover, it can be expected that the electrical conduction efficiency is improved particularly at high frequencies by adopting a configuration in which the corners of the wiring are rounded.

Note that in this embodiment mode, a mode in which corners or bent portions are rounded in three layouts of a semiconductor layer, a gate wiring, and a wiring is described; however, the present invention is not limited to this. That is, in any one of the layers, it is only necessary to round the corners or the bent portions or a part thereof so as to eliminate problems such as dust and fine powder in the manufacturing process.

  An example of an element structure and an element layout included in the semiconductor device described in Embodiment 3 (see FIG. 5) will be described.

  A semiconductor device 501 of the present invention includes a resonance circuit 502 having a MOS capacitor, a power supply circuit 503, a clock generation circuit 504, a demodulation circuit 505, a control circuit 506, a memory unit 507, and an encoding and modulation circuit 508. The resonance circuit 502 and the power supply circuit 503 are configured by analog circuits, and the control circuit 506 and the memory unit 507 are configured by digital circuits. The clock generation circuit 504, the demodulation circuit 505, and the encoding and modulation circuit 508 have an analog portion and a digital portion.

  These circuits include transistors. In addition to a MOS transistor formed on a single crystal substrate, the transistor can be a thin film transistor (TFT). FIG. 22 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 22 shows an n-channel transistor 51, an n-channel transistor 52, a capacitor element 54, a resistance element 55, and a p-channel transistor 53. Each transistor includes a semiconductor layer 35, an insulating layer 38, and a gate electrode 39. The gate electrode 39 is formed by a laminated structure of the first conductive layer 33 and the second conductive layer 32. 23A to 23E are top views corresponding to the n-channel transistor 51, the n-channel transistor 52, the capacitor 54, the resistor 55, and the p-channel transistor 53 shown in FIG. Can be referred to.

  In FIG. 22, an n-channel transistor 51 is also called a low concentration drain (LDD) on both sides of the gate electrode in the channel length direction (carrier flow direction), and forms a source and drain region that forms a contact with the wiring 34. An impurity region 37 doped in a concentration lower than the impurity concentration of the impurity region 36 to be formed is formed in the semiconductor layer 35. In the case of forming the n-channel transistor 51, phosphorus or the like is added to the impurity region 36 and the impurity region 37 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

  As shown in FIG. 23A, in the gate electrode 39 of the n-channel transistor 51, the first conductive layer 33 is formed so as to spread on both sides of the second conductive layer 32. In this case, the film thickness of the first conductive layer 33 is formed thinner than the film thickness of the second conductive layer. The thickness of the 1st conductive layer 33 is formed in the thickness which can let the ionic species accelerated with the electric field of 10-100 kV pass. The impurity region 37 is formed so as to overlap the first conductive layer 33 of the gate electrode 39. That is, an LDD region overlapping with the gate electrode 39 is formed. In this structure, an impurity region 37 is formed in a self-aligned manner in the gate electrode 39 by adding one conductivity type impurity through the first conductive layer 33 using the second conductive layer 32 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

  A transistor having LDDs on both sides is applied to a transistor constituting a rectifying TFT of the power supply circuit 503 in FIG. 5 or a transmission gate (also referred to as an analog switch) used in a logic circuit. In these TFTs, since both positive and negative voltages are applied between the source and drain electrodes, it is preferable to provide LDDs on both sides of the gate electrode.

  In FIG. 22, an n-channel transistor 52 has an impurity region 37 doped in a lower concentration than the impurity concentration of the impurity region 36 formed in the semiconductor layer 35 on one side of the gate electrode. As shown in FIG. 23B, in the gate electrode 39 of the n-channel transistor 52, the first conductive layer 33 is formed so as to spread on one side of the second conductive layer 32. In this case as well, LDD can be formed in a self-aligned manner by adding one conductivity type impurity through the first conductive layer 33 using the second conductive layer 32 as a mask.

  A transistor having an LDD on one side may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 22, the capacitive element 54 is formed by sandwiching an insulating layer 38 between a first conductive layer 33 and a semiconductor layer 35. The semiconductor layer 35 that forms the capacitor 54 includes an impurity region 36 and an impurity region 37. The impurity region 37 is formed at a position overlapping the first conductive layer 33 in the semiconductor layer 35. The impurity region 36 forms a contact with the wiring 34. Since the impurity region 37 can be doped with an impurity of one conductivity type through the first conductive layer 33, the impurity concentration contained in the impurity region 36 and the impurity region 37 can be the same or different. It is. In any case, since the semiconductor layer 35 functions as an electrode in the capacitor 54, it is preferable to reduce the resistance by adding an impurity of one conductivity type. Further, as shown in FIG. 23C, the first conductive layer 33 can sufficiently function as an electrode by using the second conductive layer 32 as an auxiliary electrode. Thus, by using a composite electrode structure in which the first conductive layer 33 and the second conductive layer 32 are combined, the capacitor element 54 can be formed in a self-aligned manner.

  In FIG. 5, the capacitor is used as a storage capacitor included in the power supply circuit 503 or a resonance capacitor included in the resonance circuit 502. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

  In FIG. 22, the resistance element 55 is formed by the first conductive layer 33. Since the first conductive layer 33 is formed to a thickness of about 30 to 150 nm, the resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element is used as a resistance load included in the modulation circuit 508 in FIG. Also, it may be used as a load when current is controlled by a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 22, the p-channel transistor 53 includes an impurity region 31 in the semiconductor layer 35. The impurity region 31 forms source and drain regions that form contacts with the wiring 34. The configuration of the gate electrode 39 is a configuration in which the first conductive layer 33 and the second conductive layer 32 overlap. The p-channel transistor 53 is a single drain transistor without an LDD. When the p-channel transistor 53 is formed, boron or the like is added to the impurity region 31 as an impurity imparting p-type. On the other hand, if phosphorus is added to the impurity region 31, an n-channel transistor having a single drain structure can be obtained.

High density plasma treatment in which one or both of the semiconductor layer 35 and the insulating layer 38 are excited by microwaves, have an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ / cm ^3. Oxidation or nitridation may be performed by the above. At this time, the substrate temperature is set to 300 to 450 ° C., and treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, etc.) or a nitriding atmosphere (N ₂ , NH _3, etc.), so that the interface between the semiconductor layer 35 and the insulating layer 38 is Defect levels can be reduced. By performing this treatment on the insulating layer 38, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or less, an insulating layer oxidized or nitrided by this plasma treatment can be used as the insulating layer 38. Further, when the driving voltage of the transistor is 3 V or higher, insulation is performed by combining an insulating layer formed on the surface of the semiconductor layer 35 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). Layer 38 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 54. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 22 and 23, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 23A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  In the case of FIGS. 22 and 23, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used for the first conductive layer, and a tungsten film can be used for the second conductive layer.

  In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same patterning process using a photomask or reticle provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

The use of the wireless chip of the present invention will be described with reference to FIG. The wireless chip of the present invention can be used for a wide range, for example, banknotes, coins, securities, certificate documents, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a wireless chip 90 (see FIG. 24A). The certificate refers to a driver's license, a resident's card, and the like, and a wireless chip 91 can be provided (see FIG. 24B). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a wireless chip 97 (see FIG. 24G). Bearer bonds refer to stamps, food certificates, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a wireless chip 93 (see FIG. 24D). Books refer to books, books, and the like, and can be provided with a wireless chip 94 (see FIG. 24E). A recording medium refers to DVD software, video tape, or the like, and can be provided with a wireless chip 95 (see FIG. 24F). Personal belongings refer to bags, glasses, and the like, and can be provided with a wireless chip 96 (see FIG. 24C). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  The wireless chip of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the wireless chip of the present invention realizes a small size, a thin shape, and a light weight, the design of the product itself is not impaired even after being fixed to the product. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the wireless chip of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

In particular, the wireless chip of the present invention has high reliability by suppressing an excessively high voltage generated inside even in a strong magnetic field, and adding no extra circuit such as a limiter circuit or a constant voltage generation circuit. Since the chip area is small and the power consumption is small, it is effective in various applications as described above. In particular, it is effective in applications where it is necessary to read a plurality of wireless chips. In addition, the wireless chip formed over the flexible substrate is effective in applications that are assumed to be used in a bent state such as paper.

  As one of the elements constituting the semiconductor device of the present invention, a layout example of a memory cell of a static RAM (SRAM) will be described with reference to FIGS.

  The semiconductor layers 10 and 11 illustrated in FIG. 25A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. The semiconductor layer is etched using the mask pattern to form island-shaped semiconductor layers 10 and 11 having a specific shape including the source and drain regions of the TFT and the channel formation region. The semiconductor layers 10 and 11 are determined in consideration of appropriate layout.

  A photomask for forming the semiconductor layers 10 and 11 shown in FIG. 25A includes a mask pattern 40 shown in FIG. The mask pattern 40 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. When a positive resist is used, the mask pattern 40 shown in FIG. 25B is manufactured as a light shielding portion. The mask pattern 40 has a shape obtained by deleting the top A of the polygon. Further, the inside B of the corner has a shape that is bent over a plurality of steps so that the corner of the corner does not become a right angle. The corner portion of this photomask pattern is deleted.

  The shape of the mask pattern 40 shown in FIG. 25B is reflected in the semiconductor layers 10 and 11 shown in FIG. In that case, a shape similar to the mask pattern 40 may be transferred, or the corner of the mask pattern 40 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 40 may be provided.

  On the semiconductor layers 10 and 11, an insulating layer containing at least part of silicon oxide or silicon nitride is formed. One purpose of forming this insulating layer is a gate insulating layer. Then, as shown in FIG. 26A, gate wirings 12, 13, and 14 are formed so as to partially overlap the semiconductor layer. The gate wiring 12 is formed corresponding to the semiconductor layer 10. The gate wiring 13 is formed corresponding to the semiconductor layers 10 and 11. The gate wiring 14 is formed corresponding to the semiconductor layers 10 and 11. As the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and the shape thereof is formed over the insulating layer by a photolithography technique.

  The photomask for forming this gate wiring is provided with a mask pattern 41 shown in FIG. In this mask pattern, the corner portion is deleted so that it is ½ or less of the line width of the wiring and １ ／ or more of the line width. The shape of the mask pattern 41 shown in FIG. 26B is reflected in the gate wirings 12, 13, and 14 shown in FIG. In that case, a shape similar to the mask pattern 41 may be transferred, but the corner of the mask pattern 41 may be transferred so as to be further rounded. That is, the gate wirings 12, 13, and 14 may be provided with rounded portions that have a smoother pattern shape than the mask pattern 41. Generation of fine powder due to abnormal discharge can be suppressed during dry etching by plasma outside the corners of the gate wirings 12, 13, and 14. Inside the corner portion, the cleaning liquid can be washed away without staying in the corner portion of the wiring pattern even when fine powder adheres to the substrate during cleaning.

  The interlayer insulating layer is a layer formed next to the gate wirings 12, 13 and 14. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material such as polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wirings 12, 13, and 14. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities that are not good for the TFT, such as exogenous metal ions and moisture.

  Openings are formed in predetermined positions in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 27A, wirings 15 to 20 are formed so as to partially overlap the semiconductor layer. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

  A photomask for forming the wirings 15 to 20 includes a mask pattern 42 shown in FIG. Also in this case, the wiring is each corner portion bent into an L shape, and one side of the right triangle is 10 μm or less, or 1/2 or less of the wiring line width and 1/5 or more of the line width. Remove the corners and make the corners rounded. That is, the outer periphery of the wiring layer at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other sandwiching the corner portion, and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the wiring layer corresponding to the right isosceles triangular portion formed by is removed. When removed, two obtuse angle parts are newly formed in the wiring layer. By appropriately setting the mask design and etching conditions, a curve that touches both the first straight line and the second straight line is formed at each obtuse angle part. It is preferable to etch the wiring layer as described above. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. Such a wiring shape can suppress generation of fine powder due to abnormal discharge during dry etching by plasma. Further, when the substrate is cleaned, even if fine powder adheres to the substrate, the cleaning liquid can be washed away without staying in the corner portion of the wiring pattern, and as a result, the yield is improved. This is also an advantage that when there are a large number of parallel wirings on the substrate, the attached fine powder can be easily removed by washing. It can be expected that the corner portion of the wiring is electrically conducted by taking a round. In addition, a large number of parallel wires are very convenient for washing away dust.

  In FIG. 27A, n-channel transistors 21 to 24 and p-channel transistors 25 and 26 are formed, and an SRAM memory cell circuit composed of six transistors is formed. The wirings 17 and 18 are wirings having VDD and GND potentials, the gate wiring 12 is a word line, and the wirings 15 and 20 are bit lines. The n-channel transistor 23 and the p-channel transistor 25, and the n-channel transistor 24 and the p-channel transistor 26 constitute an inverter, and together, a flip-flop circuit.

  The circuit shown in FIGS. 25 to 27 can be manufactured according to the same process as that of the fifth embodiment.

  This embodiment can be implemented in combination with the seventh embodiment. For example, a transistor having a lightly doped drain (LDD) is included on both sides or one side of a gate electrode using a photomask or a reticle provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. The circuit of this embodiment can be formed.

In this embodiment, as an application example using the wireless chip of the present invention, a model for appropriately determining the repair time by arranging a plurality of wireless chips in a building and sequentially obtaining the stress state applied to the building explain.

A wireless chip disposed in a building is provided with a memory and a sensor. By receiving a command (command), the wireless chip can write to and read from the memory and operate the sensor. And it becomes possible to accumulate | store the information from a sensor in memory. The accumulated information can be transmitted to the administrator by wireless communication.

Examples of such a sensor include sensors necessary for grasping the state of a building such as a temperature sensor, a pressure sensor, and a humidity sensor. A building repeats expansion and contraction due to temperature changes, and it is aged while being affected by this. Therefore, the temperature information can be said to be important information for grasping the aging of the building. Similarly, humidity and pressure can be considered as factors affecting aging. Factors that affect the aging of buildings are called stress. Information obtained by measuring stress over a certain period is referred to as stress aging information.

FIG. 30A shows a viaduct having a road. A wireless chip 3000 with a temperature sensor can be arranged on the viaduct skeleton, pillar 3011, concrete 3012, asphalt 3013, or the like. When a plurality of wireless chips 3000 are provided, they may be arranged irregularly on the viaduct or arranged regularly. The wireless chip is arranged on the viaduct in a form of being attached to the surface of the viaduct wall 3014 or the pillar 3011 or embedded in asphalt 3013 or concrete 3012 constituting the road. When the wireless chip 3000 with a temperature sensor or the wireless chip with a humidity sensor according to this embodiment is applied, the wireless chip 3000 may be attached to a surface of a road or may be embedded in a member constituting a building. In the case where a wireless chip with a pressure sensor is applied, an embedded form is preferable.

The wireless chip 3000 only needs to be associated with a wireless chip solid number and road position information, and these are stored in a memory of the wireless chip 3000. Further, the memory of the wireless chip stores the construction date, the building member, the use of the building, the contractor, the owner, the environmental information, etc. as the initial information. Since such initial information does not need to be deleted, it may be stored in the write-once memory.

In addition, a base station and a base station antenna that cover a specific area of the road as a radio wave transmittable area are provided around the road.

When receiving a radio wave from the base station via the antenna, the wireless chip 3000 can demodulate a command from the received radio wave and perform a predetermined process according to the command. The predetermined process is a process based on the instruction set of the instruction 1, the instruction 2, and the instruction 3, for example. When the instruction 1 is received, the temperature information is acquired from the temperature sensor, and the temperature information is stored in the nonvolatile memory included in the memory inside the chip. When the command 2 is received, the temperature information stored in the memory is transmitted. When the instruction 3 is received, the information stored in the memory is deleted. The instruction 3 is effective only when the memory has a rewritable nonvolatile memory. Examples of the rewritable nonvolatile memory include EEPROM (Electrically Erasable Programmable Read-Only Memory).

In addition, as a system example of the present embodiment, information processing devices 2921, 2922, and 2923 are provided for each of a region A2901 including a building A2911, a region B2902 including a building B2912, and a region C2903 including a building C2913 having a specific range. FIG. 29 shows a configuration in which time-lapse information is sent to the information processing apparatus 2942 of the administrator 2940 via the communication network 2950 via the transmission / reception unit of the information processing apparatus. In this case, the information processing device 2942 of the administrator 2940 includes a transmission / reception unit 2941 for performing information transmission with the information processing devices 2921, 2922, and 2933. As the communication network 2950, an Internet system can be used, and other telephone lines, public lines such as mobile phones, and LANs (local area networks) can be used. An example of communication means using the communication network 2950 is electronic mail. The information processing devices 2921, 2922, and 2923 are interface units 2923, 2924, and 2925 with the reader / writer devices 2914, 2915, and 2916, arithmetic processing units 2926, 2927, and 2928, databases 2929, 2930, and 2931, and transmission / reception units 2932, respectively. 2933 and 2934 at least. Information acquired via the interface units 2923, 2924, and 2925 is processed by the arithmetic processing units 2926, 2927, and 2928 as necessary, and then stored in the databases 2929, 2930, and 2931.

This embodiment will be described with reference to a flowchart. As shown in FIG. 28A, the wireless chip 3000 is placed in the road and started. The wireless chip 3000 receives initial information regarding roads (S1). At this time, the memory of the wireless chip 3000 stores initial information such as the construction date and building members.

The radio chip 3000 in the road can be periodically supplied with power by periodically transmitting a radio wave carrying the command 1 from the base station. According to the instruction 1, the temperature information sensed by the sensor at that time is stored in the memory. In this way, the wireless chip 3000 in the road can accumulate temperature information (S2). At this time, information about the temperature obtained from the sensor is written in the memory of the wireless chip 3000. In addition to temperature, information about this may be added by providing a sensor for sensing pressure, humidity, and the like.

Periodically, a command 2 is transmitted to the wireless chip 3000 by using means for transmitting / receiving to / from the wireless chip 3000 (for example, an automobile on which the reader / writer device 110 is mounted), and temperature information is collected. Information accumulated in this way can be acquired (S3). In this way, it is possible to acquire and collect temperature-related information with respect to the road obtained from the memory. At this time, if necessary, the command 3 may be transmitted to erase information in the wireless chip 3000.

Based on the collected initial information and time-lapse information, the state of the road can be determined, and the repair time can be determined (S4).

Then, time information and the like are collected in an information processing apparatus possessed by a building manager or the like, and can be processed by the information processing apparatus. For example, the repair time can be determined in descending order of deterioration. Further, the server owned by the administrator can calculate the cost and schedule estimate for the repair, and can select the candidate of the client. Then, the repair timing can be determined in consideration of costs, schedules, contractors, and the like. When it is determined that the repair is necessary in this way, the entire road or a part thereof is repaired (S5).

After renovation of the entire road or a part of the road, the wireless chip 3000 again accumulates the time-lapse information as the renovation information (S2) and repeats this. At this time, a new wireless chip may be arranged at the repaired location.

And it ends by destruction or disappearance of the building.

By arranging wireless chips with sensors on the walls, ceilings and floors of buildings as well as roads, it is also possible to collect information on the building temperature over time. For example, as illustrated in FIG. 30B, a wireless chip can be provided on the outer wall 3021 and the staircase 3022 of a building. Arranging includes embedding in the interior of a wall or pillar as in the case of roads. However, when a wireless chip 3000 with a temperature sensor or a wireless chip with a humidity sensor is applied, it may be attached to the surface of a building or embedded in a member constituting the building. On the other hand, when a wireless chip with a pressure sensor is applied, an embedded form is preferable. And it is possible to judge the deterioration of the building. A wireless chip with a sensor provided in a building can exist in an area where transmission and reception can be performed by providing one or more reader / writer devices in each building. As a result, the reader / writer device can supply power to the wireless chip 3000 and transmit a command, and can receive information from the wireless chip 3000.

Moreover, you may provide the opportunity to request | require the request | requirement from a user at the time of repair. For example, as shown in FIG. 28B, when it is determined that the repair is necessary, the repair guide is transmitted from the administrator to the person (user) using the building (S6). In the guidebook, the contents for inquiring the user's request for renovation are described. After obtaining the request information from the user (S7), it is possible to perform a modification reflecting this (S8).

The manufacturer of the building should perform sufficient reliability tests on temperature, humidity, or pressure stress to estimate the temperature, humidity, or pressure stress conditions that require refurbishment. The information processing apparatus compares these estimated conditions with the collected information, and determines whether or not the building needs to be repaired.

With such a building management system, it is possible to sequentially obtain information on stress over time, and there is no need to go to the building site. And it is possible to perform collective management related to the renovation of buildings. Note that the present invention is particularly effective when reading a plurality of wireless chips, and can be advantageously applied in such an application example.

The figure which simplified the semiconductor device of this invention, and the graph explaining the operation | movement. 5 is a characteristic curve of a MOS capacitor element included in the semiconductor device of the present invention. The figure which simplified the conventional semiconductor device, and the graph explaining the operation | movement. The figure which simplified the semiconductor device of this invention, and the graph explaining the operation | movement. 1 is a block diagram of a semiconductor device of the present invention. 4 is a power supply circuit included in the semiconductor device of the present invention; 4 is a power supply circuit included in the semiconductor device of the present invention; FIG. 4 is a simplified diagram of a semiconductor device of the present invention. FIG. 4 is a simplified diagram of a semiconductor device of the present invention. The figure which simplified the semiconductor device of this invention, and the graph explaining the operation | movement. The figure which simplified the semiconductor device of this invention, and the graph explaining the operation | movement. 1 is a layout diagram of a MOS capacitor element included in a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. FIG. 6 is a layout diagram of a circuit included in a semiconductor device of the invention. FIG. 6 is a layout diagram of a circuit included in a semiconductor device of the invention. FIG. 6 is a layout diagram of a circuit included in a semiconductor device of the invention. FIG. 14 is a cross-sectional view of a semiconductor element included in a semiconductor device of the invention. 1 is a layout diagram of a semiconductor element included in a semiconductor device of the present invention. FIG. 16 illustrates an electronic device in which a semiconductor device of the invention is mounted. FIG. 6 is a layout diagram of a circuit included in a semiconductor device of the invention. FIG. 6 is a layout diagram of a circuit included in a semiconductor device of the invention. FIG. 6 is a layout diagram of a circuit included in a semiconductor device of the invention. 6 is a flowchart of an example in which the semiconductor device of the present invention is applied. 1 shows a system configuration example to which a semiconductor device of the present invention is applied. An example in which the semiconductor device of the present invention is applied.

Claims (7)

A resonance circuit having an N-type MOS capacitor having a threshold voltage in a range of −24 V or more and −0.1 or less, and an antenna electrically connected to the resonance circuit,
The absolute value of the threshold voltage of the N-type MOS capacitor is not less than 1/2 of the minimum operating power supply voltage and not more than twice the maximum operating power supply voltage.
A semiconductor device, wherein data is transmitted and received wirelessly through the antenna. 2. The semiconductor device according to claim 1, wherein the semiconductor region of the N-type MOS capacitor element includes an N-type impurity element at a concentration of 1 × 10 ¹⁷ or more and 1 × 10 ²⁰ atoms / cm ³ or less. A resonance circuit having a P-type MOS capacitor having a threshold voltage in a range of 0.1 to 24 V, and an antenna electrically connected to the resonance circuit;
The absolute value of the threshold voltage of the P-type MOS capacitor element is not less than 1/2 of the minimum operating power supply voltage and not more than twice the maximum operating power supply voltage.
A semiconductor device, wherein data is transmitted and received wirelessly through the antenna. 4. The semiconductor device according to claim 3, wherein the semiconductor region of the P-type MOS capacitor element includes a P-type impurity element at a concentration of 1 × 10 ^{17 to} 1 × 10 ²⁰ atoms / cm ³ . 5. The semiconductor device according to claim 1, wherein the semiconductor device includes an integrated circuit provided over a glass substrate or a flexible substrate. 6. The semiconductor device according to claim 1, wherein the semiconductor device includes an integrated circuit including a thin film transistor. A bill, a coin, a securities, a certificate, a bearer bond, a packaging container, a book, a recording medium, a vehicle, a food, wherein the semiconductor device according to any one of claims 1 to 6 is mounted. , Clothing, health supplies, daily necessities, medicines or electronics.

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