JP2007012790A - Manufacturing method of stacked substrate, stacked semiconductor device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a highly reliable stacked substrate capable of vertical conduction connection. <P>SOLUTION: The manufacturing method comprises: a step of disposing an insulating member 65 for gap formation on at least one of a first substrate 20 and a second substrate 30; a step of aligning an electrode 21 of the first substrate 20 and a through-hole 32 of the second substrate 30, and disposing the second substrate 30 on the first substrate 20 putting an insulating member 65 therebetween; and a step of filling ink containing metal particles in the through-hole 32 of the second substrate 30 using an ink jet method. When filling the ink, the insulating member 65 blocks spreading of the ink on the first substrate 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a laminated substrate, a laminated semiconductor device, and an electronic apparatus.

In the field of portable electronic devices such as mobile phones, notebook personal computers, and personal data assistance (PDA), devices are becoming smaller and lighter. Along with this, high-density mounting of semiconductor components and the like on a wiring board built in the electronic device has been promoted. A stacked semiconductor device in which a plurality of semiconductor chips are stacked in the thickness direction in one package is used (see, for example, Patent Document 1).
JP 2000-276789 A

  In such a stacked semiconductor device, the mounting density is improved by bringing the through electrode for vertical conduction into direct contact with the terminal electrode. Such through electrodes are formed by filling a metal material into the through holes formed in the substrate by a plating method. However, depending on the shape of the through hole, the filling property of the plating becomes insufficient, and the penetrating electrode formed by the plating method has a concave end surface, which is likely to cause poor contact with the terminal electrode.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a laminated substrate, a laminated semiconductor device, and an electronic device capable of highly reliable vertical conduction connection.

  The method for manufacturing a multilayer substrate according to the present invention is a method for manufacturing a multilayer substrate including a first substrate on which an electrode is formed and a second substrate on which a through hole is formed, wherein the insulating member for forming a gap is the first member. The step of disposing on at least one of the substrate and the second substrate, aligning the electrode of the first substrate and the through hole of the second substrate, and sandwiching the insulating member between the first substrate and the first substrate A step of disposing a second substrate; and a step of filling an ink containing metal particles into the through-hole of the second substrate using an inkjet method, wherein the insulating member is the first substrate. The spreading of the ink on the top is blocked.

  According to such a method, the through electrode that is reliably connected to the electrode of the first substrate is formed by filling the through hole of the second substrate with the metal ink. In other words, regardless of the size of the gap between the first substrate and the second substrate, the liquid metal ink that is the material for forming the through electrode is reliably disposed on the electrode of the first substrate, and as a result, formed from the metal ink. The formed through electrode is in reliable contact with the electrode on the first substrate. Note that the through electrode using a liquid material can be formed by the dam effect of the insulating member. In addition, by using the ink jet method, it is relatively easy to dispose the ink inside the fine holes, and since the formed through electrode is solid, the possibility of disconnection is low. Therefore, this manufacturing method enables highly reliable vertical conduction connection. Furthermore, according to this method, by using the ink jet method for forming the through electrode, the process can be simplified, for example, the plating process becomes unnecessary.

In the laminated substrate manufacturing method of the present invention, it is preferable that the insulating member has a shape surrounding an electrode of the first substrate or a through hole of the second substrate.
According to such a method, spreading of the ink is reliably prevented by the shape of the insulating member.

In the method for manufacturing a laminated substrate of the present invention, it is preferable that an opening for degassing is provided in the insulating member when the ink is filled.
According to such a method, the filling property of ink into the through hole is improved by the opening for venting.

In the method for manufacturing a laminated substrate according to the present invention, the insulating member preferably has a labyrinth structure.
According to such a method, the degassing can be performed while the spreading of the ink is blocked by the insulating member having the labyrinth structure.

Moreover, it is preferable that the manufacturing method of the laminated substrate of this invention uses the inkjet method or the photolithographic method for arrangement | positioning of the said insulating member.
According to such a method, it is possible to form the insulating member in a desired fine pattern shape by using an inkjet method or a photolithography method. Further, by using the ink jet method, the process of forming the insulating member can be simplified.

The method for manufacturing a laminated substrate according to the present invention includes a step of drying the ink disposed in the through hole of the second substrate when the ink is filled in the through hole of the second substrate, It is preferable to repeat the step of further disposing the ink on the dry film.
According to this method, a through electrode having a desired film thickness can be reliably formed using a liquid material.

In the method for manufacturing a multilayer substrate according to the present invention, the multilayer substrate further includes a third substrate in which a through hole is formed, and another insulating member for forming a gap is formed between the second substrate and the third substrate. The step of arranging at least one and the through hole of the second substrate and the through hole of the third substrate are aligned, and the third substrate is arranged on the second substrate with the insulating member interposed therebetween. And a step of filling the inside of the through hole of the third substrate with an ink containing metal particles using an inkjet method, wherein the insulating member is the ink on the second substrate. It is preferable to block the spread of the water.
According to this method, the third substrate having the through hole can be further stacked on the second substrate by the highly reliable vertical conduction connection.

Further, in the method for manufacturing a multilayer substrate according to the present invention, the multilayer substrate further includes a fourth substrate on which an electrode is formed, and the insulating member for forming the gap is disposed on the third substrate; Aligning the through hole of the substrate with the electrode of the fourth substrate and placing the fourth substrate on the third substrate with the insulating member interposed therebetween, Preferably, the member blocks the spread of the ink on the third substrate.
According to this method, the fourth substrate having the electrode can be further laminated on the third substrate by the highly reliable vertical conduction connection.

In the method for manufacturing a laminated substrate according to the present invention, the ink dry film having a shape raised from the through hole of the third substrate is formed when the ink is filled into the through hole of the third substrate. preferable.
According to this method, the through electrode formed from the metal ink is surely in contact with the electrode on the third substrate.

  Moreover, it is preferable that the manufacturing method of the laminated substrate of this invention uses at least 1 of gold | metal | money, silver, and copper as said metal particle.

  In the method for producing a laminated substrate of the present invention, the step of firing the ink containing metal particles is preferably performed for each lamination of one substrate, or the step of firing the ink containing metal particles, It is preferable to collectively perform after stacking a plurality of substrates.

In the laminated substrate manufacturing method of the present invention, the second substrate is preferably a semiconductor chip.
According to this method, a stacked semiconductor device in which semiconductor chips are stacked can be manufactured.

In the laminated substrate manufacturing method of the present invention, it is preferable that the insulating members are arranged in a wafer state.
According to this method, it is possible to improve the processing capability related to the arrangement of the insulating members.

A stacked semiconductor device of the present invention is manufactured using the manufacturing method of the present invention described above.
An electronic apparatus according to the present invention includes the stacked semiconductor device according to the present invention.
According to the multilayer semiconductor device and the electronic apparatus of the present invention, the reliability of vertical conduction in the multilayer substrate is high, and the quality can be improved.

  The stacked semiconductor device of the present invention is formed in a support substrate having electrodes, a first semiconductor chip having a through hole and disposed on the support substrate, and inside the through hole of the first semiconductor chip, From the shape of the through electrode electrically connected to the electrode of the support substrate, and the shape sandwiched between the support substrate and the first semiconductor chip and surrounding the electrode of the support substrate or the through hole of the first semiconductor chip And a spacer.

  According to such a semiconductor device, it is possible to form a through electrode using a liquid material by using a spacer sandwiched between the support substrate and the chip as a dam in the manufacturing process. Therefore, the reliability of the vertical conduction connection is improved.

  In the stacked semiconductor device of the present invention, it is preferable that the spacer is in close contact with the support substrate and the first semiconductor chip, and an opening is provided in a side portion.

  In the stacked semiconductor device of the present invention, it is preferable that the spacer has a labyrinth structure.

  The stacked semiconductor device according to the present invention includes a second semiconductor chip having a through hole and disposed on the first semiconductor chip, and formed in the through hole of the second semiconductor chip. A through electrode electrically connected to a through electrode of the semiconductor chip, and sandwiched between the first semiconductor chip and the second semiconductor chip, the through hole of the first semiconductor chip or the through of the second semiconductor chip And a spacer having a shape surrounding the hole.

  Further, the stacked semiconductor device of the present invention is sandwiched between a third semiconductor chip having an electrode and disposed on the second semiconductor chip, and the second semiconductor chip and the third semiconductor chip, It is preferable to further include another spacer having a shape surrounding the through hole of the second semiconductor chip or the electrode of the third semiconductor chip.

The present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view schematically showing an example of a laminated semiconductor substrate according to the present invention.

(Stacked semiconductor device)
As shown in FIG. 1, a semiconductor device 10 includes an interposer substrate 20 as a support substrate and a plurality of semiconductors (first semiconductor chip 30, second semiconductor chip 40, third semiconductor chip) stacked on the interposer substrate 20. 50) and a through electrode 60 for vertical conduction.

  An electrode 21 is formed on one surface of the interposer substrate 20. The first semiconductor chip 30 and the second semiconductor chip 40 include through holes 32 and 42 provided in a base material made of silicon, and an insulating film 33 for leak prevention formed so as to cover the inner walls of the through holes 32 and 42. , 43. The through holes 32 and 42 of the semiconductor chips 30 and 40 are aligned with the electrode 21 of the interposer substrate 20, and the through electrode 60 is formed inside the through holes 32 and 42. An electrode 51 is formed on one surface of the third semiconductor chip 50, and this electrode 51 is disposed opposite to the electrode 21 of the interposer substrate 20. The electrode 21 of the interposer substrate 20 and the electrode 51 of the third semiconductor chip 50 are electrically connected via the through electrode 60.

  A spacer 65 made of an insulating member is sandwiched between the interposer substrate 20 and the first semiconductor chip 30. The spacer 65 is in close contact with the interposer substrate 20 and the first semiconductor chip 30 and has a shape surrounding the electrode 21 of the interposer substrate 20 and the through hole 32 of the first semiconductor chip 30. Further, the spacer 65 has a function of blocking the spread of the forming material when the through electrode 60 is formed, as will be described later, in addition to the function of ensuring the gap between the interposer substrate 20 and the first semiconductor chip 30.

FIG. 2 is a perspective view illustrating a configuration example of the spacer 65.
As shown in FIG. 2, the spacer 65 has a shape surrounding the electrode 21 of the interposer substrate and the through hole 32 of the first semiconductor chip, and is provided with openings 72 and 73 on the side portions.

  Specifically, the spacer 65 has a configuration in which two members 75 and 76 having a rectangular frame shape with one side open are combined. That is, the member 75 is formed in a U-shape, and includes parallel portions 75a and 75b extending vertically from both ends of the linear base portion 75c and parallel to each other. Similarly, the member 76 is formed in a U-shape and includes parallel portions 76a and 76b extending vertically from both ends of the linear base portion 76c and parallel to each other. And the member 75 and the member 76 are opposingly arranged so that it may overlap partially. In this example, the parallel portions 76a and 76b of the member 76 are wider than the parallel portions 75a and 75b of the member 75, and the parallel portions 76a and 76b are disposed outside the parallel portions 75a and 75b. Openings 72 and 73 are formed between the parallel part 75a and the parallel part 76a, and between the parallel part 75b and the parallel part 76b. The openings 72 and 73 communicate the inner and outer regions surrounded by the members 75 and 76. ing.

  Furthermore, the parallel portions 75a and 75b of the member 75 and the parallel portions 76a and 76b of the member 76 are arranged so as to surround substantially the entire periphery of the electrode 21 of the interposer substrate and the through hole 32 of the first semiconductor chip. Therefore, the gap portion between the parallel portion 75a and the parallel portion 76a that forms the opening 72 and the gap portion between the parallel portion 75b and the parallel portion 76b that form the opening 73 are formed on the electrodes of the interposer substrate by the inner parallel portions 75a and 75b. 21 and the through hole 32 of the first semiconductor chip, and the open end inside the gap is in a direction different from the electrode 21 and the through hole 32 (the center of the electrode 21 and the through hole 32 is the starting point). The direction is different from the radiation direction. Thus, the spacer 65 has the openings 72 and 73 and a labyrinth structure that suppresses the movement of the liquid from the inside of the enclosure to the outside.

3, 4, and 5 show other examples of the configuration of the spacer 65.
As in FIG. 2, the spacer 65 in FIG. 3 has a configuration in which two members 75 and 76 having a rectangular frame shape with one side open are combined. In this example, the width of the parallel portions 75a and 75b of the member 75 and the width of the parallel portions 76a and 76b of the member 76 are substantially the same, and the member 75 and the member 76 are arranged so as to face each other alternately. Has been. That is, one parallel portion 75 a of the member 75 is disposed inside the one parallel portion 76 a of the member 76, and the other parallel portion 75 b of the member 75 is disposed outside the other parallel portion 76 b of the member 76. Openings 72 and 73 are formed between the parallel part 75a and the parallel part 76a, and between the parallel part 75b and the parallel part 76b. The openings 72 and 73 communicate the inner and outer regions surrounded by the members 75 and 76. ing.

The spacer 65 shown in FIG. 4 has a configuration in which two annular members 81 and 82 that are partially open are combined. That is, the members 81 and 82 are formed in a C shape, and the diameter of the member 82 is larger than that of the member 81. Furthermore, the member 81 is arranged inside the member 82 in a state where the open portions 81a and 82a of the members 81 and 82 face in opposite directions. Openings 84 and 85 are formed between the member 81 and the member 82 to communicate the inside and outside of the enclosed area.
Further, the members 81 and 82 are arranged so as to surround substantially the entire periphery of the electrode 21 of the interposer substrate and the through hole 32 of the first semiconductor chip. Therefore, the gap portion between the members 81 and 82 forming the openings 84 and 85 is hidden from the electrode 21 and the through hole 32 by the inner member 81, and the open end inside these gap portions is the electrode. 21 and the through hole 32 are directed in a different direction (a direction different from the radial direction starting from the centers of the electrode 21 and the through hole 32). Thus, also in this example, the spacer 65 has the openings 84 and 85 and has a labyrinth structure that suppresses the movement of liquid from the inside of the enclosure to the outside.

  The spacer 65 in FIG. 5 has a structure in which four substantially semicircular members 91, 92, 93, 94 are combined. Specifically, the two members 91 and 92 have the same size, and the other two members 93 and 94 have the same size larger than that. The members 91 and 92 are arranged side by side with gaps 95 and 96 on the same circumference so as to form a circle as a whole. Similarly, the members 93 and 94 are arranged side by side with gaps 97 and 98 on the same circumference so as to form a circle outside the members 91 and 92 as a whole. The gaps 95 and 96 of the members 91 and 92 and the gaps 97 and 98 of the members 93 and 94 are arranged with a circumferential position (rotation angle) shifted (90 ° in this example). In this example, the gaps 95 and 96 of the inner members 91 and 92 face the electrode 21 of the interposer substrate and the through hole 32 of the first semiconductor chip, but the gaps 97 and 98 of the outer members 93 and 94 are The inner members 91 and 92 are hidden from the electrode 21 and the through hole 32. Thus, also in this example, the spacer 65 has an opening made up of the gaps 97 and 98 and has a rabbling structure that suppresses the movement of liquid from the inside of the enclosure to the outside.

  As the material for forming the spacer 65, a material having high electrical insulation is preferably used, and a resin material having elasticity is preferably used in order to improve the close contact with the substrate or the chip. Examples of the resin material include polyimide resin, silicone-modified polyimide resin, epoxy resin, acrylic resin, olefin resin, melamine resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO). ) Etc. Not only the resin material but also a material containing an inorganic material such as silica can be used.

  In the present invention, the number and shape of the members constituting the spacer 65 (insulating member) are not limited to the above example.

  Returning to FIG. 1, another spacer 66 made of an insulating member is sandwiched between the first semiconductor chip 30 and the second semiconductor chip 40. Like the spacer 65, the spacer 66 is in close contact with the first semiconductor chip 30 and the second semiconductor chip 40 and has a shape surrounding the through hole 32 of the first semiconductor chip 30 and the through hole 42 of the second semiconductor chip 40. . Further, the spacer 66 has a function of blocking the spread of the forming material when the through electrode 60 is formed, as will be described later, in addition to the function of ensuring the gap between the first semiconductor chip 30 and the second semiconductor chip 40.

  Further, another spacer 67 made of an insulating member is sandwiched between the second semiconductor chip 40 and the third semiconductor chip 50. Like the spacers 65 and 66, the spacer 67 is in close contact with the first semiconductor chip 30 and the second semiconductor chip 40 and surrounds the through hole 32 of the first semiconductor chip 30 and the through hole 42 of the second semiconductor chip 40. Consists of. Further, the spacer 67 has a function of blocking the spread of the forming material when the through electrode 60 is formed, as will be described later, in addition to the function of ensuring the gap between the second semiconductor chip 40 and the third semiconductor chip 50. The spacer 67 does not necessarily need to be provided with the openings 72 and 73 shown in FIG. 2 and may have a shape surrounding at least the through hole 42 of the second semiconductor chip 40.

(Manufacturing method of laminated substrate)
Next, an example of a method for manufacturing the semiconductor device 10 will be described.
6A to 6D and FIGS. 7A to 7D are diagrams illustrating an example of a method for manufacturing the semiconductor device 10.

  First, as shown in FIG. 6A, a spacer 65 made of an insulating member is formed on the interposer substrate 20 on which the electrode 21 is formed by using a photolithography method or an inkjet method. As described above, as a material for forming the spacer 65, in addition to polyimide resin, silicone-modified polyimide resin, epoxy resin, acrylic resin, olefin resin, melamine resin, silicone-modified epoxy resin, benzocyclobutene, polybenzoxazole, and other resins Materials can be used. In the photolithography method, a material for forming the spacer 65 is applied to the entire surface of the substrate 20, and the coating film is patterned into a desired shape (for example, the shape shown in FIG. 2) through exposure and development processing. In the ink jet method, a film 65 having a desired pattern shape (for example, the shape shown in FIG. 2) is drawn and formed on the substrate 20 by discharging the forming material 65a of the spacer 65 in the form of droplets from the discharge head. Pattern formation in the ink jet method is performed, for example, by creating a drawing pattern on a grid-like bitmap having a predetermined interval and controlling the position of the ejection head based on the drawing pattern. In addition, after the material film of the spacer 65 is formed, the pattern film is cured by light or heat treatment as necessary.

  Next, as shown in FIG. 6B, the first semiconductor chip 30 is mounted on the interposer substrate 20. A through hole 32 is formed in the first semiconductor chip 30, and an insulating film 33 is formed so as to cover the inner wall of the through hole 32. The through hole 32 of the first semiconductor chip 30 can be formed by, for example, photolithography or laser light irradiation. The insulating film 33 can be formed using, for example, a photolithography method or an inkjet method.

  Here, as shown in FIG. 8A, the formation of the insulating film 33 using the inkjet method is performed by applying droplets 33a made of a material for forming the insulating film 33 aiming at the peripheral portion (edge portion) of the through hole 32. This is done by discharging. Further, as shown in FIG. 8C, the droplet 33a is landed over the entire periphery of the peripheral portion (edge portion) of the through hole 32. As a result, as shown in FIG. 8B, the material for forming the insulating film 33 is applied to the entire inner wall of the through hole 32 of the first semiconductor chip 30 and the peripheral portion at the end of the through hole 32. An insulating film 33 covering the inner wall of 32 is formed.

  Returning to FIG. 6B, a spacer 66 made of an insulating member is formed on the first semiconductor chip 30. The spacers 66 on the first semiconductor chip 30 can also be formed by using a photolithography method or an ink jet method, like the spacers 65 on the interposer substrate 20.

  When the first semiconductor chip 30 is mounted, the first semiconductor chip 30 is aligned with the interposer substrate 20 so that the through holes 32 of the first semiconductor chip 30 are disposed on the electrodes 21 of the interposer substrate 20. Is done. Then, the first semiconductor chip 30 is disposed on the interposer substrate 20 with a spacer 65 formed on the interposer substrate 20 interposed therebetween. At this time, the influence of the unevenness on the connection surface of the interposer substrate 20 and the first semiconductor chip 30 on the lamination is avoided by the spacer 65. Note that a bonding material for bonding the interposer substrate 20 and the first semiconductor chip 30 is disposed between the interposer substrate 20 and the first semiconductor chip 30 as necessary.

  Each process of forming the through hole 32, the insulating film 33, and the spacer 66 in the first semiconductor chip 30 can be performed in the state of the wafer W before cutting, as shown in FIG. That is, the above processing is performed on one wafer W before being divided into a plurality of semiconductor chips. In this case, the processing capability can be improved as compared with the case where the above processing is performed on each of the divided semiconductor chips. The wafer W is divided into a plurality of semiconductor chips after the through-hole 32, the insulating film 33, and the spacer 66 are formed. Then, the divided semiconductor chips are mounted on the interposer substrate.

  Next, as shown in FIG. 6C, an ink containing metal particles, which are a material for forming the through electrode 60 (see FIG. 1), in the through hole 32 of the first semiconductor chip 30 using the ink jet method. 60a is filled and arranged. By using the inkjet method, it is relatively easy to dispose the ink inside the fine holes. Prior to the placement of the metal ink 60a, the through hole 32 of the first semiconductor chip 30 and its peripheral portion or the spacer 66 may be subjected to a lyophobic process or a lyophilic process.

  As the metal ink 60a, one obtained by dispersing metal fine particles such as gold, silver, copper, palladium, nickel, etc. in a dispersion liquid is used. In order to improve the dispersibility of the metal particles, the surface can be used by coating with an organic substance or the like. Examples of the coating material for coating the surface of the metal particles include polymers that induce steric hindrance and electrostatic repulsion. The dispersion to be used is not particularly limited as long as it can disperse the metal particles and does not cause aggregation. In addition to water, alcohols such as methanol, ethanol, propanol and butanol, n-heptane , N-octane, decane, tetradecane, decalin, toluene, xylene, cymene, durene, indene, dipentene, tetrahydronaphthalene, decahydronaphthalene, cyclohexylbenzene and other hydrocarbon compounds, or ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene Glycol methyl ethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, 1,2-dimethoxyethane, bis (2- Tokishiechiru) ether, p- ether compounds such as dioxane, propylene carbonate, .gamma.-butyrolactone, N- methyl-2-pyrrolidone, dimethylformamide, dimethyl sulfoxide, may be mentioned polar compounds such as cyclohexanone. Of these, water, alcohols, hydrocarbon compounds, and ether compounds are preferred, and further preferred dispersions are preferred in view of dispersibility of the fine particles, stability of the dispersion, and ease of application to the inkjet method. Examples thereof include water and hydrocarbon compounds. These dispersions can be used alone or as a mixture of two or more.

  Here, in this example, when the metal ink is filled, the spread of the ink on the interposer substrate 20 is blocked by the spacer 65 disposed between the interposer substrate 20 and the first semiconductor chip 30. That is, the spacer 65 becomes a wall, and the ink stays inside the spacer 65. The dam effect of the spacer 65 prevents the metal ink from adhering to an undesired location and prevents the occurrence of a short circuit.

  Furthermore, since the openings 72 and 73 (see FIG. 2) are formed in the spacer 65, the gas inside the through hole 32 is appropriately discharged through these openings. Such degassing prevents an increase in gas pressure inside the through hole 32 due to ink filling, and the inside of the through hole 32 is satisfactorily filled with ink. In addition, since the spacer 65 has a rabbling structure and the movement of the liquid from the inside of the enclosure to the outside is suppressed, the outflow of ink through the opening is avoided.

  Further, in this example, when the metal ink is filled, the spread of the ink on the first semiconductor chip 30 is blocked by the spacer 66 arranged on the first semiconductor chip 30. That is, even if the ink overflows from the upper part of the through hole 32, the spacer 66 becomes a wall and the ink stays inside the spacer 66. Such a dam effect of the spacer 66 prevents the metallic ink from adhering to an undesired location and prevents the occurrence of a short circuit.

  Next, as shown in FIG. 6D, a drying process is performed as necessary to remove the dispersion medium of the metal ink. The drying process can be performed, for example, by a heating process using a hot plate, an electric furnace, or the like. This heating is not necessarily performed in the air, such as in a nitrogen gas atmosphere. This drying process can also be performed by lamp annealing. The light source used for lamp annealing is not particularly limited, but an excimer laser such as an infrared lamp, a xenon lamp, a YAG laser, an argon laser, a carbon dioxide gas laser, XeF, XeCl, XeBr, KrF, KrCl, ArF, ArCl, or the like is used. be able to. By this drying process, a dry film 60b of metal ink is formed inside the through hole 32 of the first semiconductor chip 30.

  As shown in FIGS. 10A to 10D, the metal ink filling process and the drying process may be repeated a plurality of times. That is, first, as shown in FIG. 10A, the metal ink 60a is disposed inside the through hole 32 of the first semiconductor chip 30 by using an inkjet method. Subsequently, as shown in FIG. 10B, the metal ink 60a disposed in the through-hole 32 is dried to form a dry film 60b1. Subsequently, as shown in FIG. 10C, the metal ink 60a is further disposed on the dry film 60b1 of the metal ink. Then, as shown in FIG. 10D, the metal ink 60a on the dry film 60b1 is dried and formed on the previous dry film 60b1 to form a dry film 60b2. The number of repetitions of the filling process and the drying process is not limited to two, and may be three or more. By repeating the filling process and the drying process of the metal ink a plurality of times, a film (conductive film) having a desired film thickness and density can be reliably formed.

  Next, as shown in FIG. 7A, the second semiconductor chip 40 is mounted on the first semiconductor chip 30. Similar to the first semiconductor chip 30, a through hole 42 is formed in the second semiconductor chip 40, and an insulating film 43 is formed so as to cover the inner wall of the through hole 42. When the second semiconductor chip 40 is mounted, the second semiconductor chip 40 is disposed with respect to the first semiconductor chip 30 such that the through hole 42 of the second semiconductor chip 40 is disposed on the through hole 32 of the first semiconductor chip 30. Are aligned. Then, the second semiconductor chip 40 is disposed on the first semiconductor chip 30 with the spacer 66 formed on the first semiconductor chip 30 interposed therebetween. At this time, the spacer 66 prevents the unevenness on the connection surface of the first semiconductor chip 30 and the second semiconductor chip 40 from affecting the stacking. Note that a bonding material for bonding the first semiconductor chip 30 and the second semiconductor chip 40 is disposed between the first semiconductor chip 30 and the second semiconductor chip 40 as necessary.

  Next, as shown in FIG. 7B, the ink containing metal particles, which are the forming material of the through electrode 60 (see FIG. 1), is formed inside the through hole 42 of the second semiconductor chip 40 using an ink jet method. 60c is filled and arranged. As the metal ink 60c, the same ink as that for the first semiconductor chip 30 can be used. Prior to the placement of the metal ink 60c, the through hole 42 of the second semiconductor chip 40 and its peripheral portion or the spacer 67 may be subjected to a lyophobic process or a lyophilic process.

  Even during the filling of the metal ink, the ink on the first semiconductor chip 30 is formed by the spacer 66 disposed between the first semiconductor chip 30 and the second semiconductor chip 40, as in the previous ink filling. The spread is blocked. That is, the spacer 66 becomes a wall and the ink stays inside the spacer 66. Such a dam effect of the spacer 66 prevents the metallic ink from adhering to an undesired location and prevents the occurrence of a short circuit. Further, the degassing effect due to the opening formed in the spacer 66 is the same as in the previous ink filling.

  Further, as in the previous ink filling, the spread of ink on the second semiconductor chip 40 is blocked by the spacer 67 arranged on the second semiconductor chip 40. That is, even if the ink overflows from the upper part of the through hole 42, the spacer 67 becomes a wall and the ink stays inside the spacer 67. Such a dam effect of the spacer 67 prevents the metal ink from adhering to an undesired location and prevents the occurrence of a short circuit.

  Next, as shown in FIG. 7C, a drying process is performed as necessary to remove the dispersion medium of the metal ink. Similar to the case of the first semiconductor chip 30, this drying process can be performed by, for example, a heat treatment using a hot plate, an electric furnace or the like, lamp annealing, or the like. By this drying process, a dry film 60 d of metal ink is formed inside the through hole 42 of the second semiconductor chip 40. As for the formation of the dry film 60d, the metal ink filling process and the drying process may be repeated a plurality of times as in the method shown in FIGS.

  Here, the dry film 60 d is formed in a shape rising from the through hole 42 of the second semiconductor chip 40. This is because the electrode 51 of the third semiconductor chip 50 and the dry film 60d are in contact with each other when the third semiconductor chip 50 described below is mounted (see FIG. 7D). The raised dry film 60d can be formed by increasing the amount of metal ink disposed when filling the through holes 42 with metal ink. In this example, as shown in FIG. 7B, since the spread of ink on the second semiconductor chip 40 is blocked by the spacer 67, the metal ink allowed in the upper portion of the through hole 42 is blocked. Large amount of placement.

  Next, as shown in FIG. 7D, the third semiconductor chip 50 is mounted on the second semiconductor chip 40. At the time of mounting, the third semiconductor chip 50 is aligned with the second semiconductor chip 40 so that the electrode 51 of the third semiconductor chip 50 is disposed on the through hole 42 of the second semiconductor chip 40. Then, the third semiconductor chip 50 is disposed on the second semiconductor chip 40 with the spacer 67 formed on the second semiconductor chip 40 interposed therebetween, and the dry film 60d having a raised shape, and the third semiconductor chip 50 Electrode 51 is in contact. At this time, if necessary, a pressurizing process for pressing the third semiconductor chip 50 against the second semiconductor chip 40 is performed. Further, the spacer 67 avoids the influence of unevenness on the connection surface of the second semiconductor chip 40 and the third semiconductor chip 50 on the stack. Note that a bonding material for bonding the second semiconductor chip 40 and the third semiconductor chip 50 is disposed between the second semiconductor chip 40 and the third semiconductor chip 50 as necessary.

  Further, heat treatment and / or light treatment is performed as the baking treatment for the dried films 60b and 60d of the metal ink. In order to improve the electrical contact between the fine particles, the metal ink dry film needs to completely remove the dispersion medium, and in order to improve the dispersibility in the liquid, the coating agent such as organic matter is conductive. When the surface of the fine particles is coated, it is necessary to remove this coating agent. The firing treatment is usually performed in the air, but can be performed in an inert gas atmosphere such as nitrogen, argon, or helium as necessary. The treatment temperature of the firing treatment includes the boiling point (vapor pressure) of the dispersion medium, the type and pressure of the atmospheric gas, the thermal behavior such as the dispersibility and oxidation of the fine particles, the presence and amount of the coating agent, the heat resistance temperature of the substrate, etc. It is determined as appropriate in consideration. In addition, this baking process may be performed for every lamination | stacking of one board | substrate, and you may carry out collectively after the lamination | stacking of a several board | substrate. That is, the metal ink dry film 60b and the dry film 60d may be fired separately, or the dry film 60b and the dry film 60d may be fired together. By the firing step, electrical contact between the metal particles in the dry film is ensured, and the dry film is converted into a conductive film. Then, a through electrode 60 for vertical conduction that electrically connects the electrode 21 of the interposer substrate 20 and the electrode 51 of the third semiconductor chip 50 is formed.

  Through the above steps, the stacked semiconductor device 10 in which the three semiconductor chips 20, 30, and 40 are stacked on the interposer substrate 20 is completed.

  In the manufacturing method of this example, liquid metal ink is directly disposed on the electrode 21 on the interposer substrate 20 to form the through electrode 60, so that the electrode 21 on the interposer substrate 20 and the through electrode 60 are reliably applied. Can be touched. That is, by the direct arrangement of the metal ink, the tolerance range for the gap variation between the interposer substrate 20 and the first semiconductor chip 30 is wide, and the forming material of the through electrode 60 is reliably arranged on the electrode 21 of the interposer substrate 20, As a result, the through electrode 60 that is reliably connected to the electrode 21 on the interposer substrate 20 can be formed.

  Further, since the through electrode 60 formed by stacking metal inks is solid, it has a dense structure and has a low possibility of disconnection. Therefore, the semiconductor device 10 manufactured by the manufacturing method of this example has high reliability of the vertical conduction connection. Further, in the manufacturing method of this example, the ink-jet method is used to form the through electrode 60, thereby simplifying the process such that a plating process becomes unnecessary.

  In this example, the spacer 65 disposed between the interposer substrate 20 and the first semiconductor chip 30 is formed on the interposer substrate 20. However, the spacer 65 may be formed on the first semiconductor chip 30. It may be formed on both the substrate 20 and the first semiconductor chip 30. Similarly, in this example, the spacer 66 disposed between the first semiconductor chip 30 and the second semiconductor chip 40 is formed on the first semiconductor chip 30. However, the spacer 66 is formed on the second semiconductor chip 40. Alternatively, it may be formed on both the second semiconductor chip 40 and the third semiconductor chip 50.

  The stacked semiconductor device of the present invention is not limited to a four-layer structure in which three semiconductor chips are mounted on the interposer substrate 20, and can be preferably applied to a structure of two layers, three layers, five layers or more. .

  The multilayer substrate of the present invention is not limited to a semiconductor device, and can be applied to various multilayer substrates used for electronic devices such as a multilayer circuit wiring substrate.

(Electronics)
FIG. 11 is a perspective view showing an example of an electronic apparatus according to the invention.
A cellular phone 1300 shown in this figure includes a display portion 1301, a plurality of operation buttons 1302, an earpiece 1303, and a mouthpiece 1304, and high-density mounting is realized in the housing by the stacked semiconductor device of the present invention. Yes.

  The stacked semiconductor device of the present invention is not limited to the above mobile phone, but an electronic book, a personal computer, a digital still camera, a video monitor, a viewfinder type or a direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, It can also be suitably used for electronic devices such as calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Such an electronic device is excellent in reliability.

  As described above, the preferred embodiments according to the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the examples. It is obvious for those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims. It is understood that it belongs to.

1 is a cross-sectional view schematically showing a stacked semiconductor substrate according to the present invention. The perspective view which shows the structural example of a spacer (insulating member). The figure which shows the other example of a structure of a spacer (insulating member). The figure which shows the other example of a structure of a spacer (insulating member). The figure which shows the other example of a structure of a spacer (insulating member). FIGS. 5A to 5D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. FIGS. 5A to 5D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. The figure for demonstrating the formation method of the insulating film using the inkjet method with respect to a through-hole. The figure which shows a mode that a predetermined | prescribed process is performed with respect to a wafer. (A)-(D) are the figures which show the method of repeating the filling process and drying process of a metal ink in multiple times. FIG. 11 is a perspective configuration diagram illustrating an example of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 20 ... Interposer substrate (first substrate), 21, 51 ... Electrode, 30 ... First semiconductor chip (second substrate), 32, 42 ... Through-hole, 33, 43 ... Insulating film, 40 ... First 2 semiconductor chip (third substrate), 50... Third semiconductor chip (fourth substrate), 60... Penetrating electrode, 65, 66, 67 .. spacer (insulating member), 72, 73.

Claims (21)

A method for manufacturing a laminated substrate including a first substrate on which an electrode is formed and a second substrate on which a through hole is formed,
Disposing an insulating member for forming a gap on at least one of the first substrate and the second substrate;
Aligning the electrode of the first substrate and the through hole of the second substrate, and disposing the second substrate on the first substrate with the insulating member interposed therebetween;
Filling the inside of the through hole of the second substrate with ink containing metal particles using an ink jet method,
The method for manufacturing a laminated substrate, wherein the insulating member blocks the spread of the ink on the first substrate.   The method for manufacturing a multilayer substrate according to claim 1, wherein the insulating member has a shape surrounding an electrode of the first substrate or a through hole of the second substrate.   The method for manufacturing a laminated substrate according to claim 2, wherein the insulating member is provided with an opening for degassing when the ink is filled.   The method for manufacturing a laminated substrate according to claim 3, wherein the insulating member has a labyrinth structure.   The method for manufacturing a laminated substrate according to any one of claims 1 to 4, wherein an inkjet method or a photolithography method is used for arranging the insulating members.   A step of drying the ink disposed inside the through hole of the second substrate when the ink is filled in the through hole of the second substrate, and a step of further disposing the ink on the dry film of the ink; The method for manufacturing a multilayer substrate according to claim 1, wherein the method is repeated. The multilayer substrate further includes a third substrate in which a through hole is formed,
Disposing another insulating member for gap formation on at least one of the second substrate and the third substrate;
Positioning the through hole of the second substrate and the through hole of the third substrate, and disposing the third substrate on the second substrate with the insulating member interposed therebetween;
Filling an ink containing metal particles into the through hole of the third substrate using an inkjet method,
The method for manufacturing a laminated substrate according to claim 1, wherein the insulating member blocks a spread of the ink on the second substrate. The laminated substrate further includes a fourth substrate on which an electrode is formed,
Disposing the insulating member for gap formation on the third substrate;
A step of aligning the through hole of the third substrate and the electrode of the fourth substrate and disposing the fourth substrate on the third substrate with the insulating member interposed therebetween. ,
The method for manufacturing a laminated substrate according to claim 7, wherein the insulating member blocks the spread of the ink on the third substrate.   9. The laminated substrate according to claim 8, wherein a dry film of the ink having a shape raised from the through hole of the third substrate is formed when the ink is filled into the through hole of the third substrate. Production method.   The method for manufacturing a multilayer substrate according to any one of claims 1 to 9, wherein at least one of gold, silver, and copper is used as the metal particles.   The method for producing a laminated substrate according to any one of claims 1 to 10, wherein the step of baking the ink containing metal particles is performed for each lamination of one substrate.   The method for producing a laminated substrate according to any one of claims 1 to 10, wherein the step of baking the ink containing metal particles is performed collectively after laminating a plurality of substrates.   The method for manufacturing a multilayer substrate according to claim 1, wherein the second substrate is a semiconductor chip.   The method for manufacturing a laminated substrate according to claim 13, wherein the insulating member is arranged in a wafer state.   A stacked semiconductor device manufactured using the method according to claim 1.   An electronic apparatus comprising the stacked semiconductor device according to claim 15. A support substrate having electrodes;
A first semiconductor chip having a through hole and disposed on the support substrate;
A through electrode formed inside the through hole of the first semiconductor chip and electrically connected to the electrode of the support substrate;
A stacked semiconductor device comprising: a spacer sandwiched between the support substrate and the first semiconductor chip and having a shape surrounding an electrode of the support substrate or a through hole of the first semiconductor chip.   The stacked semiconductor device according to claim 17, wherein the spacer is in close contact with the support substrate and the first semiconductor chip, and an opening is provided in a side portion.   The stacked semiconductor device according to claim 18, wherein the spacer has a labyrinth structure. A second semiconductor chip having a through hole and disposed on the first semiconductor chip;
A through electrode formed inside the through hole of the second semiconductor chip and electrically connected to the through electrode of the first semiconductor chip;
And a spacer sandwiched between the first semiconductor chip and the second semiconductor chip and having a shape surrounding the through hole of the first semiconductor chip or the through hole of the second semiconductor chip. The stacked semiconductor device according to any one of claims 17 to 19. A third semiconductor chip having electrodes and disposed on the second semiconductor chip;
And further comprising another spacer sandwiched between the second semiconductor chip and the third semiconductor chip and having a shape surrounding the through hole of the second semiconductor chip or the electrode of the third semiconductor chip. The stacked semiconductor device according to claim 20.

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