JP2007005945A - Receiving circuit, and wireless lan system and offset correction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DC offset method of a differential amplifier circuit, and a receiving circuit and a wireless LAN system provided with a DC offset correction circuit. <P>SOLUTION: A frequency conversion circuit down-converts an output signal of a variable gain amplifying circuit for amplifying a high frequency signal received by an antenna. A signal measurement circuit generates a reception level strength detection signal from the down-converted signal to produce a gain control signal for the variable gain amplifying circuit. The differential amplifying circuit used for the signal measurement circuit is provided with the offset correction circuit that receives differential output signals from the differential amplifying circuit to produce a correction voltage for decreasing a DC offset of the differential amplifying circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a receiver circuit, a wireless LAN system, and an offset correction method. For example, the present invention is used for a DC offset adjustment technique of a signal measurement circuit that detects the intensity of a received signal and forms a gain control signal of the variable gain amplifier circuit. It relates to effective technology.

  Wireless LAN systems currently in practical use are analog high frequency ICs that have a frequency conversion circuit and an amplification circuit that down-convert received signals and up-convert transmitted signals, demodulators that demodulate received signals, and modulate transmitted signals. A modulator, an IC chip such as a baseband IC that restores received data from demodulated I and Q signals or generates I and Q signals before modulation based on transmission data, and power amplifies the transmission signal It is often composed of electronic components such as a power module composed of a power amplifier circuit (power amplifier) and an impedance matching circuit for driving an antenna, a front-end module equipped with a transmission / reception changeover switch and a filter circuit for removing unnecessary waves, etc. .

The wireless LAN reception system circuit includes a variable gain amplification circuit that amplifies a high-frequency signal received by an antenna, a frequency conversion circuit that down-converts the received signal to a low-frequency signal, and detects the intensity of the received signal. And a signal measuring circuit for forming a gain control signal of the variable gain amplifier circuit. This signal measurement circuit (RSSI) is designed so that temperature characteristics and power supply dependency are minimized at the time of design. Japanese Patent Laid-Open No. 2002-190789 discloses a received electric field strength compensation method that corrects an RSSI detection error using a correction parameter. As a reception level detection device that corrects an RSSI detection error using a table, there is a technique. There is an open 2004-228836 publication.
JP 2002-190789 A JP 2004-228836 A

  The inventor of the present application studied using a CMOS circuit as the signal measurement circuit. In a circuit using a MOSFET, the characteristic variation due to the process balance of the differential element is large, and it is necessary to adjust the characteristic. However, in Patent Documents 1 and 2, there is no consideration for adjusting the DC offset in the differential amplifier circuit. This is considered to be because there was no necessity for the adjustment of the DC offset itself. Therefore, the inventors of the present application have studied to automatically adjust the DC offset of the differential amplifier circuit toward the CMOS circuit of the receiving circuit, and have arrived at the present invention.

  An object of the present invention is to provide a DC offset correction method for a differential amplifier circuit, a receiving circuit including a DC offset correction circuit, and a wireless LAN system. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. The output signal of the variable gain amplifier circuit that amplifies the high-frequency signal received by the antenna is down-converted by the frequency conversion circuit. A signal measurement circuit forms a reception level strength detection signal from the down-converted signal to form a gain control signal for the variable gain amplifier circuit. The differential amplifier circuit used in the signal measuring circuit is provided with an offset correction circuit that receives the differential output signal of the differential amplifier circuit and forms a correction voltage for reducing the DC offset of the differential amplifier circuit.

  The outline of other representative ones of the inventions disclosed in the present application will be briefly described as follows. In a wireless LAN system including a transmission circuit of a reception circuit, an output signal of a variable gain amplification circuit that amplifies a high-frequency signal received by an antenna is down-converted by a frequency conversion circuit. A reception level strength detection signal is formed from the down-converted signal by the signal measurement circuit to form a gain control signal for the variable gain amplifier circuit. The differential amplifier circuit used in the signal measuring circuit is provided with an offset correction circuit that receives the differential output signal of the differential amplifier circuit and forms a correction voltage for reducing the DC offset of the differential amplifier circuit.

  It is possible to measure the reception level with high accuracy. A wireless LAN system capable of performing optimum signal amplification corresponding to the reception level can be realized.

  FIG. 1 shows a block diagram of an embodiment of a measurement circuit according to the present invention. The measurement circuit of this embodiment is provided in a reception system circuit in a wireless LAN as will be described later. That is, an LNA (low noise amplification circuit) that amplifies a high frequency signal received by an antenna, a frequency conversion circuit that downconverts the received signal to a low frequency signal, and the variable gain by detecting the intensity of the received signal. In a reception system circuit including a signal measurement circuit that forms a gain control signal of an amplification circuit, the signal measurement circuit is used.

  The measurement circuit 12 of this embodiment includes the following circuit blocks. The down-converted received signal is input to a low-pass filter (hereinafter referred to as LPF) 181. Here, the adjacent signal or non-adjacent signal is removed from the received signal, and the target signal is extracted. The extracted target signal is amplified and detected by the amplifiers & detection circuits 233 and 234. The amplifier & detector circuit is divided into a front circuit 233 and a rear circuit 234. An offset correction switching circuit 231 is provided for the preceding amplifier & detection circuit 233, and an offset correction switching circuit 232 is provided for the subsequent amplifier & detection circuit 234. The detection outputs of the amplifier & detection circuits 233 and 234 are output through the output circuit 239 as a detection signal RSSIOUT. The comparator switching circuit 235 switches between the differential output of the preceding amplifier & detection circuit 233 and the differential output of the subsequent amplifier & detection circuit 234 and inputs it to the comparator 238. The comparator 238 transmits the offset positive / negative determination output to the control circuit 240. The offset correction switching circuits 231 and 232 are provided with offset correction circuits 236 and 237, respectively, and generate a correction voltage according to a correction signal from the control circuit 240.

  The normal mode of the measurement circuit 12 of this embodiment is as follows. The control signal RSCALEN = L (low level) input from the control circuit 240 is set. The switches S1 and S2 of the offset correction switching circuit 231 are opened and the signals S3 and S4 are closed by the control signal RSCALEN, and the signal that has passed through the LPF 181 is AC-coupled by the capacitors C1 and C2 and sent to the amplifier & detector circuit 233. It is done. In addition, the switches S1 and S2 of the offset correction switching circuit 232 are opened and the switches S3 and S4 are closed by the control signal RSCALEN = L, and the output signal of the preceding circuit 234 is AC-coupled by the capacitors C1 and C2. It is sent to the amplifier & detector circuit 234.

  If the signal level is within the dynamic range of each amplifier, the amplifier & detector circuits 233 and 234 amplify the gain and pass the signal to the subsequent amplifier. The output of each amplifier is full-wave rectified and VI-converted as a DC component. The VI conversion output of each stage is integrated, converted into a voltage by the output circuit, and output from the output terminal RSSIOUT. As described above, the amplifier & detector circuits 233 and 234 are divided into blocks of four 10 dB amplifiers, and the inputs of the blocks 233 and 234 are biased by the offset correction circuits 231 and 232.

  The offset adjustment mode of the measurement circuit 12 of this embodiment is as follows. In the DC offset adjustment mode from the control circuit 240 to the preamplifier & detection circuit 233, the control signal RSCALEN = H (high level) and the control signal RSCALSEL = L (low level). With the control signal RSCALEN, the switches S1, S2 are closed, the switches S3, S4 are opened, the LPF 181 and the amplifier & detector circuits 233, 234 are cut off, and the blocks of the amplifier & detector circuits 233, 234 are offset correction circuits 236, 237 biased. In the pre-stage DC offset adjustment mode, the differential output of the pre-stage amplifier & detector circuit 233 is selected by the control signal RSCALSEL and input to the comparator 238, and the DC offset is determined as positive or negative (large or small). This determination result is output as an output signal RSADCOUT1. The control circuit 240 sequentially controls RSCAL04 to RSCAL00 so as to minimize the DC offset while monitoring the output signal RSADCOUT1. Since the amplifier & detection circuit 233 also detects the in-phase component and reflects it in the RSSI output, the DC offset correction circuit 236 changes the DC offset without causing the fluctuation of the in-phase component as will be described later.

  In the DC offset adjustment mode from the control circuit 240 to the post-stage amplifier & detection circuit 234, the control signal RSCALEN = H (high level) and the control signal RSCALSEL = H (high level). Similarly to the above, when the switches S1 and S2 are closed and the switches S3 and S4 are opened, the LPF 181 and the amplifier & detector circuits 233 and 234 are cut off. The blocks of the amplifier & detector circuits 233 and 234 are offset correction circuits 231 and 232, respectively. Biased by In the post-stage DC offset adjustment mode, the differential output of the post-stage amplifier & detector circuit 234 is selected by the control signal RCALSEL and input to the comparator 238, and the DC offset is determined as positive or negative (large or small). This determination result is output as an output signal RSADCOUT1. The control circuit 240 sequentially controls RSCAL14 to RSCAL10 so as to minimize the DC offset while monitoring the output signal RSADCOUT1. Since the amplifier & detector circuit 234 also detects the in-phase component and reflects it in the RSSI output, the DC offset correction circuit 237 similarly changes the DC offset without causing the fluctuation of the in-phase component as described later.

  FIG. 2 shows a flowchart of the offset adjustment mode, and FIG. 3 shows a timing diagram. As shown in FIG. 3, the control signals RSPON, RSADCPON, and RSCALEN are set to the high level to set the offset adjustment mode, and the control signal RASCALSEL is set to the low level to start the adjustment of the amplifier / detection circuit 233 on the preceding stage side.

  The correction signal RSCAL0 [RSCAL04 to 00: 10000] is set. In this state, if the determination result RSADOUT1 of the differential output of the amplifier & detector circuit 233 is low level (L), RSCAL04 is changed to low level (0). If the determination result RSADOUT1 is at a high level (H), RSCAL04 is maintained at a high level (1). In response to the result X, the most significant (fifth) bit is determined to be X (0 or 1) and is set to the correction signal RSCAL0 [RSCAL04 to 00: X1000].

  If the determination result RSADOUT1 of the differential output of the amplifier & detector circuit 233 is low level (L) in the state of the correction signal RSCAL0 [RSCAL04 to 00: X1000], RSCAL03 is changed to low level (0). If the determination result RSADOUT1 is at high level (H), RSCAL03 is maintained at high level (1). In response to the result X, the fourth bit becomes X, and the correction signal RSCAL0 [RSCAL04-00: XX100] is obtained.

  If the determination result RSADOUT1 of the differential output of the amplifier & detector circuit 233 is low level (L) in the state of the correction signal RSCAL0 [RSCAL04 to 00: XX100, RSCAL02 is changed to low level (0). If the determination result RSADOUT1 is at a high level (H), RSCAL02 is maintained at a high level (1). In response to the result X, the third bit becomes X, and the correction signal RSCAL0 [RSCAL04-00: XXX10] is obtained.

  If the determination result RSADOUT1 of the differential output of the amplifier & detector circuit 233 is low level (L) in the state of the correction signal RSCAL0 [RSCAL04 to 00: XXX10, RSCAL01 is changed to low level (0). If the determination result RSADOUT1 is at a high level (H), RSCAL01 is maintained at a high level (1). In response to the result X, the second bit becomes X, and the correction signal RSCAL0 [RSCAL04-00: XXXX1] is set.

  Then, in the state of the correction signal RSCAL0 [RSCAL04 to 00: XXX1], if the determination result RSADOUT1 of the differential output of the amplifier & detector circuit 233 is low level (L), RSCAL00 is changed to low level (0). If the determination result RSADOUT1 is at a high level (H), RSCAL01 is maintained at a high level (1). In response to the result X, the first bit becomes X, and all bits are determined in the correction signal RSCAL0 [RSCAL04-00: XXXX].

  In FIG. 3, the control signal RASCALSEL is set to the high level, and the offset adjustment mode of the amplifier / detection circuit 234 on the rear stage side is started. Although omitted in FIG. 2, as can be understood from the timing chart of FIG. 3, the correction signal RSCAL1 [RSCAL14 to 10: XXXXXX] is performed by the same operation as the offset adjustment mode of the amplifier and detector circuit 233 on the preceding stage side. ] Are determined.

  The offset voltage generated by the correction signal RSCAL0 [RSCAL04 to 00: XXXX] and the correction signal RSCAL0 [RSCAL14 to 10: XXXX] is reduced according to the binary weight. For example, when the offset voltage formed by RSCAL 04 and 14 is the largest voltage ΔV, the offset voltage formed by RSCAL 03 and 13 is ΔV / 2, and similarly corresponds to RSCAL 02 and 12 to 00 and 10 Each correction voltage is set to ΔV / 4, ΔV / 8, and ΔV / 16. Accordingly, for example, setting of the optimum offset voltage from among 32 kinds of offset correction voltages can be completed in a single time such as 5 steps.

  FIG. 4 is a schematic block diagram showing an embodiment of a wireless LAN system according to the present invention. FIG. 1 exemplarily shows a portion related to a measurement circuit that detects the intensity of a received signal in the wireless LAN system. The baseband integrated circuit BBIC forms a control signal for controlling the entire operation of the wireless LAN. The control circuit 240 receives the transmission / reception switching control signal and the DC offset calibration control signal. The control signal as described above for the measurement circuit (RSSI) 12 is formed. For example, the BBIC 250 gives a DC offset calibration command to the RSSI control circuit 240, and the RSSI control circuit 240 performs DC offset calibration of the measurement circuit 12 using the command as a trigger. Also, DC offset calibration is performed using a change in the transmission / reception switching signal as a trigger.

  FIG. 5 is an explanatory diagram of the DC offset calibration operation according to the present invention. FIG. 5A shows that a DC offset calibration operation is performed by a DC offset calibration control signal from the BBIC 250. That is, when a DC offset calibration control signal is given to the RSSI control circuit 240, a DC offset calibration operation is performed each time.

  In FIG. 5B, DC offset calibration is performed using a change in the transmission / reception switching signal as a trigger, the transmission mode is switched to the reception mode, and the DC offset calibration operation is performed at the beginning of the reception mode. . Therefore, in this example, the packet reception operation is performed after the end of the DC offset calibration operation.

  In FIG. 5C, an offset calibration control signal is generated during the transmission mode before the transmission mode is switched to the reception mode, and the DC offset calibration operation is performed. Therefore, in this example, when the reception mode is set, the packet reception operation is performed without waiting for the end of the DC offset calibration operation as in (B). Thereby, the DC offset calibration operation can be optimally performed without sacrificing the operation speed.

  FIG. 6 shows a circuit diagram of an embodiment of the offset correction circuits 236 and 237 of FIG. One end of a pair of resistors R1 is connected to the power supply voltage VCC. Although not particularly limited, a resistor Rr having a large resistance value is provided between the other end nodes A and B of the resistor R1. The resistor Rr is connected in series and a minute resistor r is provided in parallel. Switch MOSFETs M1 to M7 are provided between the connection point of the resistor R1 and the resistor r, the interconnection point (tap) of the resistor r, and the current source Io. In the switch MOSFETs M1 to M7, the switch MOSFET at any one connection point (tap) is turned on by a selection signal formed by a decoder that decodes the adjustment code. One tap is selected by any one of the switch MOSFETs M1 to M7 so that the current of the current source Io flows. Since the current of the current source Io flows through the selected tap, a current flows corresponding to the resistance ratio between the selected tap and the power supply voltage VCC, and a potential difference ( Offset correction voltage). The bias voltage including the offset correction voltage of the nodes A and B is supplied to the differential input (+) (−) of the differential amplifier through the bias resistor R2. A signal is input to the differential input (+) (−) through a coupling capacitor.

  The principle of this offset correction circuit is similar to that of the balance scale. First, the tap corresponding to the midpoint is selected (the balance is placed with the same weight on the balance scale), and in that state, the amplifier & detector circuit The differential output size determination (unbalance determination) is performed, an adjacent tap that corrects the differential output is selected, and the tap is moved until the differential output size determination output is inverted (reversed). Thus, the DC offset calibration is performed.

  At this time, in the offset correction circuit of this embodiment, when a correction voltage of + ΔV is applied to the node A, a complementary correction voltage such as −ΔV is applied to the node B. In such a configuration in which complementary correction voltages + ΔV and −ΔV are applied to both differential inputs (A, B), the operating point of the differential amplifier circuit does not move, so the offset voltage is applied to one input. As in the case of adding, there is no problem of moving the operating point of the differential amplifier circuit and narrowing the input dynamic range. Or DC offset calibration with few in-phase components can be implemented. Such a DC offset canceling method of the differential amplifier can be widely used as a DC offset canceling method that does not narrow the input dynamic range or a DC offset canceling method that has few in-phase components.

  FIG. 7 shows a circuit diagram of another embodiment of the offset correction circuits 236 and 237 of FIG. One end of a pair of resistors R1 is connected to the power supply voltage VCC. The other end nodes A and B of the resistor R1 are provided with a current source I1 for determining the bias center and binary weighted current sources I0, 2I0 and 4I0 for binary adjustment, and binary adjustment codes B0, B1, The offset adjustment between A and B is performed by controlling on / off of the current sources I0, 2I0 and 4I0 weighted by B2. At this time, when the on / off control of the current sources I0, 2I0, 4I0 on the node B side is controlled by the adjustment codes B0, B1, B2, the adjustment codes B0, B1, B2 are inverted by the inverter circuits NV0-NV2 and the nodes Controls ON / OFF of the current sources I0, 2I0, 4I0 on the A side. Thereby, the current sources I0, 2I0 and 4I0 of the nodes A and B are complementarily turned on / off. In this embodiment, as described with reference to FIGS. 2 and 3, the optimum correction voltage can be formed in three steps in this example by determining sequentially from the upper bit B2. Therefore, the circuit scale can be reduced and the setting time can be shortened.

  Even in the offset correction circuit of this embodiment, when the current of the current source on one side flows, the current does not flow on the other side. Therefore, a correction voltage of + ΔV is applied to the node A when the half current is considered as a reference. Is applied to node B with a complementary correction voltage such as -ΔV. In such a configuration in which complementary correction voltages + ΔV and −ΔV are applied to both differential inputs (A, B), the operating point of the differential amplifier circuit does not move, so the offset voltage is applied to one input. As in the case of adding, there is no problem of moving the operating point of the differential amplifier circuit and narrowing the input dynamic range. Or DC offset calibration with few in-phase components can be implemented. The bias voltage including the offset correction voltage of the nodes A and B is supplied to the differential input (+) (−) of the differential amplifier through the bias resistor R2. A signal is input to the differential input (+) (−) through a coupling capacitor. Such a DC offset canceling method of the differential amplifier can be widely used as a DC offset canceling method that does not narrow the input dynamic range or a DC offset canceling method that has few in-phase components.

  FIG. 8 shows an embodiment of a differential amplifier constituting the amplifier & detector circuits 233 and 234 used in the present invention. This differential amplifier is a fully differential amplifier having IN (+) and IN (−) as inputs and OUTN and OUTP as outputs. The differential input is input to IN (+) and IN (−), and based on the input, an output voltage based on the ratio of the current flowing through the resistor R and each input transistor is obtained differentially from the outputs OUTN and OUTP.

  FIG. 9 shows an embodiment of the comparator 238 used in the present invention. In the comparator 238, the differential outputs of the amplifier & detector circuits 233 and 234 of FIG. 1 are input to the YIN and XIN terminals, respectively, and the output of the amplifier 500 is a digital signal in synchronization with the clock RSADCON from the terminal ADCON by a quantizer. And an output signal RSADOUT1 is generated from the OUT1 terminal.

  FIG. 10 is a block diagram showing an embodiment of an RF processing unit (high frequency IC) and a baseband processing unit (baseband LSI) of a wireless LAN system suitable for application of the present invention. In the figure, components other than the RF processing unit 41 and the baseband processing unit 42 are omitted. In an actual wireless LAN system, the transmission amplifier 40 is configured as a module (power module) on an insulating substrate such as a ceramic substrate together with an impedance matching circuit and a filter for removing harmonics. Although not particularly limited, the circuit for forming the high frequency IC (41) is formed on one semiconductor substrate such as SiGe, and the baseband LSI (42) is a circuit using CMOS on one semiconductor substrate such as silicon. It is formed.

  With the above configuration, the RF processing unit 41 can easily obtain an operation speed for performing up-conversion and down-conversion operations, and the baseband processing unit 42 can operate with low power consumption. In addition, a band-pass filter that removes unnecessary waves from the received signal is provided between the antenna changeover switch 60 and the RF processing unit 41. This band-pass filter is not a narrow band filter such as a SAW filter, but may be a filter having a bandwidth of several hundreds of MHz composed of a capacitive element and an inductor element. The antenna changeover switch 60 and the band pass filter are configured as a module (front end module) on an insulating substrate separate from the power module. These modules, the RF processing unit (high frequency IC) 41, and the baseband processing unit (baseband LSI) 42 are mounted on one printed circuit board to constitute a wireless LAN system.

  The transmission / reception operation in the wireless LAN of this embodiment is as follows. Received signals are received from the receiving antennas 1a and 1b, amplified by an LNA (low noise amplifier) 4, converted to an intermediate frequency by a first stage mixer 6, amplified by an IF amplifier 5, and further a second stage mixer. The signals are converted into baseband signals by 7a and 7b. Thereafter, the interference signal is removed by the LPF / PGAs 11a and 11b and amplified so that the target signal is at an appropriate level. The I and Q signals are separately transmitted to the baseband processing unit and demodulated by the demodulation circuit 39. The transmission signal is a baseband signal generated by the modulation circuit 33, passes through the transmission baseband LPFs 31a and 31b, is frequency-converted to the target RF frequency by the transmission first stage mixer 30 and the transmission second stage mixer 29, Amplified by the transmission amplifier 40 and transmitted from the transmission antenna 28.

  The reception level adjustment operation is as follows. An AGC (Automatic Gain Control 1) is used as a mechanism for adjusting the level of the receiving side I and Q baseband signals. For the signal level measurement for this purpose, the first measurement circuit 12 and the second measurement circuit 13 are used. The first measurement circuit (measurement circuit 1 in FIG. 10) 12 uses the first measurement circuit 12 to remove the interference signals from the outputs 26 and 27 of the receiving system second stage mixers 7a and 7b, and detects the signal level value. Logarithmically compress and output. The second measurement circuit (measurement circuit 2 in FIG. 10) 13 performs A / D conversion on the I and Q signals to be demodulated, and then measures the level with linearity.

  The output of the first measurement circuit 12 is A / D converted and sent to the control circuit 14 together with the output of the second measurement circuit 13. Based on the result, the gain setting value time-division data 18 is generated to generate the gain control circuit. 24, the gains of the LPF / PGAs 11a and 11b are controlled so that the I and Q signal levels become the target levels. In the gain control circuit 24, the gain setting value time division data 18 received from the control circuit 14 is controlled by the gain control circuit 24 under the control of the mode control signal 25 and the DC offset cancel control 19 generated by the control circuit 14. , IF amplifier control signal 16, PGA gain set value data 17 and gain control signal 20 are developed and applied to LNA 4, IF amplifier 5 and LPF / PGA 11a, 11b, respectively, and the input level to ADC 50a, 50b of baseband processing unit 42 Adjust the gain so that is optimal.

  The transmission / reception circuit adjustment operation is as follows. The transmission / reception circuit has characteristic variations due to element variations and the like. Characteristic variation causes characteristic deterioration such as DC offset and IQ imbalance, and affects communication quality. For this reason, before performing the transmission / reception operation, these characteristic balances are adjusted as preprocessing. The procedure is described below.

<Reception system DC offset correction>
(1) MPXs (multiplexers) 48a and 48b provided at the inputs of the LFG / PGAs 11a and 11b are set to no signal.
(2) The gains of the LFG / PGAs 11a and 11b are set to 0 dB.
(3) The DC offset automatic calibration of the LFG / PGAs 11a and 11b is performed.
(4) The digital baseband processing unit 42 corrects the residual DC offset by the correction circuits 53 and 54 after the ADCs 50a and 50b.

<Transmission system DC offset correction>
(5) The MPX 48a provided at the input of the LPF / PGA 11a, 11b is set to be connected to the baseband LPF output of the transmission system 31a, and the MPX 48b is set to be connected to the baseband LPF output of the transmission system 31b. To do.
(6) The transmission circuit is cut off by the correction circuits 55 and 56 to make it untrustworthy.
(7) The second measurement circuit 13 of the baseband processing unit 42 observes the DC offset at the outputs of the ADCs 50a and 50b, and adjusts the transmission system DC offset by the correction circuits 55 and 56 so that the DC offset becomes zero. To do.

<RX gain imbalance calibration>
(8) The modulation circuit 33 of the digital base / band processing unit 42 sets the input code to the DACs 51a and 51b to a fixed value so that a DC signal is generated from the DACs 51a and 51b. (9) Either of the MPX 48a or 48b, the output of the LPF 31a and the output of the LPF 31b are alternately connected, the level difference is observed by the second measurement circuit 13, and the baseband processing unit 42 so that the level difference is eliminated. In the correction circuits 55 and 56, the gain is adjusted.

<RX dyne imbalance calibration>
(10) In both the MPX 48a and 48b, either the output of the LPF 31 or the output of the LPF 31b is connected simultaneously, the level difference is observed by the second measurement circuit 13, and the baseband is set so that the level difference is eliminated. The gain is adjusted by the correction circuits 53 and 54 of the processing unit 42.

<First measurement circuit correction>
(11) The DC offset adjustment of the first measurement circuit 12 is performed using the internal automatic adjustment function. This DC offset adjustment is performed according to the operation procedure as shown in FIGS.
(12) The MPXs 47a and 47b are set to be connected to the output sides of the second mixers 7a and 7b and the LPFs 31a and 31b.
(13) Test signals having different signal levels are generated from the modulation circuit 33 of the baseband processing unit 42, the output of the first measurement circuit 12 is observed by the control circuit 14, and the first measurement circuit 12 corresponding to each signal level is observed. Is stored as a correspondence relationship (table) with the output voltage. During the actual reception operation, the reception signal level corresponding to the output voltage of the first measurement circuit 12 is estimated according to this table.

  FIG. 11 shows a block diagram of an embodiment of the LPF / PGA of FIG. In the LPF / PGA 11 (a, b), LPF (Low Pass Filter) 101, 103, 105 and PGA (Programmable Gain Amp) 102, 104, 106 are alternately connected. Each PGA 102, 104, 106 is gain controlled by PGA gain setting data 17. The DC offset cancel control signal 20 is used to cancel a DC offset that occurs when switching the gain of the PGA.

  FIG. 12 is a characteristic diagram of each stage corresponding to the LPF / PGA of FIG. For example, in IEEE 802.11a, it is necessary to allow up to +16 dB for adjacent interference signals and +32 dB for non-adjacent interference signals with respect to the target signal. For this reason, in amplifying the target signal to the target signal level, it is necessary to prevent saturation of the circuit due to the disturbing signal. For this reason, the necessary LPF and PGA characteristics are divided into, for example, three stages, and are arranged alternately like LPF 101, PGA 102, LFP 103, PGA 104, LFP 105, and PGA 106 in the same manner as in FIG.

  When a signal in which a target signal, adjacent interference, and non-adjacent interference are mixed as an input signal, the interference signal is first removed to some extent by the LPF 101 and then amplified by the PGA 102. Next, the interference signal is further removed through the LPF 103 and further amplified by the PGA 104. Similarly, interference signal removal by the LPF 105 and amplification by the PGA 106 are performed so that the target signal has a target signal level. At this time, by controlling the interference blocking characteristics of the LPFs 101, 103, and 105 and the gains of the PGAs 102, 104, and 106, the target signal can be amplified without saturating the circuit through which the signal passes.

  FIG. 13 shows a block diagram of an embodiment of the PGA and DC offset casser circuit. The DC offset cancel voltage for each gain of the ADC (analog / digital converter) 142 for A / D conversion of the DC offset voltage, the DAC (digital / analog converter) 141 for generating the DC offset cassels voltage, and the PGA 125 is obtained. It has a memory 144 for storing data to be given to the DAC 141 for generation and a DC offset cancel control circuit 143. A DC offset cancel control signal 20 and PGA gain set value data 17 for controlling DC offset cancellation are input from the outside.

  Under the control of the DC offset cancel control signal 20, the ADC 142 performs A / D conversion on the DC offset value generated in the PGA 125. The DC offset cancel control circuit 143 outputs a voltage for canceling the DC offset subjected to A / D conversion from the DAC 141 and cancels it. In order to shorten the A / D conversion, D / A conversion, and DC offset calibration time, DC offset calibration is performed in advance for all gains of the PGA 125 in addition to the time of signal reception, and data to be given to the DAC 141 for each gain is stored in the memory 144. Remember to put on. At the time of signal reception, the DC offset calibration time at the time of signal reception can be shortened by supplying DC offset cancellation data to the DAC 141 simultaneously with the gain selection of the PGA 125 and performing instantaneous DC offset calibration.

  FIG. 14 is a block diagram showing another embodiment of the PGA according to the present invention. The PGA (Programmable Gain Amp) of this embodiment can be configured by switching and selecting a plurality of AMPs (amplifiers) 167, 168, 169 having different gains by switches 163, 170. Since each AMP 167, 168, 169 has a DC offset independently, a different DC offset voltage is generated for each gain switching. For this reason, the offset cancellation of the PAG is omitted in the figure, but an offset cancellation circuit similar to that shown in FIG. 12 is provided, and DC offset calibration is performed in advance on the gains of the AMPs 167 to 169 in addition to the time of signal reception. The data to be given to the DAC 141 for each gain is stored in the memory 144. At the time of signal reception, the DC offset calibration time at the time of signal reception can be shortened by applying DC offset cancellation data to the DAC 141 in the same manner as described above simultaneously with the gain selection of the AMPs 167 to 169 and performing instantaneous DC offset calibration. .

  FIG. 15 shows a principle block diagram of the first measurement circuit of FIG. The first measurement circuit 12 includes an adder 180 for adding two I and Q inputs, an LFP 181 for removing an interfering signal, a detection circuit 182 for converting to a DC voltage, and a log amplifier 183 for logarithmic compression. Is done. With these configurations, the presence / absence of a signal and the signal level value can be measured over a wide range of input signal levels. The first measurement circuit 12 is provided with an offset cancel circuit as shown in FIG.

  FIG. 16 shows a block diagram of an embodiment of the control circuit of FIG. The control circuit 14 includes a processor 201 that executes a program, a program memory 202 that stores a program, a data memory 203 that temporarily stores a program execution result, an input port 204 that receives outputs from the first measurement circuit and the second measurement circuit, an external An output port 205 for outputting a signal for controlling the signal, and a bus 206 for coupling these modules. The control circuit 14 controls the operation of the entire system such as reception system gain control and transmission system circuit adjustment including control of the DC offset automatic calibration operation of the first measurement circuit 12 as described above.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, specific embodiments of the fully differential amplification used in the first measurement circuit can take various embodiments other than those shown in FIG. Similarly, the comparator shown in FIG. 9 can similarly take various embodiments. The present invention can be widely used in a DC offset method of a differential amplifier circuit as included in a reception level measurement circuit, a reception circuit including a DC offset correction circuit, and a wireless LAN system.

It is a block diagram which shows one Example of the measuring circuit based on this invention. It is a flowchart figure for demonstrating the offset adjustment mode of FIG. FIG. 2 is a timing chart for explaining an offset adjustment mode in FIG. 1. 1 is a schematic block diagram showing an embodiment of a wireless LAN system according to the present invention. It is explanatory drawing of DC offset calibration operation | movement which concerns on this invention. FIG. 2 is a circuit diagram showing an embodiment of the offset correction circuit of FIG. 1. FIG. 3 is a circuit diagram showing another embodiment of the offset correction circuit of FIG. 1. It is a circuit diagram which shows one Example of the differential amplifier used for this invention. It is a circuit diagram which shows one Example of the comparator used for this invention. It is a block diagram which shows one Example of the RF process part and baseband process part of a suitable wireless LAN system to which this invention is applied. It is a block diagram which shows one Example of LPF / PGA of FIG. FIG. 12 is a characteristic diagram of each stage corresponding to the LPF / PGA of FIG. 11. It is a block diagram which shows one Example of PGA and DC offset cancellation circuit. It is a block diagram which shows another Example of PGA used for this invention. FIG. 2 is a principle block diagram of a first measurement circuit in FIG. 1. FIG. 2 is a block diagram illustrating an embodiment of the control circuit of FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a, 1b ... Reception antenna, 4 ... LNA, 5 ... IF amplifier, 6, 7 ... Mixer, 11a, 11b ... LPF / PGA, 12 ... 1st measurement circuit, 13 ... 2nd measurement circuit, 14 ... Control circuit, 16 ... LNA, IF amplifier control signal, 17 ... PGA gain set value data, 18 ... Gain set value time division data & clock, 19 ... DC offset cancel control signal, 20 ... Gain control signal, 21 ... LPF output signal, 22 ... I Signal, 23 ... Q signal, 25 ... Mode control signal, 28 ... Transmission antenna, 29,30 ... Transmission mixer, 39 ... Demodulation circuit, 40 ... Transmission amplifier, 41 ... RF processing section, 42 ... Baseband processing section, 49, 50a, 50b ... ADC, 51 ... DAC, 52-56 ... correction circuit,
181 ... Low-pass filter, 231,232 ... Offset correction switching circuit, 233,234 ... Amplifier and detection circuit, 235 ... Comparator switching circuit, 236,237 ... Offset correction circuit, 238 ... Comparator, 239 ... Output circuit, 240 ... Control circuit .

Claims (10)

A variable gain amplification circuit for amplifying a high-frequency signal received by an antenna, and a frequency conversion circuit for down-converting the received signal to a low-frequency signal;
A signal measuring circuit that detects the intensity of the received signal and forms a gain control signal of the variable gain amplifier circuit;
The signal measurement circuit is
A differential amplifier circuit for amplifying the received signal down-converted by the frequency converter circuit;
An offset correction circuit for receiving a differential output signal of the differential amplifier circuit and forming a correction voltage for reducing a DC offset of the differential amplifier circuit;
The differential amplifier circuit is configured by a MOSFET,
The receiving circuit, wherein the offset correction voltage is supplied complementarily to both of the differential inputs of the differential amplifier circuit. In claim 1,
The offset correction voltage includes a pair of first resistors having one end connected to a predetermined voltage higher than a bias voltage applied to the differential input, and a plurality of offset resistors connected between the other ends of the pair of first resistors. A second resistor, a plurality of switches provided between a connection point between the first resistor and the second resistor, a connection point between the second resistors and the current source, and any one of the plurality of switches according to an offset correction signal. Formed by a bias voltage generation circuit composed of a control circuit for selecting one of them,
A receiving circuit, wherein a bias voltage formed at the other end of the pair of first resistors is transmitted to a differential input terminal of the differential amplifier circuit via a pair of third resistors. In claim 1,
The offset correction voltage is between a pair of first resistors whose one ends are connected to a predetermined voltage higher than a bias voltage applied to the differential input, and between the other ends of the pair of first resistors and a plurality of current sources. Formed by a bias voltage generation circuit including a plurality of switches respectively provided in the control circuit and a control circuit that selects the plurality of switches according to an offset correction signal and supplies a current that changes complementarily to the pair of first resistors,
A receiving circuit, wherein a bias voltage formed at the other end of the first resistor is transmitted to a differential input terminal of the differential amplifier circuit via a pair of third resistors. In claim 2,
The offset correction circuit is
In the first step, an output signal of the differential amplifier circuit is received, and a first correction voltage corresponding to the magnitude determination output is generated,
In the second step, the output signal of the differential amplifier circuit in a state where the first correction voltage is applied is received, and a second correction voltage smaller than the first correction voltage is generated corresponding to the magnitude determination output. Repeat multiple steps to
A receiving circuit which performs an offset calibration operation in which a correction voltage formed in the final step is set to a minimum voltage. In claim 3,
The offset correction circuit is
In the first step, an output signal of the differential amplifier circuit is received, and a first correction voltage corresponding to the magnitude determination output is generated,
In the second step, the output signal of the differential amplifier circuit in a state where the first correction voltage is applied is received, and a second correction voltage smaller than the first correction voltage is generated corresponding to the magnitude determination output. Repeat multiple steps to
A receiving circuit which performs an offset calibration operation in which a correction voltage formed in the final step is set to a minimum voltage. A variable gain amplification circuit for amplifying a high-frequency signal received by an antenna, and a frequency conversion circuit for down-converting the received signal to a low-frequency signal;
A signal measuring circuit that detects the intensity of the received signal and forms a gain control signal of the variable gain amplifier circuit;
A transmission circuit that forms a transmission signal and outputs it from an antenna;
The signal measurement circuit is
A differential amplifier circuit for amplifying the received signal down-converted by the frequency converter circuit;
And an offset correction circuit for performing an offset calibration operation for receiving a differential output signal of the differential amplifier circuit and forming a correction voltage for reducing a DC offset of the differential amplifier circuit. LAN system. In claim 6,
The wireless LAN system, wherein the offset calibration operation is performed according to a control signal input during a period in which the transmission circuit performs a transmission operation. In claim 7,
A baseband semiconductor integrated circuit having a processor, a program memory, a data memory, an input port, and an output port;
The wireless LAN system, wherein the control signal is formed by the baseband semiconductor integrated circuit.   An offset correction method comprising: supplying a DC offset correction voltage of a differential amplifier circuit complementarily to both differential inputs of a differential amplifier circuit. In claim 9,
The offset correction method is
In the first step, an output signal of the differential amplifier circuit is received, and a first correction voltage corresponding to the magnitude determination output is generated,
In the second step, the output signal of the differential amplifier circuit in a state where the first correction voltage is applied is received, and a second correction voltage smaller than the first correction voltage is generated corresponding to the magnitude determination output. Repeat multiple steps to
An offset correction method, wherein the correction voltage formed by the final step is set to the smallest voltage.

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