JP2006353026A - Motor driving device and electrical apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor driving device with simple and inexpensive construction while being capable of constantly carrying out appropriate advance angle control without depending on energization angle control of a motor, and an electrical apparatus using this motor driving device. <P>SOLUTION: The motor driving device includes means (mainly a waveform shaping unit 122a) for subjecting a Hall signal from a motor to predetermined signal processing and preliminarily generating a first driving signal with an energization angle of 120°, supplied with a desired advance angle amount P° and a second driving signal with an energization angle of 150°, and similarly supplied with the desired advance angle amount P°; and a selector unit 122b that selects and outputs either of the first and second driving signals as a motor driving signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a motor drive device that performs drive control of a motor that requires a large torque (such as a three-phase full-wave motor for a fan of an air regulator), and in particular, phase shift control and energization of each phase drive signal. It relates to angle control.

  In a motor drive device that performs drive control of a motor that requires a large torque, by intentionally advancing the phase of each phase drive signal applied to the motor coil with respect to the phase of the Hall signal detected by the Hall sensor, Control (so-called advance angle control) for increasing the output torque of the motor is generally performed.

  More specifically, a motor drive device that controls a three-phase motor basically supplies a three-phase drive signal in the same phase as the counter electromotive voltage signal generated in the motor coil. In order to realize the control, the motor hall sensor is usually placed at a position advanced by a predetermined phase (generally + 30 °) with respect to the motor coil. That is, a hall signal advanced by 30 ° is input to the motor drive device with respect to the counter electromotive voltage signal generated in the motor coil, and the motor drive device outputs each phase drive signal to the motor coil based on the hall signal. Was configured to generate.

However, the phase difference at which the output torque of the motor is maximized (or the phase difference for obtaining the motor characteristics required by the user) varies widely for each motor. For this reason, the conventional motor driving device appropriately adjusts the position of the Hall sensor so that a desired phase difference is obtained between the counter electromotive voltage signal generated in the motor coil and the Hall signal detected by the Hall sensor. (For example, see Patent Document 1).
JP 2000-134978 A (particularly paragraph [0020] etc.)

  Certainly, even with the above-described conventional motor driving device, the output torque of the motor can be maximized as long as the arrangement position of the Hall sensor is appropriately adjusted.

  However, the conventional motor driving device has a problem that when the energization angle switching control of the motor (for example, the energization angle 120 ° / 150 ° switching control) is performed, the appropriate advance angle control cannot be performed. In other words, in the conventional motor drive device, the arrangement position of the Hall sensor is adjusted with reference to one energization angle. Therefore, when the energization angle is switched to the other, the adjustment described above is flawed and output There was a risk that the torque would be reduced.

  Patent Document 1 discloses and proposes a technique for performing advance angle control using a microcomputer. However, this conventional technique is merely a technique for optimizing advance angle control during motor driving. However, it was not possible to solve the above problems. In addition, since the related art has a configuration that requires a microcomputer, if the configuration is applied to solve the above-described problem, there is a possibility that an unnecessary cost increase may be caused.

  In view of the above problems, the present invention provides a motor drive device capable of always performing appropriate advance angle control without relying on motor energization angle switching control, and a simple and inexpensive configuration, and An object of the present invention is to provide an electric device using the.

  In order to achieve the above object, a motor drive device according to the present invention performs a predetermined signal processing on a hall signal from a motor to provide a first drive signal having a conduction angle m ° given a desired advance amount P °. And a means for generating in advance a second drive signal having a conduction angle n (n> m) ° given the desired advance amount P °; and either one of the first and second drive signals. And a means for selectively outputting the motor drive signal as a motor drive signal (first configuration).

  Specifically, the motor driving device according to the present invention includes means for performing a predetermined signal processing on the hall signal from the motor to generate a reference driving signal having a conduction angle m °; Means for generating a first element signal having an energization angle m ° phase-shifted from the reference drive signal by (P + α) ° by performing signal processing that is further advanced by α ° than the angular amount P °; means for generating a second element signal having a conduction angle m ° phase-shifted by P ° from the reference drive signal, and performing signal processing for further delaying the second element signal by α °. And means for generating a third element signal phase-shifted from the reference drive signal by (P−α) °; performing a logical OR operation on the first and third element signals to obtain a conduction angle n (= m + 2α) ° Means for generating a fourth element signal; Means for selectively outputting the second element signal as a motor drive signal if it should be, and means for selectively outputting the fourth element signal as a motor drive signal if the conduction angle should be n °. (Second configuration).

  More specifically, the motor driving device according to the present invention includes a combining unit that performs predetermined signal processing on the hall signal from the motor to generate a reference driving signal having a conduction angle m °; A first drive signal of energization angle m ° given a desired advance amount P ° and a second drive signal of energization angle n (n> m) ° given a desired advance angle P °. A waveform shaping unit to be generated; a selector unit that selectively outputs one of the first and second drive signals as a motor drive signal; a multiplication unit that multiplies the Hall signal; and an output pulse of the multiplication unit A counter unit that counts the number; a decoder unit that decodes the advance amount setting signal into a set value that can be compared with the count value in the counter unit; and the count value in the counter unit matches the set value in the decoder unit Whether or not both A coincidence determination unit that generates a first trigger signal that is triggered when the first trigger signal is generated; a first shift unit that generates a second trigger signal obtained by delaying the first trigger signal by α °; and a first trigger signal that is 2α ° And a second shift unit that generates a third trigger signal delayed by a predetermined amount, and the waveform shaping unit uses the first trigger signal to convert the reference drive signal to a desired advance amount P °. Means for generating a first element signal having a conduction angle m ° phase-shifted by (P + α) ° from the reference drive signal, and performing signal processing that is further advanced by α ° than the reference drive signal; Means for delaying the one element signal by α ° and generating a second element signal having a conduction angle m ° phase-shifted by P ° from the reference drive signal; and using the third trigger signal, Apply signal processing to further delay the element signal by α ° Means for generating a third element signal phase-shifted by (P−α) ° from the reference drive signal; performing a logical sum operation on the first and third element signals, and a fourth current angle n (= m + 2α) ° Means for generating an element signal; and a second element signal is output as a first drive signal while a fourth element signal is output as a second drive signal (third structure). It is said.

  An electric apparatus according to the present invention includes the motor driving device having any one of the first to third configurations and a motor that is driven and controlled by the motor driving device.

  If the motor drive device according to the present invention and an electric device using the same are used, it is possible to always perform appropriate advance angle control without relying on motor energization angle switching control, while having a simple and inexpensive configuration. Become.

  Hereinafter, the case where the present invention is applied to a motor drive device that performs drive control of a three-phase full-wave motor will be described in detail. FIG. 1 is a block diagram (partly including a circuit diagram) showing an embodiment of a motor drive device according to the present invention. As shown in this figure, the motor drive device of this embodiment is a pre-driver that generates drive signals (UH, UL, VH, VL, WH, WL) for each phase of the motor (U phase, V phase, W phase). The IC 1 includes a level shifter circuit 2 that shifts the drive signal of each phase to a predetermined voltage level, and a motor driver circuit 3 that drives the motor 4 in accordance with the level-shifted drive signal of each phase.

  FIG. 2 is a circuit diagram showing the internal configuration of the motor driver circuit 3. As shown in the figure, the motor driver circuit 3 is means for driving the motor 4 using power transistors (N-channel field effect transistors NU1, NU2, NV1, NV2, NW1, NW2) connected in an H-bridge. The transistors NU1, NV1, and NW1 are H-bridge upper switch elements, and the transistors NU2, NV2, and NW2 are H-bridge lower switch elements. The drains of the transistors NU1, NV1, and NW1 are commonly connected to the power supply line, and the sources of the transistors NU2, NV2, and NW2 are commonly connected to the ground line. The sources of the transistors NU 1, NV 1, NW 1 and the drains of the transistors NU 2, NV 2, NW 2 are connected for each phase, and the connection node is connected to one end of a coil constituting the motor 4. The power transistors connected to the H-bridge are controlled to open and close in accordance with drive signals (UH, UL, VH, VL, WH, WL) input to their gates, and drive the motor 4.

  Returning to FIG. 1, the internal configuration and operation of the pre-driver IC 1 will be described in detail. As shown in the figure, the pre-driver IC 1 includes a hall amplifier 11U, 11V, 11W, a logic unit 12, a pre-driver unit 13, and an analog / digital conversion unit 14 (hereinafter referred to as A / D [Analog / Digital]). This is a semiconductor integrated circuit device formed by packaging a conversion amplifier 14, a buffer amplifier 15, and a pull-down resistor 16.

  Hall sensors 5U, 5V, and 5W are added to the coils of each phase (U phase, V phase, and W phase) constituting the motor 4, and each Hall signal output terminal is connected to the pre-driver IC1. Externally connected. Hall signals HU, HV, HW (rectangular wave comparator outputs) obtained by the respective phase Hall sensors 5U, 5V, 5W are differentially input to the Hall amplifiers 11U, 11V, 11W. The hall amplifier 11U amplifies the input U-phase hall signal HU and sends it to the logic unit 12. Similarly, the hall amplifiers 11V and 11W amplify the input V-phase and W-phase hall signals HV and HW and send them to the logic unit 12.

  The logic unit 12 generates a pre-drive signal (uh, ul, vh, vl, wh, wl) for each phase of the motor while performing feedback control of the motor rotation speed based on the input phase signal for each phase. The pre-drive signal is sent to the pre-driver unit 13.

  Further, the logic unit 12 of the present embodiment has the above basic function, and is obtained by analog-to-digital conversion of the analog voltage signal PC (more precisely, the analog voltage signal PC applied to the external terminal T1). Advancing amount setting (0 to 30 °) according to digital (n-bit) advancing amount setting signal DPC) and energization according to digital (1 bit) energization angle switching signal MODE applied to external terminal T2 It has a function to perform angle switching (120 ° / 150 °). This function will be described in detail later.

  In addition to the above, the logic unit 12 according to the present embodiment can switch the rotation direction (forward / reverse rotation), PWM switching (upper / lower), bootstrap compatible switching (in accordance with an external control signal (not shown)). Various operation modes and circuit characteristic values can be arbitrarily switched, such as presence / absence), control pulse number switching (6 pulses / 12 pulses), PWM synchronous rectification switching (presence / absence).

  Further, the logic unit 12 of the present embodiment has a built-in Hall signal input abnormality detection circuit, and the logic of the input Hall signal is in an abnormal state (for example, all low level or all high level). More specifically, the logic of each phase drive signal (UH, UL, VH, VL, WH, WL) output from the pre-driver IC 1 is set to the low level so that the drive of the motor 4 is stopped. To work. By adopting such a configuration, even if the external terminals for connecting the hall sensors are abnormally opened due to poor connection of the hall sensors 5U, 5V, 5W, etc., the driving of the motor 4 is automatically stopped and the pre-driver It is possible to avoid destruction of the IC 1 and the motor 4 in advance.

  In addition to the above, the logic unit 12 of the present embodiment includes various protection functions (such as an overcurrent protection function, an overvoltage protection function, a low input malfunction prevention function, and a temperature protection function).

  The pre-driver unit 13 performs level shifting and waveform shaping of the pre-drive signals (uh, ul, vh, vl, wh, wl) input from the logic unit 12, and outputs each phase of the motor to be output to the level shifter circuit 13 to the outside. Drive signals (UH, UL, VH, VL, WH, WL) are generated.

  The A / D conversion unit 14 converts the analog voltage signal PC applied to the external terminal T1 into a digital (for example, 4 bits) advance amount setting signal DPC and sends it to the logic unit 12. Thereby, in the logic part 12, according to the advance amount setting signal DPC, the advance amount of each phase drive signal can be set arbitrarily (variable range: 0 to 30 °, variable step: 2 °). Accordingly, the maximum output torque (or the motor characteristics required by the user) can be obtained by appropriately setting the analog voltage signal PC and performing optimum advance angle control for each motor.

  The analog voltage signal PC is a divided voltage signal (for example, 0 to 5 [V]) drawn from the connection node of the external resistors Rex1 and Rex2 connected in series between the power supply line and the ground line. By adopting such a configuration, it is possible to easily adjust the advance amount of each phase drive signal only by replacing the external resistors Rex1 and Rex2.

  The buffer amplifier 15 sends a binary (high level / low level) energization angle switching signal MODE applied to the external terminal T2 to the logic unit 12 with a predetermined hysteresis. As a result, the logic unit 12 switches the energization angle of each phase drive signal according to the energization angle switching signal MODE (switching from the energization angle of 120 ° for the high level and the energization angle of 120 ° to the energization angle of 150 ° for the low level). It can be performed. The switching to the conduction angle of 150 ° is switched when the hall signal is monitored for several cycles (for example, four cycles) and continuously becomes a predetermined frequency or more (for example, 5 [Hz] or more).

  The input terminal of the buffer amplifier 15 is connected to the external terminal T2 for receiving the conduction angle switching signal MODE, and is also connected to the ground line via the pull-down resistor 16. With this configuration, when the external terminal T2 is opened, the terminal voltage is lowered to near the ground potential (low level), so 150 ° is selected as the default energization angle. Therefore, even when the energization angle switching signal MODE is not normally input, such as when the external terminal T2 is abnormally opened, the motor drive control is not hindered. If the conduction angle switching signal MODE is normally input, the terminal voltage of the external terminal T2 is limited to the voltage level of the signal. Therefore, the insertion of the pull-down resistor 16 does not hinder the normal conduction angle switching control. Contrary to the above, when the default energization angle is set to 120 °, the input terminal of the buffer amplifier 15 may be pulled up to the power supply line.

  Next, the internal configuration of the logic unit 12 will be described with reference to FIG. FIG. 3 is a block diagram showing an internal configuration of the logic unit 12. As shown in the figure, the logic unit 12 includes a combining unit 121, an advance / energization angle control unit 122, an output unit 123, a multiplication unit 124, a counter unit 125, a decoder unit 126, and a coincidence determination unit 127. And comprising.

  The synthesizer 121 generates an upper U-phase hall signal HUH and a lower U-phase hall signal HUL based on the U-phase hall signal HU input from the hall amplifier 11U. Similarly, the synthesis unit 121 generates upper hall signals HVH and HWH and lower hall signals HVL and HWL based on the V-phase and W-phase hall signals HV and HW input from the hall amplifiers 11V and 11W, respectively. That is, the combining unit 121 is a unit that logically combines a 6-phase Hall signal from a 3-phase Hall signal and outputs each signal to the advance / energization angle control unit 122 (see FIG. 4).

  The advance angle / energization angle control unit 122 generates a phase drive signal (energization angle: both 120 ° / 150 °, desired advance angle amount: P °) from the 6-phase Hall signal obtained by the synthesis unit 121. 122a, a first shift unit 122b that generates a signal B by delaying a first trigger signal A (to be described later) by a first phase shift amount (α ° = + 15 °), and a second phase to the first trigger signal A. A conduction angle of 120 ° obtained by the waveform shaping unit 122a based on a second shift unit 122c that generates a signal C with a delay of a shift amount (2α ° = + 30 °) and a conduction angle switching signal MODE input from the outside. A selector section 122d that selectively outputs either one of the / 150 ° phase drive signals to the output section 123 at the subsequent stage. The operation of each part will be described later.

  The output unit 123 is a unit that gives a dead time or the like to each phase drive signal obtained by the advance / energization angle control unit 122, gives a predetermined current capability, and outputs it to the pre-driver unit 13 at the subsequent stage.

  The multiplier 124 is a means for multiplying any one of the hall signals HU, HV, and HW by x. Note that the multiplication unit 124 of this embodiment is configured to multiply the U-phase Hall signal HU by 360, representing the Hall signal of each phase. Therefore, the multiplication appearing during the high level period or the low level period (that is, a half period of 60 °) of the control pulse signal FG (rectangular wave signal having six pulses in combination with the high level / low level in one period of the Hall signal). The number of pulses of the output signal is exactly 60 pulses (see FIGS. 5A and 5B).

  The counter unit 125 is a unit that counts the number of output pulses of the multiplication unit 124 and sends the result to the coincidence determination unit 127. Note that the count operation of the counter unit 125 is reset every time the control pulse signal FG is updated (rising / falling).

  The decoder unit 126 decodes the advance amount setting signal DPC input from the A / D conversion unit 14 into a set value that can be compared with the count value in the counter unit 125, and sends the result to the coincidence determination unit 127. Means. The decoder unit 126 determines a setting value of the decoder output for the advance amount setting signal DPC based on the following equation (1).

  Setting value of decoder output = 60 ° − (15 ° + P °) (1)

  In the above equation (1), “60 °” on the right side is a value corresponding to the pulse width (high level period / low level period) of the control pulse signal FG, and “15 °” is the conduction angle. This is a value corresponding to half of the difference value (30 °) required when generating a drive signal with a conduction angle of 150 ° from a drive signal of 120 °. “P °” on the right side is a value corresponding to a desired advance amount of each phase drive signal set in accordance with the advance amount setting signal DPC.

  Here, in the motor drive device of this embodiment, as described above, the advance amount P ° of each phase drive signal can be arbitrarily set within a variable range of 0 ° to 30 °. Therefore, the set value of the decoder output described above has a variable setting range of 15 ° to 45 ° with respect to the advance amount setting signal DPC of 4 bits (0 to 15), as shown in FIG. is doing.

  More specifically, when the value of the advance amount setting signal DPC is “0”, the decoder unit 126 determines that the desired advance amount P ° is “0 °” and outputs the decoder output. “45 ° (45 counts)” is set. On the other hand, if the value of the advance amount setting signal DPC is “15”, it is determined that the desired advance amount P ° is “30 °” and “15 ° (15 counts)” is set as the decoder output. Set. The same applies to the case where the value of the advance amount setting signal DPC is “1” to “14”, and the decoder unit 126 performs a 2 ° (2 count) step decoder in accordance with the advance amount setting signal DPC. Set the output.

  The coincidence determination unit 127 determines whether or not the counter value in the counter unit 125 matches the set value of the decoder unit 126, and the first trigger signal A (downward trigger pulse) that is triggered when the two match. Is a means for generating The first trigger signal A is sent to the advance / energization angle control unit 122 and used for waveform shaping processing of each phase drive signal described later. As described above, since the count operation of the counter unit 125 is reset every time the control pulse signal FG is updated (every rising / falling), the determination operation in the coincidence determining unit 127 (and hence the first trigger signal). (A generation operation) is also performed every time the control pulse signal FG is updated.

  Next, referring to FIGS. 6 and 7 in addition to FIG. 3, the internal configuration and operation of the advance / energization angle control unit 122 (particularly the internal configuration and waveform shaping operation of the waveform shaping unit 122a). Detailed explanation will be given. FIG. 6 is a block diagram showing an internal configuration of the waveform shaping unit 122a (only a portion related to generation of the U-phase drive signal), and FIG. 7 shows a waveform shaping operation (desired advance amount) of the waveform shaping unit 122a. 6 is a timing chart showing only a waveform shaping operation when generating a U-phase drive signal of P ° = 28 °.

  First, the internal configuration of the waveform shaping unit 122a will be described. As shown in FIG. 6, the waveform shaping unit 122a includes inverters INV1 to INV3, OR calculators OR1 to OR6, and D flip-flops FF1 to FF6.

  One input terminal of the logical sum operator OR1 is connected to the input terminal of the control pulse signal FG via the inverter INV1. The other input terminal of the logical sum operator OR1 is connected to the input terminal of the signal A (the output terminal of the coincidence determination unit 127). The output terminal of the logical sum operator OR1 is connected to one input terminal of the logical sum operator OR2. The other input terminal of the logical sum operator OR2 is connected to the input terminal of the lower U-phase hall signal HUL (conduction angle: 120 °, advance amount: 0 °). The output terminal of the logical sum operator OR2 is connected to the clock input terminal (CK) of the D flip-flop FF1. The data input terminal (D) of the D flip-flop FF1 is connected to the input terminal of the upper U-phase hall signal HUH via the inverter INV2. The output terminal (Q) of the D flip-flop FF1 is connected to the data input terminal (D) of the D flip-flop FF2, and is also connected to one input terminal of the OR calculator OR3. The clock input terminal (CK) of the D flip-flop FF2 is connected to the input terminal of the signal B (the output terminal of the first shift unit 122b). The output terminal (Q) of the D flip-flop FF2 is connected to the data input terminal (D) of the D flip-flop FF3, and is also connected to one input terminal of the selector 122d. The clock input terminal (CK) of the D flip-flop FF3 is connected to the input terminal of the signal C (the output terminal of the second shift unit 122c). The output terminal (Q) of the D flip-flop FF3 is connected to the other input terminal of the OR operator OR3. The output terminal of the logical sum operator OR3 is connected to one input terminal of the selector 122d.

  One input terminal of the logical sum operator OR4 is connected to the input terminal of the control pulse signal FG. The other input terminal of the logical sum operator OR4 is connected to the input terminal of the signal A. The output terminal of the logical sum operator OR4 is connected to one input terminal of the logical sum operator OR5. The other input terminal of the OR operator OR5 is connected to the input terminal of the upper U-phase hall signal HUH (energization angle: 120 °, advance angle amount: 0 °). The output terminal of the logical sum operator OR5 is connected to the clock input terminal (CK) of the D flip-flop FF4. The data input terminal (D) of the D flip-flop FF4 is connected to the input terminal of the lower U-phase hall signal HUL via the inverter INV3. The output terminal (Q) of the D flip-flop FF4 is connected to the data input terminal (D) of the D flip-flop FF5, and is also connected to one input terminal of the OR calculator OR6. The clock input terminal (CK) of the D flip-flop FF5 is connected to the input terminal of the signal B. The output terminal (Q) of the D flip-flop FF5 is connected to the data input terminal (D) of the D flip-flop FF6, and is also connected to one input terminal of the selector 122d. The clock input terminal (CK) of the D flip-flop FF6 is connected to the input terminal of the signal C. The output terminal (Q) of the D flip-flop FF6 is connected to the other input terminal of the OR operator OR6. The output terminal of the logical sum operator OR6 is connected to one input terminal of the selector 122d.

  Next, the waveform shaping operation of the waveform shaping unit 122a configured as described above and the selection operation of the selector 122d will be described.

  When the desired advance amount P ° of each phase drive signal is set to 28 °, the decoder output is set to 17 ° (= 60 ° − (15 ° + 28 °)) based on the previous equation (1). The Accordingly, as shown in FIG. 7, the waveform shaping unit 122a includes the first trigger signal A based on the decoder setting and the first and second phase shift amounts (+ 15 °, + 30 °) from the first trigger signal A. Second and third trigger signals B and C delayed by a certain amount are input.

  The logical sum operator OR1 generates a signal a1 by a logical sum operation of the first trigger signal A and the inverted control pulse signal FG bar. The logical sum operator OR2 generates a signal a2 by a logical sum operation of the signal a1 and the lower U-phase hall signal HUL. On the other hand, the logical sum operator OR4 generates a signal a3 by the logical sum operation of the first trigger signal A and the control pulse signal FG. The logical sum operator OR5 generates a signal a4 by a logical sum operation of the signal a3 and the upper U-phase hall signal HUH.

  The D flip-flop FF1 generates the first element signal 1) by using the signal a2 as a clock signal and outputting the logic state of the data signal (inverted upper U-phase Hall signal HUH bar) at the time of the trigger. The first element signal (1) generated in this way becomes a rectangular wave signal with a conduction angle of 120 ° advanced by 43 ° from the upper U-phase Hall signal HUH serving as a reference.

  The D flip-flop FF2 generates the second element signal (2) by using the second trigger signal B as a clock signal and outputting the logic state of the data signal (first element signal (1)) at the time of the trigger. . The second element signal (2) generated in this way is a rectangular wave signal with a conduction angle of 120 ° advanced by 28 ° (desired advance amount P °) from the reference upper U-phase hall signal HUH.

  The D flip-flop FF3 generates the third element signal (3) by using the third trigger signal C as a clock signal and outputting the logic state of the data signal (second element signal (2)) at the time of the trigger. . The third element signal (3) generated in this way is a rectangular wave signal with a conduction angle of 120 ° advanced by 13 ° from the reference upper U-phase Hall signal HUH.

  The logical sum operator OR4 generates the fourth element signal (4) by the logical sum operation of the first element signal (1) and the third element signal (3). The fourth element signal (4) generated in this way is a rectangular wave signal obtained by adding ± 15 ° to both ends of the second element signal (2), that is, a desired advance amount P ° (= 28 °). It becomes a rectangular wave signal with a conduction angle of 150 °, which is advanced by a certain amount.

  On the other hand, the D flip-flop FF4 generates the fifth element signal (5) by using the signal a4 as a clock signal and outputting the logic state of the data signal (inverted lower U-phase hall signal HUL bar) at the time of the trigger. To do. The fifth element signal (5) generated in this way is a rectangular wave signal with a conduction angle of 120 ° advanced by 43 ° from the reference lower U-phase Hall signal HUL.

  The D flip-flop FF5 generates the sixth element signal (6) by using the second trigger signal B as a clock signal and outputting the logic state of the data signal (fifth element signal (5)) at the time of the trigger. . The sixth element signal (6) generated in this way becomes a rectangular wave signal with a conduction angle of 120 ° advanced by 28 ° (desired advance amount P °) from the reference lower U-phase hall signal HUL. .

  The D flip-flop FF6 generates the seventh element signal (7) by using the third trigger signal C as a clock signal and outputting the logic state of the data signal (sixth element signal (6)) at the time of the trigger. . The seventh element signal (7) generated in this way is a rectangular wave signal with a conduction angle of 120 ° advanced by 13 ° from the reference lower U-phase Hall signal HUL.

  The logical sum operator OR6 generates the eighth element signal (8) by the logical sum operation of the fifth element signal (5) and the seventh element signal (7). The eighth element signal (8) thus generated is a rectangular wave signal obtained by adding ± 15 ° to both ends of the sixth element signal (6), that is, a desired advance angle P ° (= 28 °). It becomes a rectangular wave signal with a conduction angle of 150 °, which is advanced by a certain amount.

  As described above, the selector unit 122d energizes any one of the upper and lower U-phase drive signals of both the energization angles 120 ° / 150 ° obtained by the waveform shaping unit 122a based on the energization angle switching signal MODE. The angle signal is selectively output to the output unit 123 at the subsequent stage. More specifically, the selector unit 122d uses the second element signal as the upper and lower U-phase drive signals when the conduction angle should be 120 ° in accordance with the conduction angle switching signal MODE. (2) When the sixth element signal (6) is selectively output and the conduction angle is to be 150 °, the upper and lower U-phase drive signals are the fourth element signal (4), Select and output 8-element signal (8).

  In the above description, the generation of the U-phase drive signal has been described as an example. However, the V-phase and W-phase drive signals can also be generated by the same method (see FIG. 8). . FIG. 8 is a timing chart for explaining advance angle control and energization angle switching control of each phase drive signal. In this figure, the vertical hatching of the lower drive signal indicates that the drive signal is PWM (Pulse Width Modulation) controlled.

  As described above, the pre-driver IC 1 according to the present embodiment has the energization angle 120 ° and the energization advanced by the desired advance amount P according to the analog voltage signal PC (and thus the advance amount setting signal DPC) input from the outside. A configuration in which both the advance amount and the conduction angle are controlled by preparing each phase drive signal at both angles of 150 ° in advance and performing signal selection processing corresponding to the conduction angle switching signal MODE that is also input from the outside. Has been. By adopting such a configuration, unlike the conventional configuration in which the advance angle control is performed by adjusting the position of the Hall sensor, it is a simple and inexpensive configuration, but is always appropriate without depending on the motor conduction angle switching control. Advance angle control can be performed.

  In the above embodiment, the case where the present invention is applied to a motor drive device that performs drive control of a three-phase full-wave motor has been described as an example, but the scope of application of the present invention is limited to this. Instead, the present invention can also be applied to a motor drive device that performs drive control of other types of motors.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment. For example, in the above-described embodiment, the example in which the step amount of the advance amount is set to 2 ° has been described, but the step width may be finer, or conversely, may be coarser. In the above embodiment, the switching control of the energization angle has been described by taking as an example a configuration in which the binary values of the energization angle of 120 ° and the energization angle of 150 ° are selection candidates. It doesn't matter.

  INDUSTRIAL APPLICABILITY The present invention is a technique useful in optimizing the drive control of a motor that requires a large torque, and is a home appliance such as an air purifier, an outdoor unit, a washing machine, an automatic dishwasher, or a water heater. In addition, it is a technique that can be used for a motor drive device that performs drive control of a motor mounted on a paper feed mechanism unit of an OA device.

These are block diagrams which show one Embodiment of the motor drive device which concerns on this invention. FIG. 3 is a circuit diagram showing an internal configuration of a motor driver circuit 3. FIG. 3 is a block diagram showing an internal configuration of the logic unit 12. These are timing charts showing the signal generation operation of the synthesis unit 121. These are timing charts showing the signal generation operation of the coincidence determination unit 127. These are block diagrams which show the internal structure of the waveform shaping part 122a. These are timing charts showing the waveform shaping operation of the waveform shaping unit 122a. These are timing charts for explaining advance angle control and energization angle switching control of each phase drive signal.

Explanation of symbols

1 Pre-driver IC
2 level shifter circuit 3 motor driver circuit 4 motor 5U, 5V, 5W Hall sensor 11U, 11V, 11W Hall amplifier 12 logic unit 121 synthesis unit 122 advance / energization angle control unit 122a waveform shaping unit 122b first shift unit 122c second shift Section 122d Selector section 123 Output section 124 Multiplication section 125 Counter section 126 Decoder section 127 Match determination section 13 Pre-driver section 14 Analog / digital conversion section 15 Buffer amplifier 16 Pull-down resistor T1, T2 External terminal Rex1, Rex2 External resistance NU1, NU2 N Channel field effect transistor (upper U phase, lower U phase)
NV1, NV2 N-channel field effect transistors (V-phase upper side, V-phase lower side)
NW1, NW2 N-channel field effect transistor (W-phase upper side, W-phase lower side)
INV1 to INV3 Inverter OR1 to OR6 OR operator FF1 to FF6 D flip-flop

Claims (4)

  The hall signal from the motor is subjected to predetermined signal processing, and the first drive signal of the energization angle m ° given the desired advance amount P ° and the energization angle n ( means for generating a second drive signal of n> m) ° in advance; and means for selectively outputting one of the first and second drive signals as a motor drive signal. A motor drive device.   Means for performing predetermined signal processing on the hall signal from the motor to generate a reference drive signal having a conduction angle of m °; and performing signal processing for advancing the reference drive signal by α ° further than the desired advance amount P ° Means for generating a first element signal having a conduction angle m ° phase-shifted from the reference drive signal by (P + α) °; and performing signal processing for delaying the first element signal by α °, Means for generating a second element signal having a conduction angle m ° that is phase-shifted by °; signal processing for further delaying the second element signal by α ° and phase-shifting by (P−α) ° from the reference drive signal Means for generating a third element signal, and means for performing a logical sum operation on the first and third element signals to generate a fourth element signal having a conduction angle n (= m + 2α) °; The second element signal is used as the motor drive signal Select Output, if it is to be the conduction angle and n ° is a means for selecting and outputting a fourth element signal as a motor drive signal; motor driving apparatus characterized by comprising a. A combining unit that performs predetermined signal processing on the hall signal from the motor to generate a reference drive signal having a conduction angle m °; and a conduction angle m ° to which a desired advance amount P ° is given from the reference drive signal. A waveform shaping unit that generates a first drive signal and a second drive signal having a conduction angle n (n> m) °, which is also provided with a desired advance amount P °; either of the first and second drive signals A selector unit that selectively outputs the motor drive signal as a motor drive signal;
A multiplier for multiplying the Hall signal; a counter for counting the number of output pulses of the multiplier; a decoder for decoding an advance amount setting signal into a set value that can be compared with a count value in the counter; A coincidence determination unit that determines whether or not a count value in the counter unit matches a set value of the decoder unit, and generates a first trigger signal that is triggered when the two match, and a first trigger signal; a first shift unit for generating a second trigger signal delayed by α °; and a second shift unit for generating a third trigger signal by delaying the first trigger signal by 2α °, and ,
The waveform shaping unit performs signal processing for advancing the reference drive signal by α ° further than the desired advance amount P ° using the first trigger signal, and is phase-shifted by (P + α) ° from the reference drive signal. Means for generating a first element signal having a conduction angle of m °; signal processing for delaying the first element signal by α ° using the second trigger signal, and phase-shifted by P ° from the reference drive signal Means for generating a second element signal having an energization angle of m °; signal processing for further delaying the second element signal by α ° using the third trigger signal, and only (P−α) ° from the reference drive signal Means for generating a phase-shifted third element signal; and means for performing a logical sum operation on the first and third element signals to generate a fourth element signal having a conduction angle n (= m + 2α) °. While the second element signal is output as the first drive signal Motor driving apparatus which is characterized in that outputs a fourth element signal as the second drive signal.   An electric apparatus comprising: the motor drive device according to any one of claims 1 to 3; and a motor that is driven and controlled by the motor drive device.

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