JP2006352994A - Inverter controlling semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a plurality of ADCs perform AD conversion at desired timing in synchronization with a motor counter. <P>SOLUTION: An inverter control part 6 is provided with: a CPU 21; a memory 22; a three-phase waveform generation part 23; the motor counter 24; a first ADC control part 25a; a second ADC control part 25b; the first ADC 26a; the second ADC 26b; and an inverter control signal generation part 27. The three-phase waveform generation part 23 inputs a triangle wave signal SP to the motor counter 24 on the basis of a position signal RP. The motor counter 24 inputs the triangle wave signal SP outputted from the three-phase waveform generation part 23, counts the UP/DOWN of the triangle wave signal SP per cycle, and outputs the information of the count to the first ADC control part 25a and the second ADC control part 25b as a motor counter signal MCS. The first ADC 26a and the second ADC 26b are synchronized with each other in terms of a PWM peak on the basis of the motor counter signal MCS, and perform the AD conversion. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a motor control device, and more particularly, to an inverter control semiconductor device equipped with an ADC (Analog-to-Digital Converters).

  As a system for controlling a motor, a PWM (Pulse Width Modulation) inverter system is frequently used. An inverter control unit such as an inverter control microcomputer that controls the operation of the PWM inverter is provided with an ADC that AD-converts an input analog value feedback motor current signal into a digital value using a rotation position detection signal that is an analog signal. ing. And the inverter control part produces | generates a PWM signal based on the signal AD-converted, and controls a PWM inverter with a PWM signal (for example, refer patent document 1).

  In the ADC described in Patent Document 1, analog signals such as a rotational position detection signal, a U-phase feedback motor current signal, a V-phase feedback motor current signal, and a W-phase feedback motor current signal are appropriately selected and input using a multiplexer. The AD conversion is sequentially performed.

However, if a plurality of AD conversions such as the U phase, V phase, and W phase are performed by one ADC, the AD conversion time is delayed, and a certain deviation occurs in the timing, and the desired timing that is an expected value is obtained. Data acquisition becomes difficult. For this reason, there is a problem that it is difficult to control the rotation control of the motor with high accuracy.
Japanese Patent No. 3134104 (page 13, FIG. 2)

  An object of the present invention is to provide an inverter control semiconductor device provided with a plurality of ADCs that perform AD conversion at a desired timing in synchronization with a motor counter.

  In order to achieve the above object, a semiconductor device for inverter control according to one embodiment of the present invention inputs a triangular wave signal or a sawtooth wave signal generated based on a motor position signal and counts UP / DOWN for each cycle. A motor counter that outputs the counted information as a motor counter signal, an ADC control unit that generates a trigger signal based on the motor counter signal, a U-phase current signal as a motor current value feedback signal, a V-phase current signal, Alternatively, a first ADC that AD-converts one of the W-phase current signals in synchronization with the motor counter based on the trigger signal output from the ADC control unit, and a motor current value feedback signal Current signal of any one of the U-phase current signal, V-phase current signal, and W-phase current signal of the first ADC No. based on said trigger signal output different current signals from the ADC control unit and characterized by comprising a second ADC for AD conversion in synchronism with the motor counter.

  Furthermore, in order to achieve the above object, a semiconductor device for inverter control according to another aspect of the present invention inputs a triangular wave signal or a sawtooth wave signal generated based on a motor position signal and sets UP / DOWN for each cycle. A motor counter that outputs the counted information as a motor counter signal, first and second ADC control units that generate a trigger signal based on the motor counter signal, and a U-phase as a motor current value feedback signal A current signal, a V-phase current signal, or a W-phase current signal is AD-converted in synchronization with the motor counter based on the trigger signal output from the first ADC control unit. 1 ADC and any one current signal of a U-phase current signal, a V-phase current signal, or a W-phase current signal as a motor current value feedback signal And a second ADC that AD-converts a current signal different from the current signal of the first ADC in synchronization with the motor counter based on the trigger signal output from the second ADC control unit. It is characterized by doing.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device for inverter control provided with several ADC which performs AD conversion with desired timing synchronizing with a motor counter can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, an inverter control semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a motor control device, FIG. 2 is a block diagram showing an inverter control unit as a semiconductor device for inverter control, and FIG. 3 is a block diagram showing an ADC control unit. In this embodiment, AD conversion of a plurality of ADCs is performed in synchronization with the motor counter.

  As shown in FIG. 1, the motor control device 1 is provided with an AC power source 2, a power source control unit 3, an inverter unit 4, a three-phase motor 5, an inverter control unit 6, and a position detection unit 7.

  The power supply control unit 3 receives the AC voltage output from the AC power supply 2, and generates and outputs the P-side high potential power supply VP and the N-side high potential power supply VN necessary for the inverter unit 4 to operate as an inverter. .

  In the inverter unit 4, two IGBTs (Insulated Gate Bipolar Transistors) 11 are connected in cascade between the U-phase, V-phase, and W-phase P-side high-potential-side power supply VP and N-side high-potential-side power supply VN, respectively. ing. A recovery diode 12 is provided between the collector and the emitter of each IGBT 11 for preventing breakdown. The IGBT 11 operates by receiving the inverter control signal ISS output from the inverter control unit 6 at the gate. The U-phase output signal is output from the output node N 1 and input to the three-phase motor 5. The V-phase output signal is output from the output node N2 and input to the three-phase motor 5. The W-phase output signal is output from the output node N3 and input to the three-phase motor 5.

  The position detector 7 detects a position signal RP as position information of the three-phase motor 5, a U-phase current signal AN1 as a current value feedback signal, a V-phase current signal AN2 as a current value feedback signal, and the like. Is output to the inverter control unit 6. The inverter control unit 6 is also called an inverter control microprocessor or an inverter control microcontroller. Here, the W-phase current signal is not detected.

  The inverter control unit 6 receives the position signal RP, the U-phase current signal AN1, and the V-phase current signal AN2, and an output pulse signal (PWM signal) that changes the DUTY ratio for controlling the inverter unit 4 based on the signals. Is generated and output to the gate of the IGBT 11 of the inverter unit 4.

  As shown in FIG. 2, the inverter controller 6 includes a CPU (Central Processing Unit) 21, a memory 22, a three-phase waveform generator 23, a motor counter 24, a first ADC controller 25a, and a second ADC controller. 25b, a first ADC 26a, a second ADC 26b, and an inverter control signal generator 27 are provided. Each unit is electrically connected via an internal bus 20 to exchange information and signals.

  The CPU 21 performs overall control of the inverter control unit 6 and issues instructions / commands to each unit of the inverter control unit 6. The memory 22 includes a ROM (Read Only Memory), a RAM (Random Access Memory), and the like, and stores an execution program, various types of information, information subjected to execution processing, and the like.

  The three-phase waveform generation unit 23 includes an oscillator and a signal generation circuit, receives the position signal RP output from the position detection unit 7, generates a triangular wave signal or a sawtooth wave signal based on the position signal RP, and outputs the generated signal. . Here, the triangular wave signal SP is output to the motor counter 24. Instead of the position signal RP detected and output by the position detector 7 functioning as a position sensor, the position is derived from the result of AD conversion for detecting the motor current, and this is used as a position signal to generate a three-phase waveform. You may make it input to the part 23.

  The motor counter 24 receives the triangular wave signal SP output from the three-phase waveform generation unit 23, counts UP / DOWN of the triangular wave signal SP every cycle (also referred to as PWM count), and sends the information to the motor counter. The signal MCS is output to the first ADC control unit 25a and the second ADC control unit 25b.

  The first ADC controller 25a receives the position signal RP output from the position detector 7 and the motor counter signal MCS output from the motor counter 24, and generates a plurality of trigger signals based on the motor counter signal MCS. To the first ADC 26a. Similarly, the second ADC control unit 25b receives the position signal RP output from the position detection unit 7 and the motor counter signal MCS output from the motor counter 24, and a plurality of trigger signals based on the motor counter signal MCS. Is output to the second ADC 26b. The trigger signal is a signal for executing AD conversion of the first ADC 26a and the second ADC control unit 25b.

  The first ADC 26a receives a trigger signal and an analog U-phase current signal AN1, and AD-converts the U-phase current signal AN1 based on the trigger signal to generate an output signal Out1 of the first ADC as an inverter control signal. To the unit 27. Similarly, the second ADC 26b receives the V-phase current signal AN2 that is a trigger signal and an analog value, AD-converts the V-phase current signal AN2 based on the trigger signal, and converts the output signal Out2 of the second ADC into an inverter. Output to the control signal generator 27.

  Here, the AD-converted output signal output from the ADC is stored in a conversion result register (not shown) and then output to the inverter control signal generator 27, but is directly output to the inverter control signal generator 27. Also good.

  The inverter control signal generation unit 27 receives the output signal Out1 of the first ADC and the output signal Out2 of the second ADC, and outputs an inverter control signal ISS that is a PWM signal to the gate of the IGBT 11 of the inverter unit 4.

  As shown in FIG. 3, the first ADC control unit 25a and the second ADC control unit 25b include a first trigger setting unit 30a, a second trigger setting unit 30b, and a third trigger setting unit 30c, respectively. , And a selector 31 are provided.

  The first trigger setting unit 30a includes a first trigger register 32a, a first trigger buffer 33a, and a first comparator 34a.

  The first trigger register 32a stores various mode information for setting the operation of the first ADC 26a, the second ADC 26b, etc., and an arbitrary mode is selected by a command of the CPU 21, and the information is stored in the first trigger register 32a. Is output to the trigger buffer. The various mode information includes, for example, trigger output at the PWM carrier peak, trigger output at the PWM carrier bottom, trigger output at the PWM carrier peak / bottom, trigger output at the coincidence at the down count, and trigger at the coincidence at the up count. This is mode setting information such as output, trigger output during up / down counting, and trigger output inhibition. Since the second trigger register 32b and the third trigger register 32c have the same configuration and operation as the first trigger register 32a, description thereof is omitted.

  The first trigger buffer 33a drives the mode information signal output from the first trigger register 32a and outputs it to the first comparator 34a. Since the second trigger buffer 33b and the third trigger buffer 33c have the same configuration and operation as the first trigger buffer 33a, description thereof is omitted.

  The first comparator 34a receives the motor counter signal MCS output from the motor counter 24 and the mode information signal output from the first trigger buffer 33a, compares and amplifies the two signals, and outputs them to the selector 31. The second comparator 34b receives the motor counter signal MCS output from the motor counter 24 and the mode information signal output from the second trigger buffer 33b, compares and amplifies the two signals, and outputs them to the selector 31. The third comparator 34c receives the motor counter signal MCS output from the motor counter 24 and the mode information signal output from the third trigger buffer 33c, compares and amplifies the two signals, and outputs them to the selector 31.

  Here, the motor counter signal MCS input to the first comparator 34a, the motor counter signal MCS input to the second comparator 34b, and the motor counter signal MCS input to the third comparator 34c are respectively The positions of the first comparator 34a, the second comparator 34b, the third comparator 34c, and the like are arranged and formed so that signal delay does not occur. The signals output from the first comparator 34a, the second comparator 34b, and the third comparator 34c to the selector 31 are signals that are synchronized (PWM synchronized) by the motor counter 24, respectively.

  The selector 31 receives the signals output from the first comparator 34a, the second comparator 34b, and the third comparator 34c, selects the slope, selects the first trigger signal, the second trigger signal, and the third trigger signal. The trigger signal is output. Here, when a trigger clear signal generated based on the position signal RP is input, the trigger signal is cleared. When a synchronization permission signal generated based on the position signal RP is input, the trigger signal becomes a signal synchronized (PWM synchronization) by the motor counter 24.

  Next, the operation of the motor control device will be described with reference to FIGS. FIG. 4 is a flowchart showing the operation of the motor control device, and FIG. 5 is a schematic timing diagram showing the operation of the motor control device. Here, a one-time reading method is used that is synchronized with the motor counter for each period of the triangular wave signal SP. The first ADC and the second ADC operate in parallel.

  As shown in FIG. 4, first, the first ADC 26a and the second ADC 26b start to operate based on a command from the CPU 21 (step S1a and step S1b). Next, the AD input port is set, the U-phase current signal AN1 that is an analog signal is input to the first ADC 26a, and the V-phase current signal AN2 that is an analog signal is input to the second ADC 26b (step). S2a and step S2b).

  Subsequently, the first ADC 26a and the second ADC 26b are synchronously set by the motor counter. Specifically, as shown in FIG. 5, the triangular wave signal SP is PWM-counted by the motor counter 24 every cycle, and max. Synchronization is set by counting (at the peak of the triangular wave signal SP). This is called PWM peak synchronization (steps S3a and S3b).

  Then, AD conversion of the U-phase current signal AN1 that is an analog signal is started in the first ADC 26a, and AD conversion of the V-phase current signal AN2 that is an analog signal is started in the second ADC 26b (Steps S4a and S4b). ).

  Next, synchronized AD conversion is performed. Specifically, as shown in FIG. 5, the first ADC 26 a outputs max. Based on the motor counter signal MCS at the time of counting, AD conversion of the U-phase current signal AN1 is performed for a predetermined period. Similarly, the second ADC 26 b outputs max. Based on the motor counter signal MCS at the time of counting, AD conversion of the V-phase current signal AN2 is performed for a predetermined period (steps S5a and S5b).

  Subsequently, the output signal Out1 of the first ADC that is AD conversion information output from the first ADC 26a and the output signal Out2 of the second ADC that is AD conversion information output from the second ADC 26b are conversion results. It is stored in the register (step S6a and step S6b).

  Then, the inverter control signal generator 27 calculates an output pulse from the AD conversion information of the first ADC 26a and the AD conversion information of the second ADC 26b (step S7). Next, the pulse DUTY is determined and output. Specifically, as shown in FIG. 5, the inverter control signal generation unit 27 determines a pulse DUTY for controlling the “ON” and “OFF” operations of the IGBT 11 of the inverter unit 4, and for each cycle of the triangular wave signal SP, An inverter control signal ISS that is a PWM signal is output to the gate of the IGBT 11 of the inverter unit 4 for controlling the three-phase motor 5. (Step S8). In the next cycle of the triangular wave signal SP, the ADC operation is performed from the setting of the AD input port (steps S2a and S2b).

  As described above, in the semiconductor device for inverter control according to this embodiment, the three-phase waveform generation unit 23 that outputs the triangular wave signal SP to the motor counter 24 based on the position signal RP and the three-phase waveform generation unit 23 output the triangular wave signal SP. The motor counter which inputs the triangular wave signal SP, counts UP / DOWN of the triangular wave signal SP every cycle, and outputs the information to the first ADC control unit 25a and the second ADC control unit 25b as the motor counter signal MCS. 24, the first ADC control unit 25a and the second ADC control unit 25b that generate a plurality of trigger signals based on the motor counter signal MCS, and the trigger signal are input, and PWM peak synchronization is performed based on the motor counter signal MCS Thus, a first ADC 26a and a second ADC 26b that perform AD conversion are provided.

  For this reason, AD conversion is performed at a desired timing, so that the rotation control of the motor can be controlled with high accuracy.

  In the present embodiment, a plurality of IGBTs 11 that operate at a high voltage are provided in the inverter unit 4, but a power MOS transistor that operates at a relatively lower voltage than the IGBT or operates at a high voltage depending on the application product field. An SiC power MOS transistor or the like may be used.

  Next, an inverter control semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing an inverter control unit as a semiconductor device for inverter control. In this embodiment, two ADCs perform AD conversion in synchronization with a motor counter based on a trigger signal output from one ADC control unit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the inverter control unit 6a of the motor control device 1 includes a CPU 21, a memory 22, a three-phase waveform generation unit 23, a motor counter 24, an ADC control unit 25, a first ADC 26a, a second ADC 26b, An inverter control signal generation unit 27 is provided. Each unit is electrically connected via an internal bus 20 to exchange information and signals.

  The ADC control unit 25 receives the position signal RP output from the position detection unit 7 and the motor counter signal MCS output from the motor counter 24, generates a plurality of trigger signals based on the motor counter signal MCS, and generates a first trigger signal. To the second ADC 26b and the second ADC 26b.

  The first ADC 26a receives the trigger signal output from the ADC control unit 25 and the U-phase current signal AN1 that is an analog value, and AD-converts the U-phase current signal AN1 based on the trigger signal, thereby converting the first ADC 26a. The output signal Out1 is output to the inverter control signal generator 27. Similarly, the second ADC 26b receives the trigger signal output from the ADC control unit 25 and the V-phase current signal AN2 that is an analog value, and AD-converts the V-phase current signal AN2 based on the trigger signal to generate the second ADC 26b. The ADC output signal Out2 is output to the inverter control signal generator 27.

  As described above, in the semiconductor device for inverter control according to this embodiment, the three-phase waveform generation unit 23 that outputs the triangular wave signal SP to the motor counter 24 based on the position signal RP and the three-phase waveform generation unit 23 output the triangular wave signal SP. A triangular wave signal SP is input, UP / DOWN of the triangular wave signal SP is counted for each cycle, and the information is output to the ADC control unit 25 as a motor counter signal MCS, and a plurality of values are obtained based on the motor counter signal MCS. Are provided with a first ADC 26a and a second ADC 26b that receive the trigger signal and perform AD conversion in synchronization with the PWM peak based on the motor counter signal MCS.

  For this reason, AD conversion is performed at a desired timing, so that the rotation control of the motor can be controlled with high accuracy. Further, since the number of ADC control units is reduced as compared with the first embodiment, the cost of the inverter control unit as the semiconductor device for inverter control can be suppressed.

  Next, an inverter control semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing a motor control device, and FIG. 8 is a block diagram showing an inverter control unit as a semiconductor device for inverter control. In this embodiment, the U-phase current signal, V-phase current signal, and W-phase current signal output from the inverter unit are detected as feedback motor current.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 7, the motor control device 1a is provided with an AC power source 2, a power source control unit 3, an inverter unit 4, a three-phase motor 5, an inverter control unit 6b, and a position detection unit 8.

  The position detector 8 includes a position signal RP as position information of the three-phase motor 5, a U-phase current signal AN1 as a current value feedback signal, a V-phase current signal AN2 as a current value feedback signal, and a current value feedback signal. The W-phase current signal AN3 and the like are detected and the signal is output to the inverter control unit 6b.

  The inverter control unit 6b receives the position signal RP, the U-phase current signal AN1, the V-phase current signal AN2, and the W-phase current signal AN3, and an output that changes the DUTY ratio for controlling the inverter unit 4 based on the signals. An inverter control signal ISS which is a pulse signal (PWM signal) is generated and output to the gate of the IGBT 11 of the inverter unit 4.

  As shown in FIG. 8, the inverter control unit 6b includes a CPU 21, a memory 22, a three-phase waveform generation unit 23, a motor counter 24, a first ADC control unit 25a, a second ADC control unit 25b, and a third ADC. A control unit 25c, a first ADC 26a, a second ADC 26b, a third ADC 26c, and an inverter control signal generation unit 27a are provided. Each unit is electrically connected via an internal bus 20 to exchange information and signals.

  The motor counter 24 receives the triangular wave signal SP output from the three-phase waveform generation unit 23, counts UP / DOWN of the triangular wave signal SP every cycle (also referred to as PWM count), and sends the information to the motor counter. The signal MCS is output to the first ADC control unit 25a, the second ADC control unit 25b, and the third ADC control unit 25c.

  The third ADC control unit 25c receives the position signal RP output from the position detection unit 7 and the motor counter signal MCS output from the motor counter 24, and generates a plurality of trigger signals based on the motor counter signal MCS. , To the first ADC 26a, the second ADC, and the third ADC 26c.

  The third ADC 26c receives a trigger signal and an analog value W-phase current signal AN3, and AD-converts the W-phase current signal AN3 based on the trigger signal to generate an output signal Out3 of the third ADC as an inverter control signal. To the unit 27a.

  Here, the AD-converted output signal output from the ADC is stored in a conversion result register (not shown) and then output to the inverter control signal generator 27a, but is directly output to the inverter control signal generator 27a. Also good.

  The inverter control signal generation unit 27 a receives the output signal Out 1 of the first ADC, the output signal Out 2 of the second ADC, and the output signal Out 3 of the third ADC, and controls the inverter unit 4 for controlling the three-phase motor 5. An inverter control signal ISS that is a PWM signal is output to the gate of the IGBT 11.

  As described above, in the semiconductor device for inverter control according to this embodiment, the three-phase waveform generation unit 23 that outputs the triangular wave signal SP to the motor counter 24 based on the position signal RP and the three-phase waveform generation unit 23 output the triangular wave signal SP. The triangular wave signal SP is input, UP / DOWN of the triangular wave signal SP is counted every cycle, and the information is used as a motor counter signal MCS for the first ADC control unit 25a, the second ADC control unit 25b, and the third A motor counter 24 output to the ADC control unit 25c, a first ADC control unit 25a that generates a plurality of trigger signals based on the motor counter signal MCS, a second ADC control unit 25b, and a third ADC control unit 25c The trigger signal is input, and PWM peak synchronization is performed based on the motor counter signal MCS to perform AD conversion of the U-phase current signal AN1. First ADC26a, second ADC26b performing AD conversion of the V-phase current signals AN2, and a third ADC26c performing AD conversion of the W-phase current signal AN3 are provided Nau.

  Therefore, AD conversion of the U-phase current signal AN1, the V-phase current signal AN2, and the W-phase current signal AN3 is performed at a desired timing, so that the motor rotation control can be controlled with higher accuracy than in the first embodiment. it can.

  In this embodiment, the first ADC 26a has a trigger signal output from the first ADC control unit 25a, the second ADC 26b has a trigger signal output from the second ADC control unit 25b, the third ADC A trigger signal output from the third ADC control unit 25c is input to the ADC 26c. However, in the same manner as in the second embodiment, the trigger signal output from one ADC control unit is used to synchronize with the motor counter. The AD conversion of the first ADC 26a, the second ADC 26b, and the third ADC 26c may be performed.

  Next, an inverter control semiconductor device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 9 is a circuit diagram showing the motor control device. In this embodiment, the inverter control signals input to the respective inverters provided in the plurality of motors are synchronized with the motor counter, and the rotations of the plurality of motors are synchronized.

  As shown in FIG. 9, the motor control device 1b includes an AC power source 2a, an AC power source 2b, a power source control unit 3a, a power source control unit 3b, a first inverter unit 4a, a second inverter unit 4b, and a first 3 A phase motor 5a, a second three-phase motor 5b, an inverter control unit 6c, a first position detection unit 7a, and a second position detection unit 7b are provided.

  The power supply control unit 3a receives the AC voltage output from the AC power supply 2a, and generates the P-side high potential power supply VP and the N-side high potential power supply VN necessary for the first inverter unit 4a to operate as an inverter. Output.

  Two IGBTs 11 are cascade-connected between the U-phase, V-phase, and W-phase P-side high-potential-side power supply VP and N-side high-potential-side power supply VN in the first inverter unit 4a. A recovery diode 12 is provided between the collector and the emitter of each IGBT 11 for preventing breakdown. The IGBT 11 operates by receiving the first inverter control signal ISSa output from the inverter control unit 6c at the gate. The U-phase output signal is output from the output node N1a and input to the first three-phase motor 5a. The V-phase output signal is output from the output node N2a and input to the first three-phase motor 5a. The W-phase output signal is output from the output node N3a and input to the first three-phase motor 5a.

  The first position detector 7a includes a first position signal RPa as position information of the first three-phase motor 5a, a first U-phase current signal AN1a as a current value feedback signal, and a current value feedback signal. The first V-phase current signal AN2a and the like are detected, and the signal is output to the inverter control unit 6c.

  The power supply control unit 3b receives the AC voltage output from the AC power supply 2b, and generates the P-side high potential power supply VP and the N-side high potential power supply VN necessary for the second inverter unit 4b to operate as an inverter. Output.

  Two IGBTs 11 are cascaded between the U-phase, V-phase, and W-phase P-side high-potential-side power supply VP and N-side high-potential-side power supply VN in the second inverter unit 4b. A recovery diode 12 is provided between the collector and the emitter of each IGBT 11 for preventing breakdown. The IGBT 11 operates by receiving the second inverter control signal ISSb output from the inverter control unit 6c at the gate. The U-phase output signal is output from the output node N1b and input to the second three-phase motor 5b. The V-phase output signal is output from the output node N2b and input to the second three-phase motor 5b. The W-phase output signal is output from the output node N3b and input to the second three-phase motor 5b.

  The second position detector 7b includes a second position signal RPb as position information of the second three-phase motor 5b, a second U-phase current signal AN1b as a current value feedback signal, and a current value feedback signal. The second V-phase current signal AN2b and the like are detected, and the signal is output to the inverter control unit 6c.

  Here, the first position signal RPa, the first U-phase current signal AN1a, and the first V-phase current signal AN2a are used for the first inverter control signal ISSa, and the second position signal RPb, second The U-phase current signal AN1b and the second V-phase current signal AN2b are used for the second inverter control signal ISSb.

  The inverter control unit 6c includes a first position signal RPa, a second position signal RPb, a first U-phase current signal AN1a, a second U-phase current signal AN1b, a first V-phase current signal AN2a, and a second The V-phase current signal AN2b is input.

  The inverter control unit 6c AD converts the first U-phase current signal AN1a that operates in synchronization with a motor counter signal (not shown) generated based on the first position signal RPa or the second position signal RPb. An ADC (not shown) and an ADC (not shown) for AD-converting the first V-phase current signal AN2a are provided, and operate in synchronization with a motor counter signal generated based on the first position signal RPa or the second position signal RPb. An ADC (not shown) for AD converting the second U-phase current signal AN1b and an ADC (not shown) for AD converting the second V-phase current signal AN2b are provided.

  The first inverter control signal ISSa and the second inverter control signal ISSb output from the inverter control unit 6c are synchronized by the motor counter signal. Note that a slight time lag may be set for the rotation synchronization of the first three-phase motor 5a and the second three-phase motor 5b using an external correction trigger signal or the like.

  As described above, in the inverter control semiconductor device of this embodiment, the first inverter control signal ISSa input to the first inverter unit 4a of the first three-phase motor 5a and the second three-phase motor 5b. The second inverter control signal ISSb input to the second inverter unit 4b is synchronized by the motor counter. Therefore, the rotation synchronization of the first three-phase motor 5a and the second three-phase motor 5b is controlled while controlling the rotation control of the motors of the first three-phase motor 5a and the second three-phase motor 5b with high accuracy. Can be taken.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, synchronization is performed at the PWM peak, but another mode setting information stored in the trigger register may be selected and synchronization may be performed at an arbitrary timing of the PWM cycle. In addition, the present invention is applied to a two-level inverter in which two IGBTs are cascaded per phase, but can also be applied to a three-level inverter in which four IGBTs are cascaded per phase. In the first and second embodiments, U-phase and V-phase current signals are detected, but any two current signals of U-phase, V-phase, or W-phase other than this combination are detected. Also good. Furthermore, in the fourth embodiment, rotation synchronization of two three-phase motors is performed using a motor counter, but rotation synchronization of three or more three-phase motors may be performed using a motor counter.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) A motor counter that inputs a triangular wave signal or a sawtooth wave signal generated based on a motor position signal, counts UP / DOWN for each cycle, and outputs the counted information as a motor counter signal; An ADC control unit that generates a trigger signal based on a motor counter signal, and a U-phase current signal as a motor current value feedback signal based on the trigger signal output from the ADC control unit, the triangular wave signal or the sawtooth wave signal Based on the trigger signal output from the ADC controller, the first ADC that performs AD conversion in synchronization with the motor counter at the peak and the V-phase current signal as the motor current value feedback signal, or A second ADC that performs AD conversion in synchronization with the motor counter at the peak of the sawtooth signal; A semiconductor device for controlling an inverter.

(Additional remark 2) The motor counter which inputs the triangular wave signal or sawtooth wave signal produced | generated based on the position signal of a motor, counts UP / DOWN for every period, and outputs the counted information as a motor counter signal, First and second ADC control units that generate a trigger signal based on a motor counter signal, and a U-phase current signal as a motor current value feedback signal based on the trigger signal output from the first ADC control unit The second ADC control unit outputs a first ADC that performs AD conversion in synchronization with the motor counter at the peak of the triangular wave signal or the sawtooth wave signal, and a V-phase current signal as a motor current value feedback signal. Based on the trigger signal, the peak of the triangular wave signal or the sawtooth wave signal is synchronized with the motor counter. D conversion second inverter control semiconductor device including the ADC.

1 is a circuit diagram showing a motor control device according to Embodiment 1 of the present invention. The block diagram which shows the inverter control part as a semiconductor device for inverter control which concerns on Example 1 of this invention. 1 is a block diagram showing an ADC according to Embodiment 1 of the present invention. The flowchart which shows operation | movement of the motor control apparatus which concerns on Example 1 of this invention. FIG. 3 is a timing schematic diagram showing the operation of the motor control device according to the first embodiment of the present invention. The block diagram which shows the inverter control part as a semiconductor device for inverter control which concerns on Example 2 of this invention. The circuit diagram which shows the motor control part which concerns on Example 3 of this invention. The block diagram which shows the inverter control part as a semiconductor device for inverter control which concerns on Example 3 of this invention. The circuit diagram which shows the motor control apparatus which concerns on Example 4 of this invention.

Explanation of symbols

1, 1a, 1b Motor control device 2, 2a, 2b AC power supply 3, 3a, 3b Power supply control unit 4 Inverter unit 4a First inverter unit 4b Second inverter unit 5 Three-phase motor 5a First three-phase motor 5b Second three-phase motor 6, 6a, 6b, 6c Inverter control unit 7, 8 Position detection unit 7a First position detection unit 7b Second position detection unit 11 IGBT
12 Recovery diode 20 Internal bus 21 CPU
22 Memory 23 Three-phase waveform generation unit 24 Motor counter 25 ADC control unit 25a First ADC control unit 25b Second ADC control unit 25c Third ADC control unit 26a First ADC
26b Second ADC
26c Third ADC
27, 27a Inverter control signal generation unit 30a First trigger setting unit 30b Second trigger setting unit 30c Third trigger setting unit 31 Selector 32a First trigger register 32b Second trigger register 32c Third trigger register 33a 1st trigger buffer 33b 2nd trigger buffer 33c 3rd trigger buffer 34a 1st comparator 34b 2nd comparator 34c 3rd comparator AN1 U phase current signal (current value feedback signal)
AN1a First U-phase current signal (current value feedback signal)
AN1b Second U-phase current signal (current value feedback signal)
AN2 V-phase current signal (current value feedback signal)
AN2a First V-phase current signal (current value feedback signal)
AN2b Second V-phase current signal (current value feedback signal)
AN3 W phase current signal (current value feedback signal)
RP Position signal RPa First position signal Rpb Second position signal ISS Inverter control signal ISSa First inverter control signal ISSb Second inverter control signal MCS Motor counter signals N1 to N3, N1a to 3a, N1b to 3b Output node Out1 Output signal of the first ADC Out2 Output signal of the second ADC Out3 Output signal SP of the third ADC Triangular wave signal VPP P side high potential power supply VN N side high potential power supply

Claims (5)

A motor counter that inputs a triangular wave signal or a sawtooth wave signal generated based on a motor position signal, counts UP / DOWN every cycle, and outputs the counted information as a motor counter signal;
An ADC controller that generates a trigger signal based on the motor counter signal;
One of the U-phase current signal, V-phase current signal, and W-phase current signal as a motor current value feedback signal is synchronized with the motor counter based on the trigger signal output from the ADC control unit. A first ADC for AD conversion,
A current signal that is any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal and that is different from the current signal of the first ADC is output from the ADC controller. A second ADC that performs AD conversion in synchronization with the motor counter based on the output trigger signal;
An inverter control semiconductor device comprising: A motor counter that inputs a triangular wave signal or a sawtooth wave signal generated based on a motor position signal, counts UP / DOWN every cycle, and outputs the counted information as a motor counter signal;
An ADC controller that generates a trigger signal based on the motor counter signal;
One of the U-phase current signal, V-phase current signal, and W-phase current signal as a motor current value feedback signal is synchronized with the motor counter based on the trigger signal output from the ADC control unit. A first ADC for AD conversion,
A current signal that is any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal and that is different from the current signal of the first ADC is output from the ADC controller. A second ADC that performs AD conversion in synchronization with the motor counter based on the output trigger signal;
A current signal that is any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal and that is different from the current signals of the first ADC and the second ADC. A third ADC that performs AD conversion in synchronization with the motor counter based on the trigger signal output from the ADC control unit;
An inverter control semiconductor device comprising: A motor counter that inputs a triangular wave signal or a sawtooth wave signal generated based on a motor position signal, counts UP / DOWN every cycle, and outputs the counted information as a motor counter signal;
First and second ADC control units for generating a trigger signal based on the motor counter signal;
Based on the trigger signal output from the first ADC control unit, any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal is used. A first ADC that performs AD conversion in synchronization with the counter;
A current signal that is any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal and that is different from the current signal of the first ADC is used as the second ADC. A second ADC that performs AD conversion in synchronization with the motor counter based on the trigger signal output from the control unit;
An inverter control semiconductor device comprising: A motor counter that inputs a triangular wave signal or a sawtooth wave signal generated based on a motor position signal, counts UP / DOWN every cycle, and outputs the counted information as a motor counter signal;
First to third ADC control units for generating a trigger signal based on the motor counter signal;
Based on the trigger signal output from the first ADC control unit, any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal is used. A first ADC that performs AD conversion in synchronization with the counter;
A current signal that is any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal and that is different from the current signal of the first ADC is used as the second ADC. A second ADC that performs AD conversion in synchronization with the motor counter based on the trigger signal output from the control unit;
A current signal that is any one of a U-phase current signal, a V-phase current signal, and a W-phase current signal as a motor current value feedback signal and that is different from the current signals of the first ADC and the second ADC. A third ADC that performs AD conversion in synchronization with the motor counter based on the trigger signal output from the third ADC control unit;
An inverter control semiconductor device comprising: Multiple motors,
An inverter control unit that generates an inverter control signal for controlling any one of the plurality of motors in synchronization with a motor counter, and outputs the inverter control signal to each of the plurality of motors;
An inverter control semiconductor device comprising:

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