JP2006352766A - Amplitude limiter circuit for transmitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplitude limiter circuit for a transmitter capable of switching for each radio wave form and adjusting a limit value and a response speed of a limiter. <P>SOLUTION: An IF limiter 23 is provided in digital signal processing on an IF stage using an FPGA. If an IF signal is input, the IF limiter 23 multiplies the IF signal by a limiter gain G using a multiplier 33 to control an amplitude of the input signal. An absolute value of an output signal of the multiplier 33 is extracted by an absolute value circuit 35, input to a comparator 36 and compared with an amplitude limit value held in an amplitude limit value holding section 37. A comparison result of the comparator 36 is input to a multiplier 38, multiplied by a coefficient μatt or μrec selected by a coefficient setting circuit 39 and given to the multiplier 33 via a peak limit circuit 40 as a limiter gain G. The coefficient setting circuit 39 judges whether the input absolute value is above the amplitude limit value or not and if above, the coefficient μatt is selected but if below, the coefficient μrec is selected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an amplitude limiter circuit of a transmitter that is mounted on a transmitter and limits the amplitude of an IF (Intermediate Frequency) signal.

  Conventionally, the most common method for limiting the amplitude of an IF signal (intermediate frequency signal) in a transmitter is to clip the amplitude of the signal at a certain constant value. For example, limiter circuits using analog circuits using various diodes and operational amplifiers are widely used.

Further, as a known technique related to the present invention, in a transmitter that performs amplitude modulation processing on a reference high-frequency signal and outputs a pulse signal in response to a transmission trigger, a part of the transmission output signal is taken out with the same amplitude by an amplitude limiter. A technique is known in which a phase compensation signal is generated based on a signal, and the phase of the reference high-frequency signal is changed to reduce the phase modulation component included in the transmission signal (see, for example, Patent Document 1). .
JP-A-3-3507

  The conventional limiter circuit using an analog circuit using various diodes and operational amplifiers has a drawback that high-speed operation cannot be expected due to the recovery time and time constant of the diode. Further, if the signal amplitude is clipped at a certain constant value, the clipped portion becomes a complete rectangular wave, which causes a fatal band expansion for the transmitter. Furthermore, there is a problem that the limiter adjustment range is limited due to the configuration by hardware, and that it is difficult to cope with each radio wave format when incorporating into an existing circuit.

  The present invention has been made in order to solve the above-described problems, and is a transmitter that can be switched for each radio wave format by digital signal processing at the IF stage, and can also adjust a limit value and a response speed of a limiter. An object is to provide an amplitude limiter circuit.

  The present invention provides a first multiplier for limiting an amplitude of an input signal by multiplying an input intermediate frequency signal by a limiter gain in an amplitude limiter circuit provided in a digital signal processing unit at an intermediate frequency stage by an FPGA in a transmitter. And an absolute value circuit that extracts a part of the signal output from the first multiplier and obtains an absolute value, and compares the absolute value of the signal extracted by the absolute value circuit with a target amplitude limit value A comparator that outputs a limiter gain by multiplying the comparison result of the comparator by a coefficient, an intermediate frequency signal that is amplitude-limited by the first multiplier, and before the limiter processing. A transmitter amplitude limiter circuit comprising: a selector that selects the intermediate frequency signal according to the radio wave format.

  According to the present invention, since the amplitude limiter circuit performs digital signal processing at the intermediate frequency stage by the FPGA in the transmitter, there is no need to consider the recovery time and time constant of the diode as in the prior art, and the operating speed is reduced. Can be improved. In addition, the limiter process can gradually change the amplitude of the input signal according to the limiter gain value. Therefore, adjusting the value of the coefficient that controls the limiter gain value can sufficiently widen the band after passing the limiter. Can be reduced. Further, the response time of the limiter can be adjusted by adjusting the coefficient. Moreover, the limiter operation can be switched according to the radio wave format by selecting the input signal before the limiter process and the signal after the limiter process according to the radio wave format by the selector. Furthermore, by performing all of the above processing with an FPGA, the circuit configuration can be simplified as compared to an analog circuit, and the circuit can be easily changed, thereby improving the production efficiency.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration example of a transmitter 10 in which the present invention is introduced. In FIG. 1, reference numeral 11 is a reference oscillator that generates a signal of a reference frequency. A reference signal output from the reference oscillator 11 is input to an SSB (Single Side Band) modulator 12 and also to a synthesizer 13. The synthesizer 13 generates a signal having a predetermined frequency based on the reference signal output from the reference oscillator 11 and outputs the signal to the frequency converter 14.

  The SSB modulator 12 is provided with a limiter function as will be described in detail later. The externally input AF (Audio Frequency) signal is subjected to SSB modulation processing and converted into an IF signal, and this IF signal is subjected to limiter processing. And output to the frequency converter 14. The frequency converter 14 converts the IF signal output from the SSB modulator 12 into a high-frequency signal based on a signal having a predetermined frequency supplied from the synthesizer 13. The high-frequency signal output from the frequency converter 14 is amplified by the excitation amplifier 15 and the power amplifier 16, then sent to the antenna 18 through the tuning / matching circuit 17, and transmitted from the antenna 18 to the outside.

FIG. 2 is a block diagram showing a configuration example of the SSB modulator 12.
The SSB modulator 12 is configured by an FPGA (Field Programmable Gate Array) to perform digital signal processing, and includes an SSB modulation processing unit 21 and an amplitude limiter circuit 22. The amplitude limiter circuit 22 includes an IF limiter 23, a low-pass filter (LPF) 24, and a selector 25.

The SSB modulation processing unit 21 performs an SSB modulation process on an AF (Audio Frequency) signal input from the outside, converts it into an IF signal, and outputs the IF signal. The IF signal output from the SSB modulation processing unit 21 is divided into two systems and input to the IF limiter 23 of the amplitude limiter circuit 22 and the input terminal A of the selector 25. Details of the IF limiter 23 will be described later.
As described above, the amplitude limiter circuit 22 is provided in the digital signal processing unit at the intermediate frequency stage by the FPGA in the transmitter 10.

  The IF signal input from the SSB modulation processing unit 21 to the IF limiter 23 is subjected to limiter processing and sent to the low-pass filter 24. The low-pass filter 24 is for removing harmonic components generated during the limiter processing in the IF limiter 23, and its output signal is input to the input terminal B of the selector 25. The selector 25 selects an input signal at the input terminal A or B according to a radio wave format selection signal input from the outside, and outputs it to the frequency converter 14 shown in FIG. There are various types of radio wave formats such as “A1A”, “F1B”, “J3E”,..., But the selection operation of the selector 25 can be arbitrarily set according to the use request. In this example, for example, when the “F1B” radio wave format by frequency modulation is used, the selector 25 is switched to the input terminal B side to perform the limiter operation, and in other radio wave formats, the selector 25 is switched to the input terminal A side. Set not to perform limiter operation. In the case of frequency modulation, it is desirable that the amplitude of the signal is constant, so the selector 25 is switched so as to select the IF signal subjected to the limiter process.

FIG. 3 is a block diagram showing a configuration example of the IF limiter 23.
The IF limiter 23 is provided with a variable gain multiplier 33 between an input terminal 31 and an output terminal 32. An absolute value circuit 35 is connected to a signal line 34 that connects between the variable gain multiplier 33 and the output terminal 32. The absolute value circuit 35 extracts a part of the signal output from the multiplier 33 and inputs the absolute value to the comparator 36. Further, the target amplitude limit value held in the amplitude limit value holding unit 37 is input to the comparator 36. The comparator 36 compares the absolute value of the signal extracted by the absolute value circuit 35 with the amplitude limit value, and inputs the comparison result to the multiplier 38.

  The multiplier 38 is given a coefficient μ set by the coefficient setting circuit 39. The coefficient setting circuit 39 can adjust the response waveform of the limiter by setting different values depending on whether the absolute value of the input exceeds or falls below the amplitude limit value. That is, the coefficient setting circuit 39 determines the magnitude relationship between the absolute value of the input and the amplitude limit value by FPGA processing, selects the coefficient μatt when the absolute value of the input exceeds the amplitude limit value, and selects the absolute value of the input Is smaller than the amplitude limit value, the coefficient μrec is selected and supplied to the multiplier 38. The value of the coefficient μ (μatt, μrec) is set in consideration of the band expansion after passing through the limiter and the response time of the limiter.

  The multiplier 38 multiplies the comparison result of the comparator 36 by the coefficient μatt or coefficient μrec selected by the coefficient setting circuit 39, and gives the result to the multiplier 33 as a limiter gain G. In this case, if the result obtained by multiplying the output of the comparator 36 by the coefficient μ (μatt, μrec) by the multiplier 38 is used as it is, the limiter gain G may continue to increase or decrease. Therefore, the peak limiting circuit 40 is provided. Thus, the maximum value Gmax and the minimum value Gmin of the limiter gain G are limited to predetermined values.

  In the IF limiter 23 configured as described above, when the IF signal that has been subjected to the SSB modulation processing by the SSB modulation processing unit 21 is input, the multiplier 33 multiplies the limiter gain G and the amplitude of the input signal is a target value. Control to be In this case, the amplitude is corrected in the decreasing direction when G <1, and conversely the increasing direction when G> 1, but there is no change in the amplitude when G = 1. The value of the limiter gain G is determined by an input and a feedback loop for the multiplier 33.

  That is, the absolute value of the signal output from the multiplier 33 is extracted by the absolute value circuit 35 and input to the comparator 36 and compared with the amplitude limit value held in the amplitude limit value holding unit 37. The comparison result of the comparator 36 is sent to the multiplier 38, and is multiplied by the coefficient μatt or μrec selected by the coefficient setting circuit 39 to update the limiter gain G. The coefficient setting circuit 39 determines whether or not the absolute value of the input exceeds the amplitude limit value. If the absolute value of the input exceeds the amplitude limit value, the coefficient setting circuit 39 selects the coefficient μatt. If it is below the amplitude limit value, the coefficient μrec is selected.

  The limiter gain G output from the multiplier 38 is input to the multiplier 33 with the maximum value Gmax and the minimum value Gmin being limited by the peak limiting circuit 40. The multiplier 33 controls the input signal so that the amplitude of the input signal approaches a target value by multiplying the input signal by a limiter gain G. Therefore, by repeating the amplitude control using the limiter gain G, the amplitude of the input signal can be held at a target value.

  As described above, the IF signal output from the SSB modulation processing unit 21 is limited to an amplitude value set in advance by the IF limiter 23, and is sent to the low-pass filter 24 shown in FIG. The low-pass filter 24 removes harmonic components generated during the limiter process from the IF signal output from the IF limiter 23 and inputs the IF signal to the input terminal B of the selector 25. As described above, the selector 25 selects the input signal of the input terminal A or the input terminal B by the radio wave format selection signal input from the outside, and outputs it to the frequency converter 14 shown in FIG. The selector 25 selects a limiter-processed IF signal input to the input terminal B when the radio wave format is a specific radio wave format set in advance, for example, “F1B” by frequency modulation, and other radio wave formats. Is selected, the IF signal that is input to the input terminal A and is not subjected to limiter processing is selected and output.

  According to the above embodiment, the amplitude limiter circuit 22 performs digital signal processing at the intermediate frequency stage IF stage by the FPGA in the transmitter 10, and thus it is necessary to consider the recovery time and time constant of the diode as in the past. In addition, the operation speed can be improved.

  In the limiter process in the IF limiter 23, the amplitude of the input signal can be gradually changed by the value of the limiter gain G output from the multiplier 38. Therefore, the value of the coefficient μ in the coefficient setting circuit 39 is adjusted. Thus, the spread of the band after passing through the limiter can be sufficiently reduced. That is, the value of the limiter gain G given to the multiplier 33 is a value obtained by multiplying the comparison result of the comparator 36 by the coefficient μ, so that the value of the limiter gain G is adjusted by adjusting the value of the coefficient μ. can do. When the change of the limiter gain G is large, the output change of the IF signal is also large, so that the distortion with respect to the input is large. Since the waveform distortion in the time domain becomes a band expansion in the frequency domain, the band expansion can be adjusted by adjusting the coefficient μ as a result.

  Further, the response time of the limiter can be adjusted by adjusting the coefficient μ in the coefficient setting circuit 39. The response time of the limiter is the time required for the output signal to reach the amplitude limit value, and the time can be shortened as the value of the coefficient μ increases. Since “band broadening” and “limiter response time” after passing through the limiter are in a reciprocal relationship, the coefficient μ is adjusted so that both values are optimum.

  Further, the input signal before the limiter process is divided into two systems and input to the IF limiter 23 and the selector 25, and the selector 25 selects ON / OFF of the IF limiter 23 according to the radio wave format and outputs it. Therefore, the limiter operation can be switched according to the radio wave format.

  Furthermore, since all of the above processing is performed by the FPGA, the circuit configuration can be simplified as compared with an analog circuit, and the circuit can be easily changed, thereby improving the production efficiency.

It is a block diagram which shows the schematic structural example of the transmitter which concerns on one Embodiment of this invention. It is a block diagram which shows the structural example of the SSB modulator in FIG. FIG. 3 is a block diagram illustrating a configuration example of an IF limiter in FIG. 2.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Transmitter, 11 ... Reference oscillator, 12 ... SSB modulator, 13 ... Synthesizer, 14 ... Frequency converter, 15 ... Excitation amplifier, 16 ... Power amplifier, 17 ... Tuning and matching circuit, 18 ... Antenna, 21 ... SSB Modulation processing unit, 22 ... Amplitude limiter circuit, 23 ... IF limiter, 24 ... Low pass filter (LPF), 25 ... Selector, 31 ... Input terminal, 32 ... Output terminal, 33 ... Multiplier, 34 ... Signal line, 35 ... Absolute Value circuit 36... Comparator 37. Amplitude limit value holding unit 38. Multiplier 39. Coefficient setting circuit 40. Peak limit circuit

Claims (1)

In the amplitude limiter circuit provided in the digital signal processing unit at the intermediate frequency stage by the FPGA in the transmitter,
A first multiplier that limits the amplitude of the input signal by multiplying an input intermediate frequency signal by a limiter gain;
An absolute value circuit for extracting a part of the signal output from the first multiplier and obtaining an absolute value;
A comparator for comparing the absolute value of the signal extracted by the absolute value circuit with a target amplitude limit value;
A second multiplier for multiplying the comparison result of the comparator by a coefficient and outputting the limiter gain;
An amplitude limiter circuit for a transmitter, comprising: a selector that selects an intermediate frequency signal whose amplitude is limited by the first multiplier and an intermediate frequency signal before the limiter process according to a radio wave format. .

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