JP2006351851A - Semiconductor device, manufacturing method therefor and operational amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To discretely control back-gate biases together with transistors, while inhibiting junction leakage currents at the source/drain junction. <P>SOLUTION: Impurity ions are implanted partially to a semiconductor substrate 11, wells 12a and 12b are formed to the semiconductor substrate 11, and an insulating layer 13 is formed on the surface of the semiconductor substrate 11. The semiconductor substrate 21 is stuck together on the insulating layer 13 on the semiconductor substrate 11 via a single-crystal semiconductor layer 23, and the semiconductor substrate 21 is peeled from the single-crystal semiconductor layer 23, while using a porous layer 22 as a boundary by ething-removing the porous layer 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, an operational amplifier, and a method for manufacturing a semiconductor device, and is particularly suitable for application to a field effect transistor having a back gate structure.

  In recent field effect transistors, the gate length is shortened to the submicron order in order to promote higher density and higher speed of the semiconductor integrated circuit. Here, in order to reduce the source / drain parasitic resistance while suppressing the short channel effect of the miniaturized field effect transistor, there is a method of using a Schottky junction for the source / drain of the field effect transistor. Non-Patent Document 1 discloses a method of controlling the back gate bias of a Schottky barrier transistor in order to reduce the off-leak current of the Schottky barrier transistor using Schottky junctions for the source / drain.

Further, Non-Patent Document 2 discloses a method of forming a well under a buried oxide film of an SOI substrate so that the back gate bias of the Schottky barrier transistor can be individually controlled for each transistor.
Proceedings of the 65th Annual Meeting of the Japan Society of Applied Physics P775 3p-L-6 “Back gate bias dependence of cutoff current in fully depleted Schottky barrier SOI / MOSFET” P65 3p-L-7 “Evaluation of fully depleted SOI CMOSFET with back gate”

However, since the off current of the Schottky barrier transistor is determined by the physical properties of the metal compound constituting the source / drain, it is difficult to control the off current of the Schottky barrier transistor. Is used for a common source amplifier of an operational amplifier, there is a problem that power consumption is increased.
In addition, the method disclosed in Patent Document 1 has a problem in that a back gate bias is applied to the entire substrate on which the Schottky barrier transistor is formed, which may adversely affect the characteristics of other transistors.

Furthermore, in the method disclosed in Patent Document 2, in order to form a well under the buried oxide film of the SOI substrate, it is necessary to perform high energy ion implantation on the SOI substrate. Therefore, there is a problem that the SOI layer is damaged and the junction leakage current at the source / drain junction increases.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device, an operational amplifier, and a semiconductor device manufacturing method capable of individually controlling a back gate bias for each transistor while suppressing junction leakage current at a source / drain junction. That is.

In order to solve the above problems, according to a semiconductor device of one embodiment of the present invention, a single crystal semiconductor layer formed over a semiconductor substrate with an insulating layer interposed therebetween, and a shot formed in the single crystal semiconductor layer It is characterized by comprising a key barrier transistor and a well layer formed on the semiconductor substrate and arranged corresponding to the position of the Schottky barrier transistor.
As a result, the source / drain parasitic resistance can be reduced while suppressing the short channel effect of the miniaturized field effect transistor, and the back gate bias can be individually controlled for each transistor. The off-state current of the Schottky barrier transistor can be reduced without adversely affecting the characteristics of other transistors.

  In addition, according to the semiconductor device of one embodiment of the present invention, the first and second single crystal semiconductor layers formed on the semiconductor substrate with the insulating layer interposed therebetween and mesa-isolated from each other, and the first single crystal semiconductor layer A P-channel Schottky barrier transistor formed on the semiconductor substrate, an N-channel Schottky barrier transistor formed on the second single crystal semiconductor layer, and a position of the P-channel Schottky barrier transistor formed on the semiconductor substrate. And a second well layer formed on the semiconductor substrate and corresponding to the position of the N-channel Schottky barrier transistor.

  As a result, the back gate bias of the P-channel Schottky barrier transistor and the N-channel Schottky barrier transistor can be individually controlled, and the Schottky barrier transistor can be turned off without adversely affecting the characteristics of other transistors. The current can be reduced, and the source / drain parasitic resistance can be reduced while suppressing the short channel effect.

According to the operational amplifier of one embodiment of the present invention, the differential amplifier circuit, the source grounded transistor that amplifies the output from the differential amplifier circuit, and the operating point of the source grounded field effect transistor are set. A bias transistor, and a back gate of the bias transistor is connected to a power supply potential.
As a result, the off current of the bias transistor can be reduced, and the power consumption of the operational amplifier can be reduced while optimizing the driving capability of the operational amplifier.

The operational amplifier according to one aspect of the present invention is characterized in that the differential amplifier circuit, the source grounded transistor, and the bias transistor are composed of Schottky barrier transistors.
As a result, it is possible to increase the bandwidth of the operational amplifier while suppressing a decrease in the gain of the operational amplifier, and to reduce the size of the operational amplifier.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the well layer on the first semiconductor substrate and the insulating layer on the surface of the first semiconductor substrate on which the well layer is formed. A step of bonding a second semiconductor substrate on the insulating layer; and a step of thinning the second semiconductor substrate bonded on the insulating layer.

  Thereby, after forming a well layer in the first semiconductor substrate, a single crystal semiconductor layer disposed via the insulating layer can be formed on the first semiconductor substrate. Therefore, a back gate can be individually arranged for each SOI transistor, and it is not necessary to perform high energy ion implantation on the SOI substrate in order to form the back gate of the SOI transistor. Sometimes damage to the SOI layer can be prevented. Therefore, it is possible to individually control the back gate bias for each SOI transistor while suppressing the junction leakage current at the source / drain junction, and to achieve both high speed and low power consumption of the field effect transistor. Can do.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the well layer on the first semiconductor substrate and the insulating layer on the surface of the first semiconductor substrate on which the well layer is formed. A step of forming a porous layer having a porous surface layer on a second semiconductor substrate; and a step of hydrogenating the porous layer to monocrystallize the surface layer of the porous layer, thereby A step of forming a single crystal semiconductor layer on the layer, a step of bonding the second semiconductor substrate on the insulating layer via the single crystal semiconductor layer, and the second semiconductor substrate on the porous layer as a boundary. And a step of peeling from the single crystal semiconductor layer.

  As a result, it is possible to form the single crystal semiconductor layer disposed via the insulating layer on the first semiconductor substrate after forming the well layer on the first semiconductor substrate, and to form the film of the single crystal semiconductor layer. Thickness controllability can be improved, and both high speed and low power consumption of the field effect transistor can be achieved.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention.
In FIG. 1, an insulating layer 3 is formed on a semiconductor substrate 1, and single crystal semiconductor layers 4 a and 4 b that are separated from each other are formed on the insulating layer 3. In addition, as a material of the semiconductor substrate 1 and the single crystal semiconductor layers 4a and 4b, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like can be used. As 3, for example, an insulating layer such as SiO ₂ , SION, or Si ₃ N ₄ or a buried insulating film can be used. Gate electrodes 6a and 6b are arranged on the single crystal semiconductor layers 4a and 4b via gate insulating films 5a and 5b, respectively, and sidewalls 11a and 11b are formed on the side walls of the gate electrodes 6a and 6b, respectively. ing.

  Further, a source layer 8a made of an alloy layer or a metal layer in contact with the insulating layer 3 is disposed on one side of the gate electrode 6a, and a bottom surface of the insulating layer 3 is disposed on the other side of the gate electrode 6a. A drain layer 9a made of an alloy layer or a metal layer in contact with is disposed. And the alloy layer or metal layer which comprises the source layer 8a and the drain layer 9a has performed Schottky junction between the channel region 7a which consists of the single crystal semiconductor layer 4a.

  Further, a source layer 8b made of an alloy layer or a metal layer whose bottom surface is in contact with the insulating layer 3 is disposed on one side of the gate electrode 6b, and a bottom surface of the insulating layer 3 is disposed on the other side of the gate electrode 6b. A drain layer 9b made of an alloy layer or a metal layer in contact with is disposed. And the alloy layer or metal layer which comprises the source layer 8b and the drain layer 9b is Schottky junction between the channel region 7b which consists of the single crystal semiconductor layer 4b. Note that the alloy layers constituting the source layers 8a and 8b and the drain layers 9a and 9b can be formed by reacting a metal with the single crystal semiconductor layers 4a and 4b. The single crystal semiconductor layers 4a and 4b are formed of a single crystal. In the case of Si, the silicide and single crystal semiconductor layers 4a and 4b are made of single crystal SiGe. In the case of germanosilicide and the single crystal semiconductor layers 4a and 4b are made of single crystal Ge, a germanoid can be used. The metal contained in the alloy layer can be alloyed by reacting with the single crystal semiconductor layers 4a and 4b. For example, Ti, Co, W, Mo, Ni, Pt, or the like can be used.

In addition, wells 2a and 2b are formed in the semiconductor substrate 1 so as to face the channel regions 7a and 7b of the Schottky barrier transistor, respectively. In the insulating layer 3, buried electrodes 10a and 10b for individually controlling the potentials of the wells 2a and 2b are buried.
As a result, the parasitic resistance of the source layers 8a and 8b and the drain layers 9a and 9b can be reduced while suppressing the short channel effect, and the back gate bias of the channel regions 7a and 7b can be individually set for each transistor. Thus, the off-state current can be reduced without adversely affecting the characteristics of other transistors.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
In FIG. 2A, the surface layer of the semiconductor substrate 21 is made porous by anodizing the semiconductor substrate 21, and the porous layer 22 is formed on the semiconductor substrate 21.
Next, as shown in FIG. 2 (b), the porous layer 22 formed on the semiconductor substrate 21 is subjected to hydrogen treatment, so that the surface layer of the porous layer 22 is single-crystallized. A crystalline semiconductor layer 23 is formed.

On the other hand, in FIG. 2C, impurity ions are implanted locally into the semiconductor substrate 11, thereby forming wells 12 a and 12 b separated from each other in the semiconductor substrate 11. Note that when an N-channel field effect transistor is formed, boron is preferably used as an impurity, and when an P-channel field effect transistor is formed, arsenic or phosphorus is preferably used as an impurity. The dose amount of impurities can be 10 ²¹ cm ² or more. Here, by setting the impurity dose amount to 10 ²¹ cm ² or more, the wells 12a and 12b can be doped at a high concentration, and the wells 12a and 12b can be stably isolated. , Parasitic resistance can be reduced.

Next, as shown in FIG. 2D, the insulating layer 13 is formed on the surface of the semiconductor substrate 11 by thermally oxidizing the surface of the semiconductor substrate 11 on which the wells 12a and 12b are formed.
Next, as illustrated in FIG. 2E, the semiconductor substrate 21 is bonded to the insulating layer 13 over the semiconductor substrate 11 with the single crystal semiconductor layer 23 interposed therebetween.
Next, as shown in FIG. 2 (f), the porous layer 22 is removed by etching, whereby the semiconductor substrate 21 is separated from the single crystal semiconductor layer 23 with the porous layer 22 as a boundary. Then, the surface of the single crystal semiconductor layer 23 is polished by a method such as CMP (Chemical Mechanical Polishing).

Then, the single crystal semiconductor layer 23 placed over the insulating layer 13 is mesa-isolated, and an SOI transistor can be formed in the mesa-isolated single crystal semiconductor layer 23.
Thereby, after forming the wells 12 a and 12 b in the semiconductor substrate 11, the single crystal semiconductor layer 23 disposed via the insulating layer 13 can be formed on the semiconductor substrate 11. Therefore, a back gate can be individually arranged for each SOI transistor, and it is not necessary to perform high energy ion implantation on the SOI substrate in order to form the back gate of the SOI transistor. Sometimes, damage to the single crystal semiconductor layer 23 can be prevented. Therefore, it is possible to individually control the back gate bias for each SOI transistor while suppressing the junction leakage current at the source / drain junction, and to achieve both high speed and low power consumption of the field effect transistor. Can do.

FIG. 3 is a circuit diagram showing a schematic configuration of an operational amplifier according to the third embodiment of the present invention.
In FIG. 3, the operational amplifier is provided with P-channel field effect transistors P1 to P3 and N-channel field effect transistors N1 to N4. Here, the P-channel field effect transistors P1 and P2 and the N-channel field effect transistors N1 to N3 constitute a differential amplifier circuit, and the P-channel field effect transistor P3 and the N-channel field effect transistor N4 are grounded to the source. Type power amplifier. The P-channel field effect transistors P1 and P2 constitute a current mirror, and the N-channel field effect transistors N2 and N3 constitute an input transistor to which differential inputs S1 and S2 are input. Further, the N-channel field effect transistors N1 and N4 constitute a bias transistor that sets an operating point based on the bias voltage Vb.

The driving capability of the operational amplifier is determined by the current flowing through the N-channel field effect transistor N4. By increasing the size of the N-channel field effect transistor N4, the driving capability of the operational amplifier can be increased.
Here, Schottky barrier transistors can be used as the P-channel field effect transistors P1 to P3 and the N-channel field effect transistors N1 to N4. Further, the Schottky barrier transistors used for the channel field effect transistors P1 to P3 and the N channel field effect transistors N1 to N4 can be provided with a back gate as shown in FIG. Furthermore, when a back gate is provided in the Schottky barrier transistors used in the channel field effect transistors P1 to P3 and the N channel field effect transistors N1 to N4, the well formed by the method of FIG. 2 can be used.

The back gate of the N-channel field effect transistor N4 is connected to the power supply potential Vdd. Further, the back gate of the P-channel field effect transistor N3 may be connected to the power supply potential Vss.
When the differential inputs S2 and S1 are respectively input to the gates of the N-channel field effect transistors N2 and N3, the drain potential of the N-channel field effect transistor N2 corresponding to the inputs is changed to the P-channel field effect transistor P3. Input to the gate. Then, after power amplification by the P-channel field effect transistor P3, the output voltage Vo is output via the source of the P-channel field effect transistor P3.

  Here, by connecting the back gate of the N-channel field-effect transistor N4 to the power supply potential Vdd, the off-current of the bias transistor can be reduced, and the operational capability of the operational amplifier can be optimized while the operational capability of the operational amplifier is optimized. Power consumption can be reduced. Further, by using Schottky barrier transistors as the P-channel field effect transistors P1 to P3 and the N-channel field effect transistors N1 to N4, the bandwidth of the operational amplifier is expanded while suppressing a decrease in the gain of the operational amplifier. In addition, the operational amplifier can be downsized.

FIG. 4 is a diagram showing the characteristics of the operational amplifier according to the embodiment of the present invention in comparison with the conventional example. S1 is the relationship between the power consumption and the GB product (Gain Bandwidth Product) of an operational amplifier composed of a field effect transistor whose source / drain is a PN junction, and S2 is a source / drain having a PN junction. The relationship between the power consumption of an operational amplifier composed of a field effect transistor having a back gate and the GB product, S3 is the power consumption of an operational amplifier composed of a field effect transistor whose source / drain is a Schottky junction. S4 represents the relationship between the power consumption and the GB product of an operational amplifier composed of a field effect transistor having a source / drain formed of a Schottky junction and having a back gate.
In FIG. 4, a Schottky barrier transistor is used as a field effect transistor constituting the operational amplifier, and a back gate is provided in the Schottky barrier transistor, thereby reducing power consumption at the time of off and increasing the bandwidth of the operational amplifier. Can be planned.

1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The circuit diagram which shows schematic structure of the operational amplifier which concerns on 3rd Embodiment of this invention. The figure which shows the characteristic of the operational amplifier which concerns on embodiment of this invention compared with a prior art example.

Explanation of symbols

  1, 11, 21 Semiconductor substrate, 2a, 2b, 12a, 12b Well, 3, 13 Insulating layer, 4a, 4b, 23 Single crystal semiconductor layer, 5a, 5b Gate insulating film, 6a, 6b Gate electrode, 7a, 7b Body Region, 8a, 8b source layer, 9a, 9b drain layer, 10a, 10b buried electrode, 11a, 11b sidewall, 22 porous semiconductor layer, P1-P3 P-channel field effect transistor, N1-N4 N-channel field effect type Transistor

Claims (6)

A single crystal semiconductor layer formed over a semiconductor substrate via an insulating layer;
A Schottky barrier transistor formed in the single crystal semiconductor layer;
A semiconductor device comprising: a well layer formed on the semiconductor substrate and disposed corresponding to a position of the Schottky barrier transistor. First and second single crystal semiconductor layers formed on a semiconductor substrate via an insulating layer and separated from each other by mesa;
A P-channel Schottky barrier transistor formed in the first single crystal semiconductor layer;
An N-channel Schottky barrier transistor formed in the second single crystal semiconductor layer;
A first well layer formed on the semiconductor substrate and disposed corresponding to the position of the P-channel Schottky barrier transistor;
A semiconductor device comprising: a second well layer formed on the semiconductor substrate and disposed corresponding to the position of the N-channel Schottky barrier transistor. A differential amplifier circuit;
A common source transistor for amplifying an output from the differential amplifier circuit;
A bias transistor for setting an operating point of the common source field effect transistor,
An operational amplifier, wherein a back gate of the bias transistor is connected to a power supply potential.   4. The operational amplifier according to claim 3, wherein the differential amplifier circuit, the common-source transistor, and the bias transistor are each composed of a Schottky barrier transistor. Forming a well layer on the first semiconductor substrate;
Forming an insulating layer on the surface of the first semiconductor substrate on which the well layer is formed;
Bonding a second semiconductor substrate on the insulating layer;
And a step of thinning the second semiconductor substrate bonded onto the insulating layer. Forming a well layer on the first semiconductor substrate;
Forming an insulating layer on the surface of the first semiconductor substrate on which the well layer is formed;
Forming a porous layer having a porous surface layer on the second semiconductor substrate;
Forming a single crystal semiconductor layer on the porous layer by single-crystallizing a surface layer of the porous layer by hydrogen treatment of the porous layer; and
Bonding the second semiconductor substrate on the insulating layer through the single crystal semiconductor layer;
And a step of peeling the second semiconductor substrate from the single crystal semiconductor layer with the porous layer as a boundary.

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