JP2006351829A - 2-bit memory type semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a current value reading when a charging region is charged to be sufficiently small, with a small memory element area. <P>SOLUTION: Charge retainers 130 and 140 consisting of SiO films 131 and 141, SiN films 132 and 142, and SiO films 133 and 143 are provided on both sides at the lower part of a gate 160. On both side surfaces of the gate 160, a charge retainer consisting of SiO films 171 and 181 and SiN films 172 and 182 is provided. Since most electrons that move from the gate 160 to LDD regions 112 and 122 are accumulated in the SiN films 132, 142, 172, and 182 at electron accumulation operation, a current value reading when the charging region is charged can be reduced close to 0 ampere, resulting in improving a reading margin. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device including a nonvolatile memory element that stores 2-bit information and a manufacturing method thereof.

  Conventionally, nonvolatile semiconductor memory elements that store 2-bit information are known. Such a semiconductor memory device is disclosed, for example, in Patent Documents 1 and 2 below.

  The memory element disclosed in Patent Document 1 has a stack of oxide 109-nitride 110-oxide 111 between a semiconductor substrate and a polysilicon gate 112. 3 have chargeable regions 106 and 108 (see paragraph 0003 of FIG. 1 and FIG. 1).

  In the semiconductor memory device having such a configuration, only the region 106 is charged, only the region 108 is charged, both the regions 106 and 108 are charged, and both the regions 106 and 108 are not charged. Four states can be obtained, whereby quaternary information, ie 2-bit information, can be stored.

  In such a memory element, the drain current is reduced by charging the regions 106 and 108. Here, in the case where the bit line 102 is used as a source, the drain current of the memory element changes depending on the charging / uncharging of the region 106 (smaller during charging) but the charging / non-charging of the region 108. It does not depend on charging. When the bit line 104 is used as a source, the current flowing through the memory element changes depending on charging / uncharging of the region 108, but does not depend on charging / uncharging of the region 106. Therefore, 2-bit stored information can be read by flowing currents in both directions through the regions 106 and 108.

On the other hand, the memory element disclosed in Patent Document 2 has “L” type nitride material 20 on both side surfaces of the word gate 21 (see Paragraph 0019 and FIG. 3A of Patent Document 2). Even in the semiconductor memory device having such a configuration, only one “L” type nitride material 20 is charged, only the other “L” type nitride material 20 is charged, and both “L” type nitrides are charged. It is possible to obtain four states in which the material 20 is charged and both the “L” type nitride materials 20 are not charged, thereby storing 2-bit information. Further, stored information can be read from the memory element based on the same principle as that of the memory element according to Patent Document 1 described above.
JP 2001-156189 A JP 2003-163292 A

  In the 2-bit memory type memory element, the current when the source-side charging region (the individually chargeable regions 106 and 108 of Patent Document 1 and the “L” type nitride material 20 of Patent Document 2) is charged. The closer the value is to zero amperes, the better. This is because, as the current value is closer to zero ampere, the read margin can be increased, and a decrease in yield due to manufacturing variations in the read current value can be suppressed.

  However, in the conventional memory element, the current value when the charged region is charged cannot be sufficiently reduced. This is because the amount of charge accumulated in the charged region could not be increased sufficiently.

  Here, in order to increase the amount of accumulated charge, the area of the charging region may be increased. However, if the area of the charging region is increased in the memory elements as disclosed in Patent Documents 1 and 2, the area of the element is increased and the degree of integration of the semiconductor memory device is deteriorated.

  The present invention provides a 2-bit storage type semiconductor memory device having a sufficiently small read current value when the charged region is charged and a small memory element area, and such a 2-bit storage type semiconductor memory device manufactured at low cost. An object of the present invention is to provide a manufacturing method that can be used.

  (1) A two-bit storage type semiconductor memory device according to a first aspect of the present invention includes a first impurity region, a first impurity region, and a channel formation region formed on a surface region of a semiconductor substrate with a channel formation region interposed therebetween. A first lower insulating film formed on a boundary region between the first lower insulating film, a first charge holding film formed on the first lower insulating film and having a smaller energy gap than the first lower insulating film, and a first charge holding film A first charge holding portion having a first upper insulating film formed to cover the upper surface and the inner side surface and having a larger energy gap than the first charge holding film; and on a boundary region between the second impurity region and the channel formation region A second lower insulating film formed on the second lower insulating film, a second charge holding film formed on the second lower insulating film and having an energy gap smaller than that of the second lower insulating film, and an upper surface and an inner side surface of the second charge holding film. Formed to cover A second charge holding portion having a second upper insulating film having an energy gap larger than that of the second charge holding film, and a gate insulating film formed on a region sandwiched between the first and second charge holding portions. The gate portion formed in the region extending from the first and second charge holding portions to the gate insulating film, and from the side surface of the first charge holding portion and the gate portion on the first impurity region side to the surface of the first impurity region A first side having a first side insulating film covering the straddling region and a third charge retention film formed to cover the surface of the first side insulating film and having an energy gap smaller than that of the first side insulating film A wall, a second charge insulating portion, a second side insulating film covering a region extending from a side surface on the second impurity region side of the gate portion to a surface of the second impurity region, and a surface of the second side insulating film Formed on the second side insulating film. Tsu and a second side wall and a flop smaller fourth charge holding film.

  (2) In the method for manufacturing a 2-bit memory type semiconductor memory device according to the second invention, a first insulating film and a second insulating film having an energy gap smaller than that of the first insulating film are formed on the semiconductor substrate. A first step, a second step of exposing the surface of the semiconductor substrate by providing openings penetrating the first and second insulating films, and a third energy gap larger than that of the second insulating film over the entire area of the semiconductor substrate. Third step of forming an insulating film, and after forming a gate portion forming layer over the entire area of the semiconductor substrate, the gate portion forming layer and the first to third insulating films in the region other than the region where the opening is formed and its peripheral region The fourth step of forming the gate insulating film, the first and second charge holding portions, and the gate portion by removing the gate, and after forming the fourth insulating film over the entire area of the semiconductor substrate, the gate portion is used as a mask for the semiconductor. Impurities throughout the substrate By introducing the fifth insulating film, a fifth step of forming the first and second impurity regions and a fifth insulating film having an energy gap smaller than that of the fourth insulating film are formed on the surface of the fourth insulating film. Forming a sixth insulating film having a larger energy gap than the fifth insulating film on the surface, and further processing the fourth to sixth insulating films to form first and second sidewalls; Including.

  (3) A method of manufacturing a 2-bit memory type semiconductor memory device according to a third aspect of the present invention includes a first insulating film, a second insulating film having a smaller energy gap than the first insulating film, and a first insulating film on the semiconductor substrate. A first step of sequentially forming a coating film, and further exposing a surface of the second insulating film by providing a first opening penetrating the first coating film; and a second coating film over the entire area of the semiconductor substrate A second step of forming an etch back, a third step of performing etch back until the surface of the semiconductor substrate is exposed by forming the second opening in the central portion of the first opening, and the first and second steps remaining on the surface of the semiconductor substrate. 2) a fourth step of removing the covering film; a fifth step of forming a third insulating film having an energy gap larger than that of the second insulating film over the entire area of the semiconductor substrate; and a gate forming layer over the entire area of the semiconductor substrate. After the formation, the region where the second opening is formed and its peripheral region A sixth step of forming the gate insulating film, the first and second charge holding portions, and the gate portion by removing the gate portion forming layer and the first to third insulating films in the outer region, and the entire region of the semiconductor substrate After the fourth insulating film is formed, impurities are introduced into the entire region of the semiconductor substrate using the gate portion as a mask, thereby forming a first step and a second impurity region, and a seventh step on the surface of the fourth insulating film. A fifth insulating film having an energy gap smaller than that of the fourth insulating film is formed; a sixth insulating film having an energy gap larger than that of the fifth insulating film is formed on a surface of the fifth insulating film; And an eighth step of forming the first and second sidewalls by processing the film.

  (1) A two-bit memory type semiconductor memory device according to the first invention has a first charge holding film under the gate portion and a third charge holding film in the first sidewall corresponding to the first impurity region. In addition, a second charge holding film below the gate portion and a fourth charge holding film in the second sidewall are provided corresponding to the second impurity region. Therefore, according to the first invention, the current value when charges are accumulated in the charge holding film can be made sufficiently small without increasing the memory element area.

  (2) According to the method of manufacturing a 2-bit memory type semiconductor memory device according to the second invention, 2-bit memory having a small memory element area and a sufficiently small current value when charge is accumulated in the charge holding portion. Type semiconductor memory devices can be manufactured inexpensively with a small number of processes.

  (3) According to the method of manufacturing a 2-bit memory semiconductor memory device according to the third invention, the number of 2-bit memory semiconductor memory devices having a sufficiently small current value when charge is accumulated in the charge holding portion is small. It can be manufactured at a low cost by the number of steps, and further miniaturization of the memory element is easier than the manufacturing method according to the second invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement relationship of each component are shown only schematically to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. .

First Embodiment A first embodiment of a 2-bit memory type semiconductor memory device and a method for manufacturing the same according to the present invention will be described with reference to FIGS.

  FIG. 1 is a cross-sectional view schematically showing a memory element structure of a 2-bit memory type semiconductor memory device according to this embodiment.

  As shown in FIG. 1, the memory device according to this embodiment includes first and second impurity regions 110 and 120, first and second charge holding units 130 and 140 formed in a semiconductor substrate 100, A gate insulating film 150, a gate portion 160, first and second sidewalls 170 and 180 having a charge holding function, and an SiO film 190 are provided.

  The impurity region 110 includes a high concentration impurity region 111 and an LDD (Lightly Doped Drain) region 112. The impurity region 120 includes a high concentration impurity region 121 and an LDD region 122. A region between the impurity regions 110 and 120 becomes a channel formation region 101.

  The charge holding unit 130 includes a lower insulating film 131, a charge holding film 132, and an upper insulating film 133. The lower insulating film 131 is formed of, for example, SiO on the boundary region between the impurity region 110 and the channel formation region 101. The charge holding film 132 is formed on the lower insulating film 131 with an insulating material (for example, SiN) having an energy gap smaller than that of the lower insulating film 131. The upper insulating film 133 is formed using an insulating material (for example, SiO) having an energy gap larger than that of the charge holding film 132 so as to cover the upper surface and the inner surface of the charge holding film 132.

  The charge holding unit 140 includes a lower insulating film 141, a charge holding film 142, and an upper insulating film 143. The lower insulating film 141 is formed of, for example, SiO on the boundary region between the impurity region 120 and the channel formation region 101. The charge holding film 142 is formed on the lower insulating film 141 using an insulating material (for example, SiN) having a smaller energy gap than the lower insulating film 141. The upper insulating film 143 is formed using an insulating material (for example, SiO) having a larger energy gap than the charge holding film 142 so as to cover the upper surface and the inner surface of the charge holding film 142.

  The gate insulating film 150 is formed on a region sandwiched between the charge holding portions 130 and 140 on the surface of the semiconductor substrate 100.

  The gate portion 160 is formed on a region extending from the charge holding portions 130 and 140 to the gate insulating film 150. The gate portion 160 includes a polycrystalline Si film 161 and a WSi film 162 that are sequentially stacked, and further includes an SiO film 163 formed on the WSi film 162. Of the gate portion 160, the conductive polycrystalline Si film 161 and the WSi film 162 function as gate electrodes. The insulating SiO film 163 covers the upper surfaces of the gate electrodes 161 and 162.

  The sidewall 170 includes a side insulating film 171, a charge holding film 172, and an insulating film 173. The side insulating film 171 is formed of, for example, SiO so as to cover a region extending from the side surface (side surface on the impurity region 110 side) of the charge holding unit 130 and the gate unit 160 to the surface of the LDD region 112. The charge holding film 172 is formed using an insulating material (eg, SiN) having an energy gap smaller than that of the side insulating film 171 so as to cover the surface of the side insulating film 171. The insulating film 173 is a film for adjusting the shape of the sidewall 170, and is formed of, for example, SiO.

  The sidewall 180 includes a side insulating film 181, a charge holding film 182, and an insulating film 183. The side insulating film 181 is formed of, for example, SiO so as to cover a region extending from the side surface (side surface on the impurity region 120 side) of the charge holding unit 140 and the gate unit 160 to the surface of the LDD region 122. The charge holding film 182 is formed using an insulating material (eg, SiN) having an energy gap smaller than that of the side insulating film 181 so as to cover the surface of the side insulating film 181. The insulating film 183 is a film for adjusting the shape of the sidewall 180, and is formed of, for example, SiO.

  The insulating film 190 is a film that covers the entire memory element, and is formed of, for example, SiO.

  In the memory element shown in FIG. 1, 1-bit information is stored by accumulating / not accumulating electrons in the charge holding films 132 and 172. Further, 1-bit information is stored by accumulating / not accumulating electrons in the charge holding films 142 and 182. The operation of the memory element according to this embodiment will be described below.

  In order to accumulate electrons in the charge holding films 132 and 172, the potential between the semiconductor substrate 100 and the second impurity region 120 is set to 0 volts, and the first impurity region 110 and the gate electrodes 161 and 162 are interposed between them. A potential difference may be generated. For example, by applying +5 volts to the first impurity region 110 and +2 volts to the gate electrodes 161 and 162, electrons can be injected into the charge holding films 132 and 172. In the memory element according to this embodiment, the charge holding film 172 is provided so as to cover almost the entire surface of the LDD region 112, and the charge holding film 132 is provided between the end portion of the LDD region 112 and the gate portion 160. It has been. Therefore, most of the electrons moving from the gate electrodes 161 and 162 toward the LDD region 112 can be stored in the charge holding films 132 and 172.

  In addition, in order to release the electrons accumulated in the charge holding films 132 and 172, the first impurity region 110 and the gate electrode 161, while the potentials of the semiconductor substrate 100 and the second impurity region 120 are set to 0 volts. What is necessary is just to generate the electric potential difference of a reverse direction between 162.

  The electron storage operation and the electron emission operation of the charge holding films 142 and 182 are the same as those of the charge holding films 132 and 172. That is, in the memory element according to this embodiment, the charge holding film 182 is provided so as to cover almost the entire surface of the LDD region 122, and the charge holding film 142 is provided between the end portion of the LDD region 122 and the gate portion 160. Therefore, most of the electrons moving from the gate electrodes 161 and 162 toward the LDD region 122 can be stored in the charge holding films 142 and 182.

  The read operation of the memory element according to this embodiment is the same as that of the conventional memory element. That is, a potential difference may be generated between the first and second impurity regions 110 and 120 in a state where the semiconductor substrate 100 is set to 0 volt and a gate voltage (for example, +1 volt) is applied to the gate portion 160.

  In this read operation, when the first impurity region 110 is a source (for example, an applied potential of 0 volt) and the second impurity region 120 is a drain (for example, an applied voltage +2 volts), the channel formed in the channel formation region 101 is Accordingly, a drain current flows from the second impurity region 120 to the first impurity region 110. Here, when electrons are not accumulated in the charge retention films 132 and 172, the drain current value becomes large regardless of whether or not electrons are accumulated in the charge retention films 142 and 182. On the other hand, when electrons are stored in the charge holding films 132 and 172, the drain current value becomes very small regardless of whether electrons are stored in the charge holding films 142 and 182. As described above, in order to increase the read margin and improve the yield, the drain current value when electrons are accumulated in the charge holding films 132 and 172 is preferably close to 0 ampere. Since the memory element according to this embodiment has a very large amount of accumulated electrons in the charge holding films 132 and 172 for the reasons described above, the drain current value in this case can be made sufficiently close to 0 amperes.

  On the other hand, when the second impurity region 120 is used as a source and the first impurity region 110 is used as a drain, a drain current flows from the first impurity region 110 to the second impurity region 120 through a channel formed in the channel formation region 101. Flowing. As in the case described above, the drain current value is determined by the accumulation / non-accumulation of electrons in the charge retention films 142 and 182. In the memory element according to this embodiment, the drain current value when electrons are accumulated in the charge holding films 142 and 182 can be made sufficiently close to 0 amperes for the same reason as in the case of the charge holding films 132 and 172. it can.

  Next, a method for manufacturing the memory element shown in FIG. 1 will be described with reference to process cross-sectional views in FIGS.

  (1) First, a first insulating film 201 and a second insulating film 202 are sequentially deposited on the surface of the semiconductor substrate 100 by using, for example, a CVD (Chemical Vapor Deposition) method or the like (see FIG. 2A). The first insulating film 201 is a film for obtaining the lower insulating films 131 and 141 (see FIG. 1), and is thus formed of, for example, SiO. The second insulating film 202 is a film for obtaining the charge holding films 132 and 142, and is therefore formed of an insulating material (for example, SiN) having an energy gap smaller than that of the first insulating film.

  (2) A pattern of a photoresist 203 is formed over the entire area of the semiconductor substrate 100 and etching is performed to provide an opening 204 that penetrates the first and second insulating films 201 and 202 (see FIG. 2B). As a result, the surface 205 of the semiconductor substrate 100 is exposed.

  (3) The photoresist 203 is removed, and a third insulating film 206 is deposited over the entire region of the semiconductor substrate 100 by using, for example, a CVD method (see FIG. 2C). The third insulating film 206 is a film for obtaining the upper insulating films 133 and 143 and the gate oxide film 150, and is therefore formed of an insulating material (for example, SiO) having an energy gap larger than that of the second insulating film 202.

  (4) A gate portion forming layer is formed by sequentially depositing a polycrystalline Si film, a WSi film, and a SiO film over the entire area of the semiconductor substrate 100 using, for example, a CVD method. Then, for example, by using a photolithography method, an etching method, or the like, the region other than the region where the opening 204 is formed and its peripheral region is removed from the gate portion formation layer. Accordingly, the gate insulating film 150, the charge holding portions 130 and 140, and the gate portion 160 are formed at the same time (see FIG. 2D).

  (5) A fourth insulating film 207 is formed over the entire area of the semiconductor substrate 100. The fourth insulating film 207 is a film for obtaining the side insulating films 171 and 181 and is thus formed of, for example, SiO. Subsequently, using the gate portion 160 as a mask, impurity implantation by, for example, an ion implantation method or the like is performed on the entire area of the semiconductor substrate 100. Thus, LDD regions 112 and 122 are formed (see FIG. 3A). Since the SiO film 163 is provided on the uppermost surface of the gate portion 160, the characteristics of the gate electrodes 161 and 162 are not impaired by this impurity implantation.

  (6) The fifth and sixth insulating films are deposited on the surface of the fourth insulating film 207 by using, for example, the CVD method. The fifth insulating film is a film for obtaining the charge holding films 172 and 182, and is therefore formed of an insulating material (for example, SiN) having an energy gap smaller than that of the fourth insulating film 207. The sixth insulating film is a film for forming the insulating films 173 and 183, and for example, SiO is used. Thereafter, the sidewalls 170 and 180 are completed by processing the fourth to sixth insulating films using, for example, a photolithography method and an etching method (see FIG. 3B).

  (7) The insulating film 190 is formed on the entire surface of the semiconductor substrate 100 by depositing SiO using, for example, the CVD method. Subsequently, using the gate portion 160 and the sidewalls 170 and 180 as masks, impurity implantation is performed on the entire area of the semiconductor substrate 100 by, for example, ion implantation. Thus, high-concentration impurity regions 111 and 121 are formed (see FIG. 3C). Since the SiO film 163 is provided on the uppermost surface of the gate portion 160, the characteristics of the gate electrodes 161 and 162 are not impaired by this impurity implantation.

  Thereafter, through a process of forming contact holes for wiring the high concentration impurity regions 111 and 121 in the insulating film 190, the memory element as shown in FIG. 1 is completed.

  As described above, according to the 2-bit memory type semiconductor memory device according to this embodiment, the charge holding films 132, 142, 172, and 182 are provided on the lower portion of the gate portion 160 and the side walls 170 and 180. The amount of charge that can be stored in the charge holding film can be increased without increasing the element area, and thereby the current value that can be stored in these charge holding films can be sufficiently reduced.

  In addition, according to the manufacturing method of the 2-bit memory type semiconductor memory device according to this embodiment, the current value when the memory element area is small and the charge is stored in the charge holding portion is sufficiently small. A semiconductor memory device can be manufactured inexpensively with a small number of steps.

Second Embodiment Next, another embodiment of the manufacturing method according to the present invention will be described with reference to FIG.

  Since the memory element structure and operation of the 2-bit memory type semiconductor memory device according to this embodiment are the same as those of the device according to the first embodiment (see FIG. 1), description thereof will be omitted.

  Hereinafter, the manufacturing method according to this embodiment will be described with reference to process cross-sectional views of FIGS.

  (1) First, a first insulating film 401, a second insulating film 402, and a first coating film 403 are sequentially deposited on the surface of the semiconductor substrate 100 by using, for example, a CVD (Chemical Vapor Deposition) method. The first insulating film 401 is a film for obtaining the lower insulating films 131 and 141 (see FIG. 1), and is thus formed of, for example, SiO. The second insulating film 402 is a film for obtaining the charge holding films 132 and 142, and is therefore formed of an insulating material (for example, SiN) having an energy gap smaller than that of the first insulating film. The first coating film 403 is a film used for etch back in the later-described step (3), and is formed of, for example, SiO. Subsequently, a pattern of a photoresist 404 is formed over the entire area of the semiconductor substrate 100 and etching is performed. Thus, the first opening 405 (width W1) penetrating the first coating film 403 is provided, and the surface 406 of the second insulating film 402 is exposed (see FIG. 4A).

  (2) The photoresist 404 is removed, and a second coating film 407 is deposited over the entire area of the semiconductor substrate 100 using, for example, a CVD method (see FIG. 4B). The second coating film 407 is a film used for etch back in the later-described step (3), and is formed of, for example, SiO.

  (3) Etch back is performed until the second opening 408 (width W2) is formed at the center of the first opening 405 and the surface of the semiconductor substrate 100 is exposed (see FIG. 4C).

  (4) Thereafter, the first and second coating films 403 and 407 remaining on the surface of the semiconductor substrate 100 are removed, for example, by wet etching or the like (see FIG. 4D).

  Subsequent steps are the same as steps (3) to (7) in the first embodiment described above, and a description thereof will be omitted.

  As described above, according to the manufacturing method according to this embodiment, the second opening 408 having a narrower width than the first opening 405 formed by the photolithography method can be formed. That is, according to this embodiment, the second opening 408 having a width smaller than the minimum opening width that can be formed by photolithography can be obtained. Here, the width W2 of the second opening 408 defines the size of the region where the gate insulating film 150 is formed. Therefore, in this embodiment, the size of the region where the gate insulating film 150 is formed can be made smaller than the minimum opening width by the photolithography method, and thereby the size of the gate portion 160 can be made very small. .

1 is a cross-sectional view schematically showing a memory element structure of a 2-bit memory type semiconductor memory device according to a first embodiment. FIG. 4 is a cross-sectional process diagram illustrating a method for manufacturing a 2-bit memory type semiconductor memory device according to the first embodiment. FIG. 4 is a cross-sectional process diagram illustrating a method for manufacturing a 2-bit memory type semiconductor memory device according to the first embodiment. It is sectional process drawing which shows the manufacturing method of the 2-bit memory | storage type semiconductor memory device which concerns on 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 110,120 Impurity area | region 111,121 High concentration impurity area | region 112,122 LDD area | region 130,140 Charge holding part 131,141 Lower insulating film 132,142,172,182 Charge holding film 133,143 Upper insulating film 150 Gate Insulating film 160 Gate portion 161 Polycrystalline Si film 162 WSi film 163 SiO film 170,180 Side wall 171,181 Side insulating film 173,183,190 SiO film

Claims (12)

First and second impurity regions formed on a surface region of a semiconductor substrate with a channel formation region interposed therebetween;
A first lower insulating film formed on a boundary region between the first impurity region and the channel forming region; and an energy gap smaller than that of the first lower insulating film formed on the first lower insulating film. A first charge holding portion having one charge holding film and a first upper insulating film formed so as to cover an upper surface and an inner side surface of the first charge holding film and having an energy gap larger than that of the first charge holding film; ,
A second lower insulating film formed on a boundary region between the second impurity region and the channel forming region; and an energy gap smaller than that of the second lower insulating film formed on the second lower insulating film. A second charge holding portion having a two charge holding film and a second upper insulating film formed so as to cover the upper surface and the inner side surface of the second charge holding film and having an energy gap larger than that of the second charge holding film; ,
A gate insulating film formed on a region sandwiched between the first and second charge holding portions;
A gate portion formed in a region straddling the gate insulating film from the first and second charge holding portions;
A first side insulating film covering a region extending from a side surface on the first impurity region side of the first charge holding portion and the gate portion to a surface of the first impurity region; and a surface of the first side insulating film. A first sidewall having a third charge retention film formed to cover and having a smaller energy gap than the first side insulating film;
A second side insulating film that covers a region extending from a side surface on the second impurity region side of the second charge holding portion and the gate portion to a surface of the second impurity region; and a surface of the second side insulating film. A second sidewall having a fourth charge retention film formed to cover and having a smaller energy gap than the second side insulating film;
A two-bit storage type semiconductor memory device comprising:   Low concentration impurity regions are formed on the channel formation region side of the first and second impurity regions, respectively, and the first and second sidewalls are formed on these low concentration impurity regions. The 2-bit storage type semiconductor memory device according to claim 1.   The first and second lower insulating films, the first and second upper insulating films, and the first and second side insulating films are SiO films, and the first to fourth charge retention films are SiN films. The 2-bit storage type semiconductor memory device according to claim 1, wherein   The said gate part contains the gate electrode which has the polycrystal Si film | membrane and WSi film | membrane laminated | stacked one by one, and also contains the SiO film | membrane formed on this WSi film | membrane. 2. A 2-bit memory type semiconductor memory device according to item 1. Forming a first insulating film and a second insulating film having an energy gap smaller than that of the first insulating film on the semiconductor substrate;
A second step of exposing a surface of the semiconductor substrate by providing an opening penetrating the first and second insulating films;
Forming a third insulating film having an energy gap larger than that of the second insulating film over the entire area of the semiconductor substrate;
After forming the gate portion forming layer over the entire area of the semiconductor substrate, by removing the gate portion forming layer and the first to third insulating films in the region other than the region where the opening is formed and the peripheral region thereof, A fourth step of forming the gate insulating film, the first and second charge holding portions, and the gate portion;
A fifth step of forming first and second impurity regions by forming a fourth insulating film over the entire area of the semiconductor substrate and then introducing impurities into the entire area of the semiconductor substrate using the gate portion as a mask;
A fifth insulating film having an energy gap smaller than that of the fourth insulating film is formed on the surface of the fourth insulating film, and a sixth insulating film having an energy gap larger than that of the fifth insulating film is formed on the surface of the fifth insulating film. A sixth step of forming the first and second sidewalls by processing the fourth to sixth insulating films; and
A method of manufacturing a two-bit storage type semiconductor memory device.   The fifth step is a step of forming low-concentration impurity regions in the first and second impurity regions, and the gate portion and the first and second sidewalls are used as a mask after the sixth step. 6. The method of manufacturing a 2-bit storage type semiconductor memory device according to claim 5, further comprising a seventh step of forming a high-concentration impurity region in the first and second impurity regions.   7. The 2-bit according to claim 5, wherein the first, third, fourth, and sixth insulating films are SiO films, and the second and fifth insulating films are SiN films. A method for manufacturing a memory type semiconductor memory device.   The gate portion forming layer includes a gate electrode having a polycrystalline Si film and a WSi film sequentially stacked, and further includes a SiO film formed on the WSi film. A method of manufacturing a 2-bit storage type semiconductor memory device according to any one of the above. A first insulating film, a second insulating film having an energy gap smaller than that of the first insulating film, and a first coating film are sequentially formed on the semiconductor substrate, and further penetrate the first coating film. A first step of exposing a surface of the second insulating film by providing a first opening;
A second step of forming a second coating film over the entire area of the semiconductor substrate;
A third step of performing etch back until a second opening is formed in a central portion of the first opening and the surface of the semiconductor substrate is exposed;
A fourth step of removing the first and second coating films remaining on the surface of the semiconductor substrate;
A fifth step of forming a third insulating film having a larger energy gap than the second insulating film over the entire area of the semiconductor substrate;
After forming a gate portion forming layer over the entire area of the semiconductor substrate, removing the gate portion forming layer and the first to third insulating films in a region other than the region where the second opening is formed and its peripheral region A sixth step of forming the gate insulating film, the first and second charge holding portions, and the gate portion,
A seventh step of forming first and second impurity regions by forming a fourth insulating film over the entire area of the semiconductor substrate and then introducing impurities into the entire area of the semiconductor substrate using the gate portion as a mask;
A fifth insulating film having an energy gap smaller than that of the fourth insulating film is formed on the surface of the fourth insulating film, and a sixth insulating film having an energy gap larger than that of the fifth insulating film is formed on the surface of the fifth insulating film. An eighth step of forming the first and second sidewalls by processing the fourth to sixth insulating films; and
A method of manufacturing a two-bit storage type semiconductor memory device.   The seventh step is a step of forming low-concentration impurity regions in the first and second impurity regions, and after the eighth step, the gate portion and the first and second sidewalls are used as masks. 10. The method for manufacturing a 2-bit storage type semiconductor memory device according to claim 9, further comprising a ninth step of forming a high concentration impurity region in the first and second impurity regions.   The first, third, fourth, and sixth insulating films and the first and second coating films are SiO films, and the second and fifth insulating films are SiN films. 11. A method of manufacturing a 2-bit storage type semiconductor memory device according to claim 9 or 10.   The gate portion forming layer includes a gate electrode having a polycrystalline Si film and a WSi film sequentially stacked, and further includes a SiO film formed on the WSi film. A method of manufacturing a 2-bit storage type semiconductor memory device according to any one of the above.

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