JP2006351146A - Non-volatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of eliminating trouble which may occur in memory internal processing as well as command processing in the case of a contention between memory internal processing and command input from the outside, in a non-volatile memory. <P>SOLUTION: A latch 403 for holding a command (DIBAC) inputted from the outside, a decode logic combination circuit 404 for decoding an output of the latch 403, a latch 401 for holding a ready/busy signal from a RB generation part 204, and an AND gate 405 for receiving an output of the decode logic combination circuit 404 and an output of the latch 401 are provided in a command decoder. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory, and more particularly to a technique effective when applied to the configuration of a command decoder portion of a nonvolatile memory.

  In general, the nonvolatile memory has a command decoder for receiving and decoding a command input from the outside.

  As a technique examined by the present inventor, for example, the technique of Patent Document 1 or Patent Document 2 can be considered in the configuration of the command decoder portion of the nonvolatile memory.

  Patent Document 1 describes a flash memory that controls a status register (master-slave configuration) by a signal from a write status machine decoded by a decoder, sets a ready / busy signal, and outputs the signal to the outside.

Patent Document 2 describes an EEPROM in which the read / busy signal is switched after the data at the read head column address of the data for one page is transferred to the latch circuit in order to shorten the access time.
JP 2004-348809 A JP 2002-93179 A

  By the way, as a result of the study of the technique of the command decoder portion of the nonvolatile memory as described above, the following has been clarified.

  For example, since the command decoder of the conventional nonvolatile memory has mixed logics that operate asynchronously, when the internal processing of the memory and the command input from the outside compete, in either the internal processing of the memory or the command processing, A malfunction that becomes a metastable may occur.

  Accordingly, an object of the present invention is to provide a technology capable of eliminating problems that may occur in either the memory internal process or the command process when the internal process of the memory and the command input from the outside compete in the nonvolatile memory. It is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the non-volatile memory according to the present invention has a memory internal state in order to prevent a problem that may occur in either the memory internal process or the command process when the memory internal process and the command input from the outside compete. The command input state is determined at the final stage of the decoding circuit.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the nonvolatile memory, when a command input from the inside and outside of the memory competes, a problem that may occur in either the memory internal process or the command process is solved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram showing the overall configuration of a nonvolatile memory according to an embodiment of the present invention. First, an example of the entire configuration of the nonvolatile memory according to the present embodiment will be described with reference to FIG.

  The nonvolatile memory according to the present embodiment is, for example, an 8 Gbit flash memory. This flash memory includes a memory mat 1, a main decoder / gate decoder 2, a sub decoder 3, a sense latch circuit 4, a data latch circuit 5, a main amplifier 6, an input data arithmetic circuit 7, an input / output buffer 8, and a control signal input buffer 9. , Data input / output control circuit 10, ready / busy circuit 11, system clock circuit 12, status register test system circuit 13, command decoder (COMDEC) 14, ROM control system circuit 15, ROM 16, ROM decoder 17, CPU 18, power supply control circuit 19, power supply switching circuit 20, charge pump step-down circuit 21, reference power supply 22, address counter 23, relief system circuit 24, address generator 25, redundant fuse / trimming fuse 26, etc. By technology It is formed on the pieces of the semiconductor chips.

  In this flash memory, control signals such as a chip enable signal / CE, a reset signal / RES, a command enable signal CLE, and an address enable signal ALE are input to a control signal input buffer 9 via an external terminal, and a data input / output control circuit A write clock signal / WE and a read clock signal / RE are input to 10, and a command and timing signal for controlling an internal circuit are generated based on these signals. A ready / busy signal R / B is output from the ready / busy circuit 11 via an external terminal.

  In this flash memory, the memory mat 1 is composed of a plurality of memory cells MC arranged at the intersections of the word lines WL and the bit lines BL, and is divided into four in the horizontal and vertical directions. Arbitrary memory cells MC in the memory mat 1 are selected by the main decoder / gate decoder 2 and the sub-decoder 3, and a sense latch circuit 4, a data latch circuit 5, a main amplifier are selected for the selected memory cells MC. 6. Data is written / read through the input data arithmetic circuit 7 and the input / output buffer 8.

  In the flash memory configured as described above, voltages applied to the memory cells for writing and erasing the memory cells MC are the power supply control circuit 19, the power supply switching circuit 20, the charge pump step-down circuit 21, the reference power supply 22, and the like. Supplied from

  FIG. 2 is a block diagram showing a configuration of the command decoder (COMDEC) 14 in the nonvolatile memory according to the embodiment of the present invention. An example of the configuration of the COMDEC 14 according to this embodiment will be described with reference to FIG. The command decoder 14 according to the present embodiment includes, for example, an EXIF unit 201, a state control unit 202, a RESET (reset) generation unit 203, and the like. The state control unit 202 includes an RB (ready / busy) generation unit 204, a CPU command control unit 205, an address command control unit 206, an SR (status register) read control unit 207, and the like. The COMDEC 14 receives the COMDEC operation clocks CLKWE4 and BXLWE. The EXIF unit 201 receives signals BXHALE, BXHCLE, DIBAC, BXLWP, and BXHPRE and outputs signals CXHCLE, CXHALE, and CIBAC. In addition, a signal is input from the EXIF unit 201 to the CPU command control unit 205, the address command control unit 206, and the SR read control unit 207 in the state control unit 202, and a signal is input from the RB generation unit 204 to the EXIF unit 201. Yes. Further, the signal C4BUSY and the like are output from the RB generation unit 204, and the signal m2hckctl is input to the RB generation unit 204. The CPU command control unit 205 outputs a signal c_hcpuen and the like, and the CPU command control unit 205 inputs a signal m2hcpuenclr and the like. The address command control unit 206 outputs a signal CXHYLD1 and the like. The SR read control unit 207 outputs a signal C4BSTRD and the like. Further, signals BXHINTBL and BXLRES3 are input to the RESET generation unit 203, and a COMDEC internal reset (resetp) signal and a signal CXHRES are output from the RESET generation unit 203.

  The main function of the COMDEC 14 is to receive and decode a command input from the outside. Further, based on the decoded result, an internal state is generated and a control signal is output to the CPU 18 and other control blocks.

  Specifically, COMDEC 14 has the following functions. That is, as a decoding function, (1) an externally input command is decoded and an operation is instructed to the CPU 18, (2) an externally input command is decoded and an address latch is instructed, and (3) a status register (SR ) Output status read enable signal (status read mode), (4) output ID read enable signal to status register (ID read mode), (5) reset by asserting command FFh Processing (6) Decoding of a super AND command. Also, as a state generation function, (7) system clock (SCLK) operation start trigger generation, (8) normal mode and test mode transition management, (9) R / B (Ready / Busy) signal output, (10) Asynchronous reset signal generation, (11) Cache mode signal assertion to CPU 18. As control functions, (12) a mode gister setting instruction in the test mode, (13) an enable signal output to the CPU 18, (14) a write enable signal to the SRAM, (15) a clear signal to the SRAM, (16) This is an assertion of a read enable signal for the SRAM. Other functions include (17) enable power on read (PowerOnRead), (18) latch (timing synchronization) of external terminal input signals such as ALE and CLE, and (19) command buffering in the cache mode. , (20) dummy busy counter, (21) mask logic of reset (terminals RESB and INTB), and (22) data buffering in break mode.

  As shown in FIG. 2, the COMDEC 14 has three functional blocks: an EXIF unit 201, a state control unit 202, and a RESET generation unit 203.

  The EXIF unit 201 is an external input interface and synchronizes the signals BXHALE, BXHCLE, and DIBAC with the signal BXLWE. Further, a signal indicating a command reception state, an address reception state, a test mode transition state, or the like is generated from the states of the signals BXHALE and BXHCLE. It also holds commands.

  The state control unit 202 decodes the command and generates a control signal to the CPU 18 and the peripheral logic unit. It also manages the internal state (flag) of COMDEC 14.

  The RESET generation unit 203 generates a global reset to the CPU 18 and the peripheral logic unit, and generates a reset signal inside the COMDEC 14.

  FIG. 3 shows the configuration of the command decoding unit in the state control unit 202. In FIG. 3, A, B, C, D, E, F, G, H, J, and K in the corresponding command column indicate the types of commands. A is a CPU operation command, B is an address control command, C is a status read command, D is an ID read command, E is a dummy command, F is an E0h command, G is a reset command, H is a busy check command, and J is a test A mode dedicated command, K is a test mode transition command.

  The features of this command decode unit are as follows. (1) Since the number of times and the configuration are changed depending on the type of command, decoding suitable for the characteristics of the command becomes possible. (2) Since the decoded result of the fetched command is based on the flip-flop (F / F) output, the risk of occurrence of a hazard in the output signal is reduced. (3) Since each decoding unit is blocked, RTL visibility is improved.

  FIG. 4 is a logic circuit diagram showing a detailed configuration of the command decoder (COMDEC) 14 in the nonvolatile memory according to the present embodiment. In FIG. 4, only the EXIF unit 201, the RB generation unit 204, and the CPU command control unit 205 are illustrated, and the address command control unit 206, the SR read control unit 207, and the RESET generation unit 203 are omitted.

  As shown in FIG. 4, the EXIF unit 201 includes BXLWE synchronization latches 401 and 403 and the like. The CPU command control unit 205 includes a CLKWE4 synchronous F / F 402, a decode logic combination circuit 404, an AND gate 405, and the like. The RB generation unit 204 includes a combinational circuit 406 and the like. In the EXIF unit 201, the signal DIBAC is input to the BXLWE synchronization latch 403, and the signal R / B (ready / busy) indicating the internal state from the RB generation unit 204 is input to the BXLWE synchronization latch 401. In the CPU command control unit 205, the signal DIBAC from the EXIF unit 201 via the BXLWE synchronization latch 403 is input to the decode logic combination circuit 404 and the output thereof is input to the AND gate 405. The signal R / B via the BXLWE synchronization latch 401 is input to the AND gate 405. That is, the external command input signal DIBAC is fetched, the command input signal is decoded by the decode logic combination circuit 404, and the resulting command state and signal R / B indicating the internal state of the memory are input to the AND gate 405 for determination. It is carried out. In this way, by determining the internal state of the memory (signal R / B, etc.) and the command state (signal DIBAC, etc.) at the final stage of the decode logic combination circuit 404, the metastable caused by the contention of the asynchronous signal is generated. It can be avoided. In the present embodiment, the CPU command control unit 205 and the RB generation unit 204 have been described as examples. However, the present invention is not limited to this, and can be applied to other circuits in which external signals and internal signals compete asynchronously.

  Next, the metastable countermeasure described above will be described in detail with reference to FIG. FIG. 5 is a schematic diagram of the COMDEC flag logic in the command decoder. FIG. 5A shows a conventional circuit, and FIG. 5B shows a circuit of this embodiment. In order to make this embodiment easier to understand, it will be described in comparison with a conventional circuit.

  As shown in FIG. 5A, in the conventional circuit, a clock signal having a different WE signal and SCLK signal is input to the decode logic combination circuit 404. Therefore, in the latch 403, there is a possibility that all the flags are in a metastable state. That is, in the conventional COMDEC flag logic circuit, logics operating with asynchronous clocks (system clock (SCLK) and WE clock) are mixed.

  On the other hand, as shown in FIG. 5B, in the circuit according to the present embodiment, only the signal of the same clock system of the WE system signal is input to the decode logic combination circuit 404. By doing so, the metastable state does not occur in the F / F 402. In the F / F 402a, the metastable is suppressed by a path delay to the AND gate 405 in the input stage, and even if a metastable occurs, only this one bit is required. That is, the COMDEC 14 of this embodiment limits the logic that operates asynchronously to a specific flag to reduce the occurrence of metastable. In the COMDEC 14, when the external input satisfies the external specification shown in the data sheet, no metastable is generated.

  The metastable countermeasure described above is effective when a CPU operation command is input under the following conditions. In this case, the SCLK signal in the figure corresponds to the signal R / B of the external terminal.

  (1) The signal R / B indicates busy.

  (2) Enter a command that cannot be entered while busy.

  (3) The command input and the transition from busy to ready overlap.

  The flags for which the above countermeasure is implemented are the following five flags.

(1) CPU enable flag (cpuen0, cpuen1)
(2) Cache program flag (cachepg)
(3) Cache read flag (chacherd)
(4) SRAM busy flag (rd_prg_com0, rd_prg_com1)
(5) C4BCODE (dfacom_3a, dfacom_3c)
Also, input of address control commands is prohibited during busy periods other than dummy busy and erase operations. Internally, the busy period other than dummy busy and erase operation is equivalent to SRAM busy, so the metastable countermeasure shown in FIG. 5B of the address control command uses the SRAM busy signal as the SCLK system signal. However, the following flags are used.

(6) Address command set flag (adcomset)
Note that the SRAM busy flag is set to 1 by the WE clock, but the clear is a specification that is asynchronously reset by a signal (m2hcpuend) asserted from the CPU, so the timing on the 0 clear side becomes SCLK synchronous.

  Next, the COMDEC asynchronous reset countermeasure according to the present embodiment will be described. FIG. 6 is a schematic diagram showing the COMDEC asynchronous reset logic according to the present embodiment. As shown in FIG. 6, in the COMDEC according to the present embodiment, the asynchronous reset has only two systems of external terminal reset (BXLRES, BXHINTBL) and an assert signal from the CPU. Although the use of asynchronous reset is desired to be avoided as much as possible, the WE system clock is clocked only when the user needs it, such as command input. Therefore, there is a flag that cannot be cleared to 0 by COMDEC itself only by the synchronous reset by the WE system signal. Therefore, asynchronous reset is used only for limited flags.

  FIG. 7 shows a flag for asynchronous reset by a reset signal asserted by the CPU. There are four types of reset signals asserted from the CPU (m2hdbsyfull, m2hcpuenclr, m2hdinok).

  As shown in FIG. 6, in COMDEC according to the present embodiment, the asynchronous reset is performed only by the CPU assert signal except for the external terminal reset. However, since the CPU-asserted reset signal and the WE system clock are asynchronous, there may be a case where the set timing and reset timing of data input to one F / F compete. At this time, a metastable is generated in the output signal of the F / F 601. In order to avoid such inconveniences, the flags having the possibility of conflicting asynchronous signals as described above are provided with two flags having the same function and mutually exclusive. FIG. 8 shows a schematic diagram of the asynchronous signal contention countermeasure logic.

  In FIG. 8, a case where data in and the reset signal compete when enable = 1 and the selection signal = 0 is considered. Under the condition of enable = 1 and selection signal = 0, if data in = 1, 1 is set in the flag 0801. On the other hand, if the selection signal = 0 (enable is Don't care) and the reset signal = 1, the flag 1802 is reset to zero.

  When enable = 1 and selection signal = 1, if data-in conflicts with the reset signal, data-in = 1 if the enable = 1 and selection signal = 1. 1 is set in the flag 1802. On the other hand, if the selection signal = 0 (enable is Don't care) and the reset signal = 1, the flag 0801 is reset to zero.

  That is, when the asynchronous data-in conflicts with the reset signal, the flag activated by the value of the selection signal is designed exclusively, and it is unlikely that metastable will occur due to the conflict. Note that the selection signal is also an SCLK-synchronized signal, but this signal is designed with specifications that do not cause competition with the WE. The output of the data-in and reset signals on the non-selected side is 0.

  FIG. 9 shows the flags (two types) of the logical configuration shown in FIG. In FIG. 9, the clear condition incorporates a dummy busy count full (m2hdbsyfull) condition in addition to the conditions shown in the figure.

  FIG. 10 shows a set / reset timing chart of a cpuable (cpuen0, cpuen1) flag as an example of the flag. Upon input of the signal DIBAC command, the selection signal m2hcomsel = 0 at 1001, so the internal flag cpuen0 is set to 1. Thereafter, since the signal Ready / Busy = 0 is busy, the internal state does not change when a command is input. In 1002, the CPU inverts the selection signal m2hcomsel by ROM processing. In 1003, the flag is not set by command input because it is busy. In other words, there is no worry about metastable. At 1004, the reset signal m2hcpuenclr is asserted in the selection signal m2hcomsel = 1. Then, the internal flag cpuen0 is cleared to 0. In 1005, the internal flag cpuen1 is set to 1 by a command input in the selection signal m2hcomsel = 1. At 1006, the reset signal m2hcpuenclr is asserted when the selection signal m2hcomsel = 0. Then, the internal flag cpuen1 is cleared to 0.

  FIG. 11 shows, as an example of the flag, a timing chart in the case where the set / reset of the cpuable (cpuen0, cpuen1) flag in the cache mode competes. In FIG. 11, a period 1106 indicates that the CPU is in the ROM processing by the command COM1, and a period 1107 indicates that the CPU is in the ROM processing by the command COM2. By input of the command COM1 of the signal DIBAC, since the selection signal m2hcomsel = 0 at 1101, the internal flag cpuen0 is set to 1. Thereafter, at 1102, the busy state is sampled at the rising edge of signal BXLWE. In 1103, the reset signal m2hcpuenclr is asserted in the selection signal m2hcomsel = 1. Then, the internal flag cpuen0 is cleared to 0. When a command is received as a ready in 1104, there is a conflict between set and clear in terms of timing, but since the selection signal m2hcomsel = 1, the set is on the cpuen1 side. The clearing of the reset signal m2hcpuenclr is effective because it is on the cpuen0 side. That is, there is no conflict with the same flag. In 1108, at the sampling timing, the flag is not set when busy, and the flag is set when ready. In 1105, when the reset signal m2hcpuenclr is asserted in the selection signal m2hcomsel = 0, cpuen1 is cleared to 0.

  Next, other functions of the asynchronous signal contention countermeasure logic will be described.

  It is a specification that the outside always becomes busy when the COMDEC receives a CPU operation command from the outside. At this time, the ROM processing of the CPU starts by internally oscillating SCLK. On the other hand, the busy state is canceled by the ROM processing of the CPU. Here, it is assumed that SCLK always operates, and a case where the CPU does not operate for some reason (for example, ROM read cannot be normally performed) is considered. In this case, since the CPU cannot operate abnormally, that is, ROM processing cannot be performed, the CPU cannot recover from the busy state. In order to avoid these problems (Busy Stack due to inability to start), a dummy busy counter full reset (m2hdbsyfull) condition was added to the contention countermeasure logic. In addition, when the CPU runs away in the middle of the ROM processing (it is not impossible to start), the specification is such that it can be restored by inputting the FFh command.

  FIG. 12 shows a schematic diagram of the asynchronous reset signal generation logic of the cpuable (cpuen0, cpuen1) flag. FIG. 13 is a timing chart for resetting the cpuable flag when the dummy busy count is full (m2hdbsyfull). FIG. 13A shows the normal operation of the CPU. FIG. 13B shows the CPU abnormal operation time.

  In FIG. 13A, at 1301, since the CPU is operating normally, the selection signal m2hcomsel is inverted. In 1302, m2hdbsyfull is asserted with the selection signal m2hcomsel = 1, and the cpuen1 side is cleared. At this time, since cpuen1 is not set to 1, there is no influence.

  In FIG. 13B, the selection signal m2hcomsel is not inverted at 1303 because the CPU is in an abnormal operation. In 1304, when the selection signal m2hcomsel = 0, m2hdbsyfull is asserted, and the cpuen0 side is cleared. At this time, cpuen0 is cleared, so that it returns to the ready state.

  The logic shown in FIG. 12 can return from the busy state even when the CPU operates abnormally. In the cache mode, when the command is received for the second time or later, the clear logic of the cpuable flag by the m2hdbsyfull is a masking specification. This is determined from the judgment that the second time is executed, that is, the CPU should be operating.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for nonvolatile memories such as an EEPROM and a flash memory.

1 is a block diagram showing an overall configuration of a nonvolatile memory according to an embodiment of the present invention. It is a block diagram which shows the structure of the command decoder (COMDEC) which concerns on one embodiment of this invention. It is explanatory drawing which shows the structure of the command decoding part in the state control part in COMDEC which concerns on one embodiment of this invention. It is a logic circuit diagram which shows the detailed structure of COMDEC which concerns on one embodiment of this invention. (A) is the schematic which shows the conventional COMDEC flag logic, (b) is the schematic which shows the flag logic of COMDEC which concerns on one embodiment of this invention. FIG. 3 is a schematic diagram illustrating asynchronous reset logic in COMDEC according to an embodiment of the present invention. It is explanatory drawing which shows an asynchronous reset flag in COMDEC which concerns on one embodiment of this invention. In COMDEC which concerns on one embodiment of this invention, it is the schematic which shows an asynchronous signal competition countermeasure logic. It is explanatory drawing which shows an asynchronous signal competition countermeasure flag in COMDEC which concerns on one embodiment of this invention. 6 is a timing chart showing the timing of setting / resetting a cpuable flag in COMDEC according to an embodiment of the present invention. 6 is a timing chart showing the timing of setting / resetting a cpuable flag in a cache mode in COMDEC according to an embodiment of the present invention. FIG. 5 is a schematic diagram showing an asynchronous reset signal generation logic of a cpuable flag in COMDEC according to an embodiment of the present invention. (A), (b) is a timing chart which shows the reset timing of cpuable flag by dummy busy count full (m2hdbsyfull) in COMDEC which concerns on one embodiment of this invention.

Explanation of symbols

1 Memory Mat 2 Main Decoder / Gate Decoder 3 Sub Decoder 4 Sense Latch Circuit 5 Data Latch Circuit 6 Main Amplifier 7 Input Data Operation Circuit 8 Input / Output Buffer 9 Control Signal Input Buffer 10 Data Input / Output Control Circuit 11 Ready / Busy Circuit 12 System Clock circuit 13 Status register test system circuit 14 Command decoder (COMDEC)
15 ROM control system circuit 16 ROM
17 ROM decoder 18 CPU
19 power supply control circuit 20 power supply switching circuit 21 charge pump step-down circuit 22 reference power supply 23 address counter 24 relief system circuit 25 address generator 26 redundant fuse / trimming fuse 201 EXIF unit 202 state control unit 203 RESET generation unit 204 RB generation unit 205 CPU Command control unit 206 Address command control unit 207 SR read control unit 401, 403 Latch 402, 402a, 601, 801, 802 F / F
404 Decode logic combination circuit 405 AND gate 406 Combination circuit

Claims (5)

A command decoder for controlling a CPU by decoding a command input from the outside by a decoding circuit;
The non-volatile memory characterized in that the command decoder has means for determining the internal state and command state of the memory at the final stage of the decoding circuit. A command decoder for controlling the CPU by decoding a command input from the outside;
The command decoder
A first holding circuit for holding a command input from the outside;
A decoding circuit for decoding the output of the first holding circuit;
A second holding circuit for holding a signal indicating an internal state of the memory;
A non-volatile memory comprising: an AND circuit that inputs an output of the decoding circuit and an output of the second holding circuit. The non-volatile memory according to claim 2.
The nonvolatile memory is characterized in that the signal indicating the internal state of the memory is a ready / busy signal. The non-volatile memory according to claim 2.
The nonvolatile memory, wherein the command and the signal indicating the internal state of the memory are asynchronous. The non-volatile memory according to claim 4.
The nonvolatile memory according to claim 1, wherein the command is a write enable signal, and the signal indicating the internal state of the memory is a system clock signal.

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