JP2006344279A - Semiconductor device and testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device facilitating identification of cause of defects, such as whether deterioration of characteristics, defects, etc., at evaluation and analysis are caused by a frequency synchronizing circuit. <P>SOLUTION: The device is equipped with a DLL circuit 10 for inputting external clock signals from external clock terminals 13, 14 and producing signals synchronized with these external clock signals; and a selector 11 for inputting a clock signal inputted from an external terminal 15 and an output signal from the DLL circuit 10, and for outputting the clock signal inputted from the external terminal 15 at the test, based on a test mode signal and outputting the output signal from the DLL circuit 10 at normal operation times. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a configuration and method suitable for application to a clock synchronous semiconductor memory device having a frequency synchronization circuit.

  In a memory device such as SDRAM (synchronous DRAM), DDR (Double Data Rate) I-SDRAM, DDRII that transfers data from SDR (Single Data Rate) -SDRAM in synchronization with both rising and falling edges of a clock signal. -With SDRAM, the operating frequency of devices has increased significantly. In the DDRII-SDRAM, the highest grade operating frequency is, for example, 800 MHz. When performing evaluation and analysis in such a frequency range, an operation margin (timing margin) of a DLL (Delay Lock Loop) that performs clock synchronization is strict. Even in circuits other than the DLL, the operation margin is becoming strict. For this reason, when there is a problem in characteristics, it has become particularly difficult to isolate the cause.

  In addition, in a device having a frequency synchronization circuit, such as a DDRII-SDRAM, the frequency synchronization circuit does not operate normally in a low frequency operation. For this reason, logic that can operate at low speed is required separately.

  However, since the low-speed operation is completely different from the normal operation in operating conditions and the like, it may be difficult to strictly distinguish the non-defective product from the defective device in the test by the low-speed operation.

Japanese Patent Laid-Open No. 9-251057

  In the evaluation and analysis of high frequency of the SDRAM device, if there is a problem in the characteristics or if a defect occurs, whether there is a problem in the output clock signal of the frequency synchronization circuit such as DLL, It is particularly difficult to isolate whether a problem is occurring due to lack of margin.

  Also, the frequency synchronization circuit does not operate normally at low frequencies due to its nature. For example, the oscillation frequency band of a PLL (Phase Locked Loop) VCO (Voltage Controlled Oscillator), the division ratio of a frequency divider arranged in the feedback path between the VCO and a PD (Phase detector) Constrained by For this reason, at low speed, a logic configuration that enables testing in a completely different operation mode is required, or at least some circuits are operated with a logic different from the normal logic. Is done.

  As a result, the device selection by the low-speed tester is different from the normal operation of the device (low-speed mode), distinguishing between non-defective products and defective products, and there is a problem with the correlation between the good and bad in the normal operation of the device .

  In Patent Document 1, as shown in FIG. 9, a DLL circuit 31 that receives an external clock signal CLK from an external clock terminal, an output 4A of the DLL circuit 31, and an external clock signal 4B from an external clock terminal are provided. A configuration including a selector (multiplexer) 33 as an input and switching between 4A and 4B based on the output of the switching circuit 32 is disclosed. Below, the subject is analyzed in detail about the composition indicated by patent documents 1. Note that the analysis of this problem is based solely on the results of research conducted by the present inventors.

  As shown in FIG. 9, the signal 4C switched by the selector 33 is a signal generated from the external clock signal CLK. Therefore, in the output circuit, when the signal 4C is used as the control clock for determining the output timing of the output data, the output data cannot be matched with the external clock signal CLK. As a result, for example, when Patent Document 1 is applied to an SDRAM such as a DDR whose output timing is the product specification as shown in FIG. 6, the output timing is different from that in FIG. That is, in the specifications of the DDRI and DDRII-SDRAM products, as shown in FIG. 6, the signal 1C (DLL output) is output earlier by “f” than the external clock signals CLK and CLKB. The configuration cannot achieve this specification.

  In addition, when the test mode described in Patent Document 1 is used, logic circuits other than the DLL must have a logic configuration different from the normal operation, and only the DLL is separated to perform evaluation / analysis or test. I can't. Hereinafter, description will be made based on a typical DDR-SDRAM.

  FIG. 7 shows a main part of a typical output circuit that realizes the output timing of FIG. As shown in FIG. 7, the output control logic circuit 21 that receives the DLL output 1C as a control clock and generates the output enable signal OE, and the data that receives the internal data and outputs the output data to the output buffer circuit 23 by the output enable signal OE A control circuit (FIFO) 22 and an output buffer circuit 23 that receives the DLL output 1C as a control clock and drives an output terminal at a level corresponding to output data are provided. Note that the present invention described later is suitable for use in generating the signal 1C supplied to the output circuit shown in FIG.

  1C, which is an output clock of a DLL (not shown), is input to the output control logic circuit 21 in addition to controlling the timing of the output buffer circuit 23 that outputs output data. The signal 1C is generated at an earlier timing (phase is advanced) than the external clock signal CLK.

  FIG. 8 is a diagram illustrating a timing relationship between the signals CLK, OE, and 1C in FIG. FIG. 8A shows a timing operation when the output enable signal OE is generated from the external clock signal CLK. In this case, the margin of the period “d” from when the output enable signal OE is activated (set to high level) to when output data is output (synchronized with the rising edge of 1C) is reduced. This period d becomes severer as the frequency becomes higher. Also, how fast the signal 1C is output depends on the delay time of the output circuit of the product, and thus varies depending on process variations, temperature, and voltage. In the case of FIG. 8A, there is no margin to guarantee the product quality.

  On the other hand, FIG. 8B shows a timing waveform when the output enable signal OE signal is generated from the output 1C of the DLL. In the case of FIG. 8B, as apparent from the comparison with FIG. 8A, the period d is significantly longer, and the timing margin is expanded. For this reason, the timing control as shown in FIG. 8B is used in an actual product.

  Therefore, problems in the case of using the test mode of Patent Document 1 in the DDR-SDRAM having the configuration as shown in FIG.

  FIG. 11 is a block diagram of a conventional output control logic circuit 21 (see FIG. 7) that generates the output enable signal OE. The output enable signal OE is generated by the output control logic circuit 21 that inputs a signal (READ) generated from a READ command input from the outside to the DDR-SDRAM. The READ command is designed to be input at the rising edge of the external clock signal CLK, and the READ signal input to the output control logic circuit 21 is created according to the timing of the external clock signal CLK. In FIG. 11, the output control logic circuit 21 generates an output enable signal OE based on the timing of the control clock Z.

  FIG. 12 is a diagram showing timing waveforms during normal operation when the control clock Z is the DLL output 1C in FIG. In FIG. 12, the output enable OE signal is generated by the clock signal 1C. The READ signal generated from the rising edge of the external clock signal CLK is latched by 1C (the rising edge of 1C comes earlier in time than the edge of the clock CLK), which is a signal earlier in timing than the external clock signal CLK. can do.

  The timing of the signal 1C varies depending on the voltage, process, and temperature. Therefore, for example, the timing is adjusted by a DLL (not shown) so as to match the delay time of the output circuit shown in FIG. In addition, even a high frequency operation is performed with a sufficient margin.

  In the case of Patent Document 1, that is, when the output 4C of the selector 33 shown in FIG. 9 is used as the signal 1C of FIG. 7, since 4C is a signal created from the external clock signal CLK, the external clock signal CLK An earlier signal cannot be generated, and the signal 1C has a certain delay time from the external clock signal CLK. Therefore, in this case, the operation of the output control logic circuit 21 of FIG. 11 does not have the timing waveform as shown in FIG. 12, but the timing waveform as shown in FIG.

  In FIG. 13, in order to normally output the output enable signal OE, the signal READ and the signal 4C are timings defined by the same external clock signal CLK. As shown in FIG. 13, since there is no margin, it is necessary to delay at least the READ signal and secure an operation margin as shown by the white arrow in FIG. That is, a circuit configuration for delaying the READ signal is required.

  The circuit that controls the actual output is finely adjusted so that it operates even at high frequencies such as CL (Cas-Latency) and 800 MHz. Therefore, when the control clock signal Z in FIG. 11 changes from the timing of the signal 1C to the timing of the signal 4C (see FIG. 9) according to the configuration of Patent Document 1, the scale of the logic change increases. End up. This means that not only logic design and scale problems but also the use of the test mode of Patent Document 1 requires that the logic other than the DLL circuit be changed, which makes it difficult to isolate defects. ing.

  The configuration disclosed in Patent Document 1 avoids the problem that the DLL circuit does not operate in the low-speed operation of the SDR-SDRAM. The DLL output 4C (see FIG. 9) in Patent Document 1 is shown in FIG. A product having a timing like the signal 1C is not assumed. It is assumed that the product operates at the timing of 4C in FIG. 10 (output data is output in synchronization with 4C delayed from the external clock signal CLK).

  Accordingly, an object of the present invention is to provide a semiconductor device and method that facilitates the identification of the cause of failure, such as whether or not characteristic degradation, failure, etc. are caused by a frequency synchronization circuit in evaluation / analysis.

  Another object of the present invention is to provide an apparatus and a method that can be correlated with good or bad in normal operation even when selected by a low-speed tester.

  The invention disclosed in the present application is roughly as follows.

  The present invention provides a circuit for switching a clock signal output from a frequency synchronization circuit to a signal input from an external terminal different from the clock terminal of the semiconductor device in a test mode in a semiconductor device having a frequency synchronization circuit. I have.

  A method according to the present invention is a test method for a semiconductor device including a synchronization circuit that inputs an external clock signal from an external clock terminal and generates a signal synchronized with the external clock signal, and is supplied from a tester during the test. A step of selectively outputting the clock signal input to the external terminal instead of the output of the synchronization circuit.

  According to the present invention, since the clock signal output from the synchronization circuit can be input from the tester side in the test mode, the waveform of the output clock signal of the synchronization circuit becomes a normal waveform even at a high frequency, and the influence of the synchronization circuit is excluded. Thus, it is possible to easily identify the cause of the failure, such as whether or not the deterioration of the characteristic, the failure, etc. are caused by the synchronous circuit.

  Further, according to the present invention, the clock signal input from the external pin is used in the test mode, so that an expected waveform is output to a circuit that requires the output signal of the synchronous circuit without restriction even at a low frequency. be able to.

  The present invention will be described in detail below with reference to the accompanying drawings. In the present embodiment, the clock signal generated from the frequency synchronization circuit is switched to a signal input from an external pin of the device in the test mode by the test mode signal. For example, in the case of DDRII, the external terminal is not the CLK or CLKB clock pin, but the ODT pin is used (ODT (On-Die Termination) is a function only for terminating the input / output pins. (In some cases, the ODT function may be turned off).

  Since the external pin can be input from the tester with the same accuracy as the clock signal from the external clock pin, the output clock signal waveform of the frequency synchronization circuit becomes a normal waveform even at a high frequency. Can be excluded.

  In addition, since the clock signal input from the external pin is used in the test mode, it is possible to output an expected waveform to a circuit that requires the output signal of the frequency synchronization circuit without restriction even at a low frequency. . Examples will be described below.

  FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. For example, it is a semiconductor device such as an SDRAM having a frequency synchronization circuit composed of a DLL circuit. The frequency synchronization circuit performs clock synchronization, and may be a phase synchronization circuit or a phase / frequency synchronization circuit. Referring to FIG. 1, the product package 1 includes a DLL circuit 10, a selector 11, and a test mode input first stage buffer circuit 12. The DLL circuit 10 generates a signal 1A synchronized with the external clock signals (CLK, CLKB) that are differentially input from the external clock pins 13 and 14.

  The signal 1B is a signal output from the test mode input first stage buffer circuit 12 that receives a signal input from the on-chip termination (ODT) pin 15 when the test mode is used, for example, in the case of a DDRII-SDRAM. The test mode input first stage buffer circuit 12 is activated by a test mode signal TestMode. The test mode signal TestMode is generated under the control of a command decoder (not shown).

  In FIG. 1, the ODT pin 15 is used in the DDRII-SDRAM. However, the present invention is not limited to such a configuration, and the external terminal is not limited to the external clock input pin. Any pin that does not need to be used in the evaluation / analysis and test is used.

  The selector 11 receives the test mode signal TestMode as a selection control signal, selects and outputs the signal 1A during normal operation, and selects and outputs 1B during the test mode.

  FIG. 2 is a timing waveform diagram showing the operation of one embodiment of the present invention. Reference numeral 1A denotes a signal synchronized with a clock generated from the differential external clock signals CLK and CLKB by the DLL circuit 10 of FIG. 1B is a signal created from the ODT pin in the test mode input first stage buffer circuit 12 of FIG. As the output 1C, the selector 11 selects the output signal 1A of the DLL circuit 10 during normal operation, and selects the signal 1B created from the ODT pin 15 in the test mode.

  In this embodiment, the signal 1B can be freely generated in frequency, timing, amplitude, and the like by an input from a tester (not shown) during the test. For this reason, as shown in FIG. 3, for example, if there is any problem in the output signal 1A of the DLL circuit 10 (for example, the waveform disappearance of 1A in FIG. 3 or the Duty abnormality), the signal 1B (supplied from the tester) in the test mode. In this case, a desired waveform can be output as the output signal 1C of the selector 11.

  The timing shift “f” in FIG. 2 will be described. The signal 1C is output earlier by “f” than the external clock signals CLK and CLKB. This is necessary for the product specifications (specs) of DDRI and DDRII-SDRAM.

  As shown in FIG. 4, according to this timing specification, the output data must be timed to the switching edge of the external clock signal CLK. For this reason, the signal 1C that determines the timing of the output data must be generated earlier (with the phase advanced) by the delay of the output circuit. This time (phase advance) is “f”.

  As described above, in Patent Document 1, the specification shown in FIG. 4 and the like cannot be realized. However, according to this embodiment, the product having the timing specification shown in FIG. 4 can be realized.

  For example, in the failure analysis, if there is an abnormality in the output data, it is caused by the DLL circuit 10, there is a problem in the data path, there is a problem in another part, or separation is difficult. According to the test mode of the embodiment, 1C of the selector 11 is a signal 1B based on a signal input from the outside, and therefore a desired waveform as a DLL circuit output signal can be generated with high accuracy. Whether the defect is caused by the DLL circuit 10 by selecting the signal 1B as the output signal 1C of the selector 11 and performing a margin test by shifting the timing of the signal supplied from the tester to the ODT pin 15 with high accuracy. It becomes easy to separate whether or not.

  As shown in 1A of FIG. 3, when the waveform disappears or the duty (duty) becomes abnormal and sporadic defective bits appear, if the defect disappears by the test mode according to this embodiment, the DLL One can concentrate on the analysis of the circuit 10.

  Further, according to the present embodiment, an arbitrary waveform can be input to an external pin such as the ODT pin 15 from a tester or the like during a test. Therefore, it is also possible to evaluate the operation margin of the device by changing the duty of the input signal.

  As shown in FIG. 4, it is also effective when measuring with a specific specification. FIG. 4A shows an example of timing when measuring the tRCD spec, which is the timing from the bank active command (ACT) to the read command (READ). In FIG. 4A, 1C is synchronized with the external clock signal CLK. The DLL circuit 10 must keep the external clock frequency constant. For this reason, without the test mode of the present invention, when measuring tRCD, the period tCK of the external clock is uniformly distributed. In this case, since WRITE tCK and READ tCK other than tRCD are also shaken at the same time, it is difficult to evaluate the ability of tRCD alone, and in some cases, meaningless data is acquired. .

  When the test mode of the present invention is used, as shown in FIG. 4B, it is possible to fix only the clock cycle tCK other than tRCD and swing only tRCD (move timing). According to this test mode, 1C is based on a signal input from an external pin, and may be input while keeping time “f” (phase advance of 1C relative to CLK). Also, operation at a low frequency is possible. Thus, the present invention makes it possible to measure asynchronous specifications without affecting other specifications, and is effective.

  Next, a case where it is desired to investigate the cause of variations in output data will be described. Possible causes include the jitter of the DLL and the influence of power supply noise used in the output circuit (including location dependence).

In this embodiment, it keeps the test mode, as shown in FIG. 5, the clock signal 1C which is supplied to the output circuit buffer 20 _{0-20 3} is a signal from the external pin 15, supplies a signal to an external pin 15 When a high-performance tester is used as the tester (not shown), the jitter is suppressed to be sufficiently small, and the influence of the DLL circuit 10 can be ignored. By comparing the amount of variation before and after using the test mode, the influence of the DLL circuit 10 and the effect of the output circuit / buffer 20 can be separated from each other, and the jitter of the DLL circuit 10 in the total amount of variation. Can be measured.

  In the case of the configuration of Patent Document 1 described above, output data is output at a timing different from the normal operation. Therefore, the influence of power supply noise is also different. Even if it is used for this measurement, it is not possible to accurately extract only the DLL jitter before and after the test mode. Also from this viewpoint, Patent Document 1 cannot achieve the effect of the present invention.

  In the above embodiment, the frequency synchronization circuit may be a PLL (Phase Locked Loop), BDD, or SMD (Synchronous Mirror Delay) in addition to the DLL circuit.

  This is effective in determining whether or not there is a problem with the frequency synchronization circuit in evaluation and failure analysis. In addition, in the P / W (wafer test) and sorting process, the output of the frequency synchronization circuit can be operated at a low speed by applying this embodiment even in a low speed cycle where the frequency synchronization circuit cannot operate normally. Since it is not necessary to change the logic of the required circuit, the circuit scale can be reduced.

  In the above embodiment, the SDRAM has been described as an example. However, the present invention is not limited to the SDRAM, and generates an internal clock signal synchronized with the external clock signal to generate an internal circuit (sequential circuit such as a register or a latch). The present invention can be applied to any semiconductor device provided with a clock generation circuit to be supplied to (1).

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, modifications are included.

It is a figure which shows the structure of one Embodiment of this invention. It is a timing waveform diagram explaining the operation of one embodiment of the present invention. It is a timing waveform diagram explaining the operation of one embodiment of the present invention. (A) is a timing waveform diagram explaining tRCD measurement when the test mode is not used and (B) is when the test mode is used. It is a figure explaining the defect analysis in one Embodiment of this invention. It is a figure explaining an example of the timing specification of DRAM. It is a figure which shows an example of a structure of an output circuit. (A), (B) is a figure explaining the timing control of the circuit of FIG. It is a figure which shows the structure of patent document 1. FIG. FIG. 10 is a timing waveform diagram illustrating the operation of the circuit of FIG. 9. It is a figure explaining the output control circuit of FIG. FIG. 12 is a timing chart showing the operation of FIG. 11. FIG. 12 is a diagram illustrating an operation when the clock (Z) in FIG. 11 is set to 4C in FIG. 9.

Explanation of symbols

1 package 10 DLL circuit (frequency synchronization circuit)
DESCRIPTION OF SYMBOLS 11 Selector 12 Test mode input first stage buffer circuit 13, 14 External clock pin 15 ODT pin 20 Output circuit / buffer 21 Output control logic circuit 22 Data control circuit 23 Output buffer circuit 31 DLL circuit 32 Switching circuit 33 Selector (multiplexer)

Claims (7)

A synchronization circuit that inputs an external clock signal from an external clock terminal and generates a signal synchronized with the external clock signal;
First and second input terminals are connected to an external terminal different from the external clock terminal and the output of the synchronous circuit, and a test mode signal is input as a selection control signal. A selection circuit that selectively outputs the clock signal as an internal clock signal, and during normal operation, a selection circuit that selectively outputs the signal from the synchronization circuit as an internal clock signal;
A semiconductor device comprising: In a clock synchronous semiconductor memory device,
A synchronization circuit that inputs an external clock signal from an external clock terminal and generates a signal synchronized with the external clock signal;
First and second input terminals are connected to an external terminal different from the external clock terminal and the output of the synchronous circuit, and a test mode signal is input as a selection control signal. A selection circuit that selectively outputs the clock signal that is output, and during normal operation, selectively outputs the signal from the synchronization circuit;
A semiconductor memory device comprising:   3. The semiconductor memory device according to claim 2, wherein the external terminal is selected from unused terminals during a test. A control circuit that receives an output signal from the selection circuit as a control clock and generates an output enable signal in synchronization with the control clock;
A data control circuit that receives internal data and outputs output data when the output enable signal is active;
A buffer circuit that receives output data from the data control circuit and drives an output terminal according to the timing of the control clock;
The semiconductor memory device according to claim 2, further comprising:   5. The semiconductor memory device according to claim 2, wherein data transfer is performed in synchronization with rising and falling edges of the external clock signal. A test method for a semiconductor device including a synchronization circuit that inputs an external clock signal from an external clock terminal and generates a signal synchronized with the external clock signal,
And a step of selecting and outputting a clock signal supplied from a tester and input to an external terminal different from the external clock terminal, instead of an output signal of the synchronous circuit. Test method. 7. The method of testing a semiconductor device according to claim 6, wherein the external terminal is selected from unused terminals during a test.

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