JP2006332684A - Semiconductor device, functional setting method therefor, and its evaluation method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, its evaluation method, and its functional setting method which are structured, by including a plurality of chip IPs on a common semiconductor wiring substrate and which can be suitable for "small variety and mass production". <P>SOLUTION: Various IP group can be mounted as a chip IP on a silicon wiring substrate 10. The silicon wiring substrate 10 comprises a silicon substrate 11, a ground plane 12, a wiring layer, such as a first wiring layer 13 and a second wiring layer 14, and a pad 15. It is structured, having an IP (chip IP) mounted on the pad 15 by pasting/Attempt is made to make the semiconductor device to be general-purpose, by installing as many functions as possible, enabling selection of the necessary functions according to the purpose of use, and the device is made suitable for small variety and mass production by providing means for selecting, switching, and setting the function of each IP. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which various chips IP are mounted on a semiconductor wiring substrate provided with a wiring layer, an evaluation method thereof, and a function setting method thereof.

  In recent years, the concept of a system LSI in which a plurality of LSIs are formed on a common substrate has been proposed, and various proposals have been made as system LSI design methods. In particular, the advantage of the system LSI is realized by housing a memory such as a DRAM, an analog circuit such as a logic LSI and a high frequency circuit in one semiconductor device, and realizing a highly integrated multi-functional semiconductor device. Be able to.

  By the way, the above-described conventional system LSI faces the following problems in actually forming a device.

  The first problem is that it is difficult to reduce the manufacturing cost of the device. This is because the development cost of the system LSI is great and the manufacturing yield is not so high.

  The second problem is that the wiring delay becomes very large. Generally, according to the shrink rule, the height of the device is also reduced. However, as the wiring cross-sectional area is reduced, the wiring delay defined by RC (R is a resistance and C is a parasitic capacitance) is increased. In other words, as far as the wiring delay is concerned, the disadvantage increases more than the benefit of miniaturization. One means for solving this is to provide a buffer in the wiring. However, providing the buffer causes another disadvantage that the occupied area of the device and the power consumption increase.

  A third problem is that it is difficult to reduce noise. When the power supply voltage decreases, the current increases, but it becomes difficult to suppress an increase in noise corresponding to the increase in the current. This is because an increase in noise due to miniaturization is inevitable because the SN ratio deteriorates in proportion to the third to sixth power of the shrink ratio. That is, the point is how to suppress the power source impedance.

  Therefore, as one means for realizing a semiconductor device incorporating a variety of multifunctional devices while ensuring a large cross-sectional area of the wiring, various elements are formed on a semiconductor wiring substrate having a wiring layer, for example, a silicon wiring substrate. It is conceivable to realize a semiconductor device suitable for a small variety and mass production by mounting a chip IP integrated with the above. However, the LSI in the conventional chip IP is designed as IP hardware (hard IP), and the function of this hard IP is determined uniquely and in the state of a black box. It can be applied to applications and does not meet the demand for reducing the number of varieties. In other words, if the conventional system LSI construction method is adopted as it is, it becomes difficult to realize a semiconductor device suitable for a small variety and mass production.

  It is an object of the present invention to mount a chip IP that can be a design asset as an IP on a common semiconductor wiring board, and to take measures related to evaluation, selection, setting, etc. of the function, thereby reducing the number of products and mass production. The object is to provide a suitable semiconductor device, its evaluation method and its function setting method.

  A first semiconductor device of the present invention includes a semiconductor wiring substrate having a wiring layer, a chip IP mounted on the semiconductor wiring substrate by bonding, a plurality of functions provided on the chip IP, and the plurality of the plurality of functions. Functional information storage means for storing functional information related to the function.

  As a result, the functions in the chip IP, which has been designed as an IP that has conventionally been a black box, can be easily recognized from the outside, so that it is possible to meet various user requirements with a common semiconductor device.

  The function information storage means preferably stores the function information by attaching an ID number to each function.

  Moreover, it is preferable that the function information regarding the plurality of functions is standardized so that it can be displayed on the display means.

  By further including another chip IP configured to receive the function information of the chip IP and determine its own function, the function can be automatically selected.

  The chip IP is configured to output the function information stored in the function information storage means when receiving a key signal, so that only a specific user or the like is informed of the function of the chip IP. Is possible.

  By further including an encryption unit that encrypts the functional information output from the functional information storage unit, it is possible to ensure the confidentiality of the function of the chip IP.

  When receiving the key signal, it is preferable to further include decryption means for decrypting and outputting the encrypted function information.

  A second semiconductor device of the present invention is provided on a semiconductor wiring substrate having a wiring layer, a plurality of chips IP which are mounted on the semiconductor wiring substrate by bonding and have a plurality of functions, and each chip IP. And a plurality of function information storage means for storing information related to the plurality of functions. The plurality of chip IPs are configured to be able to access the function information storage means of other chip IPs and read the function information from each other. Yes.

  Thereby, the function of each chip IP can be easily and quickly known through the function information storage means in each chip IP. Then, functions can be selected and switched based on this function information, and a semiconductor device suitable for mass production of small products can be provided.

  Each of the plurality of chips IP is provided with a key signal transmission / reception unit for transmitting / receiving a key signal, and the function information stored in the function information storage means is output when the key signal transmission / reception unit receives the key signal. With this configuration, it becomes possible to select and switch functions using communication between chip IPs.

  The plurality of chips IP are configured to transmit / receive function information after the function information in the function information storage means is encoded into a mutually recognizable code. Can be seen.

  Each of the function information storage means stores the function information by attaching an ID number to each of the functions, and further includes a function recognition means for recognizing the function information based on the ID number. This makes it possible to quickly recognize, set and switch functions.

  Since the function recognizing means is provided in a chip IP different from each of the chips IP, it is not necessary to change the structure of the other chip IP, so that customization can be achieved.

  The function recognition means is provided as the stored contents of the memory, so that the function can be easily changed without replacing the chip IP.

  The function recognition means may be provided integrally with the function information storage means in each chip IP.

  Each of the function information storage means includes a first storage unit that stores lower n bits (n <m) of an m-bit address used in a semiconductor device, and (n + 1) or more upper bits of an m-bit address. A second storage unit that stores the ID number, and whether or not the upper bits of (n + 1) or more of the m-bit input address match the ID number of the second storage unit By further providing a means for performing the above, it is possible to easily recognize, set, and switch functions using the ID number as a clue.

  The plurality of chips IP are configured to be able to change or set their own functions based on the function information of the function information storage means in the other chip IP. It becomes possible to automatically correct to the optimal one.

  By further comprising a control circuit that receives the storage information of the storage information storage means in each chip IP and changes or sets the function of each chip IP. Communication between the chip IPs can be facilitated.

  According to a first method for evaluating a semiconductor device of the present invention, a step (a) of mounting a plurality of evaluation chips IP each having at least one function on a semiconductor wiring substrate having a wiring layer by bonding, and each of the above evaluations And (b) evaluating the at least one function of the chip for IP by simulation.

  By this method, it is possible to switch the function of the semiconductor device, select the function, set the function, etc. using the evaluation result of the chip IP.

  The step (b) is preferably performed by displaying an internal document storing the function of the chip IP on a display device.

  In the step (a), the wiring layer of the semiconductor wiring board is formed by dividing it into a normal operation wiring layer and an evaluation wiring layer above the normal operation wiring layer, and after the step (b). By further including the step of removing the evaluation wiring layer of the semiconductor wiring substrate and leaving the normal operation wiring layer, it is possible to shorten the delivery time of the semiconductor device and reduce the cost.

  A second semiconductor device evaluation method of the present invention is a semiconductor device evaluation method including a semiconductor wiring substrate having a wiring layer and a plurality of chips IP mounted on the semiconductor wiring substrate by bonding. In this method, a connection test is performed by exchanging information on corresponding terminals of the plurality of chips IP.

  By this method, a semiconductor device with high reliability of connection between the chip IPs can be obtained.

  The semiconductor device function setting method of the present invention is a semiconductor device function setting method including a semiconductor wiring substrate having a wiring layer and a chip IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions. In this method, only a part of the plurality of functions is activated.

  This method makes it possible to use only the functions necessary for the application of the semiconductor device without using all the functions in the semiconductor device, thus ensuring reduction in power consumption and speeding up of operation during use. be able to. On the other hand, by providing as many functions as possible, the number of types of semiconductor devices can be reduced as much as possible, so that a semiconductor device suitable for a small variety and mass production can be obtained.

  In this case, specific methods for activating only a part of the functions include a method of fixing the wiring relationship of the wiring layer, a method of fixing logic inputs supplied to the plurality of functions, and a part of the functions only. A method for enabling only a part of the functions by remote operation via a network, a method for inputting a clock signal only to the part of functions, and a part of the functions only. There are a method of supplying a power supply voltage, a method of supplying an input signal to only some of the functions, and the like.

  According to the present invention, a semiconductor device suitable for a small variety and mass production, an evaluation method thereof, and a function setting method thereof can be obtained.

-Basic structure as a premise of the present invention-
Therefore, in the present invention, as one means for realizing a semiconductor device incorporating a variety of multifunctional devices while ensuring a large cross-sectional area of the wiring, a semiconductor wiring substrate having a wiring layer, for example, a silicon wiring substrate (Super) -Sub) The structure which mounts chip | tip IP incorporating various devices is taken. A circuit (IC) provided in each chip IP can be handled as an IP (Intellectual Property) in designing the semiconductor device, and can be considered as various IPs bonded to the semiconductor wiring substrate. That is, since the entire semiconductor device is “IP On Super-Sub”, in the embodiment of the present specification, the entire semiconductor device including the silicon wiring substrate and the IP group is described as “IPOS device”.

  FIGS. 1A, 1B, and 1C are plan views of a silicon wiring substrate serving as a wiring substrate for mounting an IP (chip IP) group, and an example of an IP group mounted on the silicon wiring substrate. It is the top view shown, and sectional drawing of a silicon wiring board. As shown in FIGS. 1A and 1B, a plurality of regions for mounting various IPs are provided on the silicon wiring substrate 10, and each region is, for example, a DC / AC-IP. , Analog-IP, Logic-IP, CPU-IP, DSP-IP, Flash memory-IP, SRAM-IP, DRAM-IP, I / O-IP, etc. . As shown in FIG. 1C, the silicon wiring substrate 10 includes a silicon substrate 11, a ground plane 12 provided on the silicon substrate 10 with an insulating film (not shown) interposed therebetween, and a ground plane 12. A first wiring layer 13 provided with an interlayer insulating film interposed therebetween, a second wiring layer 14 provided with an interlayer insulating film interposed therebetween on the first wiring layer 13, and a passivation film on the second wiring layer 14 And a pad 15 provided with a gap therebetween. The pads 15, the wiring layers 13 and 14, and the ground plane 12 are connected to each other at desired portions through contacts (not shown). Each IP is affixed on the pad 15 so that each IP is electrically connected to each other or the ground plane 12 by the wiring layers 13 and 14.

  The restrictions on the dimensions of the wiring layers 13 and 14 in the silicon wiring substrate 10 are gentle, and even a wiring with a width of several μm can be provided. Empirically, in the process of miniaturization of the conventional semiconductor integrated circuit device, it is possible to provide a wiring having a generation size with the best characteristics as a wiring. In addition, the electrical impedance of the wiring can be reduced.

  The chip IP on the silicon wiring substrate has many functions, but there are two ways of thinking. One is an idea of using as many functions as possible, and the other is an idea of limiting the functions to be used. That is, in order to respond to various requests of users, it is preferable to have a configuration that can handle various usage methods, but on the other hand, it is necessary to limit to any function in actual use. In other words, by satisfying these two conflicting requirements, it is possible to construct an IPOS device suitable for a large quantity and a small variety while responding to various user requirements. Therefore, a means for selecting, limiting, and setting functions in the IPOS device having various functions in advance is required. That is, there are a method for evaluating the function of the chip IP on the silicon wiring substrate, a method for selecting the function, a configuration on the chip, and the like. In the present invention, embodiments relating to such means will be described.

(First embodiment)
In this embodiment, an embodiment relating to measures for evaluating and selectively using functions on an IPOS device will be described.

  FIG. 2 is a block diagram schematically showing the structure of a multifunction IP (chip IP) arranged in the IPOS device according to the first embodiment. In this multi-function IP, for example, four functions of function A, function B, function C, and function D are incorporated. In general, each IP (chip IP) in an IPOS device incorporates many functions. An evaluation IP for evaluating these functions is used as an evaluation catalog or as an actual chip. Can be supplied as a product. Hereinafter, a specific example relating to a means for evaluating the function in the IP will be described.

-First specific example-
FIG. 3 is a block diagram schematically showing the configuration of the evaluation IPOS device in the first specific example of the first embodiment. As shown in FIG. 3, the evaluation IPOS device 21 includes a user logic 22 and evaluation IPs 23 and 24. This IPOS device 21 evaluates and debugs IP in the IPOS device 21 before forming a final product, and evaluates a system called an IPOS device. Although the evaluation IPOS device 21 itself may be a final product, it is not generally a final product. Then, the evaluation IPOS device 21 needs to perform operations such as selecting, changing, and setting IP functions at the time of evaluation. The evaluation IPOS device 21 can check the state of many intermediate nodes in the IPOS device. In other words, it is possible to read internal information that is not known when commercialized. When software debugging is completed, an extra function in the evaluation IPOS device 21 is removed, and the software is generally shipped with a simplified configuration.

  FIG. 4 is a cross-sectional view of the evaluation IPOS device according to this example. As shown in the figure, in the silicon wiring substrate 25, a normal operation wiring layer 26 used for normal operation and an evaluation wiring layer provided on the normal operation wiring layer 26 and used only for evaluation. There are 27. The evaluation IPs 23 and 24 are connected to the evaluation wiring layer 27 and the normal operation wiring layer 26 through contacts. The evaluation wiring layer 27 is generally used only at the time of evaluation. When the evaluation is completed and commercialized, only the evaluation wiring layer 27 can be peeled off, so that the evaluation wiring layer 27 can be peeled off. Is provided. In general, a plurality of normal operation wiring layers 26 and a plurality of evaluation wiring layers 27 are provided. As described above, the evaluation wiring layer 27 is provided above the normal operation wiring layer 26, and the normal operation wiring layer 26 is left so that only the evaluation wiring layer 27 can be peeled off. In other words, an actual chip can be configured by providing the evaluation wiring layer 27 so that an internal signal can be read during debugging, but removing the evaluation wiring layer 27 during debugging. Therefore, it is possible to reduce the manufacturing cost and the delivery time.

-Second specific example-
FIG. 5 is a block diagram for explaining a general-purpose evaluation IPOS device evaluation method according to the second specific example of the present embodiment. As shown in the figure, in this case, since no user logic is mounted on the evaluation IPOS device 30, various functions in the evaluation IPOS device 30 are evaluated using the user board 31 (actual board). Will do. In this general-purpose evaluation IPOS device 30, the normal wiring layer is not provided on the silicon wiring substrate, and only the evaluation wiring layer is provided. The IPOS device of this specific example is particularly suitable for a device provided to a user as a catalog.

-Third example-
FIG. 6 is a block diagram for explaining a general-purpose evaluation IPOS device evaluation method in the third specific example. As shown in the figure, no user logic is mounted on the evaluation IPOS device 30 in this case as well. In this specific example, various functions in the evaluation IPOS device 30 are evaluated using a software emulator 32 (or simulator) instead of the actual board in the second specific example. Also in this specific example, in the general-purpose evaluation IPOS device 30, the normal wiring layer is not provided on the silicon wiring substrate, and only the evaluation wiring layer is provided.

-Fourth example-
FIG. 7 is a block diagram schematically showing an evaluation system by remote operation of a general-purpose evaluation IPOS device in the fourth specific example. As shown in the figure, the system of this specific example includes IPOS device evaluation systems 33 and 34 and a function simulator 35 connected to the evaluation systems 33 and 34 via a network. The IPOS device evaluation system 33 sends a control signal to an IPOS device 30a equipped with IP-A, IP-B, IP-C, and IP-D, and each IP terminal in the IPOS device 30a. And a control system 36 configured to receive an observation signal of each IP from the terminal. The IPOS device evaluation system 34 sends a control signal to the IPOS device 30b equipped with IP-E, IP-F, IP-G, and IP-H, and each IP terminal in the IPOS device 30b. And a control system 37 configured to receive an observation signal of each IP from a terminal. Control signals to the evaluation systems 33 and 34 or observation signals from the evaluation systems 33 and 34 are transmitted and received to and from the function simulator 35 via the network.

  The function simulator 35 includes a library 39. The function simulator 35 receives design data and test vectors created in a function description language or a function circuit diagram, and performs system construction simulation using each IP of the IPOS devices 30a and 30b. At that time, the library 39 stores IP function ID information on the IPOS device or information including a function shape symbol and a terminal configuration for graphically creating design data of the IPOS device. Arbitrarily selected, the design data can be configured.

  The evaluation systems 33 and 34 transmit the IP type and address information (IPOS device IP and its terminal location information) in the IPOS devices 30a and 30b to the function simulator 35 via the network. Here, the address information may be stored in advance in the library 39 as an IP database, or may be acquired during communication with the evaluation systems 33 and 34.

  The function simulator 35 transmits an IP input vector from the IP address information corresponding to the IP used in the design data to the evaluation systems 33 and 34 via the network, and the observation signals from the evaluation systems 33 and 34 are transmitted to the network. To obtain the function simulation result.

  According to this specific example, an accurate system verification can be performed using the IP operation on the actual IPOS device. The operation in the evaluation systems 33 and 34 can be verified in real time. Even if the above IP is not in the place to be verified, it is possible to perform the function verification, and it is possible to exhibit the effects that the function simulation can be performed flexibly and in detail. That is, conventionally, a simulation model is created separately and supplied to the user, and the user verifies using this model. If there is a real chip, it can perform simulation more quickly. However, sending real chips takes time and effort. On the other hand, in this specific example, the user can quickly perform a simulation on the actual chip by remote operation without sending the actual chip to the user.

  The functional simulation may be performed using a software emulator, a debugger, or the like instead of the simulator.

(Second Embodiment)
Next, a second embodiment relating to a specific method for selecting, setting, and limiting functions will be described. For example, when a bus protocol for an IPOS device is created, the type of bus may vary depending on the entire IPOS device or individual IP. There may be a plurality of types of clocks to be used. In such a case, a plurality of functions A and B which are the same functions in terms of content but differ in bus or clock type are provided in the IP in advance, and either of the functions A and B is selected by the user. If the device can be used, a desired function can be easily incorporated into the semiconductor device by adapting to the bus protocol. That is, the IPOS device structure is suitable for a large quantity and a small variety of products while responding to various requests of users.

  In the following first to fourth specific examples, only one of the two types of functions A and B will be described for easy understanding, but each specific example will be described. Can also be applied to selecting one of them when there are more than two functions.

-First specific example-
FIGS. 8A and 8B are respectively a plan view of an IP and a partial cross-sectional view of an IPOS device in the first specific example of the present embodiment, respectively. This specific example assumes that the user creates a silicon wiring substrate. As shown in FIG. 8A, it is assumed that the IP 40 includes a function A and a function B that are the same in contents but different in bus type. In this specific example, the functions A and B in the IP 40 are set according to the logic of the wiring in the silicon wiring substrate 43. For example, as shown in FIG. 9B, the function A is a power supply wiring 41 (power supply line) for supplying a power supply voltage (logic H), and the function B is a ground wiring 42 (ground for supplying a ground voltage (logic L)). Line) in advance. That is, in this embodiment, a function to be used is selected depending on the type of logic given to the function. As a result, the user can easily set which function A or B to use by supplying any logic H or L signal. In this specific example, the user may use both functions A and B.

-Second specific example-
FIGS. 9A and 9B are an IP plan view and a partial cross-sectional view of an IPOS device, respectively, in the second specific example of this embodiment. This specific example assumes that the user creates a silicon wiring substrate. As shown in FIG. 9A, also in this specific example, it is assumed that the IP 45 has a function A and a function B that are the same in content and have different bus types. In the IP 45, a selector 46 for selecting the function A and the function B and outputting them to the output terminal Op is provided. As shown in FIG. 9B, in this specific example, a contact 50 connected to the selector 46 is provided on either the power supply line 48 or the ground line 49 in the silicon wiring substrate 47. That is, the contact 50 is configured to select a function to be used in the IP.

-Third example-
FIGS. 10A and 10B are a plan view of an IP and a partial cross-sectional view of an IPOS device, respectively, in the third specific example of this embodiment. This specific example assumes that the user creates a silicon wiring substrate. As shown in FIG. 10A, also in this specific example, it is assumed that the IP 51 has a function A and a function B that are the same in content but different in bus type. In the IP 51, a circuit C that functions as a selector for selecting the function A and the function B and outputting them to the output terminal Op is provided. As shown in FIG. 10B, in this specific example, one of the functions A and B is switched and connected to the circuit C depending on the wiring structure in the silicon wiring substrate 52. That is, the function to be used in the IP is selected by the wiring itself.

-Fourth example-
FIGS. 11A and 11B are an IP plan view and a partial cross-sectional view of an IPOS device, respectively, in the fourth specific example of this embodiment. This specific example assumes that not only the user but also the provider creates the silicon wiring substrate. As shown in FIG. 11A, also in this specific example, it is assumed that the IP 55 has a function A and a function B that are the same in contents but different in bus type. In the IPOS device, a function selection IP 56 having a selector 57 for selecting the function A and the function B in the IP 55 is provided separately from the IP 55. As shown in FIG. 11 (b), in this specific example, the wiring on the silicon wiring substrate simply connects the functions A and B in the IP 55 and the selector 57 in the IP 56, and the function selection is performed by the selector in the IP 56. 57 is determined by the connection relationship between the power line 58 and the ground line 59. That is, depending on which of the power supply line 58 and the ground line 59 is connected to the selector 57 in the IP 56, it is selected which of the functions A and B is output from the IP 57. That is, by separately providing a function selection IP, the function used in the IP on the IPOS device is selected.

-Fifth Specific Example FIGS. 12A and 12B are a perspective view and a block circuit diagram showing a configuration of an IPOS device related to function setting in a fifth specific example of the present embodiment. This specific example assumes that not only the user but also the provider creates the silicon wiring substrate. As shown in FIG. 12A, for example, three IP-A, IP-B, and IP-C are mounted on the silicon wiring substrate 60, and each IP has a plurality of functions. Yes. In this specific example, a KeyIP 61 is provided for setting an effective function among many functions of each IP. That is, as shown in FIG. 12B, each function in IP-A, IP-B, IP-B and KeyIP 61 are connected to each other by wiring in a silicon wiring substrate (not shown). Which wiring is effectively connected is set by a circuit in the KeyIP 61. In FIG. 12B, the wirings marked with “x” are unused wirings. In this specific example, which function in many IPs is effective can be uniquely determined by changing the KeyIP 61 instead of the structure of the silicon wiring substrate. That is, since the function can be selected by changing the KeyIP or software in the KeyIP, a more flexible function can be selected.

-Sixth example-
FIGS. 13A and 13B are diagrams showing a function selection method in the sixth specific example of the present embodiment and its modification. This example assumes that the provider creates a silicon wiring board in principle. As shown in FIG. 13A, also in the IPOS device 65 of this specific example, it is assumed that there are a function A and a function B having the same contents but different bus types in the IP. In the IP, a register 67 for setting selection of function A and function B is provided. As shown in FIG. 13B, a setting register 69 that is an IP different from the IP may be provided in the IPOS device 65. In this specific example or its modification, a license code is transmitted from the user-side emulator 68 (or simulator) to the IPOS device 65, and it is set whether to use one of the functions A and B by remote operation. This license code is set by a license agreement or the like.

  According to this example, the user can quickly evaluate the device without handing over the semiconductor device itself to the user, so that the delivery time can be shortened and the transportation cost can be reduced.

(Third embodiment)
Next, a description will be given of a third embodiment relating to a structure and a method for enabling an internal function of an IP arranged in an IPOS device to be examined from the outside.

  FIG. 14 is a block diagram showing a basic configuration of IP arranged in the IPOS device in the present embodiment. As shown in the figure, the IP 70 has various functions such as a function A, a function B, a function C, and a function D. The IP 70 stores a function information storage unit 71 (information on these functions registered). Memory). Here, specific information regarding various functions includes an identification code, manufacturing history, function type, specification, document, and the like. Here, as specifications, for example, when various settings are possible, there are a setting parameter and a range of values that can be taken, and correlation between the power supply voltage (V) and the operation speed (MHz) as performance information. is there.

  In other words, by providing the function information recording unit 71 having such internal function information in the IP 70, the function in each IP that has been a conventional black box can be easily recognized from the outside. Functions corresponding to various user requests can be provided in the IPOS device. That is, the structure of an IPOS device suitable for a large quantity and a small number of products can be obtained while meeting various demands. Hereinafter, specific examples of the present embodiment will be described.

-First specific example-
FIG. 15 is a block diagram schematically showing the configuration of the IPOS device in the first specific example of the present embodiment. In this specific example, after the IP 70 having the function information storage unit 71 is pasted in the IPOS device 72, the function information storage unit 71 in the IP 70 is accessed from an external device, and information on the function of the IP 70 is sent to the IPOS device 72. Read out from 72 output terminals Op. Information regarding the read function may be used for inspection, or may be used for switching the function in the IP 70 by software in an external device. If the output terminal Op is connected to the display device 73, the internal document of the IP 70 can be browsed on the display device 73. In that case, the function information storage unit 71 in the IP 70 needs to store information in a format that can be read by an external device. For example, when a Web browser is used, the function information may be stored in the function information storage unit 72 using HTML.

  In particular, in an IPOS device, since it is necessary to select or switch functions in order to adapt to mass production of a small number of products, it is effective to provide a means for reading out function information that was hardly necessary in the past. It becomes.

-Second specific example-
FIG. 16 is a block diagram schematically showing the configuration of an IPOS device and one IP in the second specific example of the present embodiment. In this specific example, as shown in FIG. 17A, the IPOS device 72 reads out the IP 70 having the function A, the function B, the function C, the function D, and the function information storage unit 71, and the data of the IP 70. An IP 75 that automatically configures itself is provided. In other words, the IP 75 accesses the IP 70, reads the data in the IP 70, and determines the values of the respective units within itself according to the data.

  This specific example is applied, for example, when the IP 70 is a CCD and the IP 75 is a driver for driving the CCD. Here, it is assumed that IP70 is a CCD with 100 × 200 pixels and IP75 is a general-purpose driver and has a capacity that can handle both 100 × 200 and 500 × 500 pixels. In that case, the IP75 can be automatically configured by enabling (active) only the portion corresponding to 100 × 200 pixels among the terminals of the IP75 as a driver and disabling the others. With such a structure, for example, high-performance products and low-priced products of digital cameras cannot be configured using the same IPOS device, and it is possible to respond to various demands while being a small variety and mass production. it can.

-Third example-
FIG. 17 is a block diagram schematically showing the configuration of the IPOS device in the third specific example of the present embodiment. In this specific example, as shown in FIG. 17A, the IPOS device 72 includes an IP 70 having a function A, a function B, a function C, a function D, and a function information storage unit 71, a function E, a function F, An IP 76 having a function G, a function H, and a function information storage unit 77 is provided. The IP 70 and IP 76 are configured to be able to access the function information storage units 71 and 76 of the other party's IP and read the internal data. In this specific example, the IPs 70 and 76 can automatically configure themselves or automatically optimize each other using the data of the other party.

  Here, when the IPs 70 and 76 authenticate each other, data can be read using the fact that preset key signals match each other. With this configuration, in addition to the functional usage method, it is possible to avoid problems such as setting its own value with a fake IP.

  In addition, it is preferable that the IPs 70 and 76 encode their own data based on both key signals. At this time, the data encoded by the IPs 70 and 76 may be decoded and used inside, or the encoded data can be used without being decoded. This not only eliminates the data exchange with the fake IP as described above, but also keeps the data in the IPs 70 and 76 secret, that is, prevents the functions in the IPs 70 and 76 from being revealed from the outside. However, they can automatically configure themselves.

  In addition, by exchanging information on the corresponding terminals connected between the IPs 70 and 76, it is possible to determine whether the connection state between the terminals is good or not.

-Fourth example-
FIG. 18 is a block diagram schematically showing the configuration of the IPOS device in the fourth specific example of the present embodiment. In this specific example, the IPOS device 72 has an IP 70 having a function information storage unit 71 storing information related to function A, function B, function C, function D, etc., function E, function F, function G, An IP 76 having a function information storage unit 77 that stores information related to the function H and the like, and a system control unit 78 that controls the entire IPOS device are provided. Each IP 70 and IP 76 is configured to send function information from the function information storage units 71 and 77 to the system control unit 78, and the system control unit 78 changes or sets the setting of each IP according to the function information. Has been. As a result, communication between the respective chip IPs can be facilitated.

  FIG. 19 is a block diagram schematically showing a configuration of an IPOS device in a modification of the fourth specific example. In this modification, the system control unit 78 is arranged outside the IPOS device 72 instead of inside the IPOS device 72. Also in this case, the same effect as the fourth specific example can be exhibited.

(Fourth embodiment)
In a conventional system LSI, a bus is mounted as wiring on a substrate, and each IP is connected by this bus. However, the number of IPs connected to the bus causes excess or deficiency in the drive capability of each IP, resulting in problems such as waste of drive capability and restrictions on the number of IPs that can be mounted. In addition, since the bus delay depends on the number and arrangement of IPs, it has become an obstacle when designing a large-scale LSI. If such a structure is applied as it is to the structure of an IPOS device, it will not be possible to meet various requirements with a common configuration as much as possible, and the advantages of the IPOS device will not be utilized.

  Therefore, in the present embodiment, a method for integrating the buses on the IPOS device for fully exhibiting the features of the IPOS device will be described.

  FIG. 20 is a block diagram schematically showing the most basic structure of the IPOS device of this embodiment. As shown in the figure, the IPOS device 100 includes, for example, three IP-A, IP-B, and IP-C, and a bus IP101 that connects IP-A, IP-B, and IP-C in parallel. Is provided. The bus IP101 has a function of switching and controlling a connection relationship between a connection terminal to a plurality of IP-A, IP-B, and IP-C and another IP to be connected to each other. According to the present embodiment, each of the IP-A, IP-B, and IP-C only needs to have a driving capability required for connection with the bus IP101. That is, it is easy to ensure the performance defined by the bus IP without being affected by other IPs. Therefore, problems such as waste of driving capability due to the number of IPs connected to the bus and restrictions on the number of IPs can be solved, and various requests can be met with a common configuration as much as possible.

-Specific example-
FIG. 21 is a block diagram showing a specific example of the present embodiment relating to a bus integrated system having a configuration of one host-to-many peripheral circuit. As shown in the figure, the IPOS device 100 has a USB hub function for connecting, for example, three IP-A, IP-B, and IP-C in parallel with IP-A, IP-B, and IP-C. A bus IP102 having a USB host function and a host IP103 having a USB host function are provided. In addition, USB device functions 104, 105, and 106 are provided in the IP-A, IP-B, and IP-C, respectively.

  That is, in the case of a system in which one IP on the IPOS device 100 controls the bus as a host IP, a USB (Universal Serial Bus) protocol generally used in a personal computer system is adopted, and a USB hub is used. It has a bus IP102 having a function and a host IP103 having a USB host function, and is connected to the bus by providing USB device functions 104, 105, 106 in each IP-A, IP-B, IP-C. It is not necessary to make settings for IP recognition, and it is not necessary to adjust the drive capability. That is, according to the USB protocol, it is possible to recognize the peripheral device or the peripheral function without resetting it even if the peripheral device or the peripheral function connected to the bus is changed. Therefore, by using the bus IP102 having the USB hub function, even if the external condition changes depending on the number of IPs connected to the bus IP102 or the function selection in a specific IP, special processing such as resetting of the external condition is performed. Even without this, it is possible to easily recognize the peripheral function and control the bus.

  When the USB protocol is adopted, the power supply line is also mounted in the bus. However, in the IPOS device, since power is supplied to each IP, it is not necessary to mount the power supply line in the bus.

(Fifth embodiment)
FIG. 22 is a block diagram schematically showing the configuration of the IPOS device according to the fifth embodiment. As shown in the figure, in the IPOS device 110, there are confidential IP-X and confidential IP-Y holding confidential data and an interface IP of the confidential IP-X and confidential IP-Y. An encrypted IP 111 is arranged. That is, when transmitting / receiving signals between the confidential IP-X and the confidential IP-Y and an external device, the encryption IP 111 encrypts and decrypts data that requires confidentiality to perform transmission / reception.

  FIG. 23 is a block diagram illustrating an example of a signal processing method between the encrypted IP and the secret IP-X. As shown in the figure, the encryption IP 111 includes a key transmission / reception unit 112 for transmitting / receiving general-purpose key signals, an encoder 113 for encrypting data, and a decoder 114 for decrypting data. Is provided. The secret IP-X is provided with a key transmitter / receiver 115 for transmitting / receiving a key signal common to the key transmitter / receiver 112 in the encrypted IP 111, a decoder 116, an encoder 117, and a secret data storage unit 118. . In other words, when transmitting confidential data to an external device, a key signal is sent from the key transmitting / receiving unit 115 of the IP-X to the key transmitting / receiving unit 112 in the encrypted IP 111, and if the coincidence of the key signal is confirmed, the confidential data storage unit 118. After the confidential data extracted from the data is encrypted by the encoder 117, it is transmitted to the encrypted IP 111. Then, the data is decrypted by the decoder 114 in the encrypted IP 111 and then sent to the external device. When receiving confidential data, the encoder 113 in the encryption IP 111 and the decoder 116 in the confidential IP-X are processed to perform the reverse process to the above, and then the confidential data is registered in the confidential data storage unit 118. .

  With such a configuration, the confidential data is not sent to the external device unless the key signal matches, and data that is not confidential data is not erroneously registered from the external device. Accordingly, since the confidential data cannot be used on the confidential IP-X, the confidential IP-Y alone or on the IPOS device, the confidential data, for example, is registered in the function information storage unit as described in the first embodiment. Internal functions can be prevented from being analyzed by outsiders.

(Sixth embodiment)
Next, a description will be given of a sixth embodiment relating to the configuration of an IPOS device necessary for actually performing mutual authentication or controlling IP by a system control unit or software. This embodiment is suitable for performing the function selection control in the third embodiment, for example.

  The ID information (recognition information) in the present embodiment is information related to function identification, and includes information related to bus I / F, memory capacity, and register mapping, for example. By using this ID information, the function required by the host can be automatically set to each peripheral IP by the function recognition IP, and conversely, the host function is automatically limited rather than the function of the peripheral IP. You can also For example, each peripheral IP has various bus I / Fs such as A bus, B bus, C bus,..., But the host side wants to restrict use of the A bus.

  In such a case, there are methods as shown in the following specific examples as a method for selecting functions, setting restrictions, etc. using ID information.

-First specific example-
FIG. 24 is a block circuit diagram showing the configuration of the IPOS device in the first specific example of the present embodiment. As shown in the figure, the IPOS device of this example includes a CPU-IP, a function recognition IP 121, and peripheral IPs IP-A, IP-B, and IP-C. ID information 122 is built in each of IP-A, IP-B, and IP-C. Then, the function recognition IP 121 reads the ID information of each IP with respect to the ID information 122 built in each IP, and stops unnecessary functions in each IP. For example, the control for stopping the clock of the unnecessary function is performed.

  This makes it possible to reduce power consumption without changing the IP, detect stuck-at faults in unnecessary circuits, configure an LSI for a specific application, and then replace the function recognition IP (chip) with a silicon wiring board. It is possible to customize the function by simply pasting it on the screen.

-Second specific example-
FIG. 25 is a block circuit diagram showing the configuration of the IPOS device in the second specific example of the present embodiment. As shown in the figure, the IPOS device of this specific example includes a CPU-IP and peripheral IPs IP-A, IP-B, and IP-C, and the CPU-IP, IP-A, and IP. -B and IP-C each have built-in ID information and recognition function 124. Then, the CPU-IP incorporating the ID information and recognition function 124 performs control to stop a specific function or select from a plurality of functions.

  As a result, it is not necessary to change the peripheral IP (chip) for each CPU-IP, and the functions of several types of CPU-IP (bus I / F) can be made common to various types of CPU-IP. ) Can be reused for general purpose peripheral IP (chip).

-Third example-
FIG. 26 is a block circuit diagram showing the configuration of the IPOS device in the third specific example of the present embodiment. As shown in the figure, the IPOS device of this specific example includes a CPU-IP, recognition software IP126 (stored contents of a memory), and peripheral IPs IP-A, IP-B, and IP-C. The CPU-IP, IP-A, IP-B, and IP-C each have ID information 122 built therein. Then, the CPU-IP accesses each peripheral IP, reads the ID information 122 built in each IP, and performs control to stop and select unnecessary functions from the information in the recognition software IP126. For example, setting a flag in a register stops unnecessary functions.

  As a result, it is possible to select the function of the peripheral IP (chip) only by changing the memory content of the memory, and the ID information of each peripheral IP can be read. After configuring an LSI, the hardware part is not changed. Even if the recognition software (memory) is changed, the function can be changed.

(Seventh embodiment)
Next, a description will be given of a sixth embodiment related to an IP configuration necessary for actually performing mutual authentication or controlling IP by a system control unit or software. This embodiment is suitable for performing function selection control in, for example, the first, second, and third embodiments, particularly the sixth specific example of the second embodiment. The ID information in this embodiment is expressed by an n-bit register, for example.

  In such a case, there are methods such as the following specific examples as a method of setting a function to be restricted.

-First specific example-
FIG. 27 is a block circuit diagram showing a configuration and method for clock stop control in the first specific example of the present embodiment. As shown in the figure, the IP receives a register 131 corresponding to function information, an output of the register 131 and a clock, and outputs an AND operation result to each function A, function B, and function C. , 132b, 132c. In other words, a necessary function among the functions A, B, and C is set in the register 131 in advance, and the clock input to the unnecessary functions is stopped.

-Second specific example-
FIG. 28 is a block circuit diagram showing a configuration and method for function select control in the second specific example of the present embodiment. As shown in the figure, the IP is provided with a selector 133 for selecting one of function A, function B, and function C, and a register 134 corresponding to function information. That is, in this method, necessary functions among functions A, B, and C are set in the register 134 in advance, and output of unnecessary functions is stopped.

-Third example-
FIG. 29 is a block circuit diagram showing the configuration and method for power control in the third specific example of the present embodiment. As shown in the figure, the IP includes a register 135 corresponding to function information, and MOS transistors 136a and 136b that receive the output of the register 135 at the gate and output the power supply voltage VDD to the functions A, B, and C. , 136c. In other words, a necessary function among the functions A, B, and C is set in the register 135 in advance, and supply of power supply voltage to unnecessary functions is stopped.

-Fourth example-
FIG. 30 is a block circuit diagram showing a configuration and method for input fixing control in the fourth specific example of the present embodiment. As shown in the figure, the IP receives a register 137 corresponding to function information, an output of the register 137 and an input signal Sin, and outputs an AND operation result to each function A, function B, and function C. Circuits 138a, 138b, and 138c are provided. That is, in this method, a necessary function among the functions A, B, and C is set in the register 137 in advance, and the input of the input signal Sin to the unnecessary function is limited.

  Each of the above specific examples can also be applied to the first embodiment when a wiring structure is used instead of the register.

-Specific example of address reconstruction-
FIG. 31 is a block circuit diagram showing an example of a configuration and method for reconstructing register addresses applicable to the above specific examples. The IP receives an input address having a bit width from m to 0, and has an address decoder 141 for decoding a bit width from n (n <m) to 0, and a bit width from m to 0 The upper address setting register 142 that registers the bit width from m to n + 1 of the input address as the upper address, the upper address from m to n + 1 registered in the address setting register 142, and the m of the input address Are compared with the higher addresses from n + 1 to n + 1, and when both match, the comparator 143 outputs a match signal, and performs an AND operation on the match signal from the comparator 143 and the output of the address decoder 141 and outputs the result. AND circuit 145 is provided.

  That is, normally, each peripheral IP address is composed of bits from n to 0, but the address of the entire system starts from m (m> n). At that time, on the host side, upper addresses from m to n + 1 are set in a register for each peripheral IP and assigned. Access from the host side is performed by an input address having a bit width of m to 0. In the comparator 143, the upper address of the input addresses is compared with the upper address set in the address setting register 142. A match signal is output. On the other hand, the lower address of the input address is decoded through the address decoder 141. Then, by calculating an AND of the coincidence signal and the coincidence signal, it can be determined whether or not the register is set. In this way, you can automatically assign the address mapping yourself.

(A), (b), (c) is a plan view of a silicon wiring substrate serving as a wiring substrate for mounting an IP group, a plan view showing an example of an IP group mounted on the silicon wiring substrate, and silicon It is sectional drawing of a wiring board. 1 is a block diagram schematically showing the structure of a multifunction IP arranged in an IPOS device in the first embodiment. FIG. It is a block diagram which shows roughly the structure of the IPOS device for evaluation in the 1st specific example of 1st Embodiment. It is sectional drawing of the IPOS device for evaluation in the 1st specific example of 1st Embodiment. It is a block diagram for demonstrating the evaluation method of the general purpose IPOS device for evaluation in the 2nd specific example of 1st Embodiment. It is a block diagram for demonstrating the evaluation method of the general purpose IPOS device for evaluation in the 3rd specific example of 1st Embodiment. It is a block diagram which shows roughly the evaluation system by the remote control of the general purpose IPOS device for evaluation in the 4th specific example of 1st Embodiment. (A), (b) is the top view of IP in the 1st specific example of 2nd Embodiment, and the fragmentary sectional view of an IPOS device. (A), (b) is the top view of IP in the 2nd specific example of 2nd Embodiment, and the fragmentary sectional view of an IPOS device. (A), (b) is the top view of IP in the 3rd specific example of 2nd Embodiment, and the fragmentary sectional view of an IPOS device. (A), (b) is the top view of IP in the 4th specific example of 2nd Embodiment, and the fragmentary sectional view of an IPOS device. (A), (b) is the perspective view and block circuit diagram which show the structure of the IPOS device regarding the setting of the function in the 5th specific example of 2nd Embodiment. (A), (b) is a figure which shows the function selection method in the 6th specific example of 2nd Embodiment, and its modification. It is a block diagram which shows the basic composition of IP arrange | positioned at the IPOS device in 3rd Embodiment. It is a block diagram which shows roughly the structure of the IPOS device in the 1st specific example of 3rd Embodiment. It is a block diagram which shows roughly the structure of the IPOS device and one IP in the 2nd specific example of 3rd Embodiment. It is a block diagram which shows roughly the structure of the IPOS device in the 3rd specific example of 3rd Embodiment. It is a block diagram which shows roughly the structure of the IPOS device in the 4th specific example of 3rd Embodiment. It is a block diagram which shows roughly the structure of the IPOS device in the modification of the 4th specific example of 3rd Embodiment. It is a block diagram which shows roughly the most basic structure of the IPOS device of 4th Embodiment. It is a block diagram which shows the specific example of 4th Embodiment which concerns on the bus integrated system which has the structure of 1 host versus many peripheral circuits. It is a block diagram which shows roughly the structure of the IPOS device in 5th Embodiment. It is a block diagram which shows an example of the signal processing method between encryption IP and confidential IP in 5th Embodiment. It is a block circuit diagram which shows the structure of the IPOS device in the 1st specific example of 6th Embodiment. It is a block circuit diagram which shows the structure of the IPOS device in the 2nd specific example of 6th Embodiment. It is a block circuit diagram which shows the structure of the IPOS device in the 3rd specific example of 6th Embodiment. It is a block circuit diagram which shows the structure and method for clock stop control in the 1st specific example of 7th Embodiment. It is a block circuit diagram which shows the structure and the method for function selection control in the 2nd specific example of 7th Embodiment. It is a block circuit diagram which shows the structure and method for power supply control in the 3rd specific example of 7th Embodiment. It is a block circuit diagram which shows the structure and method for input fixing control in the 4th specific example of 7th Embodiment. It is a block circuit diagram which shows an example of the structure and method for reconstructing the address of the register applicable to each specific example of 7th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon wiring board 11 Silicon substrate 12 Ground plane 13 1st wiring layer 14 2nd wiring layer 15 Pad 21 IPOS device 22 User logic 23 IP for evaluation
24 IP for evaluation
25 Silicon Wiring Board 26 Normal Operation Wiring Layer 27 Evaluation Wiring Layer 30 IPOS Device 31 User Board 32 Emulator 33, 34 Evaluation System 35 Function Simulator 36, 37 Control System 39 Library 40 IP
41 Power supply wiring 42 Ground wiring 43 Silicon wiring board 45 IP
46 Selector 47 Silicon wiring board 48 Power line 49 Ground line 50 Contact 51 IP
52 Silicon wiring board 55, 56 IP
57 selector 58 power line 59 ground line 60 silicon wiring board 61 KeyIP
65 IP
67 Register 68 Emulator 69 Register for setting 70 IP
71 Function information storage unit 72 IPOS device 73 Display device 75, 76 IP
77 Function information storage unit 78 System control unit 100 IPOS device 101 Bus IP
102 Bus IP
103 Host IP
104 to 106 USB device function 110 IPOS device 111 Encrypted IP
112 Key Transmission / Reception Unit 113 Encoder 114 Decoder 115 Key Transmission / Reception Unit 116 Decoder 117 Encoder 118 Confidential Data Storage Unit 121 Function Recognition IP
122 ID information 124 ID information and recognition function 126 Recognition software IP
131 Register 132 AND circuit 133 Selector 134 Register 135 Register 136 MOS transistor 137 Register 138 AND circuit 141 Address decoder 142 Upper address setting register 143 Comparator 145 AND circuit

Claims (27)

A semiconductor wiring substrate having a wiring layer;
A chip IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions;
Provided in the chip IP, comprising functional information storage means for storing functional information related to the plurality of functions,
The function information storage means stores the function information by attaching an ID number to each function. A semiconductor wiring substrate having a wiring layer;
A chip IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions;
Provided in the chip IP, comprising functional information storage means for storing functional information related to the plurality of functions,
The semiconductor device is characterized in that the function information related to the plurality of functions is standardized so as to be displayed on the display means. A semiconductor wiring substrate having a wiring layer;
A chip IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions;
Provided in the chip IP, comprising functional information storage means for storing functional information related to the plurality of functions,
A semiconductor device, further comprising another chip IP configured to receive the function information of the chip IP and determine its function. A semiconductor wiring substrate having a wiring layer;
A chip IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions;
Provided in the chip IP, comprising functional information storage means for storing functional information related to the plurality of functions,
The chip IP is configured to output the function information stored in the function information storage means when receiving a key signal. A semiconductor wiring substrate having a wiring layer;
A chip IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions;
Function information storage means provided in the chip IP for storing function information relating to the plurality of functions;
A semiconductor device comprising: encryption means for encrypting the function information output from the function information storage means. The semiconductor device according to claim 5.
A semiconductor device, further comprising decryption means for decrypting and outputting the encrypted function information when receiving a key signal. A semiconductor wiring substrate having a wiring layer;
A plurality of chips IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions;
Provided in each of the chips IP, comprising function information storage means for storing function information relating to the plurality of functions,
The plurality of chips IP are configured to be able to access each other's function information storage means and read the function information, and each include a key signal transmission / reception unit that transmits / receives a key signal. The semiconductor device is configured to output the function information stored in the function information storage means when receiving the key signal in its own key signal transmission / reception unit. The semiconductor device according to claim 7.
The semiconductor device, wherein the plurality of chips IP are configured to transmit / receive function information after encoding the function information of the function information storage means into a code that can be mutually recognized. A semiconductor wiring substrate having a wiring layer;
A plurality of chips IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions;
Function information storage means provided in each of the chips IP, for storing function information relating to the plurality of functions by assigning an ID number to each of the plurality of functions;
A function recognition means for recognizing the function information based on the ID number;
The semiconductor device, wherein the plurality of chips IP are configured to be able to access each other's function information storage means and read the function information. The semiconductor device according to claim 9.
The semiconductor device according to claim 1, wherein the function recognition means is provided in a chip IP different from each of the chips IP. The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein the function recognition means is provided as stored contents of a memory. The semiconductor device according to claim 9.
The semiconductor device according to claim 1, wherein the function recognizing means is provided integrally with the function information storage means in each chip IP. The semiconductor device according to any one of claims 9 to 12,
Each of the function information storage means includes a first storage unit that stores lower n bits (n <m) of an m-bit address used in a semiconductor device, and (n + 1) or more upper bits of an m-bit address. A second storage unit that stores the ID number,
A semiconductor device, further comprising means for determining whether or not an upper bit of (n + 1) or more of an m-bit input address matches the ID number of the second storage unit. The semiconductor device according to claim 7.
The plurality of chips IP are configured to be capable of changing or setting their own functions based on the function information of the function information storage means in the other chips IP. The semiconductor device of claim 14, wherein
A semiconductor device, further comprising a control circuit that receives or stores information stored in the storage information storage means in each chip IP and changes or sets the function of each chip IP. Mounting a plurality of evaluation chips IP each having at least one function on a semiconductor wiring substrate having a wiring layer by bonding (a);
And (b) evaluating the at least one function of each evaluation chip IP by simulation. In the evaluation method of the semiconductor device according to claim 16,
The step (b) is performed by displaying an internal document storing the function of the chip IP on a display device. The semiconductor device evaluation method according to claim 16 or 17,
In the step (a), the wiring layer of the semiconductor wiring board is divided into a normal operation wiring layer and an evaluation wiring layer above the normal operation wiring layer.
A method of evaluating a semiconductor device, further comprising the step of removing the evaluation wiring layer of the semiconductor wiring substrate and leaving the normal operation wiring layer after the step (b). A semiconductor device evaluation method comprising a semiconductor wiring substrate having a wiring layer and a plurality of chips IP mounted on the semiconductor wiring substrate by bonding,
A method for evaluating a semiconductor device, comprising performing a connection test by exchanging information on corresponding terminals of the plurality of chips IP. A semiconductor device function setting method comprising: a semiconductor wiring substrate having a wiring layer; and a chip IP mounted on the semiconductor wiring substrate by bonding and having a plurality of functions,
A function setting method for a semiconductor device, wherein setting is performed so that only some of the plurality of functions are activated. The function setting method for a semiconductor device according to claim 20,
A function setting method for a semiconductor device, wherein only a part of the functions is activated by fixing a wiring relation of the wiring layer. The function setting method for a semiconductor device according to claim 21,
A function setting method for a semiconductor device, wherein only a part of the functions is activated by fixing logic inputs supplied to the plurality of functions. The function setting method for a semiconductor device according to claim 20,
A function setting method for a semiconductor device, wherein only the part of the functions is activated by making it possible to extract only the part of the functions. A function setting method for a semiconductor device according to claim 20,
A function setting method for a semiconductor device, wherein only a part of the functions is activated by remote operation via a network. The function setting method for a semiconductor device according to claim 20,
A function setting method for a semiconductor device, wherein only a part of the function is activated by inputting a clock signal to only the part of the function. The function setting method for a semiconductor device according to claim 20,
A function setting method for a semiconductor device, wherein only the part of the function is activated by supplying a power supply voltage to only the part of the function. The function setting method for a semiconductor device according to claim 20,
A function setting method for a semiconductor device, wherein only the part of the function is activated by supplying an input signal to only the part of the function.

Images