JP2006325289A - Step-down switching regulator, its control circuit, and electronic apparatus employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a step-down switching regulator in which conversion efficiency is improved under a light load. <P>SOLUTION: The control circuit 100 of a step-down switching regulator applies a switching voltage Vsw to an inductor L1. A driver circuit 10 creates first and second gate voltages Vg1 and Vg2 which are applied to the gate terminal of each transistor based on a PWM signal Vpwm. A comparing section 30 outputs a high level comparison signal Vcmp when Vsw>0 V. During a period where a transistor M2 for synchronous rectification must be turned on, a latch circuit 40 latches the comparison signal Vcmp and outputs it as a detection signal Vsens. During a period where the detection signal Vsens is latched to high level, a forced off switch SW1 fixes the gate voltage of the transistor M2 for synchronous rectification to 0 V. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a step-down switching regulator, and more particularly to a control technology for a synchronous rectification switching regulator.

Various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook personal computers in recent years are equipped with microcomputers that perform digital signal processing. The power supply voltage required for driving such a microcomputer has been reduced with the miniaturization of the semiconductor manufacturing process, and there is one that operates at a low voltage of 1.5 V or less.
On the other hand, a battery such as a lithium ion battery is mounted on such an electronic device as a power source. The voltage output from the lithium ion battery is about 3V to 4V. If this voltage is supplied to the microcomputer as it is, useless power consumption occurs. Therefore, a step-down switching regulator or a series regulator is used. In general, the battery voltage is stepped down to a constant voltage and supplied to a microcomputer.

  As a step-down switching regulator, there are a method using a rectifying diode (hereinafter referred to as a diode rectifying method) and a method using a rectifying transistor instead of a diode (hereinafter referred to as a synchronous rectifying method). In the former case, there is an advantage that high efficiency can be obtained when the load current flowing through the load is low. However, since a diode in addition to the inductor and the capacitor is required outside the control circuit, the circuit area becomes large. In the latter case, the efficiency when the current supplied to the load is small is inferior to that of the former, but since a transistor is used instead of a diode, it can be integrated inside the LSI, and the circuit area including peripheral components As a result, downsizing is possible. When an electronic device such as a cellular phone is required to be downsized, a switching regulator using a rectifying transistor (hereinafter referred to as a synchronous rectification switching regulator) is often used.

Here, the current consumption of the microcomputer used in the above-described electronic device varies greatly between operation and standby, and only a small amount of current flows during standby, but a certain amount of current is required during operation.
For example, Patent Documents 1 and 2 disclose switching regulators that switch between a synchronous rectification method and a diode rectification method according to a load current.

JP 2004-32875 A JP 2002-252971 A

  FIGS. 9A and 9B are diagrams showing current time waveforms of heavy and light loads of the synchronous rectification switching regulator, respectively. In the figure, IL represents the current flowing through the inductor, Io represents the load current, and the time average value of the current IL flowing through the inductor is the load current Io. As shown in FIG. 9A, during heavy load, the load current Io is large, so the current IL flowing through the inductor continues to take a positive value. However, as shown in FIG. 9B, when the load current Io decreases at the time of light load, the current IL flowing through the inductor becomes negative as indicated by the shaded portion, and the direction of the current IL flowing through the inductor is reversed. As a result, in the synchronous rectification method, a current flows from the inductor to the ground through the synchronous rectification transistor at light load. Since this current is not supplied to the load but supplied from the output capacitor, power is wasted.

  The present invention has been made in view of such a problem, and the object thereof is to reduce the current flowing to the ground via the synchronous rectification transistor in a synchronous rectification step-down switching regulator and improve the efficiency. The present invention provides a step-down switching regulator and a driving circuit thereof.

  One embodiment of the present invention relates to a control circuit for a step-down switching regulator. This control circuit includes a switching transistor and a synchronous rectification transistor connected in series between the input terminal and the ground, and the voltage of the connection point of the two transistors is used as the switching voltage of the inductor connected to the outside of the control circuit. Based on the output stage applied to one end and the pulse width modulation signal whose duty ratio is controlled so that the output voltage of the switching regulator approaches a predetermined reference voltage, the first to be applied to the gate terminals of the switching transistor and the synchronous rectification transistor A driver circuit that generates a second gate voltage, a comparison unit that compares the switching voltage with a predetermined threshold voltage, and outputs a comparison signal of a predetermined level when the switching voltage exceeds the threshold voltage, and synchronous rectification The comparison signal output from the comparison unit during the period when the Is latched and output as a detection signal, and the second gate voltage output from the driver circuit is input, and the second gate voltage is fixed to a low level while the detection signal is latched at a predetermined level. And a switch for outputting to the gate terminal of the synchronous rectification transistor.

  According to this aspect, when the switching voltage becomes a positive voltage during the period in which the synchronous rectification transistor is to be turned on, the synchronous rectification transistor is forcibly turned off regardless of the second gate voltage, and the direction of the current flowing through the inductor Can be prevented and the efficiency can be prevented from deteriorating. At this time, even if the switching voltage swings across 0V after the synchronous rectification transistor is forcibly turned off by latching the comparison signal output from the comparison unit by the latch circuit, the synchronous rectification transistor Can be kept in an OFF state, and the step-down switching regulator can be stably operated.

The latch circuit may become active while the second gate voltage output from the driver circuit is at a high level, and may latch the comparison signal output from the comparison unit.
By referring to the second gate voltage output from the driver circuit, it is possible to determine the period during which the synchronous rectification transistor is to be turned on, and to suitably latch the comparison signal output from the comparison unit.

The latch circuit may reset the latched detection signal when the second gate voltage changes from a high level to a low level.
By referring to the second gate voltage and resetting the detection signal when the period for turning on the synchronous rectification transistor is completed, the above-described latch operation is performed again in the next period for turning on the synchronous rectification transistor. It can be performed.

  The latch circuit includes a D flip-flop. The D flip-flop has a second gate voltage input to the reset terminal, a high-level fixed voltage input to the data terminal, and a comparison signal output from the comparison unit to the clock terminal. May be input.

The latch circuit may further include an OR gate that outputs a logical sum of the output signal of the D flip-flop and the comparison signal output from the comparison unit, and may output the output signal of the OR gate as a detection signal.
According to this, even if the comparison signal output from the comparison unit fluctuates once the D flip-flop is latched, the output of the OR gate is fixed to the output signal of the D flip-flop. It can be performed.

  The threshold voltage may be a ground potential.

The comparison unit includes a level shift circuit that level-shifts the switching voltage and the threshold voltage by a predetermined voltage in the positive direction, and a comparator that compares the switching voltage level-shifted by the level shift circuit with the threshold voltage. The output signal of the comparator may be output as a comparison signal.
By providing a level shift circuit in front of the comparator, voltage comparison with a low voltage such as a ground potential can be performed normally.

The comparator includes a delay circuit that receives a second gate voltage, outputs a mask signal that becomes a high level after a lapse of a predetermined delay time after the second gate voltage changes from a low level to a high level, and a delay circuit You may further include the mask signal output and the AND gate which outputs the logical sum of the output signal of a comparator. The output signal of the AND gate may be output as a comparison signal.
When the second gate voltage changes from the low level to the high level and the synchronous rectification transistor is switched to the on state, the switching voltage may swing in the positive direction. In such a case, it is possible to prevent the synchronous rectification transistor from being turned off by the swinging switching voltage by previously excluding the period during which the switching voltage swings by the mask signal from the comparison period by the comparison unit.

In the level shift circuit, a switching voltage is input to a base terminal, a collector terminal is grounded, a PNP-type first bipolar transistor that outputs a voltage obtained by level shifting the switching voltage from an emitter terminal, and a base terminal and a collector terminal are grounded. The PNP type second bipolar transistor that outputs a voltage obtained by level shifting the ground potential from the emitter terminal and the emitter terminal of the first and second bipolar transistors are connected, and the mask signal output from the delay circuit is low level. And a switch that is turned on for a period of time.
By short-circuiting the emitter terminals of the first and second bipolar transistors during the period when the mask signal is at a low level, the fluctuation of the switching voltage generated when the synchronous rectification transistor is switched from OFF to ON is caused. It is possible to prevent the input voltage from fluctuating.

  The synchronous rectification transistor may be an NMOS transistor. The control circuit may be integrated on a single semiconductor substrate.

  Another aspect of the present invention is a step-down switching regulator. This step-down switching regulator includes a capacitor having one end grounded, an inductor having one end connected to the other end of the capacitor, and the above-described control circuit that supplies a switching voltage to the other end of the inductor. The voltage at the other end is output.

  According to this aspect, the control circuit can preferably prevent the direction of the current flowing through the inductor from being reversed, and the efficiency of the step-down switching regulator can be improved.

  Yet another embodiment of the present invention is an electronic device. This electronic device includes a battery that outputs a battery voltage, a microcomputer, and the above-described step-down switching regulator that steps down the battery voltage and supplies the voltage to the microcomputer.

  According to this aspect, even when the current flowing through the microcomputer fluctuates and the load current is small and the load operation is small, the step-down operation can be performed efficiently, and the battery life can be extended.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the step-down switching regulator according to the present invention, the conversion efficiency can be improved.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of an electronic device equipped with the step-down switching regulator according to the first embodiment. The electronic device 300 is, for example, a mobile phone terminal, and includes a battery 310, a power supply device 320, an analog circuit 330, a digital circuit 340, a microcomputer 350, and an LED 360.
The battery 310 is a lithium ion battery, for example, and outputs about 3 to 4 V as the battery voltage Vbat.
The analog circuit 330 includes high-frequency circuits such as a power amplifier, an antenna switch, an LNA (Low Noise Amplifier), a mixer, and a PLL (Phase Locked Loop), and includes a circuit block that stably operates at a power supply voltage Vcc = 3.4V. . The digital circuit 340 includes various DSPs (Digital Signal Processors) and the like, and includes a circuit block that stably operates at a power supply voltage Vdd = 3.4V.
The microcomputer 350 is a block that comprehensively controls the entire electronic device 300 and operates with a power supply voltage of 1.5V.
The LED 360 includes RGB three-color LEDs (Light Emitting Diodes) and is used as a liquid crystal backlight or illumination, and a driving voltage of 4 V or more is required for driving.

The power supply device 320 is a multi-channel switching power supply, and includes a switching regulator for stepping down or stepping up the battery voltage Vbat as necessary for each channel. For the analog circuit 330, the digital circuit 340, the microcomputer 350, and the LED 360, Supply an appropriate power supply voltage.
The step-down switching regulator according to the present embodiment is suitably used for driving a stable voltage with respect to a load whose current consumption changes according to an operating state, such as a microcomputer 350 that operates at 1.5 V. It is done. Hereinafter, the configuration of the step-down switching regulator according to the present embodiment will be described in detail.

FIG. 2 is a circuit diagram showing a configuration of the step-down switching regulator 200 according to the first embodiment. The step-down switching regulator 200 is a synchronous rectification step-down switching regulator, and includes a control circuit 100, an inductor L1, and an output capacitor C1. The control circuit 100 is an LSI chip integrated on a single semiconductor substrate, and a switching transistor M1 functioning as a switching element and a synchronous rectification transistor M2 are incorporated in the control circuit 100.
The output capacitor C1 has one end grounded and the other end connected to the load circuit RL and the inductor L1. The inductor L1 is connected to the control circuit 100 and applied with the switching voltage Vsw.

The step-down switching regulator 200 controls the current flowing through the inductor L1 by the control circuit 100, steps down the battery voltage Vbat by charging the output capacitor C1, and supplies the voltage appearing at the output capacitor C1 to the load circuit RL. To do. In this embodiment, the load circuit RL corresponds to the microcomputer 350 in FIG.
Hereinafter, a voltage supplied to the load circuit RL is referred to as an output voltage Vout, a current flowing through the load circuit RL is referred to as a load current Io, and a current flowing through the inductor L1 is referred to as IL. Hereinafter, the direction in which the current IL flowing through the inductor L1 flows toward the load circuit RL is a positive direction.

  The control circuit 100 includes an input terminal 102, a switching terminal 104, and an output terminal 106 as input / output terminals. A battery 310 is connected to the input terminal 102, and a battery voltage Vbat is input as an input voltage. The switching terminal 104 is connected to the inductor L1 and outputs a switching voltage Vsw generated inside the control circuit 100. The output terminal 106 is a terminal to which the output voltage Vout applied to the load circuit RL is fed back.

  The control circuit 100 includes a driver circuit 10, a PWM control unit 20, a comparison unit 30, a latch circuit 40, a forced off switch SW1, a switching transistor M1, and a synchronous rectification transistor M2.

The switching transistor M1 is a P-channel MOS transistor, and has a source terminal connected to the input terminal 102 and a drain terminal connected to the switching terminal 104. The back gate terminal of the switching transistor M1 is connected to the input terminal 102, and a body diode (parasitic diode) D1 exists between the back gate terminal and the drain terminal.
The synchronous rectification transistor M2 is an N-channel MOS transistor, the source terminal is grounded, and the drain terminal is connected to the drain terminal of the switching transistor M1 and the switching terminal 104. The back gate terminal of the synchronous rectification transistor M2 is grounded. A body diode D2 exists between the back gate terminal and the drain terminal of the synchronous rectification transistor M2.

  The switching transistor M1 and the synchronous rectification transistor M2 are connected in series between the input terminal 102 to which the battery voltage Vbat is applied and the ground, and the control circuit 100 uses the voltage at the connection point of the two transistors as the switching voltage Vsw. Is applied to one end of an inductor L1 connected to the outside via a switching terminal 104.

The PWM control unit 20 controls a pulse width modulation signal (hereinafter referred to as “duty ratio”) that defines the duty ratio of the ON period of the switching transistor M1 and the synchronous rectification transistor M2 so that the output voltage Vout of the step-down switching regulator 200 approaches a predetermined reference voltage. A PWM signal). The output voltage Vout of the step-down switching regulator 200 is input to the PWM control unit 20 via the output terminal 106.
The resistors R1 and R2 divide the output voltage Vout, and output the output voltage Vout ′ multiplied by R2 / (R1 + R2) to the inverting input terminal of the error amplifier 22. The reference voltage Vref is input to the non-inverting input terminal of the error amplifier 22, and an error between the output voltage Vout ′ and the reference voltage Vref is amplified and output as an error voltage Verr.

  The oscillator 26 oscillates at a predetermined frequency and outputs a periodic voltage Vosc having a triangular wave shape or a sawtooth wave shape. The first comparator 24 compares the periodic voltage Vosc and the error voltage Verr, and outputs a PWM signal Vpwm that is at a high level when Vosc> Verr and at a low level when Vosc <Verr. This PWM signal Vpwm is a pulse width modulated signal having a constant cycle time and a period of high level and low level changing according to the output voltage Vout ′.

Based on the PWM signal Vpwm output from the PWM controller 20, the driver circuit 10 applies a first gate voltage Vg1 to be applied to the gate terminal of the switching transistor M1 and a second terminal to be applied to the gate terminal of the synchronous rectification transistor M2. A gate voltage Vg2 is generated. The switching transistor M1 is turned on when the first gate voltage Vg1 is at a low level and turned off when the first gate voltage Vg1 is at a high level. The synchronous rectification transistor M2 is turned on when the second gate voltage Vg2 is at a high level, and turned off when the second gate voltage Vg2 is at a low level.
The driver circuit 10 sets the ratio of the time during which the switching transistor M1 and the synchronous rectification transistor M2 are turned on based on the high-level and low-level duty ratios of the PWM signal Vpwm, and turns the two transistors on and off alternately. In order to prevent the switching transistor M1 and the synchronous rectification transistor M2 from being simultaneously turned on and a through current from flowing therethrough, the driver circuit 10 has a period in which the first gate voltage Vg1 is at a high level and the second gate voltage Vg2 is at a low level Dead time) is provided for each period.

The comparison unit 30 receives the switching voltage Vsw. The comparison unit 30 compares the switching voltage Vsw and the ground potential, and outputs a high-level comparison signal Vcmp when the switching voltage Vsw exceeds the ground potential (0 V). The comparison unit 30 includes a level shift circuit 32 and a second comparator 34.
The level shift circuit 32 includes PNP-type first and second bipolar transistors Q1 and Q2, and a switching voltage Vsw and a ground potential are input to respective base terminals. The collector terminals of the bipolar transistors Q1 and Q2 are grounded, and the emitter terminal outputs a voltage in which the switching voltage Vsw and the ground potential are level-shifted in the forward direction by a forward voltage Vf = 0.7V. .
The non-inverting input terminal of the second comparator 34 is connected to the emitter terminal of the first bipolar transistor Q1, and the inverting input terminal is connected to the emitter terminal of the second bipolar transistor Q2. The switching voltage Vsw level-shifted by the second comparator 34 and the level shift circuit 32 is compared with the ground potential (0V), and a high level is output when Vsw> 0V and a low level is output when Vsw <0V.

  The latch circuit 40 receives the second gate voltage Vg2 output from the driver circuit 10 and the comparison signal Vcmp output from the comparison unit 30. The latch circuit 40 is active during a period in which the synchronous rectification transistor M2 is to be turned on, that is, a period during which the second gate voltage Vg2 output from the driver circuit 10 is at a high level, and the comparison signal Vcmp output from the comparison unit 30. Are latched, and the latched signal is output as the detection signal Vsens. The latch circuit 40 resets the latched detection result when the second gate voltage Vg2 changes from the high level to the low level.

  The latch circuit 40 includes a D flip-flop 42, an OR gate 44, a NOR gate 46, and an inverter 48. The power supply voltage Vdd corresponding to the high level is input to the set terminal and the data terminal of the D flip-flop 42, and the reset terminal is connected to the output of the NOR gate 46. The NOR gate 46 receives the second gate voltage Vg2 inverted by the inverter 48 and the enable signal EN given from the outside, and outputs the negative logical sum of the two signals to the reset terminal of the D flip-flop 42. The enable signal EN is a signal that controls the step-down operation of the step-down switching regulator 200, and the step-down switching regulator 200 performs the step-down operation when the enable signal EN is at a low level and stops the step-down operation when the enable signal EN is at a high level. Low.

The comparison signal Vcmp output from the comparison unit 30 is input to the clock terminal of the latch circuit 40. The latch circuit 40 outputs a high level output signal Vq from the output terminal when the comparison signal Vcmp becomes high level during the period when the second gate voltage Vg2 is high level.
The OR gate 44 receives the comparison signal Vcmp output from the latch circuit 40 and the output signal Vq of the D flip-flop 42, and outputs the logical sum of the two signals to the forced-off switch SW1 as the detection signal Vsens. Note that the output signal Vq of the D flip-flop 42 may be directly output to the forced-off switch SW1 without providing the OR gate 44.

  The forced off switch SW1 is provided between the driver circuit 10 and the gate terminal of the synchronous rectification transistor M2, and based on the detection signal Vsens output from the latch circuit 40, the forced rectification switch SW1 has a second gate connected to the gate terminal of the synchronous rectification transistor M2. Either voltage Vg2 or low level is output. The forced-off switch SW1 outputs a low level to the gate terminal of the synchronous rectification transistor M2 while the detection signal Vsens output from the latch circuit 40 is latched at a high level.

FIG. 3 is a circuit diagram showing a configuration example of the forced-off switch SW1. The forced off switch SW1 includes an inverter 50 and a NOR gate 52. The second gate voltage Vg2 output from the driver circuit 10 is input to the input terminal of the inverter 50. The inverter 50 inverts the second gate voltage Vg <b> 2 and outputs it to the first input terminal of the NOR gate 52. The detection signal Vsens output from the latch circuit 40 is input to the second input terminal of the NOR gate 52. The forced off switch SW1 outputs the output signal of the NOR gate 52 as the second gate voltage Vg2 ′.
According to the forced-off switch SW1 configured in this way, the second gate voltage Vg2 is actually applied to the gate terminal of the synchronous rectification transistor M2 only when the second gate voltage Vg2 is high level and the detection signal Vsens is low level. The two-gate voltage Vg2 ′ becomes a high level, and the synchronous rectification transistor M2 is turned on. On the other hand, in other periods, the second gate voltage Vg2 ′ is at a low level, and the synchronous rectification transistor M2 is turned off.

Hereinafter, the operation of the control circuit 100 according to the present embodiment will be described with reference to FIG. FIG. 4 is a time chart showing an operation state of the control circuit 100 according to the present embodiment. The time chart of FIG. 4 explains the operation at a light load when the load current Io is small, and shows the operation when the current IL flowing through the inductor L1 through the synchronous rectification transistor M2 becomes 0A at a certain time. ing. At this time, the enable signal EN is fixed at a low level.
When the first gate voltage Vg1 is at a high level, the switching transistor M1 is turned off, and when the first gate voltage Vg1 is at a low level, the switching transistor M1 is turned on. That is, in the figure, Ton1 indicates a period during which the switching transistor M1 is on.

The second gate voltage Vg <b> 2 indicates a voltage to be applied to the synchronous rectification transistor M <b> 2 generated by the driver circuit 10. In the drawing, the second gate voltage Vg2 ′ indicates the voltage actually applied to the gate terminal of the synchronous rectification transistor M2. When the second gate voltage Vg2 ′ is at a high level, the synchronous rectification transistor M2 is turned on, and when the second gate voltage Vg2 ′ is at a low level, the synchronous rectification transistor M2 is turned off. In the figure, Ton2 indicates a period during which the synchronous rectification transistor M2 is on.
As described above, the forced off switch SW1 is provided between the driver circuit 10 and the synchronous rectification transistor M2, and Vg2 ′ = Vg2 while the detection signal Vsens output from the latch circuit 40 is at a low level. It becomes. Further, during the period in which the detection signal Vsens is at a high level, the gate voltage Vg2 ′ of the synchronous rectification transistor M2 is at a low level (0 V) regardless of the value of the gate voltage Vg2 output from the driver circuit 10, and the synchronous rectification transistor M2 Is forcibly turned off.

  During the period of time T0 to T1, the switching transistor M1 is on and the synchronous rectification transistor M2 is off. At time T1, the first gate voltage Vg1 of the switching transistor M1 becomes high level, and the switching transistor M1 is turned off. Thereafter, both the switching transistor M1 and the synchronous rectification transistor M2 are turned off during the period of time T1 to T2. When the switching transistor M1 is turned off at time T1, the current that has been flowing through the inductor L1 until then is not supplied from the switching transistor M1.

  Here, since the current IL flowing through the inductor L1 must be continuous, this current is supplied via the body diode (parasitic diode) of the synchronous rectification transistor M2. That is, the back gate terminal of the synchronous rectification transistor M2 is grounded, and the body diode D2 shown in FIG. 2 exists between the back gate terminal and the drain terminal. Therefore, a current is supplied to the inductor L1 through the body diode D2 from the time when the switching transistor M1 is turned off at time T1 to the time when the synchronous rectification transistor M2 is turned on at time T2. During this time, a switching voltage Vsw that is lower than the ground potential 0 V by the diode forward voltage Vf = 0.7 V appears at the switching terminal 104.

At time T2, the second gate voltage Vg2 changes from the low level to the high level. At this time, since the detection voltage Vsens is at a low level, the second gate voltage Vg2 ′ that is the output of the forced-off switch SW1 is at a high level, and the synchronous rectification transistor M2 is turned on. When the synchronous rectification transistor M2 is turned on, the current flowing through the inductor L1 via the body diode D2 of the synchronous rectification transistor M2 is supplied as the drain current of the synchronous rectification transistor M2.
As the drain current of the synchronous rectification transistor M2 flows to the output capacitor C1 through the inductor L1, the output voltage Vout of the output capacitor C1 gradually increases. As a result, the current flowing through the inductor L1 from the synchronous rectification transistor M2 toward the output capacitor C1 gradually decreases. When the decrease in the current IL flowing through the inductor L1 through the synchronous rectification transistor M2 decreases with time, the drain-source voltage of the synchronous rectification transistor M2 gradually decreases, so the switching voltage Vsw gradually increases, It approaches the ground potential of 0V.

  When the current IL flowing through the inductor L1 becomes 0A at time T3, the drain-source voltage of the synchronous rectification transistor M2 becomes 0V, so that the switching voltage Vsw becomes 0V. At this time, the comparison signal Vcmp output from the comparison unit 30 is switched from the low level to the high level. When the comparison signal Vcmp becomes high level, the detection signal Vsens output from the latch circuit 40 also becomes high level. As a result, the gate voltage Vg2 'of the synchronous rectification transistor M2 is fixed to 0 V by the forced-off switch SW1, and the synchronous rectification transistor M2 is turned off.

  When the high level comparison signal Vcmp is input to the clock terminal of the D flip-flop 42, the output signal Vq of the D flip-flop 42 becomes high level. Since the high level is input to the data terminal of the D flip-flop 42, the output signal Vq of the D flip-flop 42 is kept at the high level until the next reset. Thus, the latch circuit 40 including the D flip-flop 42 latches the comparison signal Vcmp output from the comparison unit 30.

When the second gate voltage Vg2 ′ becomes a low level at time T3, both the switching transistor M1 and the synchronous rectification transistor M2 are turned off to enter a high impedance state. At this time, voltage oscillation is induced by the inductor L1, and the switching voltage Vsw swings greatly as shown in FIG. At this time, if the switching voltage Vsw fluctuates across the ground potential 0V, the comparison signal Vcmp also switches between the high level and the low level.
Here, as described above, in the control circuit 100 according to the present embodiment, the forced-off switch SW1 is controlled based on the logical sum of the output signals of the comparison unit 30 and the D flip-flop 42. Therefore, even if the signal level of the comparison signal Vcmp fluctuates, the output signal Vq of the D flip-flop 42 is latched at a high level, so the output of the OR gate 44, that is, the detection signal Vsens remains at a high level. As a result, the synchronous rectification transistor M2 can be kept off regardless of the change in the switching voltage Vsw.

  At time T4, the driver circuit 10 switches the second gate voltage Vg2 to a low level. When the second gate voltage Vg2 becomes low level, the output of the NOR gate 46 is switched from high level to low level, the D flip-flop 42 is reset, and the output signal Vq becomes low level. Thereafter, at time T5, the first gate voltage Vg1 becomes low level, and the switching transistor M1 is turned on.

The control circuit 100 according to the present embodiment repeats this operation with time T0 to T5 as one cycle, thereby stepping down the battery voltage Vbat and supplying the desired output voltage Vout to the load circuit RL.
According to the control circuit 100 according to the present embodiment, the switching voltage Vsw is monitored, and when the switching voltage Vsw becomes larger than 0V during the period in which the synchronous rectification transistor M2 is to be turned on, the synchronous rectification transistor M2 is forcibly set. Turn off. As a result, the direction of the current IL flowing through the inductor L1 at the time of a light load is reversed, and the current IL can be prevented from flowing toward the ground via the synchronous rectification transistor M2, and deterioration in efficiency can be suppressed.

  Further, the control circuit 100 includes a latch circuit 40, and latches the comparison signal Vcmp that becomes high level when the switching voltage Vsw becomes higher than 0V. As a result, even when the switching voltage Vsw fluctuates over 0 V, the output of the forced off switch SW1 is not switched, and the synchronous rectification transistor M2 can continue to be kept off and perform a stable step-down operation. Can do.

(Second Embodiment)
FIG. 5 is a circuit diagram showing configurations of the comparison unit 30a and the latch circuit 40 of the control circuit 100 according to the second embodiment. In the subsequent drawings, the same or equivalent components as those of the control circuit 100 according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
The comparison unit 30a according to the present embodiment further includes an AND gate 36 and a delay circuit 38 in addition to the comparison unit 30 of FIG.

The second gate voltage Vg2 output from the driver circuit 10 is input to the delay circuit 38. The delay circuit 38 generates and outputs a mask signal Vmsk that switches from a low level to a high level after a lapse of a predetermined delay time τ from the time when the second gate voltage Vg2 switches from a low level to a high level. The delay circuit 38 sets the mask signal Vmsk to a low level when the second gate voltage Vg2 is switched from a high level to a low level.
The comparison signal Vcmp output from the second comparator 34 is input to the first input terminal of the AND gate 36. The mask signal Vmsk output from the delay circuit 38 is input to the second input terminal of the AND gate 36. The AND gate 36 outputs the logical product of the comparison signal Vcmp and the mask signal Vmsk as the second comparison signal Vcmp ′.

  FIG. 6 is a time chart showing an operation state of the control circuit 100 according to the second embodiment. When the second gate voltage Vg2 changes from the low level to the high level at the time T2, the synchronous rectification transistor M2 is suddenly turned on, so that the switching voltage Vsw may greatly fluctuate from −Vf in the positive direction as shown in FIG. is there. At this time, the comparison signal Vcmp output from the second comparator 34 once becomes a high level. At this time, since the mask signal Vmsk is at a low level, the detection signal Vsens is at a low level.

The mask signal Vmsk becomes high level at time T3 after the elapse of a predetermined delay time τ from time T2. When the comparison signal Vcmp becomes high level again at time T4 after the mask signal Vmsk becomes high level, the second comparison signal Vcmp ′ and the output signal Vq of the D flip-flop 42 become high level and are output from the OR gate 44. The detected signal Vsens becomes a high level. As a result, the second gate voltage Vg2 ′ becomes a low level, and the synchronous rectification transistor M2 is turned off.
At time T5, the second gate voltage Vg2 becomes low level, and at time T6, the first gate voltage Vg1 becomes low level, and the switching transistor M1 is turned on.

The control circuit 100 according to the present embodiment repeats this operation with time T0 to T6 as one cycle, thereby stepping down the battery voltage Vbat and supplying the desired output voltage Vout to the load circuit RL.
At this time, by eliminating the swing of the switching voltage Vsw generated at the moment when the synchronous rectification transistor M2 is switched from OFF to ON using the mask signal Vmsk, the current IL flowing through the inductor L1 is synchronously rectified during the positive period. The transistor M2 can be prevented from being turned off, and a stable step-down operation can be performed.

  FIG. 7 is a circuit diagram showing a modification of the control circuit 100 of FIG. The comparison unit 30b in FIG. 7 includes a switch SW2 between the inverting input terminal and the non-inverting input terminal of the second comparator 34, that is, between the emitter terminals of the first and second bipolar transistors Q1 and Q2. The switch SW2 is turned on / off by a mask signal Vmsk output from the delay circuit 38, and is turned on when the mask signal Vmsk is at a low level and turned off when the mask signal Vmsk is at a high level.

  FIG. 8 is a time chart showing an operation state of the control circuit 100 of FIG. As shown in FIG. 8, at time T2 when the synchronous rectification transistor M2 is switched from OFF to ON, the mask signal Vmsk is at a low level. At this time, since the switch SW2 provided at the input of the second comparator 34 is turned on, the emitter voltages of the first and second bipolar transistors Q1 and Q2 of the level shift circuit 32, that is, the input voltage of the second comparator 34 are equal. .

  Thereafter, when the mask signal Vmsk becomes a high level at time T3 after the delay time τ elapses, the switch SW2 is turned off, and the switching voltage Vsw is released from the fixed state to the ground potential 0V. Thereafter, the comparison unit 30b starts comparing the switching voltage Vsw with the ground potential.

  According to the control circuit 100 using the comparison unit 30b and the latch circuit 40 of the control circuit 100 of FIG. 7, the swing of the switching voltage Vsw generated when the synchronous rectification transistor M2 is switched from off to on is the second comparator 34. Since it is possible to suppress an adverse effect on the result of voltage detection by the above, a more stable step-down operation can be realized.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the microcomputer is described as an example of the load circuit driven by the step-down switching regulator 200 including the control circuit 100. However, the present invention is not limited to this, and the load circuit is reduced, and various operations can be performed in a light load state. A driving voltage can be supplied to a simple load circuit.

  In the embodiment, the case where the control circuit 100 is integrated in one LSI has been described. However, the present invention is not limited to this, and some components are provided as discrete elements or chip components outside the LSI. Or you may comprise by several LSI.

  Further, in the present embodiment, the setting of high level and low level logical values is merely an example, and can be freely changed by appropriately inverting it with an inverter or the like.

It is a block diagram which shows the structure of the electronic device carrying the pressure | voltage fall type switching regulator which concerns on 1st Embodiment. 1 is a circuit diagram showing a configuration of a step-down switching regulator according to a first embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a forced-off switch in FIG. 2. It is a time chart which shows the operation state of the control circuit which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the comparison part and latch circuit of the control circuit which concern on 2nd Embodiment. It is a time chart which shows the operation state of the control circuit which concerns on 2nd Embodiment. FIG. 6 is a circuit diagram showing a modification of the control circuit of FIG. 5. It is a time chart which shows the operation state of the control circuit of FIG. FIGS. 9A and 9B are diagrams showing time waveforms of current at the time of heavy load and light load of the synchronous rectification switching regulator.

Explanation of symbols

  100 control circuit, 102 input terminal, 104 switching terminal, 200 step-down switching regulator, 10 driver circuit, 20 PWM control unit, 30 comparison unit, 32 level shift circuit, 36 AND gate, 38 delay circuit, 40 latch circuit, 42 D Flip-flop, 44 OR gate, L1 inductor, C1 output capacitor, Vg1 first gate voltage, Vg2 second gate voltage, M1 switching transistor, M2 transistor for synchronous rectification, 300 electronic device, 310 battery, 350 microcomputer.

Claims (13)

A step-down switching regulator control circuit,
An output that includes a switching transistor and a synchronous rectifying transistor connected in series between the input terminal and the ground, and applies the voltage at the connection point of the two transistors to one end of the inductor connected to the outside of the control circuit as a switching voltage. Step and
First and second gate voltages to be applied to gate terminals of the switching transistor and the synchronous rectification transistor based on a pulse width modulation signal whose duty ratio is controlled so that the output voltage of the switching regulator approaches a predetermined reference voltage A driver circuit for generating
A comparator that compares the switching voltage with a predetermined threshold voltage, and outputs a comparison signal of a predetermined level when the switching voltage exceeds the threshold voltage;
A latch circuit that latches a comparison signal output from the comparison unit and outputs a detection signal in a period in which the synchronous rectification transistor is to be turned on;
While the second gate voltage output from the driver circuit is input and the detection signal is latched at the predetermined level, the second gate voltage is fixed at a low level and the gate terminal of the synchronous rectification transistor A switch that outputs to
A control circuit comprising:   2. The control circuit according to claim 1, wherein the latch circuit is active during a period in which the second gate voltage output from the driver circuit is at a high level, and latches the comparison signal output from the comparison unit. .   3. The control circuit according to claim 2, wherein the latch circuit resets the latched detection signal when the second gate voltage is changed from a high level to a low level.   The latch circuit includes a D flip-flop. The D flip-flop receives the second gate voltage as a reset terminal, receives a high-level fixed voltage as a data terminal, and outputs it from the comparator as a clock terminal. 4. The control circuit according to claim 3, wherein a comparison signal is input.   The latch circuit further includes an OR gate that outputs a logical sum of the output signal of the D flip-flop and the comparison signal output from the comparison unit, and outputs the output signal of the OR gate as the detection signal. The control circuit according to claim 4.   The control circuit according to claim 1, wherein the threshold voltage is a ground potential. The comparison unit includes:
A level shift circuit for level-shifting the switching voltage and the threshold voltage by a predetermined voltage in the positive direction;
A comparator that compares the switching voltage level-shifted by the level shift circuit with the threshold voltage;
The control circuit according to claim 1, wherein an output signal of the comparator is output as the comparison signal. The comparison unit includes:
A delay circuit that receives the second gate voltage and outputs a mask signal that becomes a high level after a lapse of a predetermined delay time after the second gate voltage changes from a low level to a high level;
A mask signal output from the delay circuit; and an AND gate that outputs a logical sum of the output signals of the comparators;
8. The control circuit according to claim 7, wherein an output signal of the AND gate is output as the comparison signal. The level shift circuit includes:
A PNP-type first bipolar transistor that inputs the switching voltage to a base terminal, grounds a collector terminal, and outputs a voltage obtained by level shifting the switching voltage from an emitter terminal;
A PNP-type second bipolar transistor that has a base terminal and a collector terminal grounded and outputs a voltage obtained by level shifting the ground potential from the emitter terminal;
8. The switch connected between the emitter terminals of the first and second bipolar transistors, and turned on during a low level of a mask signal output from the delay circuit. Control circuit.   The control circuit according to claim 1, wherein the synchronous rectification transistor is an NMOS transistor.   The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate. A capacitor with one end grounded;
An inductor having one end connected to the other end of the capacitor;
The control circuit according to any one of claims 1 to 10, wherein the switching voltage is supplied to the other end of the inductor;
And a voltage at the other end of the capacitor is output. A battery that outputs battery voltage;
A microcomputer,
The step-down switching regulator according to claim 12, wherein the battery voltage is stepped down and supplied to the microcomputer.
An electronic device comprising:

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