JP2006323963A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a voltage drop caused by a reverse current electric charge generated at the standstill of a boosting circuit in an internal power source circuit to be used for a flash memory. <P>SOLUTION: A drain of a PMOS transistor TR1 is connected to an output end whereon an output voltage VDDRO of the boosting circuit 11 is supplied, for instance. To a source of this PMOS transistor TR1, a memory cell MC is connected for supplying a boosted voltage VDDR for a leading operation. At the operating time of the boosting circuit 11, an NMOS transistor TR3 is turned on, so that a back gate voltage VDDRX of the PMOS transistor TR1 has same potential as that of the output voltage VDDRO of the boosting circuit 11. Meanwhile, at the stop of operation, an NMOS transistor TR2 is turned on, so that the back gate voltage VDDRRX of the PMOS transistor TR1 has same potential as that of the boosted voltage VDDR. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, in a semiconductor memory device such as a flash memory, a boost voltage for a read operation for reading data written in a memory cell based on a drive voltage from an external power supply. The present invention relates to an internal power supply circuit such as a charge pump circuit (boost circuit) that generates

  In recent years, in a nonvolatile semiconductor memory device such as a flash memory, a further reduction in voltage has been demanded as the voltage of logic products has been reduced. For example, a high voltage is required to read data (during a read operation). However, in the case of a single power supply voltage method, circuit technology for generating a high voltage from a low voltage inside the chip reduces the voltage. Has become very important. In addition, the design of the constant voltage source is particularly important in a device in which various levels of voltage must be controlled inside the chip depending on the operation mode.

  As a booster circuit for generating a high voltage from a low voltage inside a chip, which is used in a flash memory, etc., one electrode of a capacitor is connected to a connection point of diodes connected in series and supplied from the outside. A so-called charge pump circuit is known in which a desired boosted voltage (high voltage) is obtained by boosting a driving voltage (low voltage) according to the number of stages.

  Recently, a booster circuit with such an internal booster operation (or charge pump operation) is often incorporated in a portable device, and the demand for reduction in standby current is severe. The reason is that portable devices are basically battery-powered, so even if they are very small, if a stand-by current flows, they will directly affect the performance of the device, such as shortening the standby time of the device. .

  In order to realize an ideal booster circuit, the threshold voltage Vc of the diode needs to be 0V. If the threshold value is Vc> 0V, the increased potential is VDD−Vc, and the potential increase per stage is lost accordingly. Therefore, it is desirable to use a diode (I-type transistor) formed on the substrate without channel ion implantation as a diode constituting the charge pump circuit. Since the I-type transistor has a low impurity concentration in the channel portion, the threshold value (Vth) can be set to approximately 0V.

  However, the threshold value Vth of the I-type transistor does not always become 0 V depending on the temperature and process conditions, and may be negative. In such a case, even if the gate voltage becomes negative, the transistor A small current flows without turning off. Then, the charge pump circuit is changed from the active state to the standby state, and from the moment when the charge pump operation is stopped, a reverse flow of charge occurs through the transistors of each stage. The amount of the backflow charge increases as the difference between the drive voltage and the boosted voltage increases.

  When the level of the boosting node is lowered due to the backflow charge, the charge pump circuit must operate to replenish the potential. That is, the presence of backflow charge in the charge pump circuit causes an increase in standby current. However, if the threshold voltage Vth of the transistor is increased by channel ion implantation or the like, as described above, the potential increase per stage is lost, and at present, an I-type transistor must be used.

  Conventionally, when the amount of backflow charge is ΔQ and the capacitance of the chip is Ctotal, the boost voltage is designed to decrease by ΔQ / Ctotal = ΔV (where ΔV is within the control value of the control voltage). In the case of a large-capacity product, this condition is an environment that is easily satisfied because Ctotal is large and ΔV is small. However, recently, as chip shrink progresses, especially in the case of a small-capacity product, the allowable value of the standby current in the charge pump circuit is becoming smaller, and it is becoming difficult to tolerate the conventional value.

  Furthermore, if the difference between the drive voltage and the boosted voltage increases as the voltage of logic products decreases, it is necessary to increase the number of transistors connected in series. The increase in the number of capacitors reduces the area (size) of the charge pump circuit. Enlarge. The size of the charge pump circuit depends on the output current. When the size of the charge pump circuit is increased, the amount of backflow charge is increased and the voltage drop is increased accordingly.

  As described above, although an ideal booster circuit can be configured by using an I-type transistor, the voltage drop due to the backflow charge generated when the booster circuit is stopped cannot be prevented depending on the temperature, process conditions, and the like. was there.

In addition, in order to prevent the current from flowing back to the charge pump when the operation of the charge pump is stopped, a technique of providing a backflow prevention switch composed of a P-channel MOS transistor is already known (see, for example, Patent Document 1). In this technique, the drain of the P-channel MOS transistor is coupled to the output end of the charge pump, the source is coupled to the output line of the charge pump, and the substrate N-well is coupled to the source.
JP-A-11-186503 (page 5, FIG. 1)

  For the P-channel MOS transistor TR1, which is a MOS transistor switch, the junction becomes forward and does not function as a transistor unless the relationship of substrate potential> source potential and drain potential is satisfied. That is, it is necessary to consider the relationship between the three voltages at the time of charge pump operation / operation stop, but the substrate potential is the same as the source potential in spite of the P-channel MOS transistor in the prior art, and the reverse flow It did not function sufficiently as a prevention switch.

  The present invention has been made to solve the above-described problems, and provides a semiconductor device that can reliably prevent a voltage drop due to backflow charge that has occurred when the booster circuit is stopped and can supply a stable voltage. The purpose is to do.

  According to one aspect of the present invention, a booster circuit that generates a boosted voltage based on a drive voltage, a drive unit that operates with the boosted voltage generated by the booster circuit, and an output terminal of the booster circuit. A PMOS (Metal Oxide Semiconductor) transistor switch provided, the source is connected to the drive unit, the drain is connected to the output terminal of the booster circuit, and the well is supplied to the drain during operation of the booster circuit The PMOS transistor switch to which the same potential as the potential is supplied and the same potential as the potential supplied to the source is supplied to the well when the booster circuit stops operating, and the PMOS transistor switch is turned on when the booster circuit operates. And a control circuit for controlling to be turned off when stopped A semiconductor device is provided.

  According to one aspect of the present invention, there is provided a booster circuit that generates a boosted voltage based on a drive voltage, a drive unit that operates with the boosted voltage generated by the booster circuit, and an output terminal of the booster circuit. An NMOS (Metal Oxide Semiconductor) transistor switch provided between the NMOS transistor switch having a source connected to the drive unit and a drain connected to an output terminal of the booster circuit, and boosting the NMOS transistor switch to the booster A control circuit that controls to turn on when the circuit operates and to turn off when the circuit stops, and includes a first and second diode connected in series, and one electrode at a connection point of the first and second diodes And a capacitor connected to the other electrode of the capacitor, the capacitor And a control circuit for applying a voltage higher than the boosted voltage by the booster circuit to the gate of the NMOS transistor when the booster circuit operates. A semiconductor device is provided.

  With the above-described configuration, it is possible to provide a semiconductor device that can reliably prevent a voltage drop due to the backflow charge generated when the booster circuit is stopped and can supply a stable voltage.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 shows a basic configuration of an internal power supply circuit according to the first embodiment of the present invention. Here, based on a drive voltage (VDDO) from an external power supply, for example, a boost voltage (VDDR) for read operation for reading data written in a memory cell of a flash memory such as a NOR type EEPROM. ) In the internal power supply circuit configured to generate a reverse flow of charge during standby by providing a P-channel MOS (Metal Oxide Semiconductor) transistor switch between the booster circuit and the memory cell as the driving unit. A case where it is possible to suppress this will be described.

  For example, as shown in FIG. 1, an output terminal to which an output voltage VDDRO from a booster circuit (charge pump circuit) 11 is supplied is connected to a P channel MOS transistor (hereinafter referred to as a PMOS transistor) TR1 constituting a MOS transistor switch. The drain is connected. The source of the PMOS transistor TR1 is connected to a memory cell (driving unit) MC to which a boosted voltage VDDR that is a high voltage for read operation is supplied. Further, an inverter circuit INVa and a level shift circuit LS1 for controlling the gate voltage VG are connected to the gate of the PMOS transistor TR1. An enable signal ENABLE is input to the level shift circuit LS1 from the outside of the apparatus. Further, the boosted voltage VDDR is supplied as an operation voltage to the inverter circuit INVa and the level shift circuit LS1.

  On the other hand, the back gate (N-type well) of the PMOS transistor TR1 includes a source of an N-channel MOS transistor (hereinafter referred to as NMOS transistor) TR2, which is a first NMOS transistor, and an NMOS transistor (second NMOS transistor). ) The sources of TR3 are connected to each other. The boosted voltage VDDR is supplied to the gate and drain of the NMOS transistor TR2. A level shift circuit LS2 is connected to the gate of the NMOS transistor TR3. The level shift circuit LS2 is configured to receive the enable signal ENABLE. Further, the output voltage VDDRO from the booster circuit 11 is supplied to the drain of the NMOS transistor TR3 and the level shift circuit LS2. In the present embodiment, the NMOS transistors TR2 and TR3 are constituted by, for example, I-type transistors.

  FIG. 2 shows a configuration example of the booster circuit 11 described above. For example, as shown in FIG. 2, a drive voltage (VDDO) from an external power supply is input to one of the source / drain of the input transistor TRa. A control signal (step-up operation start signal) INa is supplied to the gate of the input transistor TRa from the outside of the device. In addition, a plurality (two in this example) of diodes Da and Db are connected in series to the other of the source / drain of the input transistor TRa. These diodes Da and Db are constituted by, for example, diode-connected I-type transistors.

  One electrode of the capacitor C1 is connected to a connection point (node V1) with the input transistor TRa on the anode side of the diode Da. A ring oscillator circuit (Ring OSC) 11a is connected to the other electrode of the capacitor C1 through an inverter circuit INV1. One electrode of the capacitor C2 is connected to a connection point (node V2) between the cathode side of the diode Da and the anode of the diode Db. A ring oscillator circuit 11a is connected to the other electrode of the capacitor C2 via inverter circuits INV2 and INV3.

  A comparator 11b is connected to the ring oscillator circuit 11a. The comparator 11b divides the output voltage Vout (= VDDRO) boosted by the booster circuit 11 with the resistors R1 and R2, and the output V0 obtained by comparing the divided voltage with the reference voltage causes the ring oscillator circuit 11a. Control on / off. The ring oscillator circuit 11a oscillates according to the output V0 from the comparator 11b, and generates a clock signal OSC for driving the capacitors C1 and C2 alternately. As a result, the charge pump operation is performed, and the output voltage (Vout) increases step by step each time the charge (drive voltage VDDO) is transferred through each stage. The comparator 11b turns off the output V0 when the divided voltage reaches a predetermined reference voltage, and stops the generation of the clock signal OCR of the ring oscillator circuit 11a. As a result, the charge pump operation is stopped and the output voltage (Vout) drops. By repeating this operation, a desired high voltage (VDDRO) necessary for the read operation is obtained as the output voltage (Vout). The basic operation of the booster circuit 11 has been described above.

  In such a configuration, by transferring the capacitors C1 and C2 of the respective stages including the diodes Da and Db and the capacitors C1 and C2 alternately by the clock signal OSC from the ring oscillator circuit 11a, charge transfer, that is, A charge pump operation is performed. The output voltage Vout boosted by this charge pump operation is output from the cathode of the final-stage diode Db.

  Here, the operation of the booster circuit 11 will be further described. A drive voltage (VDDO) is input to the input transistor TRa. At this time, assuming that the threshold value Vc of the diode Da (or the threshold value Vth of the I-type transistor) = 0, the node V1 is charged with the charge of VDDO. In this state, when the voltage (Boot1) of the other electrode of the capacitor C1 changes from VSS to VDDO, the node V1 is charged with a charge of 2VDDO. Similarly, assuming that the threshold value Vc of the diode Db = 0, the node V2 is charged with a charge of 2VDDO. In this state, when the voltage (Boot2) of the other electrode of the capacitor C2 changes from VSS to VDDO, the node V2 is charged with a charge of 3VDDO.

  For this reason, since there is a voltage difference equal to or greater than the threshold value Vc of the diodes Da and Db and charges are transferred to the next stage for the first time, the lower the threshold value Vc of the diodes Da and Db, the better. That is, the smaller the number of stages, the more efficient the booster circuit 11 is. However, if the number of stages is small, the charge MAX value due to the charge pump operation becomes low. For example, if the number of stages is one, it can be charged up to 2VDDO no matter how efficient it is, and even if it is two stages, it can only be charged up to 3VDDO no matter how efficient it is.

  As described above, the booster circuit 11 can obtain a high boosted voltage (output voltage Vout) by increasing the number of stages of the charge pump circuit. However, there is a demerit that the efficiency is deteriorated. There is a demerit that only a low boosted voltage can be obtained.

  Next, an outline of the operation of the internal power supply circuit shown in FIG. 1 will be described. First, during the charge pump operation, the signal ENABLE is set to the “H (high)” level. The H level signal ENABLE is sent to the inverter circuit INV1 via the level shift circuit LS1. Then, the gate voltage VG = 0 which is the output of the inverter circuit INVa is set, and the PMOS transistor TR1 is turned on. As a result, the output voltage VDDRO boosted by the booster circuit 11 becomes the boosted voltage VDDR and is supplied to the memory cell MC.

  At this time, the H level signal ENABLE is also supplied to the gate of the I-type NMOS transistor TR3 via the level shift circuit LS2. As a result, the NMOS transistor TR3 is turned on, and the voltage VDDRX of the back gate (N-type well) of the PMOS transistor TR1 is set to the same potential as the output voltage VDDRO of the booster circuit 11.

  On the other hand, when the charge pump operation is stopped, the signal ENABLE becomes the “L (low)” level. This L level signal ENABLE is sent to the inverter circuit INVa via the level shift circuit LS1. Then, the gate voltage VG = “H” level which is the output of the inverter circuit INVa is set, and the PMOS transistor TR1 is turned off. As a result, the backflow of charges from the drive unit (VDDR) side to the output terminal (VDDRO) side of the booster circuit 11 is prevented. In this case, since the signal ENABLE is “L” level, the I-type NMOS transistor TR3 is turned off and the I-type NMOS transistor TR2 is turned on. As a result, the voltage VDDRX of the back gate of the PMOS transistor TR1 becomes the same potential as the boosted voltage VDDR on the driver side.

  In the first embodiment of the present invention, the boosted voltage VDDR supplied to the memory cell MC is controlled by the enhancement type PMOS transistor TR1. At this time, attention should be paid to the relationship between the output voltage VDDRO of the booster circuit 11, the boosted voltage VDDR, and the back gate voltage VDDRX of the PMOS transistor TR1. As for the PMOS transistor TR1, which is a MOS transistor switch, assuming that the substrate potential is VB, the source potential is VS, and the drain potential is VD, the junction becomes forward unless it has a relationship of VB> VS, VD, and does not function as a transistor. That is, since three different voltages VDDRX (back gate), VDDRO (drain), and VDDR (source) are supplied to the PMOS transistor TR1, the relationship between the three voltages during charge pump operation / operation stop is VDDRX> VDDRO, VDDR must be satisfied.

  FIG. 3 is a cross-sectional view of the PMOS transistor TR1 shown in a simplified manner for easy understanding of the relationship between the three voltages VDDRX, VDDRO, and VDDR in the internal power supply circuit shown in FIG.

  For example, as shown in FIG. 3, in the PMOS transistor TR1, a P-type diffusion layer SDa serving as a drain on the booster circuit 11 (output voltage VDDRO) side and a P-type diffusion layer SDb serving as a source on the drive unit (boost voltage VDDR) side There is a minute resistance ron in the channel portion between. Therefore, when the PMOS transistor TR1 is turned on during the charge pump operation, the output voltage VDDRO on the booster circuit 11 side is supplied to the drive unit side as the boosted voltage VDDR. The relationship between the output voltage VDDRO and the boosted voltage VDDR is VDDRO > VDDR.

  At this time, the signal ENABLE (H level) is also input to the gate of the NMOS transistor TR3, whereby the NMOS transistor TR3 is turned on. Since the NMOS transistor TR3 is an I-type transistor, the threshold value Vth≈0, and the voltage VDDRO becomes the back gate voltage VDDRX almost as it is. Therefore, the back gate voltage VDDRX of the PMOS transistor TR1 has a relationship of VDDRX (VDDRO)> VDDR, and there is no inconvenience that the junction becomes forward.

  On the other hand, when the charge pump operation is stopped, a reverse flow of charge occurs in the final stage of the booster circuit 11, so that the relationship between the output voltage VDDRO and the boosted voltage VDDR is VDDRO <VDDR. When the charge pump operation is stopped, the signal ENABLE becomes “L” level, and the NMOS transistor TR2 is turned on. Since the NMOS transistor TR2 is an I-type transistor, the threshold value Vth≈0, and the boost voltage VDDR becomes the back gate voltage VDDRX almost as it is. Therefore, the back gate voltage VDDRX of the PMOS transistor TR1 has a relationship of VDDRX (VDDR)> VDDRO, and there is no inconvenience that the junction becomes forward.

  As described above, in the first embodiment of the present invention, even when the booster circuit 11 is configured by using an I-type transistor, three different voltages of the PMOS transistor TR1 are always VDDRX (back gate)> VDDRO. (Drain) and VDDR (source) relation, the junction becomes forward, does not cause a malfunction that does not function as a transistor, and reliably prevents a voltage drop due to the backflow of charge when the charge pump operation is stopped. be able to. Therefore, it is possible to easily supply a boost voltage (VDDR) for read operation for reading data written in the memory cell MC stably.

[Second Embodiment]
FIG. 4 shows a basic configuration of an internal power supply circuit according to the second embodiment of the present invention. Here, based on a drive voltage (VDDO) from an external power supply, for example, a boost voltage (VDDR) for read operation for reading data written in a memory cell of a flash memory such as a NOR type EEPROM is used. In the internal power supply circuit configured to be generated, by providing an N-channel MOS transistor switch between the booster circuit and the memory cell as the driving unit, it is possible to suppress the backflow of charges during standby. The case will be described. Note that the same parts as those in FIG.

  For example, as shown in FIG. 4, the drain of an N-channel MOS transistor (hereinafter referred to as NMOS transistor) RSW constituting a MOS transistor switch is connected to an output terminal to which an output voltage VDDRO from a booster circuit (charge pump circuit) 11 is supplied. It is connected. In the case of this embodiment, the NMOS transistor RSW is constituted by, for example, an I-type transistor. The source of the NMOS transistor RSW is connected to a memory cell (driving unit) MC to which a boosted voltage VDDR that is a high voltage for read operation is supplied.

  The diodes D1 and D2 are connected in series to the gate of the NMOS transistor RSW. One electrode of the capacitor CB is connected to a connection point (node VD2) between the diodes D1 and D2. A mini booster circuit (ring oscillator circuit) 21 that sends a clock signal OSC1 to the capacitor CB is connected to the other electrode of the capacitor CB. The output voltage VDDRO from the booster circuit 11 is supplied to the anode of the diode D1.

  Further, the drain of the NMOS transistor TRb for controlling the gate voltage VG1 is connected to the gate of the NMOS transistor RSW. The source of the NMOS transistor TRb is grounded, and the gate is connected to the output terminal of the inverter circuit INVb. A switching signal SW is supplied to the input terminal of the inverter circuit INVb from the outside of the apparatus.

  In the present embodiment, the boosted voltage VDDR can be turned off regardless of the level of the output voltage VDDRO of the booster circuit 11. However, when the NMOS transistor RSW is turned on, it is necessary to increase the gate voltage VG1 of the NMOS transistor RSW to a value exceeding “the output voltage of the booster circuit 11” + “the threshold value Vth of the NMOS transistor RSW”. For this purpose, a mini booster circuit 21 is added.

  FIG. 5 shows a specific example of the mini booster circuit 21 described above. For example, as shown in FIG. 5, periodic pulses of voltage “H (high level = drive voltage VDDO)” and “L (low level = ground potential)” are input to the input terminal IN1. Inverter circuits INV-A and INV-B are connected in series to the input terminal IN1. An output terminal of the inverter circuit INV-B is connected to a common gate of a CMOS (Complementary MOS) inverter circuit INV-C.

  On the other hand, an anode of a diode DA is connected to an input terminal IN2 to which a drive voltage (VDDO) from an external power supply is supplied. The cathode of the diode DA is connected to the connection point (node VD1) of the inverter circuits INV-A and INV-B via the capacitor CA. The cathode of the diode DA is connected to the CMOS inverter circuit INV-C. The output from the common drain of the CMOS inverter circuit INV-C is taken out from the output terminal OUT1 as the clock signal OSC1 to the capacitor CB.

  In such a configuration, when the input to the input terminal IN1 is “H level”, the output of the inverter circuit INV-A is “L level”, and when the threshold value Vc of the diode DA is approximately 0, the node VD1 The charge for VDDO is charged. On the other hand, when the input to the input terminal IN1 is “L level”, the output of the inverter circuit INV-A is “H level”, and the drive voltage (VDDO) is charged in the capacitor CA. A charge of 2VDDO is accumulated in VD1. Further, since the output of the inverter circuit INV-B becomes “L level”, the electric charge of 2VDDO is output from the output terminal OUT1 as a periodic pulse having a corresponding wave height (H level).

  Thus, during the charge pump operation of the booster circuit 11, the output (charge of 2VDDO) from the mini booster circuit 21 is taken out as the clock signal OSC1, so that the capacitor CB is charged with the charge of 2VDDO, for example, as shown in FIG. Is done. On the other hand, the output voltage VDDRO from the booster circuit 11 is input to the anode of the diode D1, and when the threshold value Vc of the diode D1 is approximately 0, the node VD2 is charged with VDDR + 2VDDO. When the threshold value Vc of the diode D2 is approximately 0, a gate voltage VG1 of VDDR + 2VDDO is applied to the gate of the I-type NMOS transistor RSW. As a result, the NMOS transistor RSW is turned on.

  On the contrary, when the charge pump operation of the booster circuit 11 is stopped, the switching signal SW becomes “L level” by the signal ENABLE. Then, the output of the inverter circuit INVb becomes “H level”, and the NMOS transistor TRb is turned on. As a result, the gate voltage VG1 = 0 of the NMOS transistor RSW is set, the NMOS transistor RSW is turned off, and a voltage drop due to the backflow of charges is prevented. In this way, by using an I-type MOS transistor as the NMOS transistor RSW, it is possible to reduce the on-time conductance and to reduce the mini boost level.

  As described above, in the second embodiment of the present invention, even when the booster circuit 11 is configured by using an I-type transistor, the boosted voltage VDDR is set regardless of the level of the output voltage VDDRO of the booster circuit 11. Since it can be turned off, a voltage drop due to the backflow of charges can be reliably prevented when the charge pump operation of the booster circuit 11 is stopped. Therefore, it is possible to easily supply a boost voltage (VDDR) for read operation for reading data written in the memory cell MC stably.

  In the first and second embodiments described above, an internal power supply configured to generate a boost voltage (VDDR) for read operation for reading data written in the memory cell of the flash memory. Although the case where the present invention is applied to a circuit has been described, the present invention is not limited to this, and the present invention can be similarly applied to, for example, an internal power supply circuit that generates a boost voltage for a write operation for writing data in a memory cell. Alternatively, the present invention can be similarly applied to an internal power supply circuit that generates a boosted voltage for erasing operation for erasing data written in a memory cell.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

The block diagram which shows an example of the internal power supply circuit according to the 1st Embodiment of this invention. FIG. 2 is a circuit diagram showing a configuration of a booster circuit in the internal power supply circuit of FIG. 1. FIG. 2 is a diagram showing a part of the internal power supply circuit of FIG. 1 in a simplified manner. The block diagram which shows an example of the internal power supply circuit according to the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram showing a configuration of a mini booster circuit in the internal power supply circuit of FIG. 4.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Boost circuit (charge pump circuit) 11a ... Ring oscillator circuit, 11b ... Comparator, 21 ... Mini booster circuit, MC ... Memory cell, TR1 ... PMOS transistor, RSW, TR2, TR3 ... NMOS transistor, TRa ... Input transistor INVa, INV1, INV2, INV3 ... inverter circuit, LS1, LS2 ... level shift circuit, D1, D2, Da, Db ... diode, C1, C2, CB ... capacitor, R1, R2 ... resistor.

Claims (4)

A booster circuit for generating a boosted voltage based on the drive voltage;
A PMOS (Metal Oxide Semiconductor) transistor switch provided between a drive unit that operates with the boosted voltage generated by the booster circuit and an output terminal of the booster circuit, a source connected to the drive unit, The drain is connected to the output terminal of the booster circuit, and the same potential as the potential supplied to the drain is supplied to the well when the booster circuit operates, and the well is supplied to the source when the booster circuit stops operating. A PMOS transistor switch supplied with the same potential as the potential;
And a control circuit that controls the PMOS transistor switch to be turned on when the booster circuit operates and to be turned off when the booster circuit is stopped. The control circuit includes:
A first NMOS transistor having a source connected to the well and a drain and gate connected to the source of the PMOS transistor;
A second NMOS transistor having a source connected to the well, a drain connected to the drain of the PMOS transistor, and a gate supplied with an enable signal;
During the operation of the booster circuit, the gate of the PMOS transistor becomes low level to turn on the PMOS transistor, and the gate of the second NMOS transistor becomes high level to turn on the second NMOS transistor. Supplying a source potential of the second NMOS transistor higher than a source potential of the first NMOS transistor to a well of the PMOS transistor;
When the booster circuit is stopped, the gate of the PMOS transistor becomes high level to turn off the PMOS transistor, the gate of the second NMOS transistor becomes low level to turn off the second NMOS transistor, The gate of the first NMOS transistor is at a high level, the first NMOS transistor is turned on, and the first NMOS transistor has a higher potential than the source potential of the second NMOS transistor in the well of the PMOS transistor. 2. The semiconductor device according to claim 1, wherein a source potential of the transistor is supplied.   3. The semiconductor device according to claim 2, wherein the first and second NMOS transistors are I-type MOS transistors having a threshold value (Vth) of substantially 0V. A booster circuit for generating a boosted voltage based on the drive voltage;
An NMOS (Metal Oxide Semiconductor) transistor switch provided between a drive unit that operates with the boosted voltage generated by the booster circuit and an output terminal of the booster circuit, a source connected to the drive unit, An NMOS transistor switch having a drain connected to the output terminal of the booster circuit;
A control circuit for controlling the NMOS transistor switch to be turned on when the booster circuit is in operation and to be turned off when the booster circuit is stopped, the first and second diodes connected in series, and the first and second diodes A capacitor having one electrode connected to the connection point, and a generation circuit that is connected to the other electrode of the capacitor and generates a clock signal to be supplied to the capacitor, and during operation of the booster circuit, And a control circuit for applying a voltage higher than a boosted voltage by the booster circuit to a gate of the NMOS transistor.

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