JP2006323934A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the erroneous operation of a semiconductor memory by reducing power source noise. <P>SOLUTION: A column memory block group includes memory blocks arrayed in a vertical direction. A row memory block group includes memory blocks arrayed in a horizontal direction. A first row address decoder activates one of a plurality of first decoding signals corresponding to a first row address. A plurality of amplifier circuits connected to a common power line corresponding to each row memory block group receive first decoding signals different from one another. Since power is supplied to the simultaneously operated amplifier circuits, a drop in power supply voltage is reduced, and power supply noise generated in the power line is reduced. Thus, the erroneous operation of the semiconductor memory is prevented. Since the number of power lines arranged in the amplifier circuits is reduced, the margin of the layout of the power lines is increased. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory having a plurality of memory blocks arranged in a matrix.

  Generally, in a semiconductor memory in which a plurality of memory blocks are arranged in a matrix, a sense amplifier or a write amplifier is arranged adjacent to each memory block. Japanese Patent Application Laid-Open Nos. 2004-62997 and 10-302470 describe examples in which amplifier circuits such as sense amplifiers are arranged in a staggered manner so that two memory blocks can share the amplifier circuit. . With the staggered arrangement, the amplifier circuits are arranged in a distributed manner, so that the layout design becomes easy.

Further, in a semiconductor memory in which a plurality of memory blocks are arranged in a matrix, a predetermined bit of an external data terminal may be assigned for each memory block group composed of memory blocks arranged in one direction. In this type of semiconductor memory, in order to input / output data to all external data terminals in response to an access request, an amplifier circuit corresponding to the memory block of one memory block group and a memory block of the other memory block group The corresponding amplifier circuit is activated simultaneously.
Japanese Patent Laid-Open No. 2004-62997 JP-A-10-302470

  Conventionally, a memory block that is simultaneously accessed in response to an access request and an amplifier circuit that is simultaneously activated in response to the simultaneously accessed memory block simplify the logic of a decoder and the like, and simplify the wiring path of the decode signal Therefore, they are often arranged in a row in a direction orthogonal to the one direction described above.

  On the other hand, power supply lines formed in the semiconductor memory are wired in either or both of the vertical direction and the horizontal direction of the memory chip. The above-described amplifier circuits activated simultaneously are connected to a common power supply line wired in the vertical direction or the horizontal direction. When a plurality of amplifier circuits connected to a common power supply line are simultaneously activated, power supply noise generated on the power supply line tends to increase. In particular, an amplifier circuit such as a sense amplifier tends to malfunction due to the influence of a drop in power supply voltage. In order to prevent malfunction, it is necessary to thicken the power supply wiring. Alternatively, it is necessary to increase the number of power lines to be wired.

  Further, when the semiconductor memory is mounted in the system LSI, the wiring margin of the power supply lines supplied to other blocks is reduced by increasing the number of power supply lines wired to the semiconductor memory. As a result, the degree of freedom of wiring of the design tool for laying out the power supply lines and the like is reduced, and the calculation time for layout is increased. In the worst case, automatic layout is not possible.

  An object of the present invention is to reduce power supply noise and prevent malfunction of a semiconductor memory.

  Another object of the present invention is to reduce the width of the power supply line connected to the amplifier circuit, or reduce the number of power supplies connected to the amplifier circuit, and allowance for the layout of the power supply line wired to other blocks. Is to make it larger.

  In one embodiment of the present invention, a semiconductor memory has a plurality of memory blocks arranged in a matrix. The column memory block group includes a predetermined number of memory blocks arranged in the vertical direction. The row memory block group includes a predetermined number of memory blocks arranged in the horizontal direction. The amplifier circuit block is disposed at one end of the memory cell block in order to amplify data input / output to / from the memory cell. For example, the amplifier circuit block includes a plurality of sense amplifiers that amplify the signal amount of data read from the memory cell. Alternatively, the amplifier circuit block includes a plurality of write amplifiers that amplify the signal amount of data to be written in the memory cell. For example, a semiconductor memory is mounted on a system LSI together with a logic circuit. The system LSI has a plurality of power supply lines oriented in the horizontal direction using a predetermined wiring layer on a semiconductor substrate.

  The first row address decoder activates one of the plurality of first decode signals according to the first row address in order to activate any one of the amplifier circuit blocks for each column memory block group. A common power supply line is connected to a plurality of amplifier circuit blocks corresponding to each row memory block group. A plurality of amplifier circuit blocks corresponding to each row memory block group receive different first decode signals. That is, the plurality of amplifier circuit blocks activated in accordance with the first row address belong to different row memory block groups and are connected to different power supply lines. Since power is supplied to amplifier circuit blocks operating simultaneously using different power supply lines, power supply voltage drops can be reduced and power supply noise generated in the power supply lines can be reduced. As a result, malfunction of the amplifier circuit block can be prevented.

  Further, by applying the present invention, the number of power supply lines wired on the amplifier circuit block can be reduced, or the width of the power supply line can be reduced. Therefore, in a system LSI or the like, a power supply line wired to another block can be passed over the amplifier circuit block of the semiconductor memory. As a result, it is possible to increase the degree of wiring freedom (layout margin) of the design tool for laying out the power supply lines, and shorten the calculation time for layout.

  In a preferred example of one aspect of the present invention, the second row address decoder includes a plurality of second decode signals in response to the second row address signal in order to activate one of the word lines for each column memory block group. Activate either. The word line decoder has a plurality of decoding circuits corresponding to a pair of word lines of a pair of column memory block groups. Each decode circuit has a first logic circuit and a pair of second logic circuits corresponding to each word line. The first logic circuit generates a third decode signal common to the pair of word lines according to the second decode signal. Each second logic circuit activates a corresponding word line in response to the third decode signal and the first decode signal. The first decode signals received by the pair of second logic circuits are different from each other. Therefore, the word line of the memory block corresponding to the activated amplifier circuit block can be activated using a simple logic circuit.

  In the present invention, power supply noise generated in the power supply line can be reduced, and malfunction of the amplifier circuit block can be prevented. In addition, it is possible to increase the wiring flexibility of the design tool for laying out the power supply lines, and to reduce the calculation time for layout.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Double circles in the figure indicate external terminals. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. A part of the block to which the thick line is connected is composed of a plurality of circuits. The same reference numerals as the signal names are used for signal lines through which signals are transmitted.

  FIG. 1 shows a first embodiment of the semiconductor memory of the present invention. The semiconductor memory is formed as an SRAM using, for example, CMOS technology. The SRAM is mounted on the system LSI as shown in FIG. The SRAM includes an operation control circuit 10, an address input circuit 12, a data input / output circuit 14, a row address decoder 16, a word line decoder 18, a column address decoder 20, a column switch decoder 22, a memory cell array ARY, a column switch CSW, and a sense amplifier block. It has SA (amplifier circuit block) and write amplifier block WA (amplifier circuit block).

  The operation control circuit 10 receives a control signal CNT for causing the SRAM to execute a read operation and a write operation via the external control terminal CNT, and decodes the received control signal CNT. The operation control circuit 10 outputs an internal control signal ICNT (timing signal) for executing a read operation or a write operation to the row address decoder 16 and the column address decoder 20 according to the decoding result. The internal control signal ICNT is supplied not only to the row address decoder 16 and the column address decoder 20, but also to the address input circuit 12, the data input / output circuit 14, and the like.

  The address input circuit 12 outputs an address signal AD (AD0-14) supplied via the external address terminal AD as a row address signal RA (RA0-7) and a column address signal CA (CA0-6). The row address signal RA is composed of upper bits of the address signal AD, and is used for selecting the sense amplifier block SA and the write amplifier block WA and selecting the word line WL. The column address signal CA is composed of lower bits of the address signal AD and is used to select the bit line BL. Note that the number of bits of the address signals AD, RA, and CA is not limited to this example.

  The data input / output circuit 14 outputs read data transferred from the memory cell array ARY via the data line DT and the data bus DB to the external data terminal I / O (I / O0-31) during the read operation. During a write operation, the data input / output circuit 14 receives write data via the external data terminal I / O and supplies the received write data to the memory cell array ARY via the data bus DB. The number of bits of the external data terminal I / O is not limited to this example.

  The row address decoder 16 decodes the row address signals RA0-1, RA2-3, RA4-5, RA6-7, respectively, and generates row decode signals A (A0-3), B (B0-3), C (C0- 3) Output as D (D0-3). For example, when the row address signal RA0-1 is a decimal number “0”, “1”, “2”, “3”, the row address decoder 16 outputs “A0”, “A1” of the row decode signal A, respectively. , “A2” and “A3” are changed to a high logic level, and others are changed to a low logic level. The word line decoder 18 decodes the row decode signal AD, changes the word line WL indicated by the row address signal RA0-7 to the high voltage level, and changes the other word lines WL to the low voltage level. Details of the row address decoder 16 and the word line decoder 18 will be described later with reference to FIGS.

  Column address decoder 20 decodes column address signal CA and outputs it as column decode signal CDEC. The column switch decoder 22 decodes the column decode signal CDEC, turns on the column switch CSW indicated by the column address signal CA, changes the corresponding column selection signal CS to a high logic level in order to select the bit line BL, The other column selection signal is changed to a low logic level.

The memory cell array ARY is connected to a plurality of memory cells MC arranged in a matrix, a plurality of word lines WL connected to the memory cells MC arranged in the horizontal direction in the figure, and a memory cell MC arranged in the vertical direction in the figure. A plurality of bit lines BL are provided. Although not shown in particular, the memory cell MC has a latch circuit composed of an inverter having an input and an output connected to each other and a transfer transistor for connecting a storage node of the latch circuit to the bit line BL, as in a general SRAM cell. And have. In the transfer transistor, the gate is connected to the word line WL, one of the source and the drain is connected to the storage node, and the other of the source and the drain is connected to the bit line BL.

  Each sense amplifier (amplifier circuit, not shown) of the sense amplifier block SA amplifies the signal amount of data read from the memory cell MC via the bit line BL during the read operation. Each write amplifier (amplifier circuit, not shown) of the write amplifier block WA amplifies the signal amount of the write data on the data bus DB and outputs it to the bit line BL. The column switch CSW connects the bit line BL to the data bus DB according to the column selection signal CS. Read data read to the bit line BL and amplified by the sense amplifier by the column switch CSW is transmitted to the data input / output circuit 14 via the data bus DB. Write data supplied via the data bus DB and amplified by the write amplifier is transmitted to the bit line BL.

  FIG. 2 shows an outline of the layout of the SRAM shown in FIG. In particular, the memory cell array ARY and its surrounding layout are shown. The memory cell array ARY has eight memory blocks BLK (BLKL0-3, BLKR0-3) arranged in a matrix. The sense amplifier block SA and the write amplifier block WA are arranged below each memory block BLK. A pair of column memory block groups CBLK is constituted by four memory blocks BLK arranged in the vertical direction in the figure. Four row memory block groups RBLK are constituted by two memory blocks BLK arranged in the horizontal direction in the figure. Each memory block BLK belongs to one of the column memory block group CBLK and simultaneously belongs to one of the row memory block group RBLK.

  The word line decoder 18 is arranged between a pair of column memory block groups CBLK. The row address decoder 16 is arranged below the word line decoder 18 in the drawing. The data input / output circuit 14 is arranged below each column memory block group CBLK in the drawing. For example, the column memory block group CBLK and the data input / output circuit 14 on the left side of the figure are formed corresponding to the lower external data terminals I / O0-15. The column memory block group CBLK and the data input / output circuit 14 on the right side of the figure are formed corresponding to the upper external data terminals I / O 16-31. Therefore, in response to an access request (control signal CNT), in each column memory block group CBLK, one of the four memory blocks BLK is accessed simultaneously, and the corresponding sense amplifier block SA or write amplifier block WA is activated simultaneously. Is done.

  FIG. 3 shows details of the row address decoder 16 shown in FIG. The row address decoder 16 receives the row address signals RA0-1 (second row address), RA2-3 (second row address), RA4-5 (second row address), and RA6-7 (first row address), respectively. A corresponding decode circuit RDEC (RDEC0-3) is provided. Since the decode circuits RDEC0-3 are the same circuit, the decode circuit RDEC3 will be mainly described below.

The decode circuit RDEC3 (first row address decoder) has a pair of row address registers RAR and four AND circuits. The row address register RAR latches the row address signal RA6-7, and outputs a positive logic signal and a negative logic signal of the row address signal RA6-7, respectively. The AND circuits generate decode signals D0-3 (first decode signals) according to the positive logic signal and the negative logic signal, respectively. Similarly, the decode circuits RDEC0-2 (second row address decoders) receive the decode signal A0-3 (second decode signal) and the decode signal B0 according to the row address signals RA0-1, RA2-3, RA4-5. -3 (second decode signal) and decode signal C0-3 (second decode signal) are generated.

  When the row address signal RA0-7 sequentially increases from “0” to “255” in decimal, the decode signal A0-3 is A0, A1, A2, A3, A0, A1, A2,. . . In order of high logic level. In the decode signal B0-3, B0, B1, B2, and B3 change to the high logic level four times each. In the decoded signal C0-3, C0, C1, C2, and C3 change to the high logic level 16 times each. In the decode signal D0-3, D0, D1, D2, and D3 each change to the high logic level 64 times.

  FIG. 4 shows details of the word line decoder 18 shown in FIG. The word line decoder 18 is formed in common to the pair of column memory block groups CBLK. The word line decoder 18 includes a decode circuit DEC corresponding to each of a pair of word lines WL (for example, LWL0 and RWL0) of the pair of column memory block groups CBLK.

  Each decode circuit DEC has a 3-input NAND gate, a pair of inverters, and a pair of NOR circuits (negative logic AND circuits). The NAND gate receives one of the decode signals A0-3, one of the decode signals B0-3, and one of the decode signals C0-3, decodes these signals, and outputs a decode signal / ABC (third decode signal). Output. The inverter inverts the logic of the decode signal D (for example, D0 and D1). The NOR circuit receives the decode signal / ABC and the inverted signal of the decode signal D output from the inverter, and outputs a logical operation result to the word lines LWL and RWL. In each decode circuit DEC, the decode signals D supplied to the pair of NOR circuits are different from each other.

  In this embodiment, the decoding circuit DEC corresponding to the memory blocks having the same number at the end (for example, BLKL0 and BLKR0) has the decoding signals A, B, and C (64 types) of all combinations and two different decoding signals. D (for example, D0 and D1). The word lines LWL0 to 63 of the memory block BLKL0 are selected by the decode signal D0. That is, the memory block BLKL0 is accessed when the row address signal RA7-6 is “00”. On the other hand, the word lines RWL0-63 of the memory block BLKR0 are selected when the row address signal RA7-6 is “01”. Thus, the memory blocks BLKL0-3 and BLKR0-3 that are opposed to each other with the word line decoder 18 interposed therebetween are not activated at the same time. More specifically, when the row address signal RA7-6 is “00”, the memory blocks BLKL0 and BLKR1 are accessed. When the row address signal RA7-6 is "01", the memory blocks BLKL1 and BLKR0 are accessed. When the row address signal RA7-6 is “10”, the memory blocks BLKL2 and BLKR3 are accessed. When the row address signal RA7-6 is “11”, the memory blocks BLKL3 and BLKR2 are accessed. As described above, according to the present invention, the word lines WL of the memory blocks BLK belonging to the different row memory block groups RBLK can be activated by the simple logic decode circuit DEC.

FIG. 5 shows the decode signals D0-3 supplied to the sense amplifier block SA and the write amplifier block WA in the first embodiment. The sense amplifier block SA and the write amplifier block WA are activated according to the decode signal D0-3 (first decode signal). The decode signal lines D0-3 wired to supply the decode signals D0-3 to the sense amplifier block SA and the write amplifier block WA are different from each other in the pair of memory blocks BLK constituting each row memory block group RBLK. Therefore, the sense amplifier block SA and the write amplifier block WA are connected to the column memory block group CBL.
One is activated for each K, and one is activated for each row memory block group RBLK.

  More specifically, the sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL0 and BLKR1 are activated according to the decode signal D0 (shown by shading in the figure). The sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL1 and BLKR0 are activated according to the decode signal D1. The sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL2 and BLKR3 are activated according to the decode signal D2. The sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL3 and BLKR2 are activated according to the decode signal D3.

  In this embodiment, the sense amplifier block SA or the write amplifier block WA that operates simultaneously always belongs to the row memory block group RBLK adjacent vertically. For this reason, when the sense amplifier block SA or the write amplifier block WA operates, the power supply noise generated in the power supply line PWR is almost constant regardless of the position of the operating blocks SA and WA, and the variation is small. In general, the time required for the sense amplifier and the write amplifier to amplify the data signal becomes longer due to power supply noise. In the present invention, since variations in power supply noise are small, the amplification time of the sense amplifier and the write amplifier can be made substantially the same regardless of the access address. As a result, for example, the access time (read time and write time) of the SRAM can be made constant without depending on the access address.

  FIG. 6 shows a system LSI on which the SRAM shown in FIG. 1 is mounted. The above-described SRAM is mounted on a system LSI, for example. The system LSI has two SRAMs, a CPU, two interface circuits I / F, and a logic circuit LOGIC designed by the user. These circuits are formed by using transistors formed on a semiconductor substrate and five wiring layers W1-5 (not shown) sequentially stacked on the semiconductor substrate.

  The system LSI includes power supply lines RNG and PWR formed using the sixth wiring layer W6. Power supply line RNG is formed around the system LSI chip and connected to a power supply pad (not shown). The power supply line PWR is formed at a predetermined interval in the horizontal direction in the figure, and both ends thereof are connected to the power supply line RNG. In FIG. 6, only a part of the power supply lines PWR is shown for easy understanding. Actually, the power supply line PWR is formed on the entire system LSI chip including on the SRAM. By wiring the power supply lines RNG and PWR for supplying power to the entire system LSI chip using only one wiring layer W6, the total number of wiring layers can be reduced. As a result, the cost of the system LSI can be reduced.

  FIG. 7 shows an outline of the power supply line PWR wired on the SRAM in the system LSI shown in FIG. In this example, three power supply lines PWR are wired in the areas of the sense amplifier block SA and the write amplifier block WA. The power supply line PWR is connected to power supply terminals (not shown) of the sense amplifier block SA and the write amplifier block WA. In the regions of the sense amplifier block SA and the write amplifier block WA, there is a margin for wiring two more power supply lines PWR. Therefore, for example, the power supply line PWR connected to the logic circuit LOGIC shown in FIG. 6 can be wired in the areas of the sense amplifier block SA and the write amplifier block WA. Therefore, the degree of freedom of wiring of the design tool for laying out the power supply line can be increased, and the calculation time for layout can be shortened.

The pair of sense amplifier blocks SA connected to the power supply line PWR do not operate simultaneously. Similarly, the pair of write amplifier blocks WA connected to the power supply line PWR do not operate simultaneously. For this reason, the power supply noise generated by the operations of the blocks SA and WA is relatively small. Since power supply voltage drop caused by the operations of the blocks SA and WA can be reduced, malfunction of the sense amplifier and the write amplifier can be prevented. Note that power supply noise can be further reduced by increasing the number of power supply lines PWR.

  FIG. 8 shows details of the word line decoder of the SRAM before applying the present invention. This word line decoder has a decode circuit DEC0 corresponding to a pair of word lines WL (for example, LWL0 and RWL0) of a pair of column memory block groups CBLK.

  Each decode circuit DEC0 has a 4-input NAND gate and a pair of inversion circuits INV that receive the output of the NAND gate. The NAND gate receives one of the decode signals A0-3, one of the decode signals B0-3, one of the decode signals C0-3, and one of the decode signals C0-3, decodes these signals, and outputs the decode signal / ABCD is output. The inverting circuit INV operates by a common decode signal / ABCD. For this reason, the word lines LWL and RWL connected to the output of the inverting circuit INV are activated simultaneously. That is, a pair of word lines LWL and RWL belonging to the same row memory block group RBLK are activated simultaneously.

  FIG. 9 shows the decode signals D0-3 supplied to the sense amplifier block SA and the write amplifier block WA in the SRAM shown in FIG. In the SRAM before applying the present invention, the decode signal D0-3 is supplied in common to a pair of sense amplifier blocks SA and write amplifier blocks WA corresponding to each row memory block group RBLK. For this reason, the sense amplifier block SA or the write amplifier block WA arranged in the horizontal direction in the figure are simultaneously activated (for example, SA and WA shown by hatching in the figure corresponding to the memory blocks BLKL0 and BLKR0).

  FIG. 10 shows an outline of the power supply line PWR wired on the SRAM in the system LSI on which the SRAM shown in FIG. 8 is mounted. As described with reference to FIG. 9, before the application of the present invention, the sense amplifier blocks SA or the write amplifier blocks WA arranged in the horizontal direction in the figure are simultaneously activated. In order to prevent the sense amplifier block SA or the write amplifier block WA from malfunctioning due to the influence of the drop of the power supply voltage, more power supply lines PWR (5 than those in FIG. Are wired).

  The power supply line PWR shown in FIG. 10 is wired for the sense amplifier block SA and the write amplifier block WA. Therefore, these power supply lines PWR cannot be used to supply power to the logic circuit LOGIC (FIG. 6) formed on the right side of the sense amplifier block SA and the write amplifier block WA. Therefore, the degree of freedom of wiring of the design tool for laying out the power supply line PWR is reduced.

  As described above, in the first embodiment, power is supplied to the sense amplifier block SA (or write amplifier block WA) that operates simultaneously using different power supply lines PWR, so that power supply voltage drop can be reduced and the power supply line PWR can be reduced. Can reduce power supply noise. As a result, malfunction of the sense amplifier block SA and the write amplifier block WA can be prevented.

  The number of power supply lines PWR wired on the sense amplifier block SA and the write amplifier block WA can be reduced. Therefore, the power supply line PWR wired to the logic circuit LOGIC adjacent to the SRAM can be passed over the sense amplifier block SA and the write amplifier block WA. As a result, it is possible to increase the wiring freedom (layout margin) of the design tool for laying out the power supply line PWR, and to shorten the calculation time for layout.

  FIG. 11 shows decode signals D0-3 supplied to the sense amplifier block SA and the write amplifier block WA in the second embodiment of the semiconductor memory of the present invention. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the connection specifications of the decode signal lines D0-3 supplied from the row address decoder 16 (FIG. 1) to the sense amplifier block SA and the write amplifier block are different from those in the first embodiment. Other configurations are the same as those of the first embodiment.

  In this embodiment, the sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL0 and BLKR1 are activated according to the decode signal D0. The sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL1 and BLKR2 are activated according to the decode signal D1. The sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL2 and BLKR3 are activated according to the decode signal D2. In response to the decode signal D3, the sense amplifier block SA and the write amplifier block WA corresponding to the memory blocks BLKL3 and BLKR0 are activated (shown by shading in the figure). In other words, the signal lines D0-3 wired to supply the decode signals D0-3 to the sense amplifier block SA and the write amplifier block WA are different from each other in the pair of memory blocks BLK constituting each row memory block group RBLK. As mentioned above, also in 2nd Embodiment, the effect similar to 1st Embodiment mentioned above can be acquired.

  In the above-described embodiment, the example in which the present invention is applied to the SRAM has been described. However, the present invention includes a plurality of memory blocks arranged in a matrix, and a column memory block group assigned to different external data terminals I / O, or includes these semiconductor memories It can be applied to the system LSI. Examples of other semiconductor memories include DRAM, pseudo SRAM, SDRAM, FCRAM (Fast Cycle RAM), FeRAM (Ferroelectric RAM), and flash memory.

  In the above-described embodiment, the example in which the present invention is applied to an SRAM in which four memory blocks BLK are arranged in the vertical direction and two memory blocks BLK in the horizontal direction is described. However, the present invention can also be applied to SRAMs having matrix configurations other than those described above. In general, the present invention can be applied to a semiconductor memory in which 2 m memory blocks in the vertical direction and 2 n power blocks in the horizontal direction (m and n are integers of 1 or more) are arranged.

  The present invention can be applied to a semiconductor memory having a plurality of memory cell array blocks arranged in a matrix.

1 is a block diagram showing a first embodiment of a semiconductor memory of the present invention. FIG. 2 is a block diagram showing an outline of the layout of the SRAM shown in FIG. 1. FIG. 2 is a circuit diagram showing details of a row address decoder shown in FIG. 1. FIG. 2 is a circuit diagram showing details of a word line decoder shown in FIG. 1. FIG. 3 is a block diagram showing decode signals supplied to a sense amplifier block and a write amplifier block in the first embodiment. FIG. 2 is a block diagram showing a system LSI on which the SRAM shown in FIG. 1 is mounted. FIG. 7 is a layout diagram showing an outline of power supply lines wired on an SRAM in the system LSI shown in FIG. 6. It is a circuit diagram which shows the detail of the word line decoder of SRAM before applying this invention. FIG. 9 is a block diagram showing decode signals supplied to a sense amplifier block and a write amplifier block in the SRAM shown in FIG. 8. FIG. 9 is a layout diagram showing an outline of power supply lines wired on the SRAM in the system LSI on which the SRAM shown in FIG. 8 is mounted. FIG. 6 is a block diagram showing decode signals supplied to a sense amplifier block and a write amplifier block in a second embodiment of the semiconductor memory of the present invention.

Explanation of symbols

10 operation control circuit 12 address input circuit 14 data input / output circuit 16 row address decoder 18 word line decoder 20 column address decoder 22 column switch decoder ARY memory cell array BL real bit line CSW column switch circuit DEC decode circuit MC real memory cell PWR power line SA sense amplifier block WA write amplifier block WL word line

Claims (5)

A plurality of memory blocks each having a plurality of memory cells and arranged in a matrix;
A plurality of column memory block groups configured by a predetermined number of memory blocks arranged in the vertical direction and arranged in the horizontal direction;
A plurality of row memory block groups configured by a predetermined number of memory blocks arranged in the horizontal direction and arranged in the vertical direction;
A plurality of amplifier circuit blocks, each disposed at one end of the memory cell block, for amplifying data input to and output from the memory cell;
A first row address decoder that activates one of a plurality of first decode signals in response to a first row address in order to activate one of the amplifier circuit blocks for each column memory block group;
The first decode signal is wired to transmit the first decode signal from the first row address decoder to the amplifier circuit block, and the different first decode signals are supplied to the amplifier circuit blocks corresponding to the row memory block groups. A plurality of decode signal lines;
A semiconductor memory comprising: a power supply line commonly connected to an amplifier circuit block corresponding to each row memory block group. The semiconductor memory according to claim 1.
A plurality of word lines formed in each of the memory blocks and connected to the memory cells;
A second row address decoder that activates one of a plurality of second decode signals in response to a second row address signal in order to activate one of the word lines for each column memory block group;
A word line decoder having a plurality of decoding circuits corresponding to the pair of word lines of the pair of column memory block groups;
Each of the decoding circuits
A first logic circuit for generating a third decode signal common to the pair of word lines in response to the second decode signal;
A pair of second logic circuits formed corresponding to each of the pair of word lines and activating corresponding word lines in response to the third decode signal and the first decode signal;
In each of the decode circuits, the first decode signal received by the pair of second logic circuits is different from each other. The semiconductor memory according to claim 1.
The semiconductor memory, wherein the amplifier circuit block includes a plurality of sense amplifiers that amplify a signal amount of data read from the memory cell. The semiconductor memory according to claim 1.
The semiconductor memory according to claim 1, wherein the amplifier circuit block includes a plurality of write amplifiers that amplify a signal amount of data to be written to the memory cell. A system LSI in which a semiconductor memory and a logic circuit are mounted, and a plurality of power supply lines facing in one direction are formed using a predetermined wiring layer on a semiconductor substrate,
The semiconductor memory is
A plurality of memory blocks each having a plurality of memory cells and arranged in a matrix;
A plurality of column memory block groups configured by a predetermined number of memory blocks arranged in the vertical direction and arranged in the horizontal direction;
A plurality of row memory block groups configured by a predetermined number of memory blocks arranged in the horizontal direction and arranged in the vertical direction;
A plurality of amplifier circuit blocks, each disposed at one end of the memory cell block, for amplifying data input to and output from the memory cell;
A first row address decoder that activates one of a plurality of first decode signals in response to a first row address in order to activate any one of the amplifier circuit blocks for each column memory block group;
The first decode signal is wired to transmit the first decode signal from the first row address decoder to the amplifier circuit block, and the different first decode signals are supplied to the amplifier circuit blocks corresponding to the row memory block groups. A plurality of decode signal lines;
A power line commonly connected to the amplifier circuit block corresponding to each row memory block group,
The system LSI, wherein the one direction is the horizontal direction.

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