JP2006318334A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor with excellent security protection of data and the easiness of debug. <P>SOLUTION: The processor is provided with: a decision circuit (131) for deciding whether or not the processor is in a secure state without observation from outside when a module (150) requiring security and an internal bus (160) capable of accessing the module are included; and a bus access shielding circuit (151) for separating the module from the internal bus on the basis of the decision result of the decision circuit. The security of the module is protected by the module, which requires the security, being separated from the internal bus. Also, by allowing an access via the internal bus with respect to other modules which do not require the security, debug is made possible. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly to a security and debugging function in the information processing apparatus.

  As represented by a microprocessor used as an example of an information processing apparatus, for example, as used in a portable device, hardware and software are becoming more complicated due to demands for improving the convenience of the device. On the other hand, in today's portable devices, there are increasing opportunities to handle data such as personal information and billing information that require higher confidentiality and security.

  As hardware and software become more complex, debugging functions for processor internal operations are becoming more sophisticated year by year for the purpose of improving development efficiency. In today's processors, these functions can be used to connect and operate signals to some external pins of a semiconductor integrated circuit (semiconductor integrated circuit), enabling easy and extensive operation and analysis of the processor's internal operations. It is an essential function for today's software development.

  Such a debugging function can also be used in a semiconductor integrated circuit mounted on a device as a product because of its easy connection. However, as described above, the confidentiality of data is required in today's portable devices, and an advanced debugging function is one factor that hinders the confidentiality of data. As a technique for solving these conflicting problems, a method and a computer system for setting a security computer environment are known (see, for example, Patent Document 1).

JP 2002-358137 A (FIG. 1)

  For example, as in the technique described in Patent Document 1, a latch indicating whether or not confidential information exists is provided in the microprocessor. When the confidential information exists, By shutting off the connection of the in-circuit emulator device which is an external control device, it is possible to protect confidential information. However, in a short period from the reset of the microprocessor to the completion of the latch state setting, operations such as extracting confidential information from the emulator device or invalidating the latch state setting itself may be performed. Further, if it is impossible to use any debugging function after the confidential information is set, the ease of debugging of the microprocessor is hindered.

  An object of the present invention is to provide an information processing apparatus that is excellent in data confidentiality protection and easy debugging.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] That is, in an information processing apparatus including an internal bus and a module accessed via the internal bus, a state in which observation from the outside is not received is set to a secure state, and a state in which observation from the outside is not performed A determination circuit for determining whether the state is a secure state or a non-secure state, and a bus access blocking circuit for disconnecting the module from the internal bus based on a determination result of the determination circuit Provide.

  According to the above means, the determination circuit determines whether the state is the secure state or the non-secure state, and the bus access blocking circuit disconnects the module from the internal bus based on the determination result of the determination circuit. By separating the module requiring confidentiality from the internal bus, the confidentiality of the module is protected. Also, other modules that do not require confidentiality can be debugged by making them accessible via the internal bus. This achieves the provision of an information processing apparatus excellent in the protection of confidentiality of data and the ease of debugging.

  [2] In an information processing apparatus including an internal bus and a module accessed via the internal bus, a state in which no external observation is received is set to a secure state, and a state in which external observation is received is set to a non-secure state The module scans the module based on a determination circuit that determines whether the module is in a secure state or a non-secure state, a scan path that can scan the internal state of the module, and a determination result of the determination circuit. A scan path cutoff circuit for separating from the path is provided.

  According to the above means, the scan path blocking circuit disconnects the module from the scan path based on the determination result of the determination circuit. The module requiring confidentiality is disconnected from the scan path, so that the confidentiality of the module is protected. Further, other modules that do not require confidentiality can be scanned by the scan path, thereby enabling debugging. This achieves the provision of an information processing apparatus excellent in the protection of confidentiality of data and the ease of debugging.

  [3] In the above [2], a bus access blocking circuit for disconnecting the module from the internal bus based on the determination result of the determination circuit can be provided.

[4] In the above [3], the information processing apparatus includes a debug function controller that enables debugging of internal operations;
An external terminal capable of designating whether the debug function is valid or invalid in the debug function controller, and the determination circuit performs a determination between a secure state and a non-secure state based on a logic state of the external terminal Can be configured.

  [5] In the above [3], the information processing apparatus includes a central processing unit accessible to the module via the internal bus, and the determination circuit generates an internal signal indicating an operation state of the central processing unit. Based on this, it can be configured to determine the secure state and the non-secure state.

  [6] In the above [4], the determination circuit can be configured to transition from the non-secure state to the secure state when the transition instruction signal is asserted by the debug function controller.

  [7] In the above [6], including a first register for storing a command for inputting a personal identification key, and a second register for storing a personal identification key input based on the command, When the command in the first register matches the secret key in the second register, the transition instruction signal can be asserted by the debug function controller.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide an information processing apparatus that is excellent in data confidentiality protection or debugging ease.

  FIG. 2 shows an overall configuration example of a microprocessor which is an example of an information processing apparatus according to the present invention. The microprocessor 100 shown in FIG. 2 is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

  A central processing unit (CPU) 140 is provided, and the central processing unit 140 performs predetermined arithmetic processing according to a preset program. An MPEG image compression accelerator (MPEG) 181 is provided, and the MPEG image compression accelerator 181 performs compression processing of MPEG (Motion Picture Experts Group) images. A direct memory access controller (DMAC) 182 is provided, and this direct memory access controller 182 enables data exchange with an SRAM (Static Random Access Memory) 187 without the intervention of the CPU 140. A debug test controller (DBGCNT) 110 is provided, and this debug test controller 110 is connected to the outside via a JTAG (IEEE 1149.1, “IEEE Standard Test Access Port and Boundary-Scan Architecture”) bus 311. Signal exchange is enabled, and the debugging operation of the internal operation of the microprocessor 100 is controlled. A cryptographic accelerator (CRYPTO) 150 is provided, and the cryptographic accelerator 150 performs encryption / authentication processing. Here, the cryptographic accelerator (CRYPTO) 150 is an example of a functional module that holds information that requires confidentiality. A bus access blocking circuit (BREAK) 151 is provided. The bus access blocking circuit (BREAK) 151 prohibits access via the internal bus 160 by disconnecting the cryptographic accelerator 150 from the internal bus 160. An interrupt controller (INTC) 183 is provided, and the interrupt controller 183 performs interrupt processing for the CPU 140 in accordance with a predetermined interrupt priority order. A system controller (SYSC) 184 is provided, and this system controller 184 controls the operation of various functional modules in the microprocessor 100. A security state controller (SECC) 130 is provided, and this security state controller 130 determines whether the current state is a secure state that does not receive external observation or a non-secure state that receives external observation. Based on this, the operation of the bus access blocking circuit 151 and the like is controlled. A bus state controller (BSC) 185 is provided, and this bus state controller 185 controls the bus state when the SRAM 187 coupled via the memory bus 186 is accessed. A system reset controller (RSTCNT) 120 is provided, and this system reset controller 120 determines the output of the reset signal 322 to each part in the microprocessor 100.

  FIG. 1 shows a detailed configuration of the main part of the microprocessor 100.

  The debug function controller 110 is activated by a debug function enable signal 310 fetched from the outside, and operates in response to a command input from the JTAG bus 311. In the operation, the internal state of the microprocessor is output by the scan path 200, the internal state of the microprocessor is designated by the input, and the CPU 140 is accessed via the internal bus 160. The system reset controller 120 determines the output of the reset signal 322 to the entire microprocessor based on the input of the reset signal 320 that is an external input and the internal reset request signal 321 from the CPU 140.

  The security state controller 130 includes a determination circuit (JUDG) 131 that determines whether it is a secure state or a non-secure state, and a register 132 that can hold the determination result, and whether or not the current state is secure. A secure state signal 350 indicating that is output. Here, the secure state means a state in which no external observation is received. Conversely, the non-secure state refers to a state that receives observation from the outside. Here, the determination circuit 131 includes a debug function enabling signal 310, a reset signal 320 fetched via the external terminal T2, an internal reset request signal 321, a security function validation signal 330 fetched via the external terminal T3, and a debug function. Based on various signals such as a secure state transition instruction signal 340 for instructing a transition to the secure state from the controller 110, it is determined whether or not the secure state is established. In particular, it is determined whether or not the secure state is set according to the logic state of the external terminal T1 for taking in the debug function enabling signal 310 that can specify whether the debug function is enabled or disabled in the debug function controller 110. When the debug function is enabled by the debug function enable signal 310, it is determined as a non-secure state. The determination circuit 131 is also determined to be in a non-secure state when an internal signal indicating the operation state of the CPU 140, for example, the internal reset request signal 321 is validated. The determination result in the determination circuit 131 is held in the secure state register 132. The value of the secure state register 132 is supplied to the bus access cutoff circuit 151 and the scan path cutoff circuits 210 and 220.

  FIG. 3 shows the state transition of the determination circuit 131.

  Reference numerals 401 to 405 represent states in the microprocessor. Reference numeral 403 denotes a secure state in the microprocessor. Reference numeral 401 denotes a power-off state (Power Off). A transition 501 occurs due to the supply of power and assertion of the reset signal 320 from the outside, and a resetting state (Power-On Reset) 402 indicating that resetting is in progress. Transition to.

  When the reset signal 320 is negated in the reset state 402, the state transits to the secure state 403 or the non-secure state 404 via the transition 511 or 512. Whether the transition 511 occurs or the transition 512 occurs is determined by the logic state of the debug function enabling signal 310 and the security function enabling signal 330 when the reset signal 320 is negated. Only when the debug function enabling signal 310 is negated and the security function enabling signal 330 is asserted, that is, when the debug function is disabled and the security function is enabled, the resetting state 402 A transition 511 from to the secure state 403 occurs.

  When the reset signal 320 is asserted in the secure state (Secure) 403, the non-secure state (Non Secure) 404, and the reset state (Internal Reset) 405, the resetting state is caused by the transitions 521, 522, and 523, respectively. Transition to 402.

  In the secure state 403 and the non-secure state 404, the CPU 140 is executing a program, and depending on a spontaneous request from the program or a request generated by an abnormal state in the CPU 140 caused by an unintended operation of the program, The internal reset request signal 321 is asserted. In that case, the transition to the reset state 405 by the internal reset request is made by transitions 531 and 532.

  From state 405, transition 533 occurs due to the release of reset, and only non-secure state 404 can be reached. This is because, as described above, the occurrence of the reset state 405 due to the internal reset request may be caused by an unintended operation of the program, and it is meaningful to prevent the secure resource 150 from being accessed by an unauthorized program.

  Also, from the state 404, when a notification of the secure state transition instruction signal 340, which is a transition instruction signal from the debug function controller, is received, a transition 541 occurs and the state transitions to the state 403.

  The operations of the bus access blocking circuit 151 and the scan path blocking circuits 210 and 220 are determined by the secure state register 132 determined as described above. The bus access blocking circuit 151 allows information access to the secure resource 150 by passing the bus access from the microprocessor internal bus 160 if it is in the secure state according to the contents of the secure state register 132, and on the contrary. In the secure state, the information of the secure resource 150 is protected by blocking the bus access via the bus access blocking circuit 151.

  When the determination circuit 131 determines that the secure state is established, the switches in the scan path blocking circuits 210 and 220 in FIG. 1 are connected to the nodes 211 and 221 side, and the scan path including the secure resource 160 is configured. Is done. In this state, the scan path 200 allows the test pattern signal to be scanned in and out.

  On the other hand, when the determination circuit 131 determines that it is in the non-secure state, the switches in the scan path blocking circuits 210 and 220 are connected to the nodes 212 and 222 side. That is, the cryptographic accelerator 150 is disconnected from the scan path 200 by the scan path blocking circuits 210 and 220, thereby preventing information in the cryptographic accelerator 150 from flowing out through the scan path 200 (security protection). In this case, since the switches in the scan path blocking circuits 210 and 220 are connected to the nodes 212 and 222 side, the scan path 200 bypasses the cryptographic accelerator 150. Other than the cryptographic accelerator 150, Scan-in and scan-out by the scan path 200 is possible.

  Next, the operation when the cryptographic accelerator 150 is accessed from the CPU 140 or the like via the internal bus 160 will be described.

  FIG. 4 shows a timing chart in a state where the secure state is indicated by the flag setting of the secure state register 132, that is, in a state where the cryptographic accelerator 150 is coupled to the internal bus 160 by the bus access cutoff circuit 151.

  In FIG. 4, 600 and 601 indicate operation clock periods (cycle periods) of the bus 160. Reference numerals 610, 611, and 612 denote bus access requests, commands, and address signals for the cryptographic accelerator 150, respectively. The address value indicated by 613 is an address assigned to the cryptographic accelerator 150. Reference numerals 620, 621, and 622 denote a bus access acceptance response, an access permission / non-permission response, and data from the cryptographic accelerator 150, respectively. In a state where the cryptographic accelerator 150 is coupled to the internal bus 160 by the bus access blocking circuit 151, an access permission state (OK) is indicated in the cycle period 601 for the read command output in the cycle period 600, and Read data 623 is output to the internal bus 160.

  FIG. 5 shows a timing chart in a state where the non-secure state is indicated by the flag setting of the secure state register 132, that is, the state where the cryptographic accelerator 150 is disconnected from the internal bus 160 by the bus access cutoff circuit 151.

  5, 700 and 701 indicate the operation clock period (cycle period) of the bus 160, and the signals 610, 611, 612, 620, 621, and 622, and the address value of 613 are the same as those shown in FIG. It is the same.

  When the cryptographic accelerator 150 is disconnected from the internal bus 160 by the bus access cutoff circuit 151, the read command issued from the cycle period 700 is only denied access (NG) in the cycle period 701. The data output to the internal bus 160 and the data in the cryptographic accelerator 150 is not output to the internal bus 160.

  FIG. 6 shows an operation until the debug function controller 110 asserts the secure state transition instruction signal 340. In the figure, TCK, TRST * (* indicates low active), TMS, and TDI are signals included in the JTAG bus 311. TAP-STATE indicates the state of the state machine in the debug function controller 110 compliant with JTAG, and SDIR and SDDR are registers in the debug function controller 110. Reference numerals 800 to 820 denote clock cycle periods synchronized with the TCK signal.

  In cycle 800, TRST *, which is a reset signal for TAP-STATE, is released, and after cycle 801, the values of TAP-STATE and internal registers are set according to the input of TMS and TDI signals.

  In cycles 805 to 808, a command 830 for inputting a secret key for outputting a secure state transition instruction signal is input from TDI, and in cycle 810, the command is stored in the SDIR register. The personal identification key 831 is input from TDI from cycle 813 to cycle 816, and the personal identification key 831 is stored in the SDDR register in cycle 819.

  The secure state transition instruction signal 340 is negated until cycle 819, but in cycle 820, the command 830 stored in SDIR and SDDR respectively matches the data of the personal identification key 831 in cycle 820. Is asserted at. If the command 830 and the data of the secret key 831 do not match, the secure state transition instruction signal 340 is not asserted.

  According to the above example, the following effects can be obtained.

  (1) The secure state determination circuit 131 determines whether it is in a secure state or a non-secure state, and the bus access blocking circuit 151 transfers the cryptographic accelerator 150 to the internal bus based on the determination result of the secure state determination circuit 131. Disconnect from 160. Only the cryptographic accelerator 150 requiring confidentiality is disconnected from the internal bus 160, so that the confidentiality of the cryptographic accelerator 150 is protected. Other functional modules that do not require confidentiality can be debugged by making them accessible via the internal bus 160. As a result, both confidentiality of data and ease of debugging can be achieved.

  (2) The scan path cutoff circuits 210 and 220 disconnect the cryptographic accelerator 150 from the scan path 200 based on the determination result of the secure state determination circuit 131. By separating the cryptographic accelerator 150 requiring confidentiality from the scan path 200, the confidentiality of the cryptographic accelerator 150 is protected. Further, other functional modules that do not require confidentiality can be scanned by the scan path 200, thereby enabling debugging. As a result, both confidentiality of data and ease of debugging can be achieved.

  (3) In the configuration shown in FIG. 1, since both the effects (1) and (2) are achieved, the confidentiality of data and the ease of debugging are further improved.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, the input condition for outputting the secure state transition instruction signal in FIG. 6 can be changed to a protocol using public key cryptography or the like instead of simple secret key input.

  In the above description, the case where the invention made mainly by the present inventor is applied to the microprocessor which is a field of use as the background has been described. However, the present invention is not limited to this and is widely applied to various information processing apparatuses. Can be applied.

  The present invention can be applied on condition that at least a module requiring confidentiality is included.

1 is a block diagram illustrating a configuration example of a main part of a microprocessor as an example of a semiconductor integrated circuit according to the present invention. It is a block diagram of an example of the overall configuration of the microprocessor. It is state transition explanatory drawing of the determination circuit contained in the said microprocessor. It is a timing diagram of main operations in the microprocessor. It is a timing diagram of main operations in the microprocessor. It is a timing diagram of main operations in the microprocessor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Microprocessor 110 Debug function controller 120 System reset controller 130 Security state controller 131 Secure state determination circuit 132 Secure state register 140 CPU
150 Cryptographic Accelerator 151 Bus Access Blocking Circuit 160 Internal Bus 200 Scan Path 210, 220 Scan Path Blocking Circuit 310 Debug Function Enable Signal 311 JTAG Bus 320 Reset Signal 321 Internal Reset Request Signal 330 Security Function Enable Signal

Claims (7)

An internal bus,
An information processing apparatus including a module accessed via the internal bus,
When the state that does not receive external observations is set to the secure state and the state that receives external observations is set to the non-secure state,
A determination circuit for determining whether the secure state or the non-secure state;
An information processing apparatus comprising: a bus access cutoff circuit for disconnecting the module from the internal bus based on a determination result of the determination circuit. An internal bus,
An information processing apparatus including a module accessed via the internal bus,
When the state that does not receive external observations is set to the secure state and the state that receives external observations is set to the non-secure state,
A determination circuit for determining whether the secure state or the non-secure state;
A scan path capable of scanning the internal state of the module;
An information processing apparatus comprising: a scan path cutoff circuit for separating the module from the scan path based on a determination result of the determination circuit. The information processing apparatus according to claim 2, further comprising a bus access cutoff circuit for disconnecting the module from the internal bus based on a determination result of the determination circuit. The information processing apparatus includes a debug function controller that enables debugging of internal operations;
An external terminal capable of designating whether the debug function is valid or invalid in the debug function controller, wherein the determination circuit determines a secure state and a non-secure state based on a logical state of the external terminal. 3. The information processing apparatus according to 3. The information processing apparatus includes a central processing unit that is accessible to the module via the internal bus, and the determination circuit is in a secure state and a non-secure state based on an internal signal indicating an operation state of the central processing unit. The information processing apparatus according to claim 3, wherein the determination is performed. The information processing apparatus according to claim 4, wherein the determination circuit transitions from a non-secure state to a secure state when a transition instruction signal is asserted by the debug function controller. A first register for storing a command for inputting a personal identification key;
A second register for storing a secret key input based on the command, and the debug function when the command in the first register matches the secret key in the second register. The information processing apparatus according to claim 6, wherein the transition instruction signal is asserted by the controller.

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