JP2006313765A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit provided with a wiring structure capable of lowering the maximum value of a reduction rate of power supply voltage from a power source of a power source wiring to a portion to be supplied with power, while maintaining the wiring area of the power source wiring. <P>SOLUTION: The semiconductor integrated circuit 100 includes wirings 3, 7 for power supply connected to power supply terminals 1, 2; and a plurality of power supplies 4, 5, 6 connected to the wirings 3, 7 for power supply and to be supplied with power. The wirings 3, 7 for power supply have branches 1a, 1b and 2a, 2b; and are each divided over connections between the branches 1a, 1b and 2a, 2b to the power supplies 4, 5, 6, so that the reduction rate of the power supply voltage from the power supply terminal to each of the power supplies 4, 5, 6 may become equal while maintaining the defined wiring area of the wirings 3, 7 for power supply. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit provided with power supply wiring for supplying power to a power supply target part.

  In recent years, with the increase in scale, integration, and miniaturization of logic LSIs, for example, the voltage drop in power supply wiring due to an increase in power supply wiring resistance tends to increase. In a portion where the voltage drop is large, for example, the operation of the logic gate may be delayed or a malfunction may be caused.

  For example, as a conventional semiconductor integrated circuit, a circuit portion that performs a predetermined circuit operation, a mesh-like power supply wire that is disposed on the circuit portion and supplies power to the circuit portion, and a power supply pad connected to the power supply wire The power supply voltage drop is suppressed by attaching a binary tree-shaped reinforcing power supply wiring from the power supply terminal to the main line of the power supply wiring (see, for example, Patent Document 1).

  However, the prior art has a problem that the wiring area of the power supply wiring is increased by the amount of the attached reinforcing power supply wiring.

  In addition, as another conventional semiconductor integrated circuit, a logic circuit that performs a predetermined logic operation, a first power supply wiring that is disposed on the logic circuit unit and supplies power to the logic circuit unit, and a first circuit on the logic circuit. And a second power supply wiring disposed in a different layer from the first power supply wiring and connected to the first power supply wiring through a contact at a crossing portion, and a voltage drop amount of the logic circuit portion is minimized. As described above, there is one that adjusts the number and position of contacts of a power supply wiring (see, for example, Patent Document 2).

  However, in the above prior art, for example, when a power supply source and a plurality of power supply destinations are arranged in series on the same power supply wiring, those that are far from the power supply source among those power supply destinations are close There is a problem that the amount of power supply voltage drop is larger than that.

  As another conventional semiconductor integrated circuit, first, the total width of the power supply wiring is calculated, and based on this result, different power supply wiring is connected to the circuit area near the outside of the chip and the circuit area located in the center of the chip. As described above, there is one that determines the width and number of individual power supply lines for each circuit area by dividing or combining the power supply lines to each circuit area (see, for example, Patent Document 3).

However, in the above prior art, for example, based on the wiring information and power consumption information of each circuit area, the wiring width and number of power supply wirings in the circuit area are suppressed so as to suppress the voltage drop in the circuit area located in the center of the chip. However, there is a problem that the resistance cannot be optimized for the power supply wiring in which a plurality of wiring layers having different sheet resistances are combined.
Japanese Patent Application Laid-Open No. 11-45979 (page 5-6, FIG. 1) Japanese Patent Laid-Open No. 10-284690 (page 4-5, FIG. 1) JP 2003-167936 A (page 3-4, FIG. 4)

  The present invention solves the above-described problem, and can maintain the wiring area of the power supply wiring and can reduce the maximum value of the power supply voltage drop amount from the power supply to the power supplied portion in the power supply wiring. An object of the present invention is to provide a semiconductor integrated circuit having a structure.

  A semiconductor integrated circuit according to an embodiment of the present invention includes a power supply wiring connected to a power supply terminal, and a plurality of power supplied parts connected to the power supply wiring and supplied with power. The power supply wiring has a branch portion so that the amount of power supply voltage drop from the power supply terminal to each of the power supplied parts becomes equal while maintaining the prescribed wiring area of the power supply wiring. Further, it is divided from the branching portion to the connecting portion with each of the power supplied portions.

  According to the present invention, since the power supply wiring is divided and the partial wiring that maintains the wiring area defined in the design of the power wiring is provided, the power supply from the power source in this power wiring is maintained while maintaining the wiring area. A semiconductor integrated circuit having a wiring structure capable of reducing the maximum value of the power supply voltage drop to the supply unit can be provided.

  Embodiments according to the present invention will be described below with reference to the drawings.

  In this embodiment, a description will be given based on a plan view showing a simplified main part of a semiconductor integrated circuit and a circuit diagram to which the wiring structure of the semiconductor integrated circuit is applied.

  FIG. 1 is a plan view showing a configuration of a main part of a semiconductor integrated circuit according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the semiconductor integrated circuit 100 includes a first power supply wiring 3 connected to the first power supply terminal 1 and a second power supply wiring connected to the second power supply terminal 2. 7 and a plurality of power supplied parts 4, 5 and 6 connected between the first power supply wiring 3 and the second power supply wiring 7 and supplied with power. The potential on the low potential side (second power supply terminal 2) is set to a circuit reference voltage of 0 volts, and the power supply voltage Vdd volts is supplied to the high potential side (first power supply terminal 1).

  The first power supply wiring 3 and the second power supply wiring 7 have a length 3L and a width W, respectively.

  The first power supply wiring 3 is provided between the first power supply terminal 1 and each of the power supplied parts 4, 5, 6, here, the first power supply terminal 1 and the first power supply terminal 3. The connecting portion has branch portions 1a and 1b. The first power supply wiring 3 maintains the wiring area defined in the design of the first power supply wiring 3 from the first power supply terminal 1 to each of the power supplied parts 4, 5. , 6, the partial wirings 3 a, 3 b, 3 c, 7 a, from the branch parts 1 a, 1 b to the connection parts of the power supply parts 4, 5, 6 are equalized. It is divided into 7b and 7c. That is, the first power supply wiring 3 is divided so as to correspond one-to-one from the first power supply terminal 1 to the connection portions with the power supplied parts 4, 5, 6.

  As a result, the power supply parts 4, 5 are provided at the terminal portions of the partial wirings 3 a, 3 b, 3 c, 7 a, 7 b, 7 c at distances 1 L, 2 L, 3 L from the first power supply terminal 1 and the second power supply terminal 2, respectively. , 6 are connected to each other.

  The first power supply wiring 3 having the branch portions 1a and 1b and the second power supply wiring 7 having the branch portions 2a and 2b are mainly used for laying the power supply wiring. Wiring layer, wiring layer formed by thick film process compared to lower wiring layer, and main wiring of power supply wiring such as wiring layer passing through half or more of total wiring layer It is done.

  Here, the width of each partial wiring is determined so that the amount of voltage drop in each partial wiring is equal. In the present embodiment, as shown in FIG. 1, the partial wiring 3 a connected to the power supplied part 4 has a width of about 0.196 W. In addition, the partial wiring 3b connected to the power supplied part 5 has a width of about 0.401 W and a width of about 0.383 W for each section of length L from the first power supply terminal 1. In addition, the partial wiring 3c connected to the power supplied part 6 has a width of about 0.403 W, about 0.603 W, and 1 W for each section of length L from the first power supply terminal 1. The partial wirings 7a, 7b, 7c connected to the respective power supplied parts 4, 5, 6 of the second power supply wiring 7 have the same wiring width.

  Here, the wiring area (3LW) occupied by the first power supply wiring 3 and the second power supply wiring 7 is the power supply main line in the case where the power supply wiring does not have a branch portion. It is the same as the wiring area (3LW) defined in the design.

  Next, a circuit configuration in which the voltage source Vdd is connected between the first power supply terminal 1 and the second power supply terminal 2 in FIG. FIG. 2 is a circuit diagram showing a configuration of a main part of the semiconductor integrated circuit according to the first embodiment of the present invention. In the following description, it is assumed that the same constant current I flows through each power supply section for simplicity.

  As shown in FIG. 2, the first power supply wiring 3 and the second power supply wiring 7 of FIG. 1 are represented by resistances between the respective contacts of the power supply wiring. Moreover, each power supply part 4,5,6 of FIG. 1 is represented by the structure which combined the current source of the electric current amount I, and the norator.

  The resistance values of the partial wirings 3a, 3b, and 3c of the first power supply wiring 3 are obtained based on the width and length of each wiring shown in FIG. Here, for example, the resistance value of the partial wiring 3a obtained by the circuit simulation is 5.10R. Further, the resistance value of the partial wiring 3b is 2.49R in the 1L section and 2.61R in the 2L section, and the total is 5.10R. Similarly, the resistance value of the partial wiring 3c is 5.10R. Thus, the resistance values of the partial wirings 3a, 3b, and 3c are equal.

  Here, as a comparative example, for example, when the branch portion is not formed for each of the first power supply wiring 3 and the second power supply wiring 7, that is, the length 3L and the width of each power supply wiring. Let us consider a case where the power supplied parts 4, 5 and 6 are provided at distances 1L, 2L and 3L from the first power supply terminal and the second power supply terminal, respectively. Here, the resistance value of the length L and the width W of the wiring is R. In this case, the power supply voltage drop to each of the power supplied parts 3 and 7 is 3IR for the power supplied part 4, 5IR for the power supplied part 5, and 6IR for the power supplied part 6.

  Therefore, the maximum value of the power supply voltage drop in this comparative example is 6IR. The sum of the maximum values of the voltage drop amounts on the high potential side and the low potential side is 12IR, which is twice the maximum value of each voltage drop amount. Note that the wiring area of each power supply wiring is 3 LW, which is an area defined by design.

  On the other hand, as shown in FIG. 2, in this embodiment, the power supply voltage drop of each power supplied portion is caused by the partial wiring for each of the first power supply wiring 3 and the second power supply wiring 7. Since a constant current I flows through 3a, 3b, and 3c, 5.1IR is obtained in each of the power supplied parts 4, 5, and 6. Therefore, the maximum value of the power supply voltage drop is 5.1 IR. The sum of the maximum values of the voltage drop amounts on the high potential side and the low potential side is 10.2 IR, which is smaller than that in the case where no branch portion is formed in the power supply wiring.

  In this way, by dividing the power supply wiring by forming a branch portion and supplying power to each power supply from each of the divided partial wirings, for example, an area defined in design (here, 3LW), the maximum voltage drop in the power supply wiring can be reduced. Therefore, it is not necessary to change the area of another circuit configuration, and it is possible to cope with the circuit design.

  The first power supply wiring 3 and the second power supply wiring 7 are directly or via other cells or wirings due to, for example, electromigration restrictions, dimension restrictions, or design restrictions determined by the designer. It is possible to divide by forming a branching portion except when it is difficult to be constant due to restrictions imposed indirectly.

  In this embodiment, the amount of power supply voltage drop in the main line of the power supply wiring, which is the power supply wiring, is controlled only by the wiring width. However, the number of wirings and the type of wiring layer (for example, wirings having different electrical conductivities) Layer), etc., may be controlled by connection between a plurality of power supply wirings of the same potential.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, the power supply wiring is divided by forming a branch portion, and power is supplied to each power supply from each divided partial wiring. The maximum value of the power supply voltage drop in the main line of the power supply wiring can be reduced while maintaining the wiring area defined in the design.

  In the first embodiment, the configuration in which the branch portion is formed at the connection portion between the power supply terminal and the power supply wiring is described. In this embodiment, the configuration in which the branch portion is formed in the power supply wiring is described.

  FIG. 3 is a plan view showing the configuration of the main part of the semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 3, the semiconductor integrated circuit 100 a includes a first power supply wiring 3 connected to the first power supply terminal 1 and a second power supply wiring connected to the second power supply terminal 2. 7 and a plurality of power supplied parts 4, 5 and 6 connected between the first power supply wiring 3 and the second power supply wiring 7 and supplied with power.

  The first power supply wiring 3 has a branching portion 1a at the connection portion between the first power supply terminal 1 and the first power supply terminal 3, and a branching portion 1b at a distance L from the first power supply terminal 1. is doing. The first power supply wiring 3 maintains the wiring area defined in the design of the first power supply wiring 3 from the first power supply terminal 4, 5, The power supply voltage drop amounts up to 6 are equal to each other from the branch parts 1a and 1b to the connection parts of the power supply parts 4, 5 and 6.

  That is, the first power supply wiring 3 is branched into partial wirings 3 e and 3 d at a branching portion 1 a of a connection portion with the first power supply terminal 1. The partial wiring 3d is branched into partial wirings 3g and 3f at a branching portion 1b at a distance L from the first power supply terminal 1. Terminal portions of these branched partial wirings 3e, 3g, and 3f are connected to the respective power supplied parts 4, 5, and 6. Similarly, the second power supply wiring 7 is branched into partial wirings 7e and 7d at a branching portion 2a connected to the second power supply terminal 2. The partial wiring 7d is branched into partial wirings 7g and 7f at a branching portion 2b at a distance L from the second power supply terminal 2. Terminal portions of these branched partial wirings 7e, 7g, and 7f are connected to the respective power supplied parts 4, 5, and 6.

  Here, the width of each partial wiring is determined so that the amount of voltage drop in each partial wiring is equal. In this embodiment, the widths of the partial wirings 3e and 7e connected to the power supplied part 3 are about 0.209W. Further, the widths of the partial wirings 3d and 7d serving as a common part connected to the power supplied parts 4 and 5 are about 1.062W. The widths of the partial wirings 3g and 7g connected to the power supplied part 4 are about 0.346W, and the widths of the partial wirings 3f and 7f connected to the power supplied part 5 are about 0.691W. Thereby, the wiring area of each of the power supply wirings 3 and 7 is 3 LW.

  Therefore, the wiring area (3LW) occupied by each of the first power supply wiring 3 and the second power supply wiring 7 is a power supply trunk design when the power supply wiring does not have a branching portion. This is the same as the wiring area (3LW) defined above.

  Next, a circuit configuration in which the voltage source Vdd is connected between the first power supply terminal 1 and the second power supply terminal 2 in FIG. FIG. 4 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit according to the second embodiment of the present invention. In the following description, it is assumed that the same constant current I flows through each power supply section for simplicity.

  As shown in FIG. 4, the first power supply wiring 3 and the second power supply wiring 7 in FIG. 3 are represented by resistances between the respective contacts of the power supply wiring. Further, each of the power supplied parts 4, 5, and 6 in FIG.

  The resistance values of the partial wirings 3d, 3e, 3f, and 3g of the first power supply wiring 3 are obtained based on the width and length of each wiring shown in FIG. Here, for example, the resistance value of the partial wiring 3e is 4.78R. The resistance value of the partial wiring 3d is 0.94R. The resistance value of the partial wiring 3g is 2.89R. The resistance value of the partial wiring 3f is 1.45R in the 2L section and 1.45R in the 3L section. With such a wiring configuration, the total combined resistance from the first power supply terminal 1 to each of the power supplied parts 4, 5, 6 is 4.78R. As shown in FIG. 4, each of the partial wirings 7d, 7e, 7f, and 7g of the second power supply wiring 7 has the same resistance value.

  Here, in the present embodiment, the power supply voltage drop of each power supplied portion is caused by the partial wirings 3d, 3e, 3f, and the like for the first power supply wiring 3 and the second power supply wiring 7, respectively. Since the constant current I flows through 3g, 7d, 7e, 7f, and 7g, the power supplied parts 4, 5, and 6 have 4.78IR. Therefore, the maximum value of the power supply voltage drop is 4.78IR. 8. The sum of the maximum values of the voltage drop amount on the high potential side and the low potential side is smaller than that in the case where the branch portion is not formed in the power supply wiring which is the comparative example of Example 1 described above. 58IR.

  In this way, by dividing the power supply wiring by forming a branch portion and supplying power to each power supply from each of the divided partial wirings, for example, an area defined in design (here, 3LW), the maximum voltage drop in the power supply wiring can be reduced. Therefore, it is not necessary to change the area of another circuit configuration, and it is possible to cope with the circuit design.

  The first power supply wiring 3 and the second power supply wiring 7 are directly or via other cells or wirings due to, for example, electromigration restrictions, dimension restrictions, or design restrictions determined by the designer. It is possible to divide by forming a branching portion except when it is difficult to be constant due to restrictions imposed indirectly.

  In this embodiment, the amount of power supply voltage drop in the main line of the power supply wiring, which is the power supply wiring, is controlled only by the wiring width. However, the number of wirings and the type of wiring layer (for example, wirings having different electrical conductivity) Layer), etc., may be controlled by connection between a plurality of power supply wirings of the same potential.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, the power supply wiring is divided by forming a branch portion, and power is supplied to each power supply from each divided partial wiring. The maximum value of the power supply voltage drop in the main line of the power supply wiring can be reduced while maintaining the wiring area defined in the design.

  In the first embodiment, the configuration in which the branch portion is formed at the connection portion between the power supply terminal and the power supply wiring has been described. In this embodiment, a configuration in which the width of the partial wiring branched from the branch portion is particularly uniform will be described. .

  FIG. 5 is a plan view showing the configuration of the main part of the semiconductor integrated circuit according to the third embodiment of the present invention. As illustrated in FIG. 5, the semiconductor integrated circuit 100 b includes a first power supply wiring 3 connected to the first power supply terminal 1 and a second power supply wiring connected to the second power supply terminal 2. 7 and a plurality of power supplied parts 4, 5 and 6 connected between the first power supply wiring 3 and the second power supply wiring 7 and supplied with power.

  The first power supply wiring 3 has branch portions 1 a and 1 b at the connection portion between the first power supply terminal 1 and the first power supply terminal 3. The first power supply wiring 3 maintains the wiring area defined in the design of the first power supply wiring 3 from the first power supply terminal 4, 5, 6, the partial wirings 3 h, 3 i, 3 j, 7 h, 7 i, and so on are connected from the branch parts 1 a, 1 b to the power supply parts 4, 5, 6. 7j. As described above, the first power supply wiring 3 is divided so as to correspond one-to-one over the connection portion between the first power supply terminal 1 and each of the power supplied parts 4, 5, 6. As a result, the power supply parts 4, 5 are connected to the terminal portions of the partial wirings 3 h, 3 i, 3 j, 7 h, 7 i, 7 j at distances 1 L, 2 L, 3 L from the first power terminal 1 and the second power terminal 2, respectively. , 6 are connected to each other. In particular, in the present embodiment, the widths of the divided partial wirings 3h, 3i, and 3j of the first power supply wiring 3 are set so that the power supply parts 4, 5, 6 are supplied from the first power supply terminal 1. It is constant until. Similarly, the widths of the partial wirings 7h, 7i, 7j of the second power supply wiring 7 are also constant.

  Here, the width of each partial wiring is determined so that the amount of voltage drop in each partial wiring is equal. In this embodiment, the widths of the partial wirings 3h and 7h connected to the power supply part 3 are about 0.214W. Further, the width of the partial wirings 3i and 7i connected to the power supplied part 4 is about 0.0.429W. The width of the partial wirings 3j and 7j connected to the power supplied part 5 is about 0.643W. Thereby, the wiring area of each of the power supply wirings 3 and 7 is 3 LW.

  Therefore, the wiring area (3LW) occupied by each of the first power supply wiring 3 and the second power supply wiring 7 is a power supply trunk design when the power supply wiring does not have a branching portion. This is the same as the wiring area (3LW) defined above.

  Next, a circuit configuration in which the voltage source Vdd is connected between the first power supply terminal 1 and the second power supply terminal 2 in FIG. FIG. 6 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit according to the second embodiment of the present invention. In the following description, it is assumed that the same constant current I flows through each power supply section for simplicity.

  As shown in FIG. 6, the first power supply wiring 3 and the second power supply wiring 7 in FIG. 5 are represented by resistances between the respective contacts of the power supply wiring. Moreover, each power supply part 4,5,6 of FIG. 6 is represented by the structure which combined the current source of the electric current amount I, and a norator.

  The resistance values of the partial wirings 3h, 3i, and 3j of the first power supply wiring 3 are obtained based on the width and length of each wiring shown in FIG. Here, for example, the resistance value of the partial wiring 3h is 5R. Further, the resistance value of the partial wiring 3i is 2.5R in the 1L section and 2.5R in the 2L section. Further, the resistance value of the partial wiring 3h is 1.66R in the 1L section, 1.66R in the 2L section, and 1.66R in the 3L section. With such a wiring configuration, the total combined resistance from the first power supply terminal 1 to each of the power supplied parts 4, 5, 6 is about 5R. Note that, as shown in FIG. 6, the partial wirings 7h, 7i, and 7j of the second power supply wiring 7 have the same resistance value.

  Here, in the present embodiment, the power supply voltage drop of each power supplied portion is caused by the partial wirings 3h, 3i, 3j, and the like for the first power supply wiring 3 and the second power supply wiring 7, respectively. Since the constant current I flows through 7h, 7i, and 7j, the power supply parts 4, 5, and 6 have about 5IR. Therefore, the maximum value of the power supply voltage drop is about 5IR. The sum of the maximum values of the voltage drop amounts on the high potential side and the low potential side is smaller than that in the case where the branch portion is not formed in the power supply wiring which is the comparative example of Example 1 described above, about 10 IR. It becomes.

  In this way, by dividing the power supply wiring by forming a branch portion and supplying power to each power supply from each of the divided partial wirings, for example, an area defined in design (here, 3LW), the maximum voltage drop in the power supply wiring can be reduced. Therefore, it is not necessary to change the area of another circuit configuration, and it is possible to cope with the circuit design.

  The first power supply wiring 3 and the second power supply wiring 7 are directly or via other cells or wirings due to, for example, electromigration restrictions, dimension restrictions, or design restrictions determined by the designer. It is possible to divide by forming a branching portion except when it is difficult to be constant due to restrictions imposed indirectly.

  In this embodiment, the amount of power supply voltage drop in the main line of the power supply wiring, which is the power supply wiring, is controlled only by the wiring width. However, the number of wirings and the type of wiring layer (for example, wirings having different electrical conductivity) Layer), etc., may be controlled by connection between a plurality of power supply wirings of the same potential.

  As described above, according to the semiconductor integrated circuit of the present embodiment, a branch portion is formed in the power supply wiring and divided with a uniform width, and power is supplied to each power supply from each divided partial wiring. Thus, for example, it is possible to reduce the maximum value of the power supply voltage drop in the main line of the power supply wiring while maintaining the wiring area defined in the design.

  In each of the first to third embodiments, the configuration in which the first power supply wiring 3 and the second power supply wiring 2 have branch portions 1a, 1b, 2a, and 2b has been described. If at least one of the first power supply wiring 3 and the second power supply wiring 2 has a branch portion and a partial wiring is formed, at least the power supply wiring in which the partial wiring is formed Of course, the same effects can be obtained.

  In each of the above-described first to third embodiments, the partial configuration of the power supply wiring is described. However, in the following embodiments, the configuration of the first to third embodiments is applied to a more specific circuit configuration. Is described. In this embodiment, in particular, a ring-shaped power wiring trunk having a generally widely used structure, and a mesh-shaped power supply that supplies power to each power supply portion from the ring-shaped power wiring trunk. A configuration in which the third embodiment is applied to a semiconductor integrated circuit including a power supply wiring that is a wiring will be described.

  FIG. 7 is a schematic diagram showing the configuration of the main part of the semiconductor integrated circuit according to the fourth embodiment of the present invention. As shown in FIG. 7, the semiconductor integrated circuit 100c includes a high-potential first power supply terminal 1, a high-potential ring power supply wiring 8, high-potential mesh-like power supply wirings 9a to 9f, and a power supply cover. A supply unit 10 is provided. In the drawing, the power supply wiring on the high potential side is omitted, and only the power supply wiring on the high potential side is shown for simplicity because of the symmetry between the high potential side and the low potential side of the power supply wiring. Also, here, regarding the power supply wiring, it is assumed that the ring power supply wiring 8 is formed of a sufficiently thick wiring and the voltage drop is so small that it can be ignored, and the power supplied part 10 is uniformly distributed inside the ring power supply wiring. Assuming that In the figure, the power supplied unit 10 is divided into 36 equal parts for explanation, and the current consumption per power supplied unit 10 is I.

  Here, as a comparative example, as shown in FIG. 8, the power supply wiring 11 a connected between the ring power supply wiring 8 and the power supplied part 10 located on the outer periphery and the power supplied parts 10 are connected to each other. Consider a model of a semiconductor integrated circuit 100x having a mesh-like power supply wiring 11b to be connected. The power supply wiring 11a connected to the ring power supply wiring 8 has a length of 0.5L, a width W, and a resistance of 0.5R, respectively. The mesh-shaped power supply wiring 11b other than the power supply wiring has a long length. Let L, width W, and resistance R. At this time, according to the circuit simulation, the maximum value of the power supply voltage drop in the power supplied part 10 is 2.59IR.

  On the other hand, as shown in FIG. 7, the power supply wiring from the ring to each power supplied portion is made independent based on the wiring structure according to the present embodiment, and each power supply wiring 9a, 9b, 9c, 9d, 9e, 9f is provided. For example, the width is about 0.316 W, 0.947 W, 0.789 W, 0.315 W, 0.474 W, and 0.158 W in this order. As a result, the maximum value of the power supply voltage drop is about 1.58 IR with the same power supply wiring area as in the comparative example. Therefore, the semiconductor integrated circuit 100c can reduce the maximum value of the power supply voltage drop more than the comparative example in which the mesh-like power supply wiring is made uniform.

  In the present embodiment, the power supply wiring structure of the third embodiment is applied as the power supply wiring structure, and the power supply wiring to each power supplied portion is an independent power supply wiring having a uniform width. Of course, the second embodiment or a combination of these can be applied.

  As described above, according to the semiconductor integrated circuit of the present embodiment, a branch portion is formed in the power supply wiring and divided with a uniform width, and power is supplied to each power supply from each divided partial wiring. Thus, for example, it is possible to reduce the maximum value of the power supply voltage drop in the main line of the power supply wiring while maintaining the wiring area defined in the design.

  In the fourth embodiment, the configuration of the third embodiment is applied to a semiconductor integrated circuit including a power supply wiring that is a mesh-shaped power supply wiring that supplies power to each power supply target portion from a trunk line of a ring-shaped power supply wiring. Although the configuration has been described, this embodiment particularly describes a case where the circuit configuration includes a fuse, an analog circuit, or the like and the wiring is limited.

  FIG. 9 is a plan view showing the configuration of the main part of the semiconductor integrated circuit according to the fifth embodiment of the present invention. As shown in FIG. 9, in the semiconductor integrated circuit 100d, the partial wirings 12a, 12b, and 12c respectively supply power from the ring power supply wiring 8 so as to equalize the power supply voltage drop while maintaining the prescribed wiring area. Wiring is performed with a wiring width based on the distance to each power supply section 10 to be supplied. Further, in the semiconductor integrated circuit 100 d, a region 13 such as a fuse or an analog circuit is formed separately from the power supplied part 10.

  Here, since no power supply wiring is provided in the region 13, the ring power supply wire 8 is bent so as to avoid the region 13, for example, as in the partial wiring 12 d, so as to equalize the power supply voltage drop amount. Wiring is performed with a wiring width based on the distance to the power supplied portion 10 to which power is to be supplied. As described above, the semiconductor integrated circuit 100d can uniformize the power supply voltage drop amount while maintaining the prescribed wiring area even when the wiring is limited by a fuse, an analog circuit, or the like in the circuit configuration. It has become.

  Further, as described above, the amount of voltage drop may be controlled by the number of wires or the connection between a plurality of power supply wires having the same potential. FIG. 10 is a plan view showing another configuration example of the main part of the semiconductor integrated circuit according to the fifth embodiment of the present invention. As shown in FIG. 10, each of the partial wirings 14a, 14b, and 14c of the semiconductor integrated circuit 100e has two wirings so as to equalize the amount of power supply voltage drop while maintaining a prescribed wiring area. Wired to the supplied part 10. In addition, the common wiring 15 connects parts having the same maximum power supply voltage drop amount of the partial wiring (power supply wiring) to stabilize the power supply voltage.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, even if the distribution and arrangement of the current amount of each power supplied portion and the shape of the wiring mesh are not uniform, the power supply voltage drop amount is made uniform. Thus, by individually adjusting the resistance of the power supply wiring, the maximum value of the power supply voltage drop can be reduced without increasing the wiring area of the power supply wiring.

  In the above-described fourth and fifth embodiments, the present invention relates to a semiconductor integrated circuit including a power supply wiring that is a mesh-shaped power supply wiring that supplies power to each power supply unit from a ring-shaped power supply main line. Although the example to which the configuration is applied has been described, in the following examples, a semiconductor including a power supply wiring that is a stripe-shaped power supply wiring that supplies power to each power supply portion from a trunk of a ring-shaped power supply wiring An example in which the configuration according to the present invention is applied to an integrated circuit will be described. In the present embodiment, a configuration to which the first embodiment is applied will be particularly described.

  Here, as a comparative example, FIG. 11 shows a configuration of a main part of a semiconductor integrated circuit provided with a stripe-shaped power supply wiring. As shown in FIG. 11, the semiconductor integrated circuit 100 y includes a high potential first power supply terminal 1, a low potential second power supply terminal 2, and a ring power supply wiring 16 connected to the first power supply terminal 1. The ring power supply wiring 17 connected to the second power supply terminal 2, the high-potential stripe-shaped power supply wiring 18, and the low-potential stripe-shaped power supply wiring 19 are electrically connected to each other. And a pad 50 for carrying out the operation. In the figure, for the sake of simplicity, the power supply portion is omitted, and the same is omitted in the description of the following embodiments.

  As shown in FIG. 11, assuming that the distribution of current consumption is uniform, the power supply section 10 present in the center has the largest power supply voltage drop, and the power supply voltage drop of the power supply sections present in the left and right sections. Is less than that.

  On the other hand, FIG. 12 is a plan view showing the configuration of the main part of the semiconductor integrated circuit according to the sixth embodiment of the present invention, to which the configuration of the first embodiment is applied. The semiconductor integrated circuit 100 f includes a high-potential first power supply terminal 1, a low-potential second power supply terminal 2, a ring power supply wiring 16 connected to the first power supply terminal 1, and a second power supply terminal 2. A ring power supply wiring 17 connected to the high-potential power supply wiring 18 formed with the partial wirings 18a to 18c, and a low-potential power supply wiring 19 formed with the partial wirings 19a to 19c. ing.

  As shown in FIG. 12, the partial wirings 18a to 18c and 19a to 19c are formed so as to equalize the amount of power supply voltage drop while maintaining the prescribed wiring area. Thus, the maximum amount of power supply voltage drop can be suppressed without increasing the wiring area of the power supply wiring, and the same effects as those of the first embodiment can be achieved.

  Furthermore, in the present embodiment, as described above, the power supply wires having the same potential may be connected. FIG. 13 is a plan view showing another configuration example of the main part of the semiconductor integrated circuit according to the sixth embodiment of the present invention. In the semiconductor integrated circuit 100g, a high-potential power supply having one end connected to the other end of the high-potential power supply wiring 18 connected at one end to the ring power supply wiring 16 and a portion of the ring wiring 16 facing the connection portion. The other end of the supply wiring 18 is connected via a common wiring 20. Similarly, the low-potential power supply wirings 19 are connected to each other through a common wiring 21. As a result, the power supply voltage is stabilized.

  As described above, according to the semiconductor integrated circuit of this embodiment, the power supply wiring resistance is individually adjusted so as to equalize the power supply voltage drop amount even for the stripe-shaped power supply wiring structure. The maximum value of the power supply voltage drop can be reduced without increasing the wiring area of the wiring.

  In the sixth embodiment, the example in which the configuration of the power supply wiring according to the first embodiment is applied to the semiconductor integrated circuit provided with the power supply wiring that is the stripe-shaped power supply wiring is described. An example in which the configuration of the power supply wiring according to the above is applied will be described.

  FIG. 14 is a plan view showing the configuration of the main part of the semiconductor integrated circuit according to the seventh embodiment of the present invention. As shown in FIG. 14, the semiconductor integrated circuit 100 h includes a high-potential first power supply terminal 1, a low-potential second power supply terminal 2, and a ring power supply wiring 16 connected to the first power supply terminal 1. The ring power supply wiring 17 connected to the second power supply terminal 2, the high potential power supply wiring 22 formed with the partial wirings 22a to 22c, and the low potential power supply formed with the partial wirings 23a to 23c. Wiring 23.

  As shown in FIG. 14, the partial wirings 22a to 22c and 23a to 23c are formed so as to equalize the amount of power supply voltage drop while maintaining the prescribed wiring area. In comparison, the maximum amount of power supply voltage drop can be suppressed without increasing the wiring area of the power supply wiring, and the same effects as those of the second embodiment can be achieved.

  In addition, as in the semiconductor integrated circuit 100i shown in FIG. 15, the power supply wiring 22 is divided so as to equalize the amount of power supply voltage drop while maintaining the prescribed wiring area, and each partial wiring is divided. 22a and 22b are formed and divided inside the power supply wiring 23 to form the partial wirings 23a and 23b, respectively, thereby increasing the wiring area of the power wiring as compared with the above-described comparative example. Therefore, the maximum amount of power supply voltage drop can be suppressed, and the same effects as those of the second embodiment can be achieved.

  As described above, according to the semiconductor integrated circuit of this embodiment, the power supply wiring resistance is individually adjusted so as to equalize the power supply voltage drop amount even for the stripe-shaped power supply wiring structure. The maximum value of the power supply voltage drop can be reduced without increasing the wiring area of the wiring.

  In this embodiment, an example in which the configuration of the power supply wiring according to the third embodiment is applied to a semiconductor integrated circuit provided with a power supply wiring that is a stripe-shaped power supply wiring will be described.

  FIG. 16 is a plan view showing the configuration of the main part of the semiconductor integrated circuit according to the eighth embodiment of the present invention. As shown in FIG. 16, the semiconductor integrated circuit 100j includes partial wirings 24a to 24c having a uniform width and partial wirings 25a to 25c having a uniform width as power supply wirings.

  As shown in FIG. 16, the partial wirings 24 a to 24 c and 25 a to 25 c are formed so as to equalize the power supply voltage drop amount while maintaining the prescribed wiring area, so that In comparison, the maximum amount of power supply voltage drop can be suppressed without increasing the wiring area of the power supply wiring, and the same effects as those of the third embodiment can be achieved.

  In this embodiment, the high potential side partial wiring and the low potential side partial wiring may be arranged adjacent to each other for each power supply target portion. Like the semiconductor integrated circuit 100k shown in FIG. 17, the partial wiring 24a connected to the high potential side of the power supply portion (not shown) is adjacent to the partial wiring 25a connected to the low potential side of the power supply portion. Arranged. Similarly, a high-potential-side partial wiring 24b and a low-potential-side partial wiring 25b are disposed adjacent to each other for each power supply portion, and the high-potential-side partial wiring 24c, the low-potential-side partial wiring 25c, Are arranged adjacent to each other. As described above, the semiconductor integrated circuit 100k achieves the effects of the second embodiment, and allows the power supply current and the feedback current to flow adjacent to each other for each power supply target portion, thereby reducing the power supply inductance. Yes.

  In the present embodiment, as described above, the power supply wirings having the same potential may be connected. As shown in FIG. 18, in the semiconductor integrated circuit 100l, one end is connected to the other end of the high potential partial wiring 24a, one end of which is connected to the ring power supply wiring 16, and the portion of the ring wiring 16 facing this connection portion. The other end of the high potential partial wiring 24a is connected via the common wiring 26a. Similarly, the high potential partial wirings 24b and 24c are connected via common wirings 26b and 26c, respectively. Similarly, the low potential partial wirings 25a, 25b, and 25c are connected through common wirings 27a, 27b, and 27c, respectively. As a result, the power supply voltage is stabilized.

  Furthermore, in this embodiment, the common wirings may be connected. As shown in FIG. 19, in the semiconductor integrated circuit 100m, one end is connected to the other end of the high potential partial wirings 24a, 24b, and 24c connected to the ring power supply wiring 16, and the portion of the ring wiring 16 facing this connection portion. The other ends of the high potential partial wirings 24 a, 24 b and 24 c to which one end is connected are connected via a common wiring 28. Similarly, the low potential partial wirings 25 a, 25 b and 25 c are connected to each other through a common wiring 29. As a result, the power supply voltage is further stabilized.

  As described above, according to the semiconductor integrated circuit of this embodiment, the power supply wiring resistance is individually adjusted so as to equalize the power supply voltage drop amount even for the stripe-shaped power supply wiring structure. The maximum value of the power supply voltage drop can be reduced without increasing the wiring area of the wiring.

  In the above-described embodiment, an example in which the configuration according to the present invention is applied to a semiconductor integrated circuit provided with a power supply wiring that is a stripe-shaped power supply wiring has been described. However, in the following embodiments, a ring-shaped power supply wiring An example in which the configuration according to the present invention is applied to a semiconductor integrated circuit provided with a power supply wiring that is an L-shaped power supply wiring for supplying power from the main line to each power supply target portion will be described. In the present embodiment, a configuration to which the third embodiment is applied will be particularly described.

  Here, as a comparative example, a semiconductor integrated circuit including an L-shaped power supply wiring is shown in FIG. The semiconductor integrated circuit 100z is connected to the ring power supply wiring 16 and is connected to the L power supply wiring 30 laid on one wiring layer and the ring power supply wiring 17 and is L laid on one wiring layer. Power supply wiring 31. In the semiconductor integrated circuit 100z, the amount of power supply voltage drop in the L-shaped power supply wirings 30 and 31 in the central portion is larger than that in the peripheral portion.

  Next, FIG. 21 shows a main configuration of a semiconductor integrated circuit according to the present embodiment in which the wiring configuration of the third embodiment is applied to the L-shaped power supply wiring. For example, the semiconductor integrated circuit 100n is connected to the ring power supply wiring 16 and is connected to the ring power supply wiring 17 with a uniform width of partial wiring 32 laid on one wiring layer and the same wiring layer laid on one wiring layer. And a partial wiring 33 having a uniform width.

  The partial wirings 32 and 33 are formed so as to equalize the power supply voltage drop while maintaining the prescribed wiring area, and the power supply without increasing the wiring area of the power supply wiring as compared with the comparative example. The maximum amount of voltage drop is reduced.

  Similarly, of course, the wiring structures of the first and second embodiments can be applied to the L-shaped power supply wiring.

  Of course, power supply lines having the same voltage drop amount can be connected to each other to stabilize the power supply voltage.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, even for the L-shaped power supply wiring structure, by individually adjusting the resistance of the power supply wiring so as to equalize the power supply voltage drop amount, The maximum value of the power supply voltage drop can be reduced without increasing the wiring area of the power supply wiring.

  In each of the above embodiments, the case where the current flowing through each power supply unit is a constant current has been described. However, even if the current flowing through each power supply unit is different, the power to each power supply unit is It goes without saying that the same effect can be obtained by making the power supply voltage drops in the supply wirings equal.

1 is a plan view showing a configuration of a main part of a semiconductor integrated circuit according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit according to Embodiment 1 of the present invention. It is a top view which shows the structure of the principal part of the semiconductor integrated circuit based on Example 2 of this invention. FIG. 6 is a circuit diagram illustrating a configuration of a main part of a semiconductor integrated circuit according to a second embodiment of the present invention. It is a top view which shows the structure of the principal part of the semiconductor integrated circuit which concerns on Example 3 of this invention. It is a circuit diagram which shows the structure of the principal part of the semiconductor integrated circuit which concerns on Example 3 of this invention. It is the schematic which shows the structure of the principal part of the semiconductor integrated circuit provided with the mesh-shaped power supply wiring which concerns on Example 4 of this invention. It is a top view which shows the principal part structure of the comparative example of a semiconductor integrated circuit. It is a top view which shows the structure of the principal part of the semiconductor integrated circuit provided with the mesh-shaped power supply wiring which concerns on Example 5 of this invention. It is a top view which shows the other structural example of the principal part of the semiconductor integrated circuit provided with the mesh-shaped power supply wiring which concerns on Example 5 of this invention. It is a top view which shows the principal part structure of the comparative example of a semiconductor integrated circuit. It is a top view which shows the structure of the principal part of the semiconductor integrated circuit based on Example 6 of this invention. It is a top view which shows the other structural example of the principal part of the semiconductor integrated circuit based on Example 6 of this invention. It is a top view which shows the structure of the principal part of the semiconductor integrated circuit based on Example 7 of this invention. It is a top view which shows the other structural example of the principal part of the semiconductor integrated circuit which concerns on Example 7 of this invention. It is a top view which shows the structure of the principal part of the semiconductor integrated circuit based on Example 8 of this invention. It is a top view which shows the other structural example of the principal part of the semiconductor integrated circuit based on Example 8 of this invention. It is a top view which shows the other structural example of the principal part of the semiconductor integrated circuit based on Example 8 of this invention. It is a top view which shows the other structural example of the principal part of the semiconductor integrated circuit based on Example 8 of this invention. It is a top view which shows the structure of the principal part of the comparative example of a semiconductor integrated circuit. It is a top view which shows the structure of the principal part of the semiconductor integrated circuit based on Example 9 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st power supply terminal 1a, 1b Branch part 2 2nd power supply terminal 2a, 2b Branch part 3 1st power supply wiring 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3i, 3j part wiring
4 Power supplied part 5 Power supplied part 6 Power supplied part 7 Second power supply wirings 7a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, 7i, 7j Partial wiring 8 Ring power supply wiring 9a, 9b, 9c, 9d, 9e, 9f Partial wiring 10 Power supplied portion 11a Power supply wiring 11b Mesh-shaped power supply wiring
12a, 12b, 12c, 12d Partial wiring
13 region 14a, 14b, 14c partial wiring 15 common wiring 16 ring power supply wiring 17 ring power supply wiring 18 power supply wiring 18a, 18b, 18c partial wiring 19 power supply wiring 19a, 19b, 19c partial wiring 20 common wiring 21 common wiring 22 Power supply wiring 22a, 22b, 22c Partial wiring 23 Power supply wiring 23a, 23b, 23c Partial wiring 24a, 24b, 24c Partial wiring 25a, 25b, 25c Partial wiring 26a, 26b, 26c Common wiring 27a, 27b, 27c Common wiring 28 Common wiring 29 Common wiring 30 L-shaped power supply wiring 31 L-shaped power supply wiring 32 Partial wiring 33 Partial wiring 50 Pads 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j, 100k, 1 0l, 100m, 100n, 100x, 100y, 100z semiconductor integrated circuit

Claims (5)

Power supply wiring connected to the power terminal;
A plurality of power supplied parts connected to the power supply wiring and supplied with power; and
The power supply wiring has a branch portion so that the amount of power supply voltage drop from the power supply terminal to each of the power supplied parts becomes equal while maintaining the prescribed wiring area of the power supply wiring. A semiconductor integrated circuit, wherein the semiconductor integrated circuit is divided from the branching portion to a connecting portion with each of the power supplied portions. The branch portion is a connection portion between the power supply terminal and the power supply terminal,
2. The semiconductor integrated circuit according to claim 1, wherein the power supply wiring is divided from the power supply terminal to a connection portion with each of the power supplied portions.   3. The semiconductor integrated circuit according to claim 2, wherein the power supply wiring is divided so as to correspond one-to-one from the power supply terminal to a connection portion with each of the power supplied portions.   4. The semiconductor integrated circuit according to claim 2, wherein a width of each of the divided partial wirings of the power supply wiring is constant from the power supply terminal to each of the power supply target parts.   5. The semiconductor integrated circuit according to claim 1, wherein the power supply wiring is provided on a trunk line of the power wiring.

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