JP2006311740A - Power supply and method of reducing dip during parallel operation of power supplies - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply that reduces the amplitude of a dip voltage with a simple circuit that reduces sharp load fluctuation in order to reduce a dip that occurs to an output voltage, and a method of reducing the dip during the parallel operation of power supplies. <P>SOLUTION: In a plurality of the power supplies SP1, SP2 driven in parallel using a MOS field-effect transistor (FET1) for preventing countercurrent, on/off control signals of a drive amplification circuit OP1 is supplied to the gate electrode G of the FET1. A voltage of dip amplitude Dp is reduced by supplying the gate signal to a reference voltage source of a comparison circuit OP2 for output voltage control through a series circuit of a resistor R5 and a diode D2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply device that reduces load fluctuations during parallel operation by a plurality of power supply devices and a dip reduction method during parallel power supply operation, and in particular, when one power supply device is switched and controlled during parallel operation, the other power supply The present invention relates to a power supply apparatus that attenuates a dip (Dip) waveform generated in an output voltage line of the apparatus, and a dip reduction method during parallel power supply operation.

  Conventionally, in parallel redundant operation, since a diode for preventing backflow is connected to the output voltage lines of a plurality of power supply devices, a forward voltage drop is unavoidable when a large amount of output current flows. The diode caused a power loss proportional to the output current, resulting in a decrease in efficiency and heat generation. Patent Document 1 discloses a power supply device that improves power loss and efficiency reduction during such parallel redundant operation.

  FIG. 6 shows a power supply device disclosed in Patent Document 1. In FIG. In FIG. 6, reference numeral 1 denotes one of a plurality of power supply circuit bodies, which supply predetermined DC voltages + V and -V from output terminals + T and -T. Although not shown, other power supply circuit bodies 1n are also connected in parallel. Each is connected in parallel to the load 2 so that redundant operation is possible. The FET 1 is a MOS field effect transistor (hereinafter referred to as FET) that is inserted and connected to an output voltage line between the positive output terminal + T of the power supply circuit body 1 and the load 2, and the drain D and source S of the FET 1. In the meantime, a backflow prevention diode D1 having an anode connected to the source S side and a cathode connected to the drain D side is connected. 3 includes a current detection resistor R5 for detecting the output current Io of the power circuit body 1 and a comparator 4 for detecting a failure of the power circuit body 1 based on a voltage drop generated at both ends of the resistor R5. This is a current detection circuit that turns off the FET 1 when a directional current is generated.

  A resistor R5 of the current detection circuit 3 is inserted and connected to a voltage line between the output terminal -T of the power supply circuit body 1 and the load 2, and a voltage divider is provided between one end of the resistor R5 and the output terminal + T of the power supply circuit body 1 A series circuit of resistors R1 and R2 is connected, and a series circuit of resistors R3 and R4 for voltage division is also connected between the other end of the resistor R5 and the output terminal + T of the power supply circuit body 1. The connection points of the resistors R1 and R2 and the resistors R3 and R4 are connected to the inverting input terminal − and the non-inverting input terminal + of the comparator 4. The output terminal of the comparator 4 is connected to the gate of the FET 1. A resistor R 6 is connected between the gate G of the FET 1 and the operating voltage Vcc line of the comparator 4 so that the operating voltage Vcc is supplied to the gate G of the FET 1. Is done. The ground of the comparator 4 is connected to the connection point between the other end of the resistor R5 and the load 2.

In the current detection circuit 3, the operating voltage _VCC needs to be higher than the voltage value applied to the output voltage Vo between the gate G and the source S of the FET 1 in order to reliably turn on the FET 1. Further, the resistance values of the resistors R1 to R4 are determined so that the voltage level of the non-inverting input terminal + of the comparator 4 is higher than the voltage level of the inverting input terminal − when the power supply circuit body 1 is normal. In this case, if the resistance values of one of the resistors R1 and R3 are set to be the same, the operating point at the time of on / off control of the FET1 can be changed simply by appropriately adjusting the resistance values of the other resistors R2 and R4. Can do.

The operation of the above configuration will be described. Since the output current Io flows from the load 2 toward the output terminal -T during normal parallel operation of the power supply circuit body 1, the resistance is higher than the voltage level V1 on one end side of the resistor R5. The voltage level V2 on the other end side of R5 becomes higher, the voltage level V2 of the non-inverting input terminal of the comparator 4 becomes higher than the voltage level V1 of the inverting input terminal, and the output terminal of the comparator 4 becomes H level. An operating voltage _VCC sufficient to turn on the source S and drain D of the FET 1 is supplied to the gate G, and the output terminal voltage + V → FET 1 (or the diode D 1) from the output terminal + T on the power circuit body 1 side. The output current Io is supplied through the path of the load 2 → the resistor R5 → the output terminal −T.

  On the other hand, if the power supply circuit body 1 fails for some reason, the supply of the output current Io stops, and a current in the opposite direction to the output current Io is generated in the output voltage line, the other end of the resistor R5 The voltage level V1 on one end side of the resistor R5 becomes higher than the voltage level V2 on the side. Therefore, this time, the voltage level V1 of the inverting input terminal − of the comparator 4 becomes higher than the voltage level V2 of the non-inverting input terminal +, the output terminal of the comparator 4 immediately becomes L level, and the FET 1 is turned off. Inflow of the reverse current to the output terminal + T of the power supply circuit body 1 is prevented. In this case, power is continuously supplied to the load 2 from, for example, N power supply circuit bodies excluding the failed power supply circuit body 1.

  In the series of operations, the abnormality determination of the power supply circuit body 1 by the comparator 4 depends on the resistance values of the resistors R1 to R3. Now, when the resistors R1 and R3 are set to the same resistance value, if the resistance values of the resistors R2 and R3 are set to the same value, the FET1 is turned on / off when the output current Io becomes zero. If the resistance value of the resistor R2 is set larger than the resistance value of the resistor R4 (R2> R4), the FET1 is switched on and off before the output current Io becomes zero. In this case, the power loss of the diode D1 is reduced by setting the resistance values of the resistors R2 and R3 so that the FET1 is switched on and off when the output current Io is relatively small.

  In the above configuration, when the output current from the predetermined power supply circuit body 1 becomes a predetermined level or less during parallel operation by the plurality of power supply circuit bodies 1 to 1n, the current detection circuit 3 detects the failure of the power supply circuit body 1, Although there is a disclosure that the FET 1 is forcibly turned off to prevent the reverse current from flowing into the power supply circuit body 1 that has failed, it is only related to the on / off control of the FET 1.

  Patent Document 2 discloses a power supply device in which the reference voltage of an error amplifier that compares the reference voltage and the error voltage is changed in order to reduce the drop in the load supply voltage when the standby power supply is switched.

  FIG. 7 shows a circuit diagram of the power supply device described in Patent Document 2. 1A and 1B are two power supply circuit bodies, 2 is a load, 5A and 5B are + voltage detection lines, and 6A and 6B are −voltages. Detection lines, 7A and 7B are positive output lines, 8A and 8B are negative output lines, and D1A and D1B are backflow prevention diodes. Since the voltage at the point C at the load 2 end of the + voltage detection line fluctuates with respect to changes in the forward voltage drop of the diodes D1A and D1B, error amplifiers 10A and 10B are provided in the power supply circuit bodies 1A and 1B.

9A and 9B shown in the power supply circuit bodies 1A and 1B are power amplifiers, 10A and 10B are error amplifiers, 11A and 11B are reference power supplies, 12A and 12B are input points for output detection voltages, and 13A and 13B are input points for reference voltages. , R1A, R2A, R3A, R4A , R1B, R2B, R3B, but R4B is dividing resistors, now, the voltage applied to the load 2 and _{V 0,} the power supply circuit body 1A, the output setting voltage 1B _{V a,} If V _B is set, the set voltages V _{A and} V _B cannot be made equal due to variations in the power supply circuit bodies 1A and 1B, but if the output set voltage V _A is larger than the output set voltage V _B , the error amplifier of the power supply circuit body 1B Since the voltage at the input point 12B of the output detection voltage of 10B is higher than the voltage at the input point 13B of the reference voltage, the error amplifier 10B is cut off and the power amplifier 9B does not operate normally. The output voltage of the source circuit body 1B is lower than the voltage of the load 2. Therefore, when one power supply circuit body 1A fails, the voltage of the load 2 is prevented from decreasing until the other power supply circuit body 1B rises to a normal voltage as follows.

  That is, in FIG. 7, the anodes of the diodes D1A and D1B connected to the output circuits of the power supply circuit bodies 1A and 1B are connected to the bases of the respective transistors TrA and TrB, and the cathodes are connected via the resistors R7A and R7B, respectively. Are connected to the emitters of the transistors TrA and TrB, the collectors of the transistors TrA and TrB are connected to the error amplifiers 10A and 10B of the power supply circuit bodies 1A and 1B, respectively, and the potential difference between both ends of the diodes D1A and D1B is used. The configuration is such that TrB is controlled to increase the voltage at the input points 13A and 13B of the reference voltage of the error amplifiers 10A and 10B, and the output voltage of the power amplifiers 9A and 9B is increased and held so as to be substantially equal to the supply voltage to the load 2. It is disclosed.

The technique disclosed in Patent Document 2 described above changes the reference voltage at the time of switching between the two power supplies to reduce the drop in the output voltage. However, the present invention relates to a MOS type FET for preventing backflow in a power supply device driven in parallel ( FET 1) is provided with a gate control circuit (drive amplifier circuit) that controls the gate voltage of the error amplifier in the output voltage control comparator circuit when one of the power supply circuit bodies is turned off, and the dep voltage of the load output line The amplitude is reduced.
JP-A-7-281766 JP-A 61-295830

  As described above, the object of the present invention is to reduce the dip voltage of the output voltage during the switching control of the parallel drive of the power supply device. In the state where two power supply units are operating in parallel, a dip occurs in the output voltage at the moment when one power supply is turned off. The cause of this is, for example, when the first power supply device and the second power supply device are operating, and the output current is almost 50% at a time, and the second power supply device is turned off. As a result, the current of the first power supply device changes abruptly so that the total output current that has been provided by two units until now is output only by the first power supply device. Due to this sudden change (rapid increase) in the load current, the response of the output voltage control of the first power supply device cannot catch up, and as a result, the output voltage deps. Usually, the larger the total load current is, the larger the fluctuation range of the load of the first power supply device is, so the dip amplitude is also increased.

  The simplest countermeasure against the output voltage dipping during sudden load changes is to increase the capacitance of the output capacitor connected to the output voltage line. However, increasing the capacitance of the output capacitor C1 (see FIG. 1) causes problems such as expansion of the component layout space and cost increase. If there is no problem in the layout of parts, this measure can be considered, but this measure is difficult to consider in the design of a high-density power supply device. In addition, measures to increase the size and cost of the power supply circuit should be avoided in any power supply device. In addition, by increasing the output voltage transient response speed, it is possible to reduce the dip voltage amplitude when the load current suddenly changes. However, if the transient response speed is too high, output control can be performed due to abnormal oscillation. This causes the problem of becoming unstable.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to reduce the amplitude of the dep voltage with a simple circuit that reduces the abrupt change in the load in order to reduce the dep generated in the output voltage. It aims at proposing the power supply device which reduces, and the dep reduction method at the time of parallel power supply operation.

  According to a first aspect of the present invention, there is provided a power supply device comprising a plurality of power supply circuit bodies connected in parallel, a backflow prevention diode connected to an output voltage line for supplying a predetermined output voltage from an output terminal, a switching transistor, and a power supply circuit. A power supply device comprising: an output voltage control comparison circuit for detecting the output voltage of the main body; and a drive amplifier circuit for controlling on / off of the switching diode when the power supply circuit main body is abnormal based on the detection result of the output voltage control comparison circuit When the control signal supplied from the drive amplifier circuit to the switching transistor falls below the reference voltage supplied to the output voltage control comparison circuit, the reference voltage is lowered to reduce the output voltage dep. It is a thing.

  According to a second aspect of the present invention, there is provided a method for reducing a dip during parallel power supply operation. A diode and a switching circuit for preventing a backflow connected to an output voltage line for supplying a predetermined output voltage from an output terminal to a power supply circuit body in which a plurality of units are connected in parallel. Transistor, an output voltage control comparison circuit for detecting the output voltage of the power supply circuit body, and a drive for controlling on / off of the switching diode when the power supply circuit body is abnormal based on the detection result of the output voltage control comparison circuit In the method for reducing the dip during parallel power supply operation comprising the amplifier circuit, the reference voltage when the control signal supplied from the drive amplifier circuit to the switching transistor falls below the reference voltage supplied to the output voltage control comparison circuit. To reduce the output voltage dep.

  The power supply apparatus and the method of reducing the dip during parallel power supply operation of the present invention reduce the dip amplitude of the output voltage generated when one power supply apparatus is turned off, for example, in a state where current sharing is performed by two power supply apparatuses. Since the capacitance of the output capacitor of the output voltage line can be reduced, the component layout becomes easier and the size can be reduced.

  An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram showing an embodiment of the power supply device of the present invention, FIG. 2 is a waveform explanatory diagram of the power supply device of the present invention, and FIG. 3 is a waveform when one of the power supply devices of the present invention is turned off in parallel operation. 4A and 4B are circuits and waveform diagrams for explaining the sequence of on / off control of the MOS type FET (FET1), and FIGS. 5A and 5B are generations of deps generated in the output voltage. It is the circuit diagram and waveform diagram for demonstrating a cause.

  Prior to explaining the power supply device according to one embodiment of the present invention with reference to FIG. 1 to FIG. 3, the switching type MOS FET (FET 1) of FIG. 4 (A) (B) and FIG. 5 (A) (B) is used. The cause of the occurrence of the dip amplitude occurring in the sequence and the output voltage will be described.

  4A and 5A, the same reference numerals are given to the portions corresponding to those in FIG. 6 and FIG. 4A is supplied with a commercial AC signal from a commercial AC power supply AC, and is supplied to a filter circuit 1a, a power factor correction circuit (PFC) 1b, a resonance circuit 1c, etc., and a furnace wave and a power factor improvement. An output capacitor C1 is connected to the output terminal of the resonance conversion circuit 1c, and a switching transistor FET1 made of a MOS FET is connected to an output line between one terminal of the capacitor C1 and the output terminal T1 to which the load 2 is connected. The anode of the diode D1 for preventing backflow is connected to the source S of the FET1, the cathode of the diode D1 is connected to the drain D of the FET1, and the diode D1 is connected in parallel between the source S and the drain D of the FET1. Is done. A resistor R5 is connected between the other end of the capacitor C1 and the output terminal T2 to which the load 2 is connected. In FIG. 1, C2 is a pass capacitor, and R7 is a gate resistor.

  The voltage extracted from both ends of the resistor R5 connected between the resonance circuit 1c and the output terminal T2 is input to the control circuits 10A and 10B [see FIG. 5A]. The control voltages from the control circuits 10A and 10B are supplied to the filter circuit 1a, the PFC circuit 1b, and the like, and are supplied to the gate of the FET 1 through the resistor R7 as a gate control signal for controlling the FET 1 on / off.

  In the above configuration, only one power supply device is shown. However, in the case of a power supply device that is normally operated in parallel, the output current flows back from the power supply device that is turned on to the output of the power supply device that is turned off. In order to prevent this, as described above, the diode D1 for preventing backflow is inserted into the power supply circuit body 1 and the output terminals T1 and T2, and this output current is about several tens to several hundreds A. In many cases, the FET 1 described above is used for the purpose of reducing the loss of the diode D1.

  Naturally, in this case, the FET 1 detects the backflow of the output current and the like, and is controlled to be turned on / off as described with reference to FIG. 6. However, as other control, a power supply circuit as shown by a waveform W2 in FIG. When the main body 1 is in the off state, the switching transistor FET1 is kept in the off state as in the waveform W2. When the power supply circuit body 1 is turned on, the backflow prevention FET 1 is turned on as shown by the waveform W2 after the waveform W1 of the output voltage completely rises. Further, when the power circuit main body 1 changes from the on state to the off state shown in the waveform W1, the FET 1 is turned off as shown by the waveform W2 slightly before the output voltage of the power circuit main body 1 is turned on. In this way, the method of controlling the ON / OFF of the FET 1 in synchronism with the ON / OFF control of the power supply circuit body 1 and turning on the FET 1 for backflow prevention only when the output voltage is surely rising is generally used. It is used. Thereby, the backflow prevention to the power supply circuit main body 1 which is turned off can be reliably performed.

FIG. 5A shows power supply devices PS1 and PS2 having the same configuration as FIG. 4A connected in parallel to the load 2 in the same manner as FIG. 7, and for example, as shown in FIG. When two PS2 units are operating in parallel, the cause of the dip amplitude in the output voltage at the moment when one power unit PS2 is turned off is that the two power units PS1 and PS2 operate in parallel redundant operation. from the output current _I 1, _{I 2} in a state where there is flowing by approximately 50% as shown in FIG. 5 (B) state, turning off the one power supply PS2, the output current _{I 1} of the power supply PS1 Figure As shown in FIG. 5 (B), the total output current I ₀ that has been covered by two units so far changes rapidly so as to be output only by the output current I _{1 of one} power source device PS1. The response of the control circuit 10A to the load current become abrupt change in total output current I ₀ (surge) controls the output voltage of the power supply PS1 is not catch up, the output voltage waveform W1 as a result to occur is Depp amplitude Dp End up. Usually, this dip as the amplitude Dp is larger total load current I _0, since the fluctuation range of the load power supply PS1 is larger, the larger dip amplitude Dp.

  As a measure to reduce the dip amplitude Dp of the output voltage at the time of sudden load change, the present invention uses a drive amplifier circuit that controls the gate electrode of the FET 1 according to the on / off state of the power supply device that is generally performed. Thus, when the gate signal becomes lower than the reference voltage of the output voltage control comparison circuit, the reference voltage is slightly reduced to reduce the depth Dp.

  An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a specific circuit configuration of the present invention. In FIG. 1, portions corresponding to those in FIG. The power supply circuit body 1 is supplied with a commercial AC signal from a commercial AC power supply AC, and is supplied to a filter circuit 1a, a power factor correction circuit (PFC) 1b, a resonance circuit (not shown), a DC-DC conversion circuit 1d, and the like. , Power factor improvement and DC conversion are performed, and an output capacitor C1 is connected to the output end of the DC-DC conversion circuit 1d, and an output line between one end of the capacitor C1 and the output terminal T1 to which the load 2 is connected A switching FET 1 made of a MOS type FET is connected, the anode S of the backflow prevention diode D1 is connected to the source S of the FET 1, and the cathode of the diode D1 is connected to the drain D of the FET 1 in parallel. The resistor R5 is connected to the output line between the other end of the capacitor C1 and the output terminal T2 to which the load 2 is connected.

  A drive amplifier circuit OP1 configured by an operational amplifier provided in the control circuit 10A (10B) outputs a DC voltage for gate control supplied to the gate of the FET 1 for switching, and the FET 1 via the drive amplifier circuit OP1. A gate signal voltage for on / off control is supplied to the gate G.

  The gate signal voltage of the drive amplifier circuit OP1 is supplied to a series circuit connected in series to the resistor R8 and the cathode of the diode D2. The anode of the series circuit diode D2 is connected to the reference voltage source input terminal Trf of the output voltage control comparison circuit OP2 composed of an operational amplifier constituting the control circuit 10A (10B). One end of the reference voltage source Vref is grounded, and the other end is connected to the anode of the diode D2 connected to the reference voltage source input terminal Trf of the output voltage control comparison circuit OP2 via the resistor R9. The other input terminal Tcn of the output voltage control comparison circuit OP2 is supplied with the output voltage supplied to the output terminal T1, and the output of the output voltage control comparison circuit OP2 is supplied to the DC-DC conversion circuit 1d. .

  A configuration in which the output of the drive amplifier circuit OP1 for controlling the FET 1 for preventing backflow described above is supplied to the output of the reference voltage source Vref used for the output voltage control comparison circuit OP2 through a series circuit of a resistor R8 and a diode D2. As for the operation in FIG. 4, the output of the drive amplifier circuit OP1 of the FET 1 has the sequence as described with reference to FIG. 4B, but the output voltage control circuit corresponds to the output of the drive amplifier circuit OP1. The reference voltage V2 at the connection point of the series circuit of the resistor R9 and the diode D2 connected to the reference voltage source Vref of the comparison circuit OP2 is the output waveform W2 of the drive amplifier circuit OP1 that controls the on / off of the FET1 as the waveform W3 of FIG. In synchronism with this, the resistors R8 and R9 are adjusted so as to change slightly as shown by ΔA3 and ΔA4, and the reference voltage V2 at the connection point is changed, thereby allowing the output of the power supply circuit body 1 to change. The force voltage also changes slightly as shown by ΔA1 and ΔA2 like the waveform W1 in synchronization with the output of the drive amplifier circuit OP1.

  FIG. 3 shows the operation when one power supply device PS2 is turned off when two power supply devices PS1 and SP2 [see FIG. 5A] similar to those shown in FIG. explain. First, as an operation when one power supply device PS2 is turned off from the parallel operation, the drive amplifier circuit OP1 becomes low (Lo), and the switching FET1 for backflow current prevention is turned off. In synchronization with this, the output voltage of the off-side power supply device PS2 slightly decreases to a voltage determined by the resistors R8 and R9.

  As the voltage decreases, the output current I2 of the power supply device PS2 that has been turned off is 50% in the fully-on state, but is reduced to, for example, about 20%. Then, the power supply device PS2 is completely turned off next, and is changed from the 20% state to 0%. From the viewpoint of the power supply device PS1 on the ON side, the load current ratio changes from the 50% state to the 80% state and then to the 100% state. Therefore, the dip amplitude Dp of the output voltage can be reduced as shown by the waveform W1 in FIG. 3 than when the load current ratio is suddenly changed from 50% to 100%.

  According to the present invention, using the gate signal voltage of the drive amplifier circuit that controls the FET 1 for switching according to the on / off state of a power supply device that is generally performed, the gate signal voltage is expressed as an output voltage. When the voltage drops below the reference voltage value of the control comparison circuit, the dip amplitude Dp is reduced by slightly reducing the reference voltage value, so that the two power supply units are currently sharing current Thus, the dip amplitude Dp of the output voltage generated when one power supply device is turned off can be reduced. In addition, since the capacity of the output capacitor C1 connected to the output line can be reduced, there is an effect that the component layout becomes easy and the electronic device can be miniaturized. The power supply apparatus and the method for reducing dip during parallel power supply operation of the present invention can be applied to small portable electronic devices such as a mobile phone, a PAD, a disk recording / reproducing apparatus, a digital camera, and a handy cam.

It is a circuit diagram which shows one example of a power supply device of this invention. It is waveform explanatory drawing of the power supply device of this invention. It is waveform explanatory drawing when one side at the time of the parallel operation of the power supply device of this invention is turned off. It is a circuit and waveform diagram for explaining a sequence of on / off control of a MOS FET. It is the circuit diagram and waveform diagram for demonstrating the cause of generation | occurrence | production of the dip which generate | occur | produces in an output voltage. It is a circuit diagram of one example of a conventional power supply device. It is a circuit diagram which shows the other example of a conventional power supply device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Power supply circuit main body, 1a ... Filter circuit, 1b ... Power factor improvement circuit (PFC), 1d ... DC-DC conversion circuit, 2 ... Load, 10A, 10B ... Control Circuits 6 ... D1, D2 ... Diodes, FET1 ... Switching MOS field effect transistors, OP1 ... Drive amplifier circuits, OP2 ... Output voltage control comparison circuits, R1 to R9. ..Resistance, Vref ... reference voltage source, C1 ... output capacitor

Claims (4)

A backflow prevention diode and a switching transistor connected to an output voltage line for supplying a predetermined output voltage from an output terminal to a power supply circuit body in which a plurality of units are connected in parallel, and an output voltage for detecting the output voltage of the power supply circuit body In a power supply device comprising a control comparison circuit and a drive amplification circuit that controls on / off of the switching diode when the power supply circuit body is abnormal based on a detection result of the output voltage control comparison circuit,
When the control signal supplied from the drive amplifier circuit to the switching transistor falls below the reference voltage supplied to the output voltage control comparison circuit, the reference voltage is lowered to reduce the output voltage dip. A power supply device characterized by that.   2. The control signal supplied from the drive amplifier circuit to the switching transistor is supplied through a resistor and a diode connected in series to a reference voltage source connected to the output voltage control comparison circuit. The power supply described. A backflow prevention diode and a switching transistor connected to an output voltage line for supplying a predetermined output voltage from an output terminal to a power supply circuit body in which a plurality of units are connected in parallel, and an output voltage for detecting the output voltage of the power supply circuit body In a method for reducing dip during parallel power supply operation, comprising: a control comparison circuit; and a drive amplifier circuit that controls on / off of the switching diode when the power supply circuit body is abnormal based on a detection result of the output voltage control comparison circuit ,
When the control signal supplied from the drive amplifier circuit to the switching transistor falls below the reference voltage supplied to the output voltage control comparison circuit, the reference voltage is lowered to reduce the output voltage dip. A method for reducing dip during parallel power supply operation.   4. A resistor and a diode connected in series to a reference voltage source connected to the output voltage control comparison circuit for the control signal supplied from the drive amplifier circuit to the switching transistor. Depth reduction method during parallel power supply operation.

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